Fix some bug or other to do with moving values out of the way

of rreg live ranges too early.  All this stuff needs revisiting.

git-svn-id: svn://svn.valgrind.org/vex/trunk@119

diff --git a/VEX/priv/host-generic/reg_alloc.c b/VEX/priv/host-generic/reg_alloc.c
index 36c610f3ca715fca4eeb8f640f48e80727ddd14c..2aebf95446a1ab47c80aac5e31ba2baad87a9dde 100644 (file)
--- a/VEX/priv/host-generic/reg_alloc.c
+++ b/VEX/priv/host-generic/reg_alloc.c
@@ -749,7 +749,7 @@ HInstrArray* doRegisterAllocation (
                   still live. */
                m = hregNumber(state[k].vreg);
                vassert(m >= 0 && m < n_vregs);
-               if (vreg_info[m].dead_before > ii) {
+               if (vreg_info[m].dead_before >= ii) {
                   vassert(vreg_info[m].reg_class != HRcINVALID);
                   EMIT_INSTR( (*genSpill)( state[k].rreg,
                                            vreg_info[m].spill_offset ) );