clk: renesas: r9a08g045: Add I3C clocks and resets

Extracted from the BSP driver and rebased.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250630192438.38311-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index ed0661997928b0ca38b87dc49d8d8730c7586162..643dec45e39d75d8f4f6c9b6df74a6c6d3479cc5 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -183,6 +183,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
        DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
                    dtable_1_32, 0, 0, 0, NULL),
        DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
+       DEF_FIXED("P5", R9A08G045_CLK_P5, CLK_PLL2_DIV2, 1, 4),
        DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),
        DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
        DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
@@ -291,6 +292,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
                                        MSTOP(BUS_MCPU2, BIT(14))),
        DEF_MOD("tsu_pclk",             R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
                                        MSTOP(BUS_MCPU2, BIT(15))),
+       DEF_MOD("i3c_pclk",             R9A08G045_I3C_PCLK, R9A08G045_CLK_TSU, 0x610, 0,
+                                       MSTOP(BUS_MCPU3, BIT(10))),
+       DEF_MOD("i3c_tclk",             R9A08G045_I3C_TCLK, R9A08G045_CLK_P5, 0x610, 1,
+                                       MSTOP(BUS_MCPU3, BIT(10))),
        DEF_MOD("vbat_bclk",            R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,
                                        MSTOP(BUS_MCPU3, GENMASK(8, 7))),
 };
@@ -331,6 +336,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
        DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
        DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
+       DEF_RST(R9A08G045_I3C_TRESETN, 0x910, 0),
+       DEF_RST(R9A08G045_I3C_PRESETN, 0x910, 1),
        DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
 };