]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
accel/amdxdna: Add IOCTL parameter for resource data
authorLizhi Hou <lizhi.hou@amd.com>
Tue, 4 Nov 2025 06:25:44 +0000 (22:25 -0800)
committerLizhi Hou <lizhi.hou@amd.com>
Tue, 4 Nov 2025 17:03:11 +0000 (09:03 -0800)
Extend DRM_IOCTL_AMDXDNA_GET_INFO to include additional parameters
that allow collection of resource data.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20251104062546.833771-2-lizhi.hou@amd.com
drivers/accel/amdxdna/aie2_ctx.c
drivers/accel/amdxdna/aie2_message.c
drivers/accel/amdxdna/aie2_pci.c
drivers/accel/amdxdna/amdxdna_pci_drv.c
include/uapi/drm/amdxdna_accel.h

index 289a2aaf4cae8a61e390ddc2fb781b3409bd00e6..b78c47ed0d34daa2b6ad7930d4078c74e4cca47e 100644 (file)
@@ -556,7 +556,6 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
        struct drm_gpu_scheduler *sched;
        struct amdxdna_hwctx_priv *priv;
        struct amdxdna_gem_obj *heap;
-       struct amdxdna_dev_hdl *ndev;
        int i, ret;
 
        priv = kzalloc(sizeof(*hwctx->priv), GFP_KERNEL);
@@ -654,8 +653,6 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
        amdxdna_pm_suspend_put(xdna);
 
        hwctx->status = HWCTX_STAT_INIT;
-       ndev = xdna->dev_handle;
-       ndev->hwctx_num++;
        init_waitqueue_head(&priv->job_free_wq);
 
        XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);
@@ -688,13 +685,10 @@ free_priv:
 
 void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx)
 {
-       struct amdxdna_dev_hdl *ndev;
        struct amdxdna_dev *xdna;
        int idx;
 
        xdna = hwctx->client->xdna;
-       ndev = xdna->dev_handle;
-       ndev->hwctx_num--;
 
        XDNA_DBG(xdna, "%s sequence number %lld", hwctx->name, hwctx->priv->seq);
        drm_sched_entity_destroy(&hwctx->priv->entity);
index 339dec99824746e21b38dbe81c9626d15c698360..39214253d804317cf43bd7a01d155334c1020e5c 100644 (file)
@@ -235,6 +235,7 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct
                ret = -EINVAL;
                goto out_destroy_context;
        }
+       ndev->hwctx_num++;
 
        XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d",
                 hwctx->name, ret, resp.msix_id);
@@ -269,6 +270,7 @@ int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwc
                 hwctx->fw_ctx_id);
        hwctx->priv->mbox_chann = NULL;
        hwctx->fw_ctx_id = -1;
+       ndev->hwctx_num--;
 
        return ret;
 }
index ce57b915004eb69f8c2a0af42a9e1601ff21718f..396dc6e060077b92b22e8e2de4c085d1846354e3 100644 (file)
@@ -838,6 +838,30 @@ static int aie2_get_hwctx_status(struct amdxdna_client *client,
        return 0;
 }
 
+static int aie2_query_resource_info(struct amdxdna_client *client,
+                                   struct amdxdna_drm_get_info *args)
+{
+       struct amdxdna_drm_get_resource_info res_info;
+       const struct amdxdna_dev_priv *priv;
+       struct amdxdna_dev_hdl *ndev;
+       struct amdxdna_dev *xdna;
+
+       xdna = client->xdna;
+       ndev = xdna->dev_handle;
+       priv = ndev->priv;
+
+       res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk;
+       res_info.npu_tops_max = ndev->max_tops;
+       res_info.npu_task_max = priv->hwctx_limit;
+       res_info.npu_tops_curr = ndev->curr_tops;
+       res_info.npu_task_curr = ndev->hwctx_num;
+
+       if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, sizeof(res_info)))
+               return -EFAULT;
+
+       return 0;
+}
+
 static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
 {
        struct amdxdna_dev *xdna = client->xdna;
@@ -872,6 +896,9 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
        case DRM_AMDXDNA_GET_POWER_MODE:
                ret = aie2_get_power_mode(client, args);
                break;
+       case DRM_AMDXDNA_QUERY_RESOURCE_INFO:
+               ret = aie2_query_resource_info(client, args);
+               break;
        default:
                XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
                ret = -EOPNOTSUPP;
index 3599e713bfcb5f1685ef9f53471de4ac10260127..af943a603ad1589a79f236df32c0176cd3e9543a 100644 (file)
@@ -29,9 +29,10 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
  * 0.1: Support getting all hardware contexts by DRM_IOCTL_AMDXDNA_GET_ARRAY
  * 0.2: Support getting last error hardware error
  * 0.3: Support firmware debug buffer
+ * 0.4: Support getting resource information
  */
 #define AMDXDNA_DRIVER_MAJOR           0
-#define AMDXDNA_DRIVER_MINOR           3
+#define AMDXDNA_DRIVER_MINOR           4
 
 /*
  * Bind the driver base on (vendor_id, device_id) pair and later use the
index c7eec9ceb2aee910711593c810be9d78619e5e7a..8b679c38d30864eb753e07031fd30be7f29dd0fb 100644 (file)
@@ -442,6 +442,23 @@ enum amdxdna_drm_get_param {
        DRM_AMDXDNA_QUERY_HW_CONTEXTS,
        DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8,
        DRM_AMDXDNA_GET_POWER_MODE,
+       DRM_AMDXDNA_QUERY_RESOURCE_INFO = 12,
+};
+
+/**
+ * struct amdxdna_drm_get_resource_info - Get resource information
+ */
+struct amdxdna_drm_get_resource_info {
+       /** @npu_clk_max: max H-Clocks */
+       __u64 npu_clk_max;
+       /** @npu_tops_max: max TOPs */
+       __u64 npu_tops_max;
+       /** @npu_task_max: max number of tasks */
+       __u64 npu_task_max;
+       /** @npu_tops_curr: current TOPs */
+       __u64 npu_tops_curr;
+       /** @npu_task_curr: current number of tasks */
+       __u64 npu_task_curr;
 };
 
 /**