re PR lto/59326 (FAIL: gcc.dg/vect/vect-simd-clone-*.c)

	PR lto/59326
	* gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
	* lib/target-supports.exp (check_effective_target_avx2): ... here.
	(check_effective_target_vect_simd_clones): New.
	* gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
	vect_simd_clones.
	* gcc.dg/vect/vect-simd-clone-2.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-3.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-4.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-5.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-6.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-7.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-8.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-9.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-10.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-11.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-12.c: Likewise.

From-SVN: r205606

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f92967a671c14bb9b808e53309d1094cf494c21c..b9c2b6e719837ab24d3ab499e9563c2a97fc1c8f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,23 @@
+2013-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+       PR lto/59326
+       * gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
+       * lib/target-supports.exp (check_effective_target_avx2): ... here.
+       (check_effective_target_vect_simd_clones): New.
+       * gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
+       vect_simd_clones.
+       * gcc.dg/vect/vect-simd-clone-2.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-3.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-4.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-5.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-6.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-7.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-8.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-9.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-10.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-11.c: Likewise.
+       * gcc.dg/vect/vect-simd-clone-12.c: Likewise.
+
 2013-12-02  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
        * gcc.dg/pr56997-4.c: New testcase.

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
index d802dfb7e27172571ee973148c10ecf8517cb3f1..9fdd056388997ee08fb372cb9cf929c093dc848c 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
index 3f29b52a8c3b3ba37fc5ca1c953db6b74d5e6c8f..923a9453c25f92397047a2e7512abc6e389d2774 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 /* { dg-additional-sources vect-simd-clone-10a.c } */

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
index 4cccf852d0e4f19a1098331d77876f0e1518f315..a04530e251eb836b91c8b4b3fcd5ac4f1d3c022c 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
index 5c94153ea808b712e5fbf2d838ee597af66698b5..279abd7c6824e29d3160733aef29ce3e998524ef 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 /* { dg-additional-sources vect-simd-clone-12a.c } */

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
index 4447607ef518a84f68abe51f63ad9a382812d5c6..0eae49db97aea388b87ed014d573431ef26ae613 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
index 222d88e3016f06cb2b854c611978b5f5d7c0c30e..857c6f783e3cdf4968eb364904ce83f7fad88541 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
index 5b0a93a53d7cc1c42e67571bb221caf942e1aa54..c64f1b0bfe5563f64f8cc20f39beef666ad82320 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
index fd1d5ffd322837671f5037c912dda2a89682be34..1d2b067a7d5281c756ea7ae3ab401cdde66fca58 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
index 5e5641476c5338b9ea6ce7564b932ec3118468e8..26995da86e3ece87bfe437809d8196dfe842a593 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
index 24856eaa41a08bd07993d43bb2a97640350f1aad..2745c5e41d198ad1dd90e7b8fc97fc09865f34ca 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
index 19c25c9db490c57e4d8f4003cdbbec60d4b1d42d..e0b09b645d44f373dd7d78cd8e15cb3f10eda1f4 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
index 95156b90f011b213b778fba240dea6d691c1841c..0c5ff4fa4382d908de762fe13f3dec48dd559226 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-additional-options "-fopenmp-simd" } */
 /* { dg-additional-options "-mavx" { target avx_runtime } } */
 

diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp
index 15f744cf2de96e83036272484a057050275a230d..c7c26766bc214a586a9fc5a65cb455ac085e2aa8 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/i386.exp
+++ b/gcc/testsuite/gcc.target/i386/i386.exp
@@ -209,18 +209,6 @@ proc check_effective_target_lzcnt { } {
     } "-mlzcnt" ]
 }
 
-# Return 1 if avx2 instructions can be compiled.
-proc check_effective_target_avx2 { } {
-    return [check_no_compiler_messages avx2 object {
-       typedef long long __v4di __attribute__ ((__vector_size__ (32)));
-       __v4di
-       mm256_is32_andnotsi256  (__v4di __X, __v4di __Y)
-        {
-          return __builtin_ia32_andnotsi256 (__X, __Y);
-       }
-    } "-O0 -mavx2" ]
-}
-
 # Return 1 if bmi instructions can be compiled.
 proc check_effective_target_bmi { } {
     return [check_no_compiler_messages bmi object {

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 104818d327e6ad5dc9e547faa723d59c206f2bbc..e0f097d624185bca1c6462f0e704e73e5fa686b2 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2146,6 +2146,32 @@ proc check_effective_target_vect_floatuint_cvt { } {
     return $et_vect_floatuint_cvt_saved
 }
 
+# Return 1 if the target supports #pragma omp declare simd, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_simd_clones { } {
+    global et_vect_simd_clones_saved
+
+    if [info exists et_vect_simd_clones_saved] {
+       verbose "check_effective_target_vect_simd_clones: using cached result" 2
+    } else {
+       set et_vect_simd_clones_saved 0
+       if { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
+           # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx and
+           # avx2 clone.  Only the right clone for the specified arch will be
+           # chosen, but still we need to at least be able to assemble
+           # avx2.
+           if { [check_effective_target_avx2] } {
+               set et_vect_simd_clones_saved 1
+           }
+       }
+    }
+
+    verbose "check_effective_target_vect_simd_clones: returning $et_vect_simd_clones_saved" 2
+    return $et_vect_simd_clones_saved
+}
+
 # Return 1 if this is a AArch64 target supporting big endian
 proc check_effective_target_aarch64_big_endian { } {
     return [check_no_compiler_messages aarch64_big_endian assembly {
@@ -5106,6 +5132,18 @@ proc check_effective_target_avx { } {
     } "-O2 -mavx" ]
 }
 
+# Return 1 if avx2 instructions can be compiled.
+proc check_effective_target_avx2 { } {
+    return [check_no_compiler_messages avx2 object {
+       typedef long long __v4di __attribute__ ((__vector_size__ (32)));
+       __v4di
+       mm256_is32_andnotsi256  (__v4di __X, __v4di __Y)
+        {
+          return __builtin_ia32_andnotsi256 (__X, __Y);
+       }
+    } "-O0 -mavx2" ]
+}
+
 # Return 1 if sse instructions can be compiled.
 proc check_effective_target_sse { } {
     return [check_no_compiler_messages sse object {