arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes

These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:

* The #shift immediate value not in the check-function-bodies as expected
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
  this case the test rewritten from the ACLE had the lsr+and pattern,
  but the compiler was able to optimise to ubfx. Hence I've changed the
  test to now match on ubfx.
* Added a separate test to check shift on constants being optimised to
  movs.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/mve_const_shifts.c: New test.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42fd33aaf981c0b4bc1296e41f20346705e..734375d58c0664eb8c58a5a53f180bf9ebd74c9f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     srshr   (?:ip|fp|r[0-9]+), #shift(?:    @.*|)
+**     srshr   (?:ip|fp|r[0-9]+), #1(?:        @.*|)
 **     ...
 */
 int32_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28ccbfdea445b3249b7c8ada9922e89b059da..a91943c38a017e2e26583d80f8e8665b54ed015e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     srshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+**     srshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:     @.*|)
 **     ...
 */
 int64_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d97ba653af798f76f9e8e68968b7c75d074..462531cad54e5bfe21e8a5cbd72ef41200a2399b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     uqshl   (?:ip|fp|r[0-9]+), #shift(?:    @.*|)
+**     uqshl   (?:ip|fp|r[0-9]+), #1(?:        @.*|)
 **     ...
 */
 uint32_t
@@ -21,18 +21,6 @@ foo (uint32_t value)
   return uqshl (value, 1);
 }
 
-/*
-**foo1:
-**     ...
-**     uqshl   (?:ip|fp|r[0-9]+), #shift(?:    @.*|)
-**     ...
-*/
-uint32_t
-foo1 ()
-{
-  return uqshl (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08eea756afeed57be09b8f2f70dbb3275ac6..6fa97a561e317b7e1dfa11d0ef7f0fdd7ec3b5ee 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     uqshll  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+**     uqshll  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:     @.*|)
 **     ...
 */
 uint64_t
@@ -21,18 +21,6 @@ foo (uint64_t value)
   return uqshll (value, 1);
 }
 
-/*
-**foo1:
-**     ...
-**     uqshll  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
-**     ...
-*/
-uint64_t
-foo1 ()
-{
-  return uqshll (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8da4c407429fd25c5bfb252e5dbe3ed570..ff97bf5c473bf169c9028eaf7b23f0bcb6a980b6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     urshr   (?:ip|fp|r[0-9]+), #shift(?:    @.*|)
+**     urshr   (?:ip|fp|r[0-9]+), #1(?:        @.*|)
 **     ...
 */
 uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
 /*
 **foo1:
 **     ...
-**     urshr   (?:ip|fp|r[0-9]+), #shift(?:    @.*|)
+**     urshr   (?:ip|fp|r[0-9]+), #1(?:        @.*|)
 **     ...
 */
 uint32_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371f47fa8d134d240ebca72d9500978cbbe4..ff6a69d300fa64782777f9952d81edf45e115664 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **     ...
-**     urshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+**     urshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:     @.*|)
 **     ...
 */
 uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
 /*
 **foo1:
 **     ...
-**     urshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+**     urshrl  (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:     @.*|)
 **     ...
 */
 uint64_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf94d39315a18af4098cfcb2cebc0acf9338..a6a059a19e959c8e3855f0596bdad4d694fcb391 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349caed36ac1ed5d830dbad09c84d301840cfb9..942111339f0debdd42c1962f3892f1a8e07af2de 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993a3555858f5cf8c98a78f2641d5eb96533..3b68bb6ac33eabd0d2f825f5c7728740b8935dd5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61d23852bc5786691646223e0500ec31e13..82228491043202273e1254ef3e694cbf2d731735 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 5c2702a3142889eb687aba25b805b470fffb4eb1..da29bb765dd10b5954486f9d431b289b31032397 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -30,9 +30,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -63,9 +61,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index a3c0171062735089edc40c2194fe62e9a28d88cc..be490aaaae7b0b18a734f6872ae6d542c9bd38f4 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -30,9 +30,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -63,9 +61,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index efe4f8c778b47aecbe73687ade33e27fbd425923..d72190d53b5fe764b68922c6ec410fd0af455818 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index af778be6917900ac26c29d770b4714b7d8ed4de6..dbc1ebf3c46251a22d6a4d311c05c08b96a241ab 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c9da3e3d1fb1be8db264a3ab45f0cc1c05..dcbaef1a5717cdce8fe6ee7b715f0346c13bbde0 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f152cdeb0c9daba19b3e3855ddcd3d9f83aa..08f67f665c1c2137ad948b4c077540d4e394cf6d 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f0b2a23720bdb61f82af06c8a754dbc612..803246c32352d8108b27365b1e7828367629f293 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a64daad398250e253a1967a03c576dd5ba8..22d2b4355bc12477f9899f5c80b0c42ad473733f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index ed9e48ce7bbacaf923d36fc37ffe8f9f0c6eaa73..0c62778d4827f2a96fa028056b46d63449cf85b8 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -30,9 +30,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -63,9 +61,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 442a52ed5f3a7c082b3792edeb8551c4ee8dcdda..2532a23fac81571c14704017b18de72709292a4b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -30,9 +30,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -63,9 +61,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index fa88ec5dcd82003e3b2a9261d57477e280d900f8..5deff8c4018c0909abb6e1fe09c03c9bc3e5c21e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 int32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index c3ae208ff825906d46731b5d7c2f09ecae7afbb6..bd0ea2df1276739e8492a0eb1da88d5d5a445d13 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **     ...
 **     vmrs    (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:      @.*|)
 **     ...
-**     lsr     (?:ip|fp|r[0-9]+), #29(?:       @.*|)
-**     ...
-**     and     (?:ip|fp|r[0-9]+), #1(?:        @.*|)
+**     ubfx    (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:        @.*|)
 **     ...
 */
 uint32x4_t

diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
new file mode 100644 (file)
index 0000000..b17f9f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
@@ -0,0 +1,41 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo11:
+**     ...
+**     movs    r0, #2
+**     ...
+*/
+uint32_t
+foo11 ()
+{
+  return uqshl (1, 1);
+}
+
+/*
+**foo12:
+**     ...
+**     movs    r0, #2
+**     movs    r1, #0
+**     ...
+*/
+uint64_t
+foo12 ()
+{
+  return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */