arm64: dts: qcom: talos: Add CCI definitions

Qualcomm Talos SoC contains single controller,
containing 2 I2C hosts.

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-sm6150_evk-v6-3-38ce4360d5e0@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index e4489c0cf27f2f18aadda086b9627f16baae9110..bdd9a3c448f5fa4a5d682bdc884fcbf94905b1c0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1562,6 +1562,22 @@
                        #interrupt-cells = <2>;
                        wakeup-parent = <&pdc>;
 
+                       cci_i2c0_default: cci-i2c0-default-state {
+                               /* SDA, SCL */
+                               pins = "gpio32", "gpio33";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
+                       cci_i2c1_default: cci-i2c1-default-state {
+                               /* SDA, SCL */
+                               pins = "gpio34", "gpio35";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
                        qup_i2c1_data_clk: qup-i2c1-data-clk-state {
                                pins = "gpio4", "gpio5";
                                function = "qup0";
@@ -3955,6 +3971,41 @@
                        #power-domain-cells = <1>;
                };
 
+               cci: cci@ac4a000 {
+                       compatible = "qcom,sm6150-cci", "qcom,msm8996-cci";
+
+                       reg = <0x0 0x0ac4a000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING 0>;
+                       power-domains = <&camcc TITAN_TOP_GDSC>;
+                       clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_AHB_CLK>,
+                                <&camcc CAM_CC_CCI_CLK>;
+                       clock-names = "camnoc_axi",
+                                     "cpas_ahb",
+                                     "cci";
+                       pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
+                       pinctrl-names = "default";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+
+                       cci_i2c0: i2c-bus@0 {
+                               reg = <0>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       cci_i2c1: i2c-bus@1 {
+                               reg = <1>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                camss: isp@acb3000 {
                        compatible = "qcom,sm6150-camss";