RISC-V: Add test for vec_duplicate + vwsubu.wv combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vwsubu.wv
combine to vwsubu.wx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vwsubu.wx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper
	macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 76ef2d3f0206a6b5f15d2f71daa70d4435001974..be4d23c2f437e3ff8dabc1b2bf2f43c3b2b9debb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -13,7 +13,7 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
-/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 55fa57dec35d0a44f0eb1cf66267efd4abf1d5de..56dd314a7e168238a81e3c030ed01bf37f94d3b9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -13,7 +13,7 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
-/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index d5176834494eaec79e9f1e3f2a14b37f489eec08..685f5f631ef505d7b74728a439e64ab1838f7d4f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -36,3 +36,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a234505ce81c4347ee1cdca377405178cd538c02..391c59f502a1231ec90ec7f190db6cd36d246c62 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index a46c874d0a440190702872de036a0f3ecd5b68a1..2bcb6a136ff8915730837fab9a22f7044014d714 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 94ce774fc2aa164661f02e05730d5dd66a1a1832..0aa6a212c1e564ff6b9734cc77cb9c4a21468244 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a1278cec61d4c6e274e13871b812b97d9416fc2e..48e095f63ff1abf091b79dc927de7487edcc0198 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 910fa6e315804610a425377539fc03d257fe182a..761ce5d1a56e00c3bfb9e2a1b781f132d6f9abe4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 9ce0211603ecc3c77c7974f264d0de59fe5ad260..1eebec94a6db184eedc5be3354c8857bbcca6422 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.wx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
index 03fba3c2a0c4efba79c9503ad805fe813bbadfbc..5be5f2d456e15e1bf1529f637af18a7f39aa1f9a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -50,5 +50,6 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT * restrict vd,   \
   DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \
   DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \
   DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, add) \
+  DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, sub) \
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
index faf46a81e6abeba43dbcac80eae539a1c5856447..af7d8358ad90a124eb1e0d981268a3161850e59e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -72,6 +72,7 @@ DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul)
   DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME)
 
 DEF_BINARY_WIDEN_STRUCT_1_WRAP(uint64_t, uint32_t, add)
+DEF_BINARY_WIDEN_STRUCT_1_WRAP(uint64_t, uint32_t, sub)
 
 DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
   {
@@ -229,4 +230,43 @@ DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, add)[] = {
   },
 };
 
+DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, sub)[] = {
+  {
+    /* vs2 */
+    {
+         2147483648,    2147483648,    2147483648,    2147483648,
+         2147483647,    2147483647,    2147483647,    2147483647,
+         4294967294,    4294967294,    4294967294,    4294967294,
+      4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull,
+    },
+    /* rs1 */
+    2147483647,
+    /* expect */
+    {
+               1,          1,          1,          1,
+               0,          0,          0,          0,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      2147483649, 2147483649, 2147483649, 2147483649,
+    },
+  },
+  {
+    /* vs2 */
+    {
+      4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull,
+      4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+      8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull,
+      8589934591ull, 8589934591ull, 8589934591ull, 8589934591ull,
+    },
+    /* rs1 */
+    4294967295,
+    /* expect */
+    {
+                  1,             1,             1,             1,
+                  0,             0,             0,             0,
+      4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+      4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c
new file mode 100644 (file)
index 0000000..23043b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwsubu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT        uint64_t
+#define NT        uint32_t
+#define NAME      sub
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_1_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+  RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_wx_run.h"