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constraints.md (Bw): Rename from 'w'.
authorUros Bizjak <uros@gcc.gnu.org>
Sun, 1 Jun 2014 20:53:18 +0000 (22:53 +0200)
committerUros Bizjak <uros@gcc.gnu.org>
Sun, 1 Jun 2014 20:53:18 +0000 (22:53 +0200)
* config/i386/constraints.md (Bw): Rename from 'w'.
(Bz): Rename from 'z'.
* config/i386/i386.md: Change 'w' to 'Bw' and 'z' to 'Bz' globally.

From-SVN: r211119

gcc/ChangeLog patch | blob | blame | history
gcc/config/i386/constraints.md patch | blob | blame | history
gcc/config/i386/i386.md patch | blob | blame | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 29ce4be553ffee64a1a17e26b81a312ac72f4db8..120ada9d8161cf09982d372bdc50785395281c40 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,8 +1,15 @@
+2014-06-01  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/constraints.md (Bw): Rename from 'w'.
+       (Bz): Rename from 'z'.
+       * config/i386/i386.md: Change 'w' to 'Bw' and 'z' to 'Bz' globally.
+
 2014-06-01  Kai Tietz  <ktietz@redhat.com>
 
        PR target/61377
-       * constrains.md (define_constrain): New 'Bs' constraint.
-       * i386.md (sibcall_insn_operand): Use Bs instead of m constraint.
+       * config/i386/constrains.md (define_constrain): New 'Bs' constraint.
+       * config/i386/i386.md (sibcall_insn_operand): Use Bs
+       instead of m constraint.
 
 2014-05-31  Andreas Schwab  <schwab@linux-m68k.org>
 
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index b142c1913782afd7eac34d253d05f0feeefb5300..8e0a58355ecdf26ff87150fbf3b869efd1742f98 100644 (file)
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -19,7 +19,7 @@
 
 ;;; Unused letters:
 ;;;           H
-;;;           h j
+;;;           h j            w  z
 
 ;; Integer register constraints.
 ;; It is not necessary to define 'r' here.
@@ -91,6 +91,9 @@
 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
  "Any SSE register.")
 
+(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
+ "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
+
 ;; We use the Y prefix to denote any number of conditional register sets:
 ;;  z  First SSE register.
 ;;  i  SSE2 inter-unit moves to SSE register enabled
@@ -144,26 +147,25 @@
  "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
  "@internal Any x87 register when 80387 FP arithmetic is enabled.")
 
-;; We use the B prefix to denote any number of internal memory operands:
-;;  s  Sibling memory operand.
+;; We use the B prefix to denote any number of internal operands:
+;;  s  Sibcall memory operand, not valid for TARGET_X32
+;;  w  Call memory operand, not valid for TARGET_X32
+;;  z  Constant call address operand.
 
 (define_constraint "Bs"
   "@internal Sibcall memory operand."
   (and (not (match_test "TARGET_X32"))
        (match_operand 0 "sibcall_memory_operand")))
 
-(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
- "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
-
-(define_constraint "z"
-  "@internal Constant call address operand."
-  (match_operand 0 "constant_call_address_operand"))
-
-(define_constraint "w"
+(define_constraint "Bw"
   "@internal Call memory operand."
   (and (not (match_test "TARGET_X32"))
        (match_operand 0 "memory_operand")))
 
+(define_constraint "Bz"
+  "@internal Constant call address operand."
+  (match_operand 0 "constant_call_address_operand"))
+
 ;; Integer constant constraints.
 (define_constraint "I"
   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6fc69ff163e3c062fb094c52bd630b7615202024..f7716a82381066c08c51950da12dea6bddaa635d 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -11182,7 +11182,7 @@
 })
 
 (define_insn "*indirect_jump"
-  [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))]
+  [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))]
   ""
   "jmp\t%A0"
   [(set_attr "type" "ibr")
@@ -11230,7 +11230,7 @@
 })
 
 (define_insn "*tablejump_1"
-  [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))
+  [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))
    (use (label_ref (match_operand 1)))]
   ""
   "jmp\t%A0"
@@ -11360,7 +11360,7 @@
 })
 
 (define_insn "*call"
-  [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw"))
+  [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>BwBz"))
         (match_operand 1))]
   "!SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[0]);"
@@ -11368,7 +11368,7 @@
 
 (define_insn "*call_rex64_ms_sysv"
   [(match_parallel 2 "call_rex64_ms_sysv_operation"
-    [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
+    [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rBwBz"))
           (match_operand 1))
      (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)])]
   "TARGET_64BIT && !SIBLING_CALL_P (insn)"
@@ -11376,7 +11376,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall"
-  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UzBs"))
+  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UBsBz"))
         (match_operand 1))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[0]);"
@@ -11396,7 +11396,7 @@
 })
 
 (define_insn "*call_pop"
-  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
+  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lmBz"))
         (match_operand 1))
    (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG)
@@ -11406,7 +11406,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall_pop"
-  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "UzBs"))
+  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "UBsBz"))
         (match_operand 1))
    (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG)
@@ -11443,7 +11443,7 @@
 
 (define_insn "*call_value"
   [(set (match_operand 0)
-       (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw"))
+       (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>BwBz"))
              (match_operand 2)))]
   "!SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[1]);"
@@ -11451,7 +11451,7 @@
 
 (define_insn "*sibcall_value"
   [(set (match_operand 0)
-       (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UzBs"))
+       (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UBsBz"))
              (match_operand 2)))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[1]);"
@@ -11460,7 +11460,7 @@
 (define_insn "*call_value_rex64_ms_sysv"
   [(match_parallel 3 "call_rex64_ms_sysv_operation"
     [(set (match_operand 0)
-         (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
+         (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rBwBz"))
                (match_operand 2)))
      (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)])]
  "TARGET_64BIT && !SIBLING_CALL_P (insn)"
@@ -11483,7 +11483,7 @@
 
 (define_insn "*call_value_pop"
   [(set (match_operand 0)
-       (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
+       (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lmBz"))
              (match_operand 2)))
    (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG)
@@ -11494,7 +11494,7 @@
 
 (define_insn "*sibcall_value_pop"
   [(set (match_operand 0)
-       (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "UzBs"))
+       (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "UBsBz"))
              (match_operand 2)))
    (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG)
@@ -12539,7 +12539,7 @@
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "b")
          (match_operand 2 "tls_symbolic_operand")
-         (match_operand 3 "constant_call_address_operand" "z")
+         (match_operand 3 "constant_call_address_operand" "Bz")
          (reg:SI SP_REG)]
         UNSPEC_TLS_GD))
    (clobber (match_scratch:SI 4 "=d"))
@@ -12577,7 +12577,7 @@
 (define_insn "*tls_global_dynamic_64_<mode>"
   [(set (match_operand:P 0 "register_operand" "=a")
        (call:P
-        (mem:QI (match_operand 2 "constant_call_address_operand" "z"))
+        (mem:QI (match_operand 2 "constant_call_address_operand" "Bz"))
         (match_operand 3)))
    (unspec:P [(match_operand 1 "tls_symbolic_operand")]
             UNSPEC_TLS_GD)]
@@ -12634,7 +12634,7 @@
   [(set (match_operand:SI 0 "register_operand" "=a")
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "b")
-         (match_operand 2 "constant_call_address_operand" "z")
+         (match_operand 2 "constant_call_address_operand" "Bz")
          (reg:SI SP_REG)]
         UNSPEC_TLS_LD_BASE))
    (clobber (match_scratch:SI 3 "=d"))
@@ -12673,7 +12673,7 @@
 (define_insn "*tls_local_dynamic_base_64_<mode>"
   [(set (match_operand:P 0 "register_operand" "=a")
        (call:P
-        (mem:QI (match_operand 1 "constant_call_address_operand" "z"))
+        (mem:QI (match_operand 1 "constant_call_address_operand" "Bz"))
         (match_operand 2)))
    (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)]
   "TARGET_64BIT"
@@ -12725,7 +12725,7 @@
   [(set (match_operand:SI 0 "register_operand" "=a")
        (plus:SI
         (unspec:SI [(match_operand:SI 1 "register_operand" "b")
-                    (match_operand 2 "constant_call_address_operand" "z")
+                    (match_operand 2 "constant_call_address_operand" "Bz")
                     (reg:SI SP_REG)]
                    UNSPEC_TLS_LD_BASE)
         (const:SI (unspec:SI
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