pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins

[ Upstream commit 5ef6914e0bf578357b4c906ffe6b26e7eedb8ccf ]

The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
specified in RK3328 TRM, however we can get hint from pad name and its
correspinding IOMUX setting for pins in interface descriptions. The
correspinding IOMIX settings for these pins can be found in the same
row next to occurrences of following pad names in RK3328 TRM.

GPIO3-B1:  IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6

Add pinmux data to rk3328_mux_recalced_data as mux register offset for
these pins does not follow rockchip convention.

Signed-off-by: Huang-Huang Bao <i@eh5.me>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")
Link: https://lore.kernel.org/r/20240606125755.53778-3-i@eh5.me
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index a9a8b515a80725c14f7f9119752ed49865c0732e..deedfc4da2d76852b035d2f7abb224f83d2aaa5f 100644 (file)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -661,17 +661,68 @@ static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
        {
+               /* gpio2_b7_sel */
                .num = 2,
                .pin = 15,
                .reg = 0x28,
                .bit = 0,
                .mask = 0x7
        }, {
+               /* gpio2_c7_sel */
                .num = 2,
                .pin = 23,
                .reg = 0x30,
                .bit = 14,
                .mask = 0x3
+       }, {
+               /* gpio3_b1_sel */
+               .num = 3,
+               .pin = 9,
+               .reg = 0x44,
+               .bit = 2,
+               .mask = 0x3
+       }, {
+               /* gpio3_b2_sel */
+               .num = 3,
+               .pin = 10,
+               .reg = 0x44,
+               .bit = 4,
+               .mask = 0x3
+       }, {
+               /* gpio3_b3_sel */
+               .num = 3,
+               .pin = 11,
+               .reg = 0x44,
+               .bit = 6,
+               .mask = 0x3
+       }, {
+               /* gpio3_b4_sel */
+               .num = 3,
+               .pin = 12,
+               .reg = 0x44,
+               .bit = 8,
+               .mask = 0x3
+       }, {
+               /* gpio3_b5_sel */
+               .num = 3,
+               .pin = 13,
+               .reg = 0x44,
+               .bit = 10,
+               .mask = 0x3
+       }, {
+               /* gpio3_b6_sel */
+               .num = 3,
+               .pin = 14,
+               .reg = 0x44,
+               .bit = 12,
+               .mask = 0x3
+       }, {
+               /* gpio3_b7_sel */
+               .num = 3,
+               .pin = 15,
+               .reg = 0x44,
+               .bit = 14,
+               .mask = 0x3
        },
 };