+++ /dev/null
-From 2daa2a2adcbaf45f17b14546a31f32ab9f0150f1 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 25 Oct 2023 18:30:29 +0530
-Subject: PCI: qcom-ep: Add dedicated callback for writing to DBI2 registers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-
-[ Upstream commit a07d2497ed657eb2efeb967af47e22f573dcd1d6 ]
-
-The DWC core driver exposes the write_dbi2() callback for writing to the
-DBI2 registers in a vendor-specific way.
-
-On the Qcom EP platforms, the DBI_CS2 bit in the ELBI region needs to be
-asserted before writing to any DBI2 registers and deasserted once done.
-
-So, let's implement the callback for the Qcom PCIe EP driver so that the
-DBI2 writes are correctly handled in the hardware.
-
-Without this callback, the DBI2 register writes like BAR size won't go
-through and as a result, the default BAR size is set for all BARs.
-
-[kwilczynski: commit log, renamed function to match the DWC convention]
-Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
-Suggested-by: Serge Semin <fancer.lancer@gmail.com>
-Link: https://lore.kernel.org/linux-pci/20231025130029.74693-2-manivannan.sadhasivam@linaro.org
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-Signed-off-by: Krzysztof WilczyĆski <kwilczynski@kernel.org>
-Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
-Cc: stable@vger.kernel.org # 5.16+
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/pci/controller/dwc/pcie-qcom-ep.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
-index d4c566c1c8725..1c7fd05ce0280 100644
---- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
-@@ -120,6 +120,7 @@
-
- /* ELBI registers */
- #define ELBI_SYS_STTS 0x08
-+#define ELBI_CS2_ENABLE 0xa4
-
- /* DBI registers */
- #define DBI_CON_STATUS 0x44
-@@ -252,6 +253,21 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
- disable_irq(pcie_ep->perst_irq);
- }
-
-+static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
-+ u32 reg, size_t size, u32 val)
-+{
-+ struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
-+ int ret;
-+
-+ writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE);
-+
-+ ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
-+ if (ret)
-+ dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);
-+
-+ writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE);
-+}
-+
- static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
- {
- int ret;
-@@ -446,6 +462,7 @@ static const struct dw_pcie_ops pci_ops = {
- .link_up = qcom_pcie_dw_link_up,
- .start_link = qcom_pcie_dw_start_link,
- .stop_link = qcom_pcie_dw_stop_link,
-+ .write_dbi2 = qcom_pcie_dw_write_dbi2,
- };
-
- static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
---
-2.42.0
-