drm/xe/xe3p_lpg: Add Wa_16029437861

Wa_16029437861 requires disabling COAMA atomics by setting bit 22
(SQ_DISABLE_COAMA) of L3SQCREG2 (0xb104) for Xe3p_LPG graphics
version 35.10 stepping A0..B0. This bit is already set by the existing
Wa_14026144927 entry, so add the new WA ID to the same implementation.

Signed-off-by: Varun Gupta <varun.gupta@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patch.msgid.link/20260317040447.1792687-1-varun.gupta@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index d2fc1f50c508a464f935ab91931846c1a88469bc..1d77f5b6401f39e1a88c485b08d70791a9d5bc52 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -292,7 +292,7 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
                             DIS_ATS_WRONLY_PG))
        },
-       { XE_RTP_NAME("14026144927"),
+       { XE_RTP_NAME("14026144927, 16029437861"),
          XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
          XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
                             L3_SQ_DISABLE_COAMA))