RISC-V: KVM: Add support for Raw event v2

SBI v3.0 introduced a new raw event type v2 for wider mhpmeventX
programming. Add the support in kvm for that.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-3-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index 78ac3216a54ddbb2189b65ef1c88777e3aaa8d94..15d71a7b75ba6369b58ca28f1991ec05f46cd141 100644 (file)
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -60,6 +60,7 @@ static u32 kvm_pmu_get_perf_event_type(unsigned long eidx)
                type = PERF_TYPE_HW_CACHE;
                break;
        case SBI_PMU_EVENT_TYPE_RAW:
+       case SBI_PMU_EVENT_TYPE_RAW_V2:
        case SBI_PMU_EVENT_TYPE_FW:
                type = PERF_TYPE_RAW;
                break;
@@ -128,6 +129,9 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data)
        case SBI_PMU_EVENT_TYPE_RAW:
                config = evt_data & RISCV_PMU_RAW_EVENT_MASK;
                break;
+       case SBI_PMU_EVENT_TYPE_RAW_V2:
+               config = evt_data & RISCV_PMU_RAW_EVENT_V2_MASK;
+               break;
        case SBI_PMU_EVENT_TYPE_FW:
                if (ecode < SBI_PMU_FW_MAX)
                        config = (1ULL << 63) | ecode;