#define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_AHCI
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_EP_H */
#include <configs/xilinx_zynqmp.h>
/* Undef unneeded configs */
-#undef CONFIG_SYS_SDRAM_BASE
-#undef CONFIG_SYS_SDRAM_SIZE
#undef CONFIG_OF_LIBFDT
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOARD_LATE_INIT
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x80000000
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x80000000
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */