]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
zynqmp: Setup correct memory size for ep108
authorMichal Simek <michal.simek@xilinx.com>
Mon, 5 Oct 2015 09:02:33 +0000 (11:02 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 5 Oct 2015 09:13:33 +0000 (11:13 +0200)
Move memory configuration to board configuration file to ensure memory
setup for every particular board.
Support 2GB ram for dc1 and dc2. Patch for extending it to 4GB will be
added when it is properly tested.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
include/configs/xilinx_zynqmp.h
include/configs/xilinx_zynqmp_ep.h
include/configs/xilinx_zynqmp_mini.h
include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h

index 5db6f44984fbd44293e8a49b99970bf0f0abab41..8482547342d2a5deb559a79b066ee28718948c76 100644 (file)
 #define GICD_BASE      0xF9010000
 #define GICC_BASE      0xF9020000
 
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_SDRAM_BASE          0
-#define CONFIG_SYS_SDRAM_SIZE          0x40000000
-
 #define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END         CONFIG_SYS_SDRAM_SIZE
 
index 27a8d4fe218e71bf3aed88eb553cc04c1586a604..b00b83c7055c4a4085b2cf0459f10d2547f3f899 100644 (file)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_AHCI
 
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_SYS_SDRAM_SIZE          0x40000000
+
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_EP_H */
index 3b11758fbe262f668a26b6d89c1895b96f8b1f18..730ea67858ba654c61a6c1dcbb13a4eafe0df173 100644 (file)
@@ -22,8 +22,6 @@
 #include <configs/xilinx_zynqmp.h>
 
 /* Undef unneeded configs */
-#undef CONFIG_SYS_SDRAM_BASE
-#undef CONFIG_SYS_SDRAM_SIZE
 #undef CONFIG_OF_LIBFDT
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOARD_LATE_INIT
index 3138c311e39ae4b6a1d6a0d7cf3217307f91b009..ecc6dc0c57968d9dc6244c58c593917d15c75920 100644 (file)
 
 #define CONFIG_IDENT_STRING    " Xilinx ZynqMP ZC1751 xm015 dc1"
 
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_SYS_SDRAM_SIZE          0x80000000
+
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
index a001706fe4a5813e05eea725653b12914629fa2f..ec8411291d2e8d1c0fca206c97dfa19e059e2f0e 100644 (file)
 
 #define CONFIG_IDENT_STRING    " Xilinx ZynqMP ZC1751 xm016 dc2"
 
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_SYS_SDRAM_SIZE          0x80000000
+
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */