arm64: dts: ti: k3-j721s2-main: Add DSI & DSI PHY

Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is
Cadence DSI and the PHY is a Cadence DPHY with TI wrapper.

Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250716060114.52122-4-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 62f45377a2c9e6f0d8192de28e382f326152330d..c31d7f3eab28951a6b503dccc11d8c2b3637758f 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1795,6 +1795,45 @@
                status = "disabled";
        };
 
+       dphy_tx0: phy@4480000 {
+               compatible = "ti,j721e-dphy";
+               reg = <0x00 0x04480000 0x00 0x00001000>;
+               clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
+               clock-names = "psm", "pll_ref";
+               #phy-cells = <0>;
+               power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 363 14>;
+               assigned-clock-parents = <&k3_clks 363 15>;
+               assigned-clock-rates = <19200000>;
+               status = "disabled";
+       };
+
+       dsi0: dsi@4800000 {
+               compatible = "ti,j721e-dsi";
+               reg = <0x00 0x04800000 0x00 0x00100000>,
+                     <0x00 0x04710000 0x00 0x00000100>;
+               clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
+               clock-names = "dsi_p_clk", "dsi_sys_clk";
+               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+               interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+               phys = <&dphy_tx0>;
+               phy-names = "dphy";
+               status = "disabled";
+
+               dsi0_ports: ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        dss: dss@4a00000 {
                compatible = "ti,j721e-dss";
                reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */