clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes

Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3.
Using the wrong register leads to incorrect parent selection and rates.

Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-1-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 8d3f193d2b4d4c2146d9b8b57d76605b88dc9bbb..12e98bf5005ae2dc32da0da684a15133d64ed305 100644 (file)
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -239,12 +239,19 @@ static const unsigned long top_clk_regs[] __initconst = {
        PLL_LOCKTIME_PLL_SHARED2,
        PLL_LOCKTIME_PLL_SHARED3,
        PLL_LOCKTIME_PLL_SHARED4,
+       PLL_CON0_PLL_G3D,
        PLL_CON3_PLL_G3D,
+       PLL_CON0_PLL_MMC,
        PLL_CON3_PLL_MMC,
+       PLL_CON0_PLL_SHARED0,
        PLL_CON3_PLL_SHARED0,
+       PLL_CON0_PLL_SHARED1,
        PLL_CON3_PLL_SHARED1,
+       PLL_CON0_PLL_SHARED2,
        PLL_CON3_PLL_SHARED2,
+       PLL_CON0_PLL_SHARED3,
        PLL_CON3_PLL_SHARED3,
+       PLL_CON0_PLL_SHARED4,
        PLL_CON3_PLL_SHARED4,
        CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
        CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
@@ -689,13 +696,13 @@ PNAME(mout_cmu_vra_bus_p)         = { "dout_cmu_shared0_div3",
 
 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
        MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
-           PLL_CON3_PLL_SHARED0, 4, 1),
+           PLL_CON0_PLL_SHARED0, 4, 1),
        MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
-           PLL_CON3_PLL_SHARED1, 4, 1),
+           PLL_CON0_PLL_SHARED1, 4, 1),
        MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
-           PLL_CON3_PLL_SHARED2, 4, 1),
+           PLL_CON0_PLL_SHARED2, 4, 1),
        MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
-           PLL_CON3_PLL_SHARED3, 4, 1),
+           PLL_CON0_PLL_SHARED3, 4, 1),
        MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
            PLL_CON0_PLL_SHARED4, 4, 1),
        MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,