arm64: dts: qcom: sm8750: Add PCIe PHY and controller node

Add PCIe controller and PHY nodes which supports data rates of 8GT/s
and x2 lane.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250826-pakala-v3-2-721627bd5bb0@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 79ca262f58115ccc4b0bd91d4efa75715e2b7397..a82d9867c7cb67749f04bca671195590e71400f4 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -631,7 +631,7 @@
                        clocks = <&bi_tcxo_div2>,
                                 <0>,
                                 <&sleep_clk>,
-                                <0>,
+                                <&pcie0_phy>,
                                 <0>,
                                 <0>,
                                 <0>,
@@ -3304,6 +3304,184 @@
                        };
                };
 
+               pcie0: pcie@1c00000 {
+                       device_type = "pci";
+                       compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
+                       reg = <0x0 0x01c00000 0x0 0x3000>,
+                             <0x0 0x40000000 0x0 0xf1d>,
+                             <0x0 0x40000f20 0x0 0xa8>,
+                             <0x0 0x40001000 0x0 0x1000>,
+                             <0x0 0x40100000 0x0 0x100000>,
+                             <0x0 0x01C03000 0x0 0x1000>;
+                       reg-names = "parf",
+                                   "dbi",
+                                   "elbi",
+                                   "atu",
+                                   "config",
+                                   "mhi";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
+                                <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
+                       bus-range = <0x00 0xff>;
+
+                       dma-coherent;
+
+                       linux,pci-domain = <0>;
+
+                       msi-map = <0x0 &gic_its 0x1400 0x1>,
+                                 <0x100 &gic_its 0x1401 0x1>;
+                       msi-map-mask = <0xff00>;
+
+                       num-lanes = <2>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+                                <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+                       clock-names = "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "ddrss_sf_tbu",
+                                     "noc_aggr",
+                                     "cnoc_sf_axi";
+
+                       interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+                                        &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "pcie-mem",
+                                            "cpu-pcie";
+
+                       iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
+                                   <0x100 &apps_smmu 0x1401 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+                       operating-points-v2 = <&pcie0_opp_table>;
+
+                       status = "disabled";
+
+                       pcie0_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               /* GEN 1 x1 */
+                               opp-2500000 {
+                                       opp-hz = /bits/ 64 <2500000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <250000 1>;
+                               };
+
+                               /* GEN 1 x2 and GEN 2 x1 */
+                               opp-5000000 {
+                                       opp-hz = /bits/ 64 <5000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <500000 1>;
+                               };
+
+                               /* GEN 2 x2 */
+                               opp-10000000 {
+                                       opp-hz = /bits/ 64 <10000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <1000000 1>;
+                               };
+
+                               /* GEN 3 x1 */
+                               opp-8000000 {
+                                       opp-hz = /bits/ 64 <8000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <984500 1>;
+                               };
+
+                               /* GEN 3 x2 */
+                               opp-16000000 {
+                                       opp-hz = /bits/ 64 <16000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <1969000 1>;
+                               };
+
+                       };
+
+                       pcieport0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                               phys = <&pcie0_phy>;
+                       };
+               };
+
+               pcie0_phy: phy@1c06000 {
+                       compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
+                       reg = <0 0x01c06000 0 0x2000>;
+
+                       clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+                                <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "rchng",
+                                     "pipe";
+
+                       assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+                       reset-names = "phy";
+
+                       power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie0_pipe_clk";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
                ufs_mem_phy: phy@1d80000 {
                        compatible = "qcom,sm8750-qmp-ufs-phy";
                        reg = <0x0 0x01d80000 0x0 0x2000>;