PCI: mediatek-gen3: Integrate new pwrctrl API

With the new PCI pwrctrl API and PCI slot binding and power drivers, we now
have a way to describe and power up WiFi/BT adapters connected through a
PCIe or M.2 slot, or populated onto the mainboard itself.  The latter case
has the adapter layout or design copied verbatim, replacing the slot with
direct connections.

Integrate the PCI pwrctrl API into the PCIe driver, so that power is
properly enabled before PCIe link training is done, allowing the card to
successfully be detected.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260324052002.4072430-8-wenst@chromium.org

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 5aaed8ac6e443b17e717281ac8e40bbe5344974c..686349e09cd3cd4baeb66f67268e78f9e363f23d 100644 (file)
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -222,6 +222,7 @@ config PCIE_MEDIATEK_GEN3
        depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
        depends on PCI_MSI
        select IRQ_MSI_LIB
+       select PCI_PWRCTRL_GENERIC
        help
          Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
          This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index aa14b021834f4d60d2f2d51bdbf86a155a4bfe2f..a94fdbaf47fe9ff15913c9b266043da50d446668 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -22,6 +22,7 @@
 #include <linux/of_device.h>
 #include <linux/of_pci.h>
 #include <linux/pci.h>
+#include <linux/pci-pwrctrl.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
@@ -405,6 +406,7 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
 
 static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)
 {
+       int err;
        u32 val;
 
        /*
@@ -420,15 +422,23 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)
                val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
                       PCIE_PE_RSTB;
                writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+       }
+
+       err = pci_pwrctrl_power_on_devices(pcie->dev);
+       if (err) {
+               dev_err(pcie->dev, "Failed to power on devices: %pe\n", ERR_PTR(err));
+               return err;
+       }
 
-               /*
-                * Described in PCIe CEM specification revision 6.0.
-                *
-                * The deassertion of PERST# should be delayed 100ms (TPVPERL)
-                * for the power and clock to become stable.
-                */
-               msleep(PCIE_T_PVPERL_MS);
+       /*
+        * Described in PCIe CEM specification revision 6.0.
+        *
+        * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+        * for the power and clock to become stable.
+        */
+       msleep(PCIE_T_PVPERL_MS);
 
+       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
                /* De-assert reset signals */
                val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
                         PCIE_PE_RSTB);
@@ -448,6 +458,8 @@ static void mtk_pcie_devices_power_down(struct mtk_gen3_pcie *pcie)
                val |= PCIE_PE_RSTB;
                writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
        }
+
+       pci_pwrctrl_power_off_devices(pcie->dev);
 }
 
 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
@@ -1208,9 +1220,15 @@ static int mtk_pcie_probe(struct platform_device *pdev)
        if (err)
                return dev_err_probe(dev, err, "Failed to setup IRQ domains\n");
 
+       err = pci_pwrctrl_create_devices(pcie->dev);
+       if (err) {
+               goto err_tear_down_irq;
+               dev_err_probe(dev, err, "failed to create pwrctrl devices\n");
+       }
+
        err = mtk_pcie_setup(pcie);
        if (err)
-               goto err_tear_down_irq;
+               goto err_destroy_pwrctrl;
 
        host->ops = &mtk_pcie_ops;
        host->sysdata = pcie;
@@ -1224,6 +1242,9 @@ static int mtk_pcie_probe(struct platform_device *pdev)
 err_power_down_pcie:
        mtk_pcie_devices_power_down(pcie);
        mtk_pcie_power_down(pcie);
+err_destroy_pwrctrl:
+       if (err != -EPROBE_DEFER)
+               pci_pwrctrl_destroy_devices(pcie->dev);
 err_tear_down_irq:
        mtk_pcie_irq_teardown(pcie);
        return err;
@@ -1239,7 +1260,9 @@ static void mtk_pcie_remove(struct platform_device *pdev)
        pci_remove_root_bus(host->bus);
        pci_unlock_rescan_remove();
 
+       pci_pwrctrl_power_off_devices(pcie->dev);
        mtk_pcie_power_down(pcie);
+       pci_pwrctrl_destroy_devices(pcie->dev);
        mtk_pcie_irq_teardown(pcie);
 }