+++ /dev/null
-From 68e61f6fd65610e73b17882f86fedfd784d99229 Mon Sep 17 00:00:00 2001
-From: Sean Christopherson <seanjc@google.com>
-Date: Fri, 11 Jul 2025 10:27:46 -0700
-Subject: KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2
-
-From: Sean Christopherson <seanjc@google.com>
-
-commit 68e61f6fd65610e73b17882f86fedfd784d99229 upstream.
-
-Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
-guest, as the MSR is supposed to exist in all AMD v2 PMUs.
-
-Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
-Cc: stable@vger.kernel.org
-Cc: Sandipan Das <sandipan.das@amd.com>
-Link: https://lore.kernel.org/r/20250711172746.1579423-1-seanjc@google.com
-Signed-off-by: Sean Christopherson <seanjc@google.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/msr-index.h | 1 +
- arch/x86/kvm/pmu.c | 5 +++++
- arch/x86/kvm/svm/pmu.c | 1 +
- arch/x86/kvm/x86.c | 2 ++
- 4 files changed, 9 insertions(+)
-
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -661,6 +661,7 @@
- #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
- #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
- #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
-+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET 0xc0000303
-
- /* AMD Last Branch Record MSRs */
- #define MSR_AMD64_LBR_SELECT 0xc000010e
---- a/arch/x86/kvm/pmu.c
-+++ b/arch/x86/kvm/pmu.c
-@@ -588,6 +588,7 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcp
- msr_info->data = pmu->global_ctrl;
- break;
- case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
-+ case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
- case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
- msr_info->data = 0;
- break;
-@@ -649,6 +650,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcp
- if (!msr_info->host_initiated)
- pmu->global_status &= ~data;
- break;
-+ case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
-+ if (!msr_info->host_initiated)
-+ pmu->global_status |= data & ~pmu->global_status_rsvd;
-+ break;
- default:
- kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
- return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info);
---- a/arch/x86/kvm/svm/pmu.c
-+++ b/arch/x86/kvm/svm/pmu.c
-@@ -117,6 +117,7 @@ static bool amd_is_valid_msr(struct kvm_
- case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
- case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
- case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
-+ case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
- return pmu->version > 1;
- default:
- if (msr > MSR_F15H_PERF_CTR5 &&
---- a/arch/x86/kvm/x86.c
-+++ b/arch/x86/kvm/x86.c
-@@ -1495,6 +1495,7 @@ static const u32 msrs_to_save_pmu[] = {
- MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
- MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
- MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
-+ MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET,
- };
-
- static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
-@@ -7194,6 +7195,7 @@ static void kvm_probe_msr_to_save(u32 ms
- case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
- case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
- case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
-+ case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
- if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
- return;
- break;