RISC-V: Update .SAT_TRUNC dump check due to middle-end change

Due to recent middle-end change, update the .SAT_TRUNC expand dump
check from 2 to 4.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Adjust
	asm check times from 2 to 4.

Signed-off-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 7f047f3f6a2b40b537f8cf7a9690af13426db109..ae3e44cd57e80b8a6aee741ba343c21b5bc3f3fa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -16,4 +16,4 @@
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */