sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.

	* config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.

From-SVN: r210033

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6464565bca202a284db7fa1d309ed383436c8105..e6b50130b0f28cac54a2da68db6e67c5953356e0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-05-03  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       * config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.
+
 2014-05-03  Oleg Endo  <olegendo@gcc.gnu.org>
 
        * config/sh/sh.h (ROUND_ADVANCE): Delete macro.

diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 0b6bd1bc94a69c0c13093c40fefc3ba81cb50055..00ee0edffdaa210d7c74ea316fa7718387ccd8c1 100644 (file)
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -267,9 +267,25 @@ extern int code_for_indirect_jump_scratch;
 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
 #endif
 
+/* Define which ISA type to pass to the assembler.
+   For SH4 we pass SH4A to allow using some instructions that are available
+   on some SH4 variants, but officially are part of the SH4A ISA.  */
 #define SH_ASM_SPEC \
  "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
+%{m1:--isa=sh} \
+%{m2:--isa=sh2} \
+%{m2e:--isa=sh2e} \
+%{m3:--isa=sh3} \
+%{m3e:--isa=sh3e} \
+%{m4:--isa=sh4a} \
+%{m4-single:--isa=sh4a} \
+%{m4-single-only:--isa=sh4a} \
+%{m4-nofpu:--isa=sh4a-nofpu} \
+%{m4a:--isa=sh4a} \
+%{m4a-single:--isa=sh4a} \
+%{m4a-single-only:--isa=sh4a} \
+%{m4a-nofpu:--isa=sh4a-nofpu} \
 %{m2a:--isa=sh2a} \
 %{m2a-single:--isa=sh2a} \
 %{m2a-single-only:--isa=sh2a} \