drm/amdgpu/vce1: Clean up register definitions

The sid.h header contained some VCE1 register definitions, but
they were using byte offsets (probably copied from the old radeon
driver). Move all of these to the proper VCE1 headers and ensure
they are in dword offsets.

Also add the register definitions that we need for the
firmware validation mechanism in VCE1.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index cbd4f8951cfae03a0c3d09284b067af84b5d740d..561462a8332e4b4a583bb401849f3f04664830dc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -582,45 +582,6 @@
 #define        DMA_PACKET_NOP                                    0xf
 
 /* VCE */
-#define VCE_STATUS                                     0x20004
-#define VCE_VCPU_CNTL                                  0x20014
-#define                VCE_CLK_EN                              (1 << 0)
-#define VCE_VCPU_CACHE_OFFSET0                         0x20024
-#define VCE_VCPU_CACHE_SIZE0                           0x20028
-#define VCE_VCPU_CACHE_OFFSET1                         0x2002c
-#define VCE_VCPU_CACHE_SIZE1                           0x20030
-#define VCE_VCPU_CACHE_OFFSET2                         0x20034
-#define VCE_VCPU_CACHE_SIZE2                           0x20038
-#define VCE_SOFT_RESET                                 0x20120
-#define        VCE_ECPU_SOFT_RESET                     (1 << 0)
-#define        VCE_FME_SOFT_RESET                      (1 << 2)
-#define VCE_RB_BASE_LO2                                        0x2016c
-#define VCE_RB_BASE_HI2                                        0x20170
-#define VCE_RB_SIZE2                                   0x20174
-#define VCE_RB_RPTR2                                   0x20178
-#define VCE_RB_WPTR2                                   0x2017c
-#define VCE_RB_BASE_LO                                 0x20180
-#define VCE_RB_BASE_HI                                 0x20184
-#define VCE_RB_SIZE                                    0x20188
-#define VCE_RB_RPTR                                    0x2018c
-#define VCE_RB_WPTR                                    0x20190
-#define VCE_CLOCK_GATING_A                             0x202f8
-#define VCE_CLOCK_GATING_B                             0x202fc
-#define VCE_UENC_CLOCK_GATING                          0x205bc
-#define VCE_UENC_REG_CLOCK_GATING                      0x205c0
-#define VCE_FW_REG_STATUS                              0x20e10
-#      define VCE_FW_REG_STATUS_BUSY                   (1 << 0)
-#      define VCE_FW_REG_STATUS_PASS                   (1 << 3)
-#      define VCE_FW_REG_STATUS_DONE                   (1 << 11)
-#define VCE_LMI_FW_START_KEYSEL                                0x20e18
-#define VCE_LMI_FW_PERIODIC_CTRL                       0x20e20
-#define VCE_LMI_CTRL2                                  0x20e74
-#define VCE_LMI_CTRL                                   0x20e98
-#define VCE_LMI_VM_CTRL                                        0x20ea0
-#define VCE_LMI_SWAP_CNTL                              0x20eb4
-#define VCE_LMI_SWAP_CNTL1                             0x20eb8
-#define VCE_LMI_CACHE_CTRL                             0x20ef4
-
 #define VCE_CMD_NO_OP                                  0x00000000
 #define VCE_CMD_END                                    0x00000001
 #define VCE_CMD_IB                                     0x00000002
@@ -629,7 +590,6 @@
 #define VCE_CMD_IB_AUTO                                        0x00000005
 #define VCE_CMD_SEMAPHORE                              0x00000006
 
-
 //#dce stupp
 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
 #define CRTC0_REGISTER_OFFSET                 (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
index 2176548e9203b610a9d84ad025044b417992daab..9778822dd2a07911587eacb12b187f95b2bd9017 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
@@ -60,5 +60,10 @@
 #define mmVCE_VCPU_CACHE_SIZE1 0x800C
 #define mmVCE_VCPU_CACHE_SIZE2 0x800E
 #define mmVCE_VCPU_CNTL 0x8005
+#define mmVCE_VCPU_SCRATCH7 0x8037
+#define mmVCE_FW_REG_STATUS 0x8384
+#define mmVCE_LMI_FW_PERIODIC_CTRL 0x8388
+#define mmVCE_LMI_FW_START_KEYSEL 0x8386
+
 
 #endif

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
index ea5b26b11cb14b0c88c98cabd862f71d4d7334e0..1f82d6f5abdec608c47e11651f1e19a62d8bc4f6 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
@@ -61,6 +61,8 @@
 #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004
 #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
 #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000
+#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L
+#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x00000002
 #define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
 #define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000
 #define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
@@ -95,5 +97,13 @@
 #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000
 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012
+#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK 0x00010000
+#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_SHIFT 0x00000010
+#define VCE_FW_REG_STATUS__BUSY_MASK 0x0000001
+#define VCE_FW_REG_STATUS__BUSY__SHIFT 0x0000001
+#define VCE_FW_REG_STATUS__PASS_MASK 0x0000008
+#define VCE_FW_REG_STATUS__PASS__SHIFT 0x0000003
+#define VCE_FW_REG_STATUS__DONE_MASK 0x0000800
+#define VCE_FW_REG_STATUS__DONE__SHIFT 0x000000b
 
 #endif