net: stmmac: enable RPS and RBU interrupts

Enable receive process stopped and receive buffer unavailable
interrupts, so that the statistic counters can be updated.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1wBBaR-0000000GZHR-1dbM@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index af6580332d49f43d719d19fa9a939fd6df303f4e..43b036d4e95bdde882ab79e57e7cf6e0b9cb2e39 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -99,6 +99,8 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
 #define DMA_CHAN_INTR_ENA_NIE_4_10     BIT(15)
 #define DMA_CHAN_INTR_ENA_AIE_4_10     BIT(14)
 #define DMA_CHAN_INTR_ENA_FBE          BIT(12)
+#define DMA_CHAN_INTR_ENA_RPS          BIT(8)
+#define DMA_CHAN_INTR_ENA_RBU          BIT(7)
 #define DMA_CHAN_INTR_ENA_RIE          BIT(6)
 #define DMA_CHAN_INTR_ENA_TIE          BIT(0)
 
@@ -107,6 +109,8 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
                                         DMA_CHAN_INTR_ENA_TIE)
 
 #define DMA_CHAN_INTR_ABNORMAL         (DMA_CHAN_INTR_ENA_AIE | \
+                                        DMA_CHAN_INTR_ENA_RPS | \
+                                        DMA_CHAN_INTR_ENA_RBU | \
                                         DMA_CHAN_INTR_ENA_FBE)
 /* DMA default interrupt mask for 4.00 */
 #define DMA_CHAN_INTR_DEFAULT_MASK     (DMA_CHAN_INTR_NORMAL | \
@@ -117,6 +121,8 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
                                         DMA_CHAN_INTR_ENA_TIE)
 
 #define DMA_CHAN_INTR_ABNORMAL_4_10    (DMA_CHAN_INTR_ENA_AIE_4_10 | \
+                                        DMA_CHAN_INTR_ENA_RPS | \
+                                        DMA_CHAN_INTR_ENA_RBU | \
                                         DMA_CHAN_INTR_ENA_FBE)
 /* DMA default interrupt mask for 4.10a */
 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10        (DMA_CHAN_INTR_NORMAL_4_10 | \