Emitted Div, fixed mul... that's the lot for return0.orig\!

git-svn-id: svn://svn.valgrind.org/vex/trunk@914

diff --git a/VEX/priv/host-ppc32/hdefs.c b/VEX/priv/host-ppc32/hdefs.c
index 093bdc4f8af0a33749a510bb8df7d8f58bd4d413..6ede6bf964cb7ee7960b9692ba3c41ab6bd3e5d5 100644 (file)
--- a/VEX/priv/host-ppc32/hdefs.c
+++ b/VEX/priv/host-ppc32/hdefs.c
@@ -2064,24 +2064,21 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i )
       goto done;
    }
 
-//..    case Xin_Div:
-//..       subopc = i->Xin.Div.syned ? 7 : 6;
-//..       if (i->Xin.Div.ssz == Xss_32) {
-//..          *p++ = 0xF7;
-//..          switch (i->Xin.Div.src->tag)  {
-//..             case Xrm_Mem:
-//..                p = doAMode_M(p, fake(subopc),
-//..                                 i->Xin.Div.src->Xrm.Mem.am);
-//..                goto done;
-//..             case Xrm_Reg:
-//..                p = doAMode_R(p, fake(subopc), 
-//..                                 i->Xin.Div.src->Xrm.Reg.reg);
-//..                goto done;
-//..             default:
-//..                goto bad;
-//..          }
-//..       }
-//..       break;
+   case Pin_Div: {
+      Bool syned  = i->Pin.MulL.syned;
+      UInt r_dst  = iregNo(i->Pin.Div.dst);
+      UInt r_src1 = iregNo(i->Pin.Div.src1);
+      UInt r_src2 = iregNo(i->Pin.Div.src2);
+
+      if (syned == True) {
+         // divw r_dst,r_src1,r_src2
+         p = mkFormXO(p, 31, r_dst, r_src1, r_src2, 0, 491, 0);
+      } else {
+         // divwu r_dst,r_src1,r_src2
+         p = mkFormXO(p, 31, r_dst, r_src1, r_src2, 0, 459, 0);
+      }
+      goto done;
+   }
 
 //..    case Xin_Sh3232:
 //..       vassert(i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHR);

diff --git a/VEX/priv/host-ppc32/isel.c b/VEX/priv/host-ppc32/isel.c
index 04d5b2f949f5c8468a86be94e60bd16b6738a4ff..dafc111d2730c0bd673cc8bfda4717c459f40490 100644 (file)
--- a/VEX/priv/host-ppc32/isel.c
+++ b/VEX/priv/host-ppc32/isel.c
@@ -106,10 +106,12 @@ static IRExpr* unop ( IROp op, IRExpr* a )
    return IRExpr_Unop(op, a);
 }
 
+#if 0
 static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 )
 {
    return IRExpr_Binop(op, a1, a2);
 }
+#endif
 
 //.. static IRExpr* mkU64 ( ULong i )
 //.. {
@@ -1137,8 +1139,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
       }
       case Iop_64to32: {
 
-#if 1
-// CAB: This right? Need to figure out sign issues...
+#if 0
          /* 64to32(MullS32(expr,expr)) */
          {
             DECLARE_PATTERN(p_MullS32_then_64to32);
@@ -1153,10 +1154,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
                return dst;
             }
          }
-#endif
 
-#if 0
-// CAB: This right? Need to figure out sign issues...
          /* 64to32(MullU32(expr,expr)) */
          {
             DECLARE_PATTERN(p_MullU32_then_64to32);
@@ -1171,6 +1169,9 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
                return dst;
             }
          }
+
+         // CAB: Also: 64HIto32(MullU32(expr,expr))
+         // CAB: Also: 64HIto32(MullS32(expr,expr))
 #endif
 
          HReg rHi, rLo;
@@ -1792,7 +1793,9 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
          HReg     tHi   = newVRegI(env);
          Bool     syned = e->Iex.Binop.op == Iop_MullS32;
          HReg     src1  = iselIntExpr_R(env, e->Iex.Binop.arg1);
-         PPC32RI* src2  = mk_FitRI16(env, iselIntExpr_RI(env, e->Iex.Binop.arg2));
+         PPC32RI* ri    = iselIntExpr_RI(env, e->Iex.Binop.arg2);
+// CAB: could do better than this...
+         PPC32RI* src2  = PPC32RI_Reg( mk_RItoR(env, ri) );
          addInstr(env, PPC32Instr_MulL(syned, 0, tLo, src1, src2));
          addInstr(env, PPC32Instr_MulL(syned, 1, tHi, src1, src2));
          *rHi = tHi;