]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.15-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 30 Nov 2022 17:45:19 +0000 (18:45 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 30 Nov 2022 17:45:19 +0000 (18:45 +0100)
added patches:
drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch

queue-5.15/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch [new file with mode: 0644]
queue-5.15/series

diff --git a/queue-5.15/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch b/queue-5.15/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
new file mode 100644 (file)
index 0000000..ccf8546
--- /dev/null
@@ -0,0 +1,39 @@
+From 04aa64375f48a5d430b5550d9271f8428883e550 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <andrzej.hajda@intel.com>
+Date: Mon, 14 Nov 2022 11:38:24 +0100
+Subject: drm/i915: fix TLB invalidation for Gen12 video and compute engines
+
+From: Andrzej Hajda <andrzej.hajda@intel.com>
+
+commit 04aa64375f48a5d430b5550d9271f8428883e550 upstream.
+
+In case of Gen12 video and compute engines, TLB_INV registers are masked -
+to modify one bit, corresponding bit in upper half of the register must
+be enabled, otherwise nothing happens.
+
+CVE: CVE-2022-4139
+Suggested-by: Chris Wilson <chris.p.wilson@intel.com>
+Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
+Cc: stable@vger.kernel.org
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gt/intel_gt.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/i915/gt/intel_gt.c
++++ b/drivers/gpu/drm/i915/gt/intel_gt.c
+@@ -982,6 +982,11 @@ void intel_gt_invalidate_tlbs(struct int
+               if (!i915_mmio_reg_offset(rb.reg))
+                       continue;
++              if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
++                  engine->class == VIDEO_ENHANCEMENT_CLASS ||
++                  engine->class == COMPUTE_CLASS))
++                      rb.bit = _MASKED_BIT_ENABLE(rb.bit);
++
+               intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+       }
index 78084c6c93d1a4aee1c51df72143b0c9b2543aad..ed4608aad3d2022dbb47c0d563509611d79d1eb1 100644 (file)
@@ -203,3 +203,4 @@ drm-amd-dc-dce120-fix-audio-register-mapping-stop-triggering-kasan.patch
 drm-amd-display-no-display-after-resume-from-wb-cb.patch
 drm-amdgpu-enable-aldebaran-devices-to-report-cu-occupancy.patch
 drm-amdgpu-always-register-an-mmu-notifier-for-userptr.patch
+drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch