Xilinx: ARM: BSP: remove DDR init for zc770

This should not be needed as FSBL will be doing it. The DDR init
was causing a hang and was not needed anyway.

diff --git a/board/xilinx/dfe/lowlevel_init.S b/board/xilinx/dfe/lowlevel_init.S
index 72c245bf95df2f1c732ad2b2ffc4c6e958478591..2094abd02c49b4b8a7f2a88d4e3f8eceedc262df 100755 (executable)
--- a/board/xilinx/dfe/lowlevel_init.S
+++ b/board/xilinx/dfe/lowlevel_init.S
@@ -65,12 +65,16 @@ lowlevel_init:
        ldr r2, =0x767B
        str r2, [r1]
 
+#ifdef CONFIG_EP107
+       # this should not be needed after EP107
+
        # Do nothing if DDR already running
        ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0)
        ldr r2, [r1]
        ldr r3, =0x201
        cmp r2, r3
        bne doit
+#endif
 
        mov pc, lr