aarch64: Use VNx16BI for svrev_b* [PR121294]

The previous patch for PR121294 handled svtrn1/2, svuzp1/2, and svzip1/2.
This one extends it to handle svrev intrinsics, where the same kind of
wrong code can be generated.

gcc/
	PR target/121294
	* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
	* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle)
	(*aarch64_sve_rev<mode>_acle): New patterns.
	* config/aarch64/aarch64-sve-builtins-base.cc
	(svrev_impl::expand): Use the new patterns for boolean svrev.

gcc/testsuite/
	PR target/121294
	* gcc.target/aarch64/sve/acle/general/rev_2.c: New test.

(cherry picked from commit 701193a7a6d3f3f345bf336e7ebc7d6fa1e0c5ac)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 85585c5941c8662b3caee5f3658eb615a68c0c6e..dc5f41e01ccb358944dccc57a3cb1044f29f7471 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -2032,7 +2032,10 @@ public:
   rtx
   expand (function_expander &e) const override
   {
-    return e.use_exact_insn (code_for_aarch64_sve_rev (e.vector_mode (0)));
+    auto mode = e.vector_mode (0);
+    return e.use_exact_insn (e.type_suffix (0).bool_p
+                            ? code_for_aarch64_sve_rev_acle (mode)
+                            : code_for_aarch64_sve_rev (mode));
   }
 };
 

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 1187746e5946fdf10b918d6dc23b20429271b163..9cb09187c620bb04ab372b132f0ff294fb8887de 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -8834,7 +8834,30 @@
        (unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")]
                         UNSPEC_REV))]
   "TARGET_SVE"
-  "rev\t%0.<Vetype>, %1.<Vetype>")
+  "rev\t%0.<Vetype>, %1.<Vetype>"
+)
+
+(define_expand "@aarch64_sve_rev<mode>_acle"
+  [(set (match_operand:VNx16BI 0 "register_operand")
+       (unspec:VNx16BI
+         [(match_operand:VNx16BI 1 "register_operand")
+          (match_dup:PRED_ALL 2)]
+         UNSPEC_REV_PRED))]
+  "TARGET_SVE"
+  {
+    operands[2] = CONST0_RTX (<MODE>mode);
+  }
+)
+
+(define_insn "*aarch64_sve_rev<mode>_acle"
+  [(set (match_operand:VNx16BI 0 "register_operand" "=Upa")
+       (unspec:VNx16BI
+         [(match_operand:VNx16BI 1 "register_operand" "Upa")
+          (match_operand:PRED_ALL 2 "aarch64_simd_imm_zero")]
+         UNSPEC_REV_PRED))]
+  "TARGET_SVE"
+  "rev\t%0.<Vetype>, %1.<Vetype>"
+)
 
 ;; -------------------------------------------------------------------------
 ;; ---- [PRED] Special-purpose binary permutes

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ff74e7dcef65b38e691d173a6744d072d0c48843..d9798edce505051482ecb5321c00a9c3e9f4b675 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -203,6 +203,7 @@
     UNSPEC_PACIBSP
     UNSPEC_PRLG_STK
     UNSPEC_REV
+    UNSPEC_REV_PRED
     UNSPEC_RBIT
     UNSPEC_SABAL
     UNSPEC_SABAL2

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c
new file mode 100644 (file)
index 0000000..3dc4eb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include <arm_sve.h>
+
+svbool_t test1()
+{
+  return svrev_b16 (svptrue_b16 ());
+}
+
+svbool_t test2()
+{
+  return svrev_b32 (svptrue_b32 ());
+}
+
+svbool_t test3()
+{
+  return svrev_b64 (svptrue_b64 ());
+}
+
+/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h} } } */
+/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s} } } */
+/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d} } } */
+/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.b} } } */
+/* { dg-final { scan-assembler {\trev\tp0\.h} } } */
+/* { dg-final { scan-assembler {\trev\tp0\.s} } } */
+/* { dg-final { scan-assembler {\trev\tp0\.d} } } */