zynq_qspips:Break infinite loop after 1000 status read after trying to set qbit

Currently, u-boot end up in infinite loop when the status reg of the SPI flash
is not 0 after it tries to set the quad bit. If quad bit setting fails, u-boot
hangs because of this infinite loop.

We introduce a counter. If the status register value is still not 0 after 1000
runs, it break the loop.

Signed-off-by: Wendy Liang <jliang@xilinx.com>

diff --git a/drivers/spi/zynq_qspips.c b/drivers/spi/zynq_qspips.c
index 689793a7c91c7c198d82a63508a913de5eb9c794..886c945de4aea4947fcecd3238a913af5b34f5a1 100644 (file)
--- a/drivers/spi/zynq_qspips.c
+++ b/drivers/spi/zynq_qspips.c
@@ -898,6 +898,7 @@ void spi_enable_quad_bit(struct spi_slave *spi)
        u8 rcr_cmd = 0x35;      /* RCR */
        u8 rdsr_cmd = 0x05;     /* RDSR */
        u8 wren_cmd = 0x06;     /* WREN */
+       int count = 0;
 
        ret = spi_flash_cmd(spi, rdid_cmd, &idcode, sizeof(idcode));
        if (ret) {
@@ -930,11 +931,12 @@ void spi_enable_quad_bit(struct spi_slave *spi)
                        xqspips_write_quad_bit((void *)XPSS_QSPI_BASEADDR);
 
                        /* Read RDSR */
+                       count = 0;
                        do {
                                ret = spi_flash_cmd_read(spi, &rdsr_cmd,
                                                sizeof(rdsr_cmd), &rcr_data,
                                                sizeof(rcr_data));
-                       } while ((ret == 0) && (rcr_data != 0));
+                       } while ((ret == 0) && (rcr_data != 0) && (count++<1000));
 
                        /* Read config register */
                        ret = spi_flash_cmd_read(spi, &rcr_cmd, sizeof(rcr_cmd),