--- /dev/null
+From 077b2da8c0660f9b58b5059b20ae75c2deb51b8a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 15:49:53 +0800
+Subject: ACPI: APEI: do not add task_work to kernel thread to avoid memory
+ leak
+
+From: Shuai Xue <xueshuai@linux.alibaba.com>
+
+[ Upstream commit 415fed694fe11395df56e05022d6e7cee1d39dd3 ]
+
+If an error is detected as a result of user-space process accessing a
+corrupt memory location, the CPU may take an abort. Then the platform
+firmware reports kernel via NMI like notifications, e.g. NOTIFY_SEA,
+NOTIFY_SOFTWARE_DELEGATED, etc.
+
+For NMI like notifications, commit 7f17b4a121d0 ("ACPI: APEI: Kick the
+memory_failure() queue for synchronous errors") keep track of whether
+memory_failure() work was queued, and make task_work pending to flush out
+the queue so that the work is processed before return to user-space.
+
+The code use init_mm to check whether the error occurs in user space:
+
+ if (current->mm != &init_mm)
+
+The condition is always true, becase _nobody_ ever has "init_mm" as a real
+VM any more.
+
+In addition to abort, errors can also be signaled as asynchronous
+exceptions, such as interrupt and SError. In such case, the interrupted
+current process could be any kind of thread. When a kernel thread is
+interrupted, the work ghes_kick_task_work deferred to task_work will never
+be processed because entry_handler returns to call ret_to_kernel() instead
+of ret_to_user(). Consequently, the estatus_node alloced from
+ghes_estatus_pool in ghes_in_nmi_queue_one_entry() will not be freed.
+After around 200 allocations in our platform, the ghes_estatus_pool will
+run of memory and ghes_in_nmi_queue_one_entry() returns ENOMEM. As a
+result, the event failed to be processed.
+
+ sdei: event 805 on CPU 113 failed with error: -2
+
+Finally, a lot of unhandled events may cause platform firmware to exceed
+some threshold and reboot.
+
+The condition should generally just do
+
+ if (current->mm)
+
+as described in active_mm.rst documentation.
+
+Then if an asynchronous error is detected when a kernel thread is running,
+(e.g. when detected by a background scrubber), do not add task_work to it
+as the original patch intends to do.
+
+Fixes: 7f17b4a121d0 ("ACPI: APEI: Kick the memory_failure() queue for synchronous errors")
+Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
+Reviewed-by: Tony Luck <tony.luck@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/apei/ghes.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
+index 06b0184fa912..d490670f8d55 100644
+--- a/drivers/acpi/apei/ghes.c
++++ b/drivers/acpi/apei/ghes.c
+@@ -985,7 +985,7 @@ static void ghes_proc_in_irq(struct irq_work *irq_work)
+ ghes_estatus_cache_add(generic, estatus);
+ }
+
+- if (task_work_pending && current->mm != &init_mm) {
++ if (task_work_pending && current->mm) {
+ estatus_node->task_work.func = ghes_kick_task_work;
+ estatus_node->task_work_cpu = smp_processor_id();
+ ret = task_work_add(current, &estatus_node->task_work,
+--
+2.35.1
+
--- /dev/null
+From 5ef815d3071a3d108568e33815efa441a9064659 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 14:34:12 +0200
+Subject: ACPI: tables: FPDT: Don't call acpi_os_map_memory() on invalid phys
+ address
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit 211391bf04b3c74e250c566eeff9cf808156c693 ]
+
+On a Packard Bell Dot SC (Intel Atom N2600 model) there is a FPDT table
+which contains invalid physical addresses, with high bits set which fall
+outside the range of the CPU-s supported physical address range.
+
+Calling acpi_os_map_memory() on such an invalid phys address leads to
+the below WARN_ON in ioremap triggering resulting in an oops/stacktrace.
+
+Add code to verify the physical address before calling acpi_os_map_memory()
+to fix / avoid the oops.
+
+[ 1.226900] ioremap: invalid physical address 3001000000000000
+[ 1.226949] ------------[ cut here ]------------
+[ 1.226962] WARNING: CPU: 1 PID: 1 at arch/x86/mm/ioremap.c:200 __ioremap_caller.cold+0x43/0x5f
+[ 1.226996] Modules linked in:
+[ 1.227016] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.0.0-rc3+ #490
+[ 1.227029] Hardware name: Packard Bell dot s/SJE01_CT, BIOS V1.10 07/23/2013
+[ 1.227038] RIP: 0010:__ioremap_caller.cold+0x43/0x5f
+[ 1.227054] Code: 96 00 00 e9 f8 af 24 ff 89 c6 48 c7 c7 d8 0c 84 99 e8 6a 96 00 00 e9 76 af 24 ff 48 89 fe 48 c7 c7 a8 0c 84 99 e8 56 96 00 00 <0f> 0b e9 60 af 24 ff 48 8b 34 24 48 c7 c7 40 0d 84 99 e8 3f 96 00
+[ 1.227067] RSP: 0000:ffffb18c40033d60 EFLAGS: 00010286
+[ 1.227084] RAX: 0000000000000032 RBX: 3001000000000000 RCX: 0000000000000000
+[ 1.227095] RDX: 0000000000000001 RSI: 00000000ffffdfff RDI: 00000000ffffffff
+[ 1.227105] RBP: 3001000000000000 R08: 0000000000000000 R09: ffffb18c40033c18
+[ 1.227115] R10: 0000000000000003 R11: ffffffff99d62fe8 R12: 0000000000000008
+[ 1.227124] R13: 0003001000000000 R14: 0000000000001000 R15: 3001000000000000
+[ 1.227135] FS: 0000000000000000(0000) GS:ffff913a3c080000(0000) knlGS:0000000000000000
+[ 1.227146] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[ 1.227156] CR2: 0000000000000000 CR3: 0000000018c26000 CR4: 00000000000006e0
+[ 1.227167] Call Trace:
+[ 1.227176] <TASK>
+[ 1.227185] ? acpi_os_map_iomem+0x1c9/0x1e0
+[ 1.227215] ? kmem_cache_alloc_trace+0x187/0x370
+[ 1.227254] acpi_os_map_iomem+0x1c9/0x1e0
+[ 1.227288] acpi_init_fpdt+0xa8/0x253
+[ 1.227308] ? acpi_debugfs_init+0x1f/0x1f
+[ 1.227339] do_one_initcall+0x5a/0x300
+[ 1.227406] ? rcu_read_lock_sched_held+0x3f/0x80
+[ 1.227442] kernel_init_freeable+0x28b/0x2cc
+[ 1.227512] ? rest_init+0x170/0x170
+[ 1.227538] kernel_init+0x16/0x140
+[ 1.227552] ret_from_fork+0x1f/0x30
+[ 1.227639] </TASK>
+[ 1.227647] irq event stamp: 186819
+[ 1.227656] hardirqs last enabled at (186825): [<ffffffff98184a6e>] __up_console_sem+0x5e/0x70
+[ 1.227672] hardirqs last disabled at (186830): [<ffffffff98184a53>] __up_console_sem+0x43/0x70
+[ 1.227686] softirqs last enabled at (186576): [<ffffffff980fbc9d>] __irq_exit_rcu+0xed/0x160
+[ 1.227701] softirqs last disabled at (186569): [<ffffffff980fbc9d>] __irq_exit_rcu+0xed/0x160
+[ 1.227715] ---[ end trace 0000000000000000 ]---
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/acpi_fpdt.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/acpi/acpi_fpdt.c b/drivers/acpi/acpi_fpdt.c
+index 6922a44b3ce7..a2056c4c8cb7 100644
+--- a/drivers/acpi/acpi_fpdt.c
++++ b/drivers/acpi/acpi_fpdt.c
+@@ -143,6 +143,23 @@ static const struct attribute_group boot_attr_group = {
+
+ static struct kobject *fpdt_kobj;
+
++#if defined CONFIG_X86 && defined CONFIG_PHYS_ADDR_T_64BIT
++#include <linux/processor.h>
++static bool fpdt_address_valid(u64 address)
++{
++ /*
++ * On some systems the table contains invalid addresses
++ * with unsuppored high address bits set, check for this.
++ */
++ return !(address >> boot_cpu_data.x86_phys_bits);
++}
++#else
++static bool fpdt_address_valid(u64 address)
++{
++ return true;
++}
++#endif
++
+ static int fpdt_process_subtable(u64 address, u32 subtable_type)
+ {
+ struct fpdt_subtable_header *subtable_header;
+@@ -151,6 +168,11 @@ static int fpdt_process_subtable(u64 address, u32 subtable_type)
+ u32 length, offset;
+ int result;
+
++ if (!fpdt_address_valid(address)) {
++ pr_info(FW_BUG "invalid physical address: 0x%llx!\n", address);
++ return -EINVAL;
++ }
++
+ subtable_header = acpi_os_map_memory(address, sizeof(*subtable_header));
+ if (!subtable_header)
+ return -ENOMEM;
+--
+2.35.1
+
--- /dev/null
+From 2a39b8c09f4e2b231540468ed9f20347e1e5b614 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 20:49:50 +0200
+Subject: ACPI: video: Add Toshiba Satellite/Portege Z830 quirk
+
+From: Arvid Norlander <lkml@vorpal.se>
+
+[ Upstream commit 574160b8548deff8b80b174f03201e94ab8431e2 ]
+
+Toshiba Satellite Z830 needs the quirk video_disable_backlight_sysfs_if
+for proper backlight control after suspend/resume cycles.
+
+Toshiba Portege Z830 is simply the same laptop rebranded for certain
+markets (I looked through the manual to other language sections to confirm
+this) and thus also needs this quirk.
+
+Thanks to Hans de Goede for suggesting this fix.
+
+Link: https://www.spinics.net/lists/platform-driver-x86/msg34394.html
+Suggested-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Arvid Norlander <lkml@vorpal.se>
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Tested-by: Arvid Norlander <lkml@vorpal.se>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/acpi_video.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
+index 390af28f6faf..2b18b51f6351 100644
+--- a/drivers/acpi/acpi_video.c
++++ b/drivers/acpi/acpi_video.c
+@@ -496,6 +496,22 @@ static const struct dmi_system_id video_dmi_table[] = {
+ DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE R830"),
+ },
+ },
++ {
++ .callback = video_disable_backlight_sysfs_if,
++ .ident = "Toshiba Satellite Z830",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE Z830"),
++ },
++ },
++ {
++ .callback = video_disable_backlight_sysfs_if,
++ .ident = "Toshiba Portege Z830",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE Z830"),
++ },
++ },
+ /*
+ * Some machine's _DOD IDs don't have bit 31(Device ID Scheme) set
+ * but the IDs actually follow the Device ID Scheme.
+--
+2.35.1
+
--- /dev/null
+From b949e173298022bb120ffad51d9f02ed48e59ac7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 15 Sep 2022 13:23:14 -0500
+Subject: ACPI: x86: Add a quirk for Dell Inspiron 14 2-in-1 for
+ StorageD3Enable
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit 018d6711c26e4bd26e20a819fcc7f8ab902608f3 ]
+
+Dell Inspiron 14 2-in-1 has two ACPI nodes under GPP1 both with _ADR of
+0, both without _HID. It's ambiguous which the kernel should take, but
+it seems to take "DEV0". Unfortunately "DEV0" is missing the device
+property `StorageD3Enable` which is present on "NVME".
+
+To avoid this causing problems for suspend, add a quirk for this system
+to behave like `StorageD3Enable` property was found.
+
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=216440
+Reported-and-tested-by: Luya Tshimbalanga <luya@fedoraproject.org>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/x86/utils.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c
+index b3fb428461c6..3a3f09b6cbfc 100644
+--- a/drivers/acpi/x86/utils.c
++++ b/drivers/acpi/x86/utils.c
+@@ -198,7 +198,24 @@ static const struct x86_cpu_id storage_d3_cpu_ids[] = {
+ {}
+ };
+
++static const struct dmi_system_id force_storage_d3_dmi[] = {
++ {
++ /*
++ * _ADR is ambiguous between GPP1.DEV0 and GPP1.NVME
++ * but .NVME is needed to get StorageD3Enable node
++ * https://bugzilla.kernel.org/show_bug.cgi?id=216440
++ */
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
++ DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14 7425 2-in-1"),
++ }
++ },
++ {}
++};
++
+ bool force_storage_d3(void)
+ {
+- return x86_match_cpu(storage_d3_cpu_ids);
++ const struct dmi_system_id *dmi_id = dmi_first_match(force_storage_d3_dmi);
++
++ return dmi_id || x86_match_cpu(storage_d3_cpu_ids);
+ }
+--
+2.35.1
+
--- /dev/null
+From 5a45a36fe87320f5679154aeead8f4fa6f2c668c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 18:58:13 +0200
+Subject: ALSA: dmaengine: increment buffer pointer atomically
+
+From: Andreas Pape <apape@de.adit-jv.com>
+
+[ Upstream commit d1c442019594692c64a70a86ad88eb5b6db92216 ]
+
+Setting pointer and afterwards checking for wraparound leads
+to the possibility of returning the inconsistent pointer position.
+
+This patch increments buffer pointer atomically to avoid this issue.
+
+Fixes: e7f73a1613567a ("ASoC: Add dmaengine PCM helper functions")
+Signed-off-by: Andreas Pape <apape@de.adit-jv.com>
+Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
+Link: https://lore.kernel.org/r/1664211493-11789-1-git-send-email-erosca@de.adit-jv.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/core/pcm_dmaengine.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/sound/core/pcm_dmaengine.c b/sound/core/pcm_dmaengine.c
+index 1fc2fa077574..0fe93b423c4e 100644
+--- a/sound/core/pcm_dmaengine.c
++++ b/sound/core/pcm_dmaengine.c
+@@ -132,12 +132,14 @@ EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_set_config_from_dai_data);
+
+ static void dmaengine_pcm_dma_complete(void *arg)
+ {
++ unsigned int new_pos;
+ struct snd_pcm_substream *substream = arg;
+ struct dmaengine_pcm_runtime_data *prtd = substream_to_prtd(substream);
+
+- prtd->pos += snd_pcm_lib_period_bytes(substream);
+- if (prtd->pos >= snd_pcm_lib_buffer_bytes(substream))
+- prtd->pos = 0;
++ new_pos = prtd->pos + snd_pcm_lib_period_bytes(substream);
++ if (new_pos >= snd_pcm_lib_buffer_bytes(substream))
++ new_pos = 0;
++ prtd->pos = new_pos;
+
+ snd_pcm_period_elapsed(substream);
+ }
+--
+2.35.1
+
--- /dev/null
+From eeea353ce89814dfaa614064449cbc1bc755f43d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 11:23:06 +0200
+Subject: ALSA: hda: beep: Simplify keep-power-at-enable behavior
+
+From: Takashi Iwai <tiwai@suse.de>
+
+[ Upstream commit 4c8d695cb9bc5f6fd298a586602947b2fc099a64 ]
+
+The recent fix for IDT codecs to keep the power up while the beep is
+enabled can be better integrated into the beep helper code.
+This patch cleans up the code with refactoring.
+
+Fixes: 414d38ba8710 ("ALSA: hda/sigmatel: Keep power up while beep is enabled")
+Link: https://lore.kernel.org/r/20220906092306.26183-1-tiwai@suse.de
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/hda_beep.c | 15 +++++++++++++--
+ sound/pci/hda/hda_beep.h | 1 +
+ sound/pci/hda/patch_sigmatel.c | 25 ++-----------------------
+ 3 files changed, 16 insertions(+), 25 deletions(-)
+
+diff --git a/sound/pci/hda/hda_beep.c b/sound/pci/hda/hda_beep.c
+index 53a2b89f8983..e63621bcb214 100644
+--- a/sound/pci/hda/hda_beep.c
++++ b/sound/pci/hda/hda_beep.c
+@@ -118,6 +118,12 @@ static int snd_hda_beep_event(struct input_dev *dev, unsigned int type,
+ return 0;
+ }
+
++static void turn_on_beep(struct hda_beep *beep)
++{
++ if (beep->keep_power_at_enable)
++ snd_hda_power_up_pm(beep->codec);
++}
++
+ static void turn_off_beep(struct hda_beep *beep)
+ {
+ cancel_work_sync(&beep->beep_work);
+@@ -125,6 +131,8 @@ static void turn_off_beep(struct hda_beep *beep)
+ /* turn off beep */
+ generate_tone(beep, 0);
+ }
++ if (beep->keep_power_at_enable)
++ snd_hda_power_down_pm(beep->codec);
+ }
+
+ /**
+@@ -140,7 +148,9 @@ int snd_hda_enable_beep_device(struct hda_codec *codec, int enable)
+ enable = !!enable;
+ if (beep->enabled != enable) {
+ beep->enabled = enable;
+- if (!enable)
++ if (enable)
++ turn_on_beep(beep);
++ else
+ turn_off_beep(beep);
+ return 1;
+ }
+@@ -167,7 +177,8 @@ static int beep_dev_disconnect(struct snd_device *device)
+ input_unregister_device(beep->dev);
+ else
+ input_free_device(beep->dev);
+- turn_off_beep(beep);
++ if (beep->enabled)
++ turn_off_beep(beep);
+ return 0;
+ }
+
+diff --git a/sound/pci/hda/hda_beep.h b/sound/pci/hda/hda_beep.h
+index a25358a4807a..db76e3ddba65 100644
+--- a/sound/pci/hda/hda_beep.h
++++ b/sound/pci/hda/hda_beep.h
+@@ -25,6 +25,7 @@ struct hda_beep {
+ unsigned int enabled:1;
+ unsigned int linear_tone:1; /* linear tone for IDT/STAC codec */
+ unsigned int playing:1;
++ unsigned int keep_power_at_enable:1; /* set by driver */
+ struct work_struct beep_work; /* scheduled task for beep event */
+ struct mutex mutex;
+ void (*power_hook)(struct hda_beep *beep, bool on);
+diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
+index 7f340f18599c..a794a01a68ca 100644
+--- a/sound/pci/hda/patch_sigmatel.c
++++ b/sound/pci/hda/patch_sigmatel.c
+@@ -4311,6 +4311,8 @@ static int stac_parse_auto_config(struct hda_codec *codec)
+ if (codec->beep) {
+ /* IDT/STAC codecs have linear beep tone parameter */
+ codec->beep->linear_tone = spec->linear_tone_beep;
++ /* keep power up while beep is enabled */
++ codec->beep->keep_power_at_enable = 1;
+ /* if no beep switch is available, make its own one */
+ caps = query_amp_caps(codec, nid, HDA_OUTPUT);
+ if (!(caps & AC_AMPCAP_MUTE)) {
+@@ -4444,28 +4446,6 @@ static int stac_suspend(struct hda_codec *codec)
+
+ return 0;
+ }
+-
+-static int stac_check_power_status(struct hda_codec *codec, hda_nid_t nid)
+-{
+-#ifdef CONFIG_SND_HDA_INPUT_BEEP
+- struct sigmatel_spec *spec = codec->spec;
+-#endif
+- int ret = snd_hda_gen_check_power_status(codec, nid);
+-
+-#ifdef CONFIG_SND_HDA_INPUT_BEEP
+- if (nid == spec->gen.beep_nid && codec->beep) {
+- if (codec->beep->enabled != spec->beep_power_on) {
+- spec->beep_power_on = codec->beep->enabled;
+- if (spec->beep_power_on)
+- snd_hda_power_up_pm(codec);
+- else
+- snd_hda_power_down_pm(codec);
+- }
+- ret |= spec->beep_power_on;
+- }
+-#endif
+- return ret;
+-}
+ #else
+ #define stac_suspend NULL
+ #endif /* CONFIG_PM */
+@@ -4478,7 +4458,6 @@ static const struct hda_codec_ops stac_patch_ops = {
+ .unsol_event = snd_hda_jack_unsol_event,
+ #ifdef CONFIG_PM
+ .suspend = stac_suspend,
+- .check_power_status = stac_check_power_status,
+ #endif
+ };
+
+--
+2.35.1
+
--- /dev/null
+From e3a26aca36af3cbce2630fdcfec617ba39e4f1ac Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 1 Oct 2022 09:48:10 +0200
+Subject: ALSA: hda/hdmi: Don't skip notification handling during PM operation
+
+From: Takashi Iwai <tiwai@suse.de>
+
+[ Upstream commit 5226c7b9784eee215e3914f440b3c2e1764f67a8 ]
+
+The HDMI driver skips the notification handling from the graphics
+driver when the codec driver is being in the PM operation. This
+behavior was introduced by the commit eb399d3c99d8 ("ALSA: hda - Skip
+ELD notification during PM process"). This skip may cause a problem,
+as we may miss the ELD update when the connection/disconnection
+happens right at the runtime-PM operation of the audio codec.
+
+Although this workaround was valid at that time, it's no longer true;
+the fix was required just because the ELD update procedure needed to
+wake up the audio codec, which had lead to a runtime-resume during a
+runtime-suspend. Meanwhile, the ELD update procedure doesn't need a
+codec wake up any longer since the commit 788d441a164c ("ALSA: hda -
+Use component ops for i915 HDMI/DP audio jack handling"); i.e. there
+is no much reason for skipping the notification.
+
+Let's drop those checks for addressing the missing notification.
+
+Fixes: 788d441a164c ("ALSA: hda - Use component ops for i915 HDMI/DP audio jack handling")
+Reported-by: Brent Lu <brent.lu@intel.com>
+Link: https://lore.kernel.org/r/20220927135807.4097052-1-brent.lu@intel.com
+Link: https://lore.kernel.org/r/20221001074809.7461-1-tiwai@suse.de
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/patch_hdmi.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
+index 1994a83fa391..ba1289abd45f 100644
+--- a/sound/pci/hda/patch_hdmi.c
++++ b/sound/pci/hda/patch_hdmi.c
+@@ -2685,9 +2685,6 @@ static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
+ */
+ if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
+ return;
+- /* ditto during suspend/resume process itself */
+- if (snd_hdac_is_in_pm(&codec->core))
+- return;
+
+ check_presence_and_report(codec, pin_nid, dev_id);
+ }
+@@ -2871,9 +2868,6 @@ static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
+ */
+ if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
+ return;
+- /* ditto during suspend/resume process itself */
+- if (snd_hdac_is_in_pm(&codec->core))
+- return;
+
+ snd_hdac_i915_set_bclk(&codec->bus->core);
+ check_presence_and_report(codec, pin_nid, dev_id);
+--
+2.35.1
+
--- /dev/null
+From 2a27106905c25ad4a0f47c0bb5528c1081651acb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 18 Aug 2022 17:14:33 -0300
+Subject: ALSA: usb-audio: Add quirk to enable Avid Mbox 3 support
+
+From: Conner Knox <connerknoxpublic@gmail.com>
+
+[ Upstream commit b01104fc62b6194c852124f6c6df1c0a5c031fc1 ]
+
+Add support for Avid Mbox3 USB audio interface at 48kHz
+
+Signed-off-by: Conner Knox <connerknoxpublic@gmail.com>
+Link: https://lore.kernel.org/r/20220818201433.16360-1-mbarriolinares@gmail.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/usb/quirks-table.h | 76 ++++++++++
+ sound/usb/quirks.c | 302 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 378 insertions(+)
+
+diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
+index f93201a830b5..06dfdd45cff8 100644
+--- a/sound/usb/quirks-table.h
++++ b/sound/usb/quirks-table.h
+@@ -2985,6 +2985,82 @@ YAMAHA_DEVICE(0x7010, "UB99"),
+ }
+ }
+ },
++/* DIGIDESIGN MBOX 3 */
++{
++ USB_DEVICE(0x0dba, 0x5000),
++ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
++ .vendor_name = "Digidesign",
++ .product_name = "Mbox 3",
++ .ifnum = QUIRK_ANY_INTERFACE,
++ .type = QUIRK_COMPOSITE,
++ .data = (const struct snd_usb_audio_quirk[]) {
++ {
++ .ifnum = 0,
++ .type = QUIRK_IGNORE_INTERFACE
++ },
++ {
++ .ifnum = 1,
++ .type = QUIRK_IGNORE_INTERFACE
++ },
++ {
++ .ifnum = 2,
++ .type = QUIRK_AUDIO_FIXED_ENDPOINT,
++ .data = &(const struct audioformat) {
++ .formats = SNDRV_PCM_FMTBIT_S24_3LE,
++ .channels = 4,
++ .iface = 2,
++ .altsetting = 1,
++ .altset_idx = 1,
++ .attributes = 0x00,
++ .endpoint = 0x01,
++ .ep_attr = USB_ENDPOINT_XFER_ISOC |
++ USB_ENDPOINT_SYNC_ASYNC,
++ .rates = SNDRV_PCM_RATE_48000,
++ .rate_min = 48000,
++ .rate_max = 48000,
++ .nr_rates = 1,
++ .rate_table = (unsigned int[]) {
++ 48000
++ }
++ }
++ },
++ {
++ .ifnum = 3,
++ .type = QUIRK_AUDIO_FIXED_ENDPOINT,
++ .data = &(const struct audioformat) {
++ .formats = SNDRV_PCM_FMTBIT_S24_3LE,
++ .channels = 4,
++ .iface = 3,
++ .altsetting = 1,
++ .altset_idx = 1,
++ .endpoint = 0x81,
++ .attributes = 0x00,
++ .ep_attr = USB_ENDPOINT_XFER_ISOC |
++ USB_ENDPOINT_SYNC_ASYNC,
++ .maxpacksize = 0x009c,
++ .rates = SNDRV_PCM_RATE_48000,
++ .rate_min = 48000,
++ .rate_max = 48000,
++ .nr_rates = 1,
++ .rate_table = (unsigned int[]) {
++ 48000
++ }
++ }
++ },
++ {
++ .ifnum = 4,
++ .type = QUIRK_MIDI_FIXED_ENDPOINT,
++ .data = &(const struct snd_usb_midi_endpoint_info) {
++ .out_cables = 0x0001,
++ .in_cables = 0x0001
++ }
++ },
++ {
++ .ifnum = -1
++ }
++ }
++ }
++},
+ {
+ /* Tascam US122 MKII - playback-only support */
+ USB_DEVICE_VENDOR_SPEC(0x0644, 0x8021),
+diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
+index 5b4d8f5eade2..194c75c45628 100644
+--- a/sound/usb/quirks.c
++++ b/sound/usb/quirks.c
+@@ -1020,6 +1020,304 @@ static int snd_usb_axefx3_boot_quirk(struct usb_device *dev)
+ return 0;
+ }
+
++static void mbox3_setup_48_24_magic(struct usb_device *dev)
++{
++ /* The Mbox 3 is "little endian" */
++ /* max volume is: 0x0000. */
++ /* min volume is: 0x0080 (shown in little endian form) */
++
++
++ /* Load 48000Hz rate into buffer */
++ u8 com_buff[4] = {0x80, 0xbb, 0x00, 0x00};
++
++ /* Set 48000Hz sample rate */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 0x01, 0x21, 0x0100, 0x0001, &com_buff, 4); //Is this really needed?
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 0x01, 0x21, 0x0100, 0x8101, &com_buff, 4);
++
++ /* Deactivate Tuner */
++ /* on = 0x01*/
++ /* off = 0x00*/
++ com_buff[0] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 0x01, 0x21, 0x0003, 0x2001, &com_buff, 1);
++
++ /* Set clock source to Internal (as opposed to S/PDIF) */
++ com_buff[0] = 0x01;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0100, 0x8001, &com_buff, 1);
++
++ /* Mute the hardware loopbacks to start the device in a known state. */
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* Analogue input 1 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0110, 0x4001, &com_buff, 2);
++ /* Analogue input 1 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0111, 0x4001, &com_buff, 2);
++ /* Analogue input 2 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0114, 0x4001, &com_buff, 2);
++ /* Analogue input 2 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0115, 0x4001, &com_buff, 2);
++ /* Analogue input 3 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0118, 0x4001, &com_buff, 2);
++ /* Analogue input 3 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0119, 0x4001, &com_buff, 2);
++ /* Analogue input 4 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011c, 0x4001, &com_buff, 2);
++ /* Analogue input 4 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011d, 0x4001, &com_buff, 2);
++
++ /* Set software sends to output */
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x00;
++ /* Analogue software return 1 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0100, 0x4001, &com_buff, 2);
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* Analogue software return 1 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0101, 0x4001, &com_buff, 2);
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* Analogue software return 2 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0104, 0x4001, &com_buff, 2);
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x00;
++ /* Analogue software return 2 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0105, 0x4001, &com_buff, 2);
++
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* Analogue software return 3 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0108, 0x4001, &com_buff, 2);
++ /* Analogue software return 3 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0109, 0x4001, &com_buff, 2);
++ /* Analogue software return 4 left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010c, 0x4001, &com_buff, 2);
++ /* Analogue software return 4 right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010d, 0x4001, &com_buff, 2);
++
++ /* Return to muting sends */
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* Analogue fx return left channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0120, 0x4001, &com_buff, 2);
++ /* Analogue fx return right channel: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0121, 0x4001, &com_buff, 2);
++
++ /* Analogue software input 1 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0100, 0x4201, &com_buff, 2);
++ /* Analogue software input 2 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0101, 0x4201, &com_buff, 2);
++ /* Analogue software input 3 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0102, 0x4201, &com_buff, 2);
++ /* Analogue software input 4 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0103, 0x4201, &com_buff, 2);
++ /* Analogue input 1 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0104, 0x4201, &com_buff, 2);
++ /* Analogue input 2 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0105, 0x4201, &com_buff, 2);
++ /* Analogue input 3 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0106, 0x4201, &com_buff, 2);
++ /* Analogue input 4 fx send: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0107, 0x4201, &com_buff, 2);
++
++ /* Toggle allowing host control */
++ com_buff[0] = 0x02;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 3, 0x21, 0x0000, 0x2001, &com_buff, 1);
++
++ /* Do not dim fx returns */
++ com_buff[0] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 3, 0x21, 0x0002, 0x2001, &com_buff, 1);
++
++ /* Do not set fx returns to mono */
++ com_buff[0] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 3, 0x21, 0x0001, 0x2001, &com_buff, 1);
++
++ /* Mute the S/PDIF hardware loopback
++ * same odd volume logic here as above
++ */
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* S/PDIF hardware input 1 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0112, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 1 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0113, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 2 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0116, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 2 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0117, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 3 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011a, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 3 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011b, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 4 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011e, 0x4001, &com_buff, 2);
++ /* S/PDIF hardware input 4 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x011f, 0x4001, &com_buff, 2);
++ /* S/PDIF software return 1 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0102, 0x4001, &com_buff, 2);
++ /* S/PDIF software return 1 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0103, 0x4001, &com_buff, 2);
++ /* S/PDIF software return 2 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0106, 0x4001, &com_buff, 2);
++ /* S/PDIF software return 2 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0107, 0x4001, &com_buff, 2);
++
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x00;
++ /* S/PDIF software return 3 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010a, 0x4001, &com_buff, 2);
++
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* S/PDIF software return 3 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010b, 0x4001, &com_buff, 2);
++ /* S/PDIF software return 4 left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010e, 0x4001, &com_buff, 2);
++
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x00;
++ /* S/PDIF software return 4 right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x010f, 0x4001, &com_buff, 2);
++
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x80;
++ /* S/PDIF fx returns left channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0122, 0x4001, &com_buff, 2);
++ /* S/PDIF fx returns right channel */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0123, 0x4001, &com_buff, 2);
++
++ /* Set the dropdown "Effect" to the first option */
++ /* Room1 = 0x00 */
++ /* Room2 = 0x01 */
++ /* Room3 = 0x02 */
++ /* Hall 1 = 0x03 */
++ /* Hall 2 = 0x04 */
++ /* Plate = 0x05 */
++ /* Delay = 0x06 */
++ /* Echo = 0x07 */
++ com_buff[0] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0200, 0x4301, &com_buff, 1); /* max is 0xff */
++ /* min is 0x00 */
++
++
++ /* Set the effect duration to 0 */
++ /* max is 0xffff */
++ /* min is 0x0000 */
++ com_buff[0] = 0x00;
++ com_buff[1] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0400, 0x4301, &com_buff, 2);
++
++ /* Set the effect volume and feedback to 0 */
++ /* max is 0xff */
++ /* min is 0x00 */
++ com_buff[0] = 0x00;
++ /* feedback: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0500, 0x4301, &com_buff, 1);
++ /* volume: */
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 1, 0x21, 0x0300, 0x4301, &com_buff, 1);
++
++ /* Set soft button hold duration */
++ /* 0x03 = 250ms */
++ /* 0x05 = 500ms DEFAULT */
++ /* 0x08 = 750ms */
++ /* 0x0a = 1sec */
++ com_buff[0] = 0x05;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 3, 0x21, 0x0005, 0x2001, &com_buff, 1);
++
++ /* Use dim LEDs for button of state */
++ com_buff[0] = 0x00;
++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0),
++ 3, 0x21, 0x0004, 0x2001, &com_buff, 1);
++}
++
++#define MBOX3_DESCRIPTOR_SIZE 464
++
++static int snd_usb_mbox3_boot_quirk(struct usb_device *dev)
++{
++ struct usb_host_config *config = dev->actconfig;
++ int err;
++ int descriptor_size;
++
++ descriptor_size = le16_to_cpu(get_cfg_desc(config)->wTotalLength);
++
++ if (descriptor_size != MBOX3_DESCRIPTOR_SIZE) {
++ dev_err(&dev->dev, "Invalid descriptor size=%d.\n", descriptor_size);
++ return -ENODEV;
++ }
++
++ dev_dbg(&dev->dev, "device initialised!\n");
++
++ err = usb_get_descriptor(dev, USB_DT_DEVICE, 0,
++ &dev->descriptor, sizeof(dev->descriptor));
++ config = dev->actconfig;
++ if (err < 0)
++ dev_dbg(&dev->dev, "error usb_get_descriptor: %d\n", err);
++
++ err = usb_reset_configuration(dev);
++ if (err < 0)
++ dev_dbg(&dev->dev, "error usb_reset_configuration: %d\n", err);
++ dev_dbg(&dev->dev, "mbox3_boot: new boot length = %d\n",
++ le16_to_cpu(get_cfg_desc(config)->wTotalLength));
++
++ mbox3_setup_48_24_magic(dev);
++ dev_info(&dev->dev, "Digidesign Mbox 3: 24bit 48kHz");
++
++ return 0; /* Successful boot */
++}
+
+ #define MICROBOOK_BUF_SIZE 128
+
+@@ -1324,6 +1622,10 @@ int snd_usb_apply_boot_quirk(struct usb_device *dev,
+ case USB_ID(0x0dba, 0x3000):
+ /* Digidesign Mbox 2 */
+ return snd_usb_mbox2_boot_quirk(dev);
++ case USB_ID(0x0dba, 0x5000):
++ /* Digidesign Mbox 3 */
++ return snd_usb_mbox3_boot_quirk(dev);
++
+
+ case USB_ID(0x1235, 0x0010): /* Focusrite Novation Saffire 6 USB */
+ case USB_ID(0x1235, 0x0018): /* Focusrite Novation Twitch */
+--
+2.35.1
+
--- /dev/null
+From c543ffaea1dcf363bfd3fbe09c2752508ba97e47 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 18:12:47 +0200
+Subject: ALSA: usb-audio: Register card at the last interface
+
+From: Takashi Iwai <tiwai@suse.de>
+
+[ Upstream commit 6392dcd1d0c7034ccf630ec55fc9e5810ecadf3b ]
+
+The USB-audio driver matches per interface, and as default, it
+registers the card instance at the very first instance. This can be a
+problem for the devices that have multiple interfaces to be probed, as
+the udev rule isn't applied properly for the later appearing
+interfaces. Although we introduced the delayed_register option and
+the quirks for covering those shortcomings, it's nothing but a
+workaround for specific devices.
+
+This patch is an another attempt to fix the problem in a more generic
+way. Now the driver checks the whole USB device descriptor at the
+very first time when an interface is attached to a sound card. It
+looks at each matching interface in the descriptor and remembers the
+last matching one. The snd_card_register() is invoked only when this
+last interface is probed.
+
+After this change, the quirks for the delayed registration become
+superfluous, hence they are removed along with the patch. OTOH, the
+delayed_register option is still kept, as it might be useful for some
+corner cases (e.g. a special driver overtakes the interface probe from
+the standard driver, and the last interface probe may miss).
+
+Link: https://lore.kernel.org/r/20220904161247.16461-1-tiwai@suse.de
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/usb/card.c | 32 +++++++++++++++++++++++++-------
+ sound/usb/quirks.c | 42 ------------------------------------------
+ sound/usb/quirks.h | 2 --
+ sound/usb/usbaudio.h | 1 +
+ 4 files changed, 26 insertions(+), 51 deletions(-)
+
+diff --git a/sound/usb/card.c b/sound/usb/card.c
+index 713b84d8d42f..207c212eabde 100644
+--- a/sound/usb/card.c
++++ b/sound/usb/card.c
+@@ -689,7 +689,7 @@ static bool get_alias_id(struct usb_device *dev, unsigned int *id)
+ return false;
+ }
+
+-static bool check_delayed_register_option(struct snd_usb_audio *chip, int iface)
++static int check_delayed_register_option(struct snd_usb_audio *chip)
+ {
+ int i;
+ unsigned int id, inum;
+@@ -698,14 +698,31 @@ static bool check_delayed_register_option(struct snd_usb_audio *chip, int iface)
+ if (delayed_register[i] &&
+ sscanf(delayed_register[i], "%x:%x", &id, &inum) == 2 &&
+ id == chip->usb_id)
+- return iface < inum;
++ return inum;
+ }
+
+- return false;
++ return -1;
+ }
+
+ static const struct usb_device_id usb_audio_ids[]; /* defined below */
+
++/* look for the last interface that matches with our ids and remember it */
++static void find_last_interface(struct snd_usb_audio *chip)
++{
++ struct usb_host_config *config = chip->dev->actconfig;
++ struct usb_interface *intf;
++ int i;
++
++ if (!config)
++ return;
++ for (i = 0; i < config->desc.bNumInterfaces; i++) {
++ intf = config->interface[i];
++ if (usb_match_id(intf, usb_audio_ids))
++ chip->last_iface = intf->altsetting[0].desc.bInterfaceNumber;
++ }
++ usb_audio_dbg(chip, "Found last interface = %d\n", chip->last_iface);
++}
++
+ /* look for the corresponding quirk */
+ static const struct snd_usb_audio_quirk *
+ get_alias_quirk(struct usb_device *dev, unsigned int id)
+@@ -812,6 +829,7 @@ static int usb_audio_probe(struct usb_interface *intf,
+ err = -ENODEV;
+ goto __error;
+ }
++ find_last_interface(chip);
+ }
+
+ if (chip->num_interfaces >= MAX_CARD_INTERFACES) {
+@@ -861,11 +879,11 @@ static int usb_audio_probe(struct usb_interface *intf,
+ chip->need_delayed_register = false; /* clear again */
+ }
+
+- /* we are allowed to call snd_card_register() many times, but first
+- * check to see if a device needs to skip it or do anything special
++ /* register card if we reach to the last interface or to the specified
++ * one given via option
+ */
+- if (!snd_usb_registration_quirk(chip, ifnum) &&
+- !check_delayed_register_option(chip, ifnum)) {
++ if (check_delayed_register_option(chip) == ifnum ||
++ chip->last_iface == ifnum) {
+ err = snd_card_register(chip->card);
+ if (err < 0)
+ goto __error;
+diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
+index 194c75c45628..eadac586bcc8 100644
+--- a/sound/usb/quirks.c
++++ b/sound/usb/quirks.c
+@@ -2030,48 +2030,6 @@ void snd_usb_audioformat_attributes_quirk(struct snd_usb_audio *chip,
+ }
+ }
+
+-/*
+- * registration quirk:
+- * the registration is skipped if a device matches with the given ID,
+- * unless the interface reaches to the defined one. This is for delaying
+- * the registration until the last known interface, so that the card and
+- * devices appear at the same time.
+- */
+-
+-struct registration_quirk {
+- unsigned int usb_id; /* composed via USB_ID() */
+- unsigned int interface; /* the interface to trigger register */
+-};
+-
+-#define REG_QUIRK_ENTRY(vendor, product, iface) \
+- { .usb_id = USB_ID(vendor, product), .interface = (iface) }
+-
+-static const struct registration_quirk registration_quirks[] = {
+- REG_QUIRK_ENTRY(0x0951, 0x16d8, 2), /* Kingston HyperX AMP */
+- REG_QUIRK_ENTRY(0x0951, 0x16ed, 2), /* Kingston HyperX Cloud Alpha S */
+- REG_QUIRK_ENTRY(0x0951, 0x16ea, 2), /* Kingston HyperX Cloud Flight S */
+- REG_QUIRK_ENTRY(0x0ecb, 0x1f46, 2), /* JBL Quantum 600 */
+- REG_QUIRK_ENTRY(0x0ecb, 0x1f47, 2), /* JBL Quantum 800 */
+- REG_QUIRK_ENTRY(0x0ecb, 0x1f4c, 2), /* JBL Quantum 400 */
+- REG_QUIRK_ENTRY(0x0ecb, 0x2039, 2), /* JBL Quantum 400 */
+- REG_QUIRK_ENTRY(0x0ecb, 0x203c, 2), /* JBL Quantum 600 */
+- REG_QUIRK_ENTRY(0x0ecb, 0x203e, 2), /* JBL Quantum 800 */
+- { 0 } /* terminator */
+-};
+-
+-/* return true if skipping registration */
+-bool snd_usb_registration_quirk(struct snd_usb_audio *chip, int iface)
+-{
+- const struct registration_quirk *q;
+-
+- for (q = registration_quirks; q->usb_id; q++)
+- if (chip->usb_id == q->usb_id)
+- return iface < q->interface;
+-
+- /* Register as normal */
+- return false;
+-}
+-
+ /*
+ * driver behavior quirk flags
+ */
+diff --git a/sound/usb/quirks.h b/sound/usb/quirks.h
+index 31abb7cb01a5..f9bfd5ac7bab 100644
+--- a/sound/usb/quirks.h
++++ b/sound/usb/quirks.h
+@@ -48,8 +48,6 @@ void snd_usb_audioformat_attributes_quirk(struct snd_usb_audio *chip,
+ struct audioformat *fp,
+ int stream);
+
+-bool snd_usb_registration_quirk(struct snd_usb_audio *chip, int iface);
+-
+ void snd_usb_init_quirk_flags(struct snd_usb_audio *chip);
+
+ #endif /* __USBAUDIO_QUIRKS_H */
+diff --git a/sound/usb/usbaudio.h b/sound/usb/usbaudio.h
+index 044cd7ab27cb..39c3c61a7e49 100644
+--- a/sound/usb/usbaudio.h
++++ b/sound/usb/usbaudio.h
+@@ -37,6 +37,7 @@ struct snd_usb_audio {
+ unsigned int quirk_flags;
+ unsigned int need_delayed_register:1; /* warn for delayed registration */
+ int num_interfaces;
++ int last_iface;
+ int num_suspended_intf;
+ int sample_rate_read_error;
+
+--
+2.35.1
+
--- /dev/null
+From 303d9665f160d2f61a139c8d360d86a28c9f1afb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 16:26:59 +0100
+Subject: ARM: 9242/1: kasan: Only map modules if CONFIG_KASAN_VMALLOC=n
+
+From: Alex Sverdlin <alexander.sverdlin@nokia.com>
+
+[ Upstream commit 823f606ab6b4759a1faf0388abcf4fb0776710d2 ]
+
+In case CONFIG_KASAN_VMALLOC=y kasan_populate_vmalloc() allocates the
+shadow pages dynamically. But even worse is that kasan_release_vmalloc()
+releases them, which is not compatible with create_mapping() of
+MODULES_VADDR..MODULES_END range:
+
+BUG: Bad page state in process kworker/9:1 pfn:2068b
+page:e5e06160 refcount:0 mapcount:0 mapping:00000000 index:0x0
+flags: 0x1000(reserved)
+raw: 00001000 e5e06164 e5e06164 00000000 00000000 00000000 ffffffff 00000000
+page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set
+bad because of flags: 0x1000(reserved)
+Modules linked in: ip_tables
+CPU: 9 PID: 154 Comm: kworker/9:1 Not tainted 5.4.188-... #1
+Hardware name: LSI Axxia AXM55XX
+Workqueue: events do_free_init
+unwind_backtrace
+show_stack
+dump_stack
+bad_page
+free_pcp_prepare
+free_unref_page
+kasan_depopulate_vmalloc_pte
+__apply_to_page_range
+apply_to_existing_page_range
+kasan_release_vmalloc
+__purge_vmap_area_lazy
+_vm_unmap_aliases.part.0
+__vunmap
+do_free_init
+process_one_work
+worker_thread
+kthread
+
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mm/kasan_init.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mm/kasan_init.c b/arch/arm/mm/kasan_init.c
+index 4b1619584b23..948ada4a2938 100644
+--- a/arch/arm/mm/kasan_init.c
++++ b/arch/arm/mm/kasan_init.c
+@@ -264,12 +264,17 @@ void __init kasan_init(void)
+
+ /*
+ * 1. The module global variables are in MODULES_VADDR ~ MODULES_END,
+- * so we need to map this area.
++ * so we need to map this area if CONFIG_KASAN_VMALLOC=n. With
++ * VMALLOC support KASAN will manage this region dynamically,
++ * refer to kasan_populate_vmalloc() and ARM's implementation of
++ * module_alloc().
+ * 2. PKMAP_BASE ~ PKMAP_BASE+PMD_SIZE's shadow and MODULES_VADDR
+ * ~ MODULES_END's shadow is in the same PMD_SIZE, so we can't
+ * use kasan_populate_zero_shadow.
+ */
+- create_mapping((void *)MODULES_VADDR, (void *)(PKMAP_BASE + PMD_SIZE));
++ if (!IS_ENABLED(CONFIG_KASAN_VMALLOC) && IS_ENABLED(CONFIG_MODULES))
++ create_mapping((void *)MODULES_VADDR, (void *)(MODULES_END));
++ create_mapping((void *)PKMAP_BASE, (void *)(PKMAP_BASE + PMD_SIZE));
+
+ /*
+ * KAsan may reuse the contents of kasan_early_shadow_pte directly, so
+--
+2.35.1
+
--- /dev/null
+From fc674d36d45237f3c677661a8c397dd3fd4e9b79 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 05:25:51 +0100
+Subject: ARM: 9244/1: dump: Fix wrong pg_level in walk_pmd()
+
+From: Wang Kefeng <wangkefeng.wang@huawei.com>
+
+[ Upstream commit 2ccd19b3ffac07cc7e75a2bd1ed779728bb67197 ]
+
+After ARM supports p4d page tables, the pg_level for note_page()
+in walk_pmd() should be 4, not 3, fix it.
+
+Fixes: 84e6ffb2c49c ("arm: add support for folded p4d page tables")
+Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mm/dump.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
+index fb688003d156..712da6a81b23 100644
+--- a/arch/arm/mm/dump.c
++++ b/arch/arm/mm/dump.c
+@@ -346,7 +346,7 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
+ addr = start + i * PMD_SIZE;
+ domain = get_domain_name(pmd);
+ if (pmd_none(*pmd) || pmd_large(*pmd) || !pmd_present(*pmd))
+- note_page(st, addr, 3, pmd_val(*pmd), domain);
++ note_page(st, addr, 4, pmd_val(*pmd), domain);
+ else
+ walk_pte(st, pmd, addr, domain);
+
+--
+2.35.1
+
--- /dev/null
+From a2feffa4c418e154eec2ab008f56a8453e88d563 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:10:49 +0100
+Subject: ARM: 9247/1: mm: set readonly for MT_MEMORY_RO with ARM_LPAE
+
+From: Wang Kefeng <wangkefeng.wang@huawei.com>
+
+[ Upstream commit 14ca1a4690750bb54e1049e49f3140ef48958a6e ]
+
+MT_MEMORY_RO is introduced by commit 598f0a99fa8a ("ARM: 9210/1:
+Mark the FDT_FIXED sections as shareable"), which is a readonly
+memory type for FDT area, but there are some different between
+ARM_LPAE and non-ARM_LPAE, we need to setup PMD_SECT_AP2 and
+L_PMD_SECT_RDONLY for MT_MEMORY_RO when ARM_LAPE enabled.
+
+non-ARM_LPAE 0xff800000-0xffa00000 2M PGD KERNEL ro NX SHD
+ARM_LPAE 0xff800000-0xffc00000 4M PMD RW NX SHD
+ARM_LPAE+fix 0xff800000-0xffc00000 4M PMD ro NX SHD
+
+Fixes: 598f0a99fa8a ("ARM: 9210/1: Mark the FDT_FIXED sections as shareable")
+Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mm/mmu.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
+index cd17e324aa51..83a91e0ab848 100644
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -300,7 +300,11 @@ static struct mem_type mem_types[] __ro_after_init = {
+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+ L_PTE_XN | L_PTE_RDONLY,
+ .prot_l1 = PMD_TYPE_TABLE,
++#ifdef CONFIG_ARM_LPAE
++ .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
++#else
+ .prot_sect = PMD_TYPE_SECT,
++#endif
+ .domain = DOMAIN_KERNEL,
+ },
+ [MT_ROM] = {
+--
+2.35.1
+
--- /dev/null
+From 5aa8d7c8528870f7cc579d36297f22212c0935d4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 15:41:03 -0700
+Subject: ARM: decompressor: Include .data.rel.ro.local
+
+From: Kees Cook <keescook@chromium.org>
+
+[ Upstream commit 1b64daf413acd86c2c13f5443f6b4ef3690c8061 ]
+
+The .data.rel.ro.local section has the same semantics as .data.rel.ro
+here, so include it in the .rodata section of the decompressor.
+Additionally since the .printk_index section isn't usable outside of
+the core kernel, discard it in the decompressor. Avoids these warnings:
+
+arm-linux-gnueabi-ld: warning: orphan section `.data.rel.ro.local' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.data.rel.ro.local'
+arm-linux-gnueabi-ld: warning: orphan section `.printk_index' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.printk_index'
+
+Reported-by: kernel test robot <lkp@intel.com>
+Link: https://lore.kernel.org/linux-mm/202209080545.qMIVj7YM-lkp@intel.com
+Cc: Russell King <linux@armlinux.org.uk>
+Cc: linux-arm-kernel@lists.infradead.org
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/compressed/vmlinux.lds.S | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
+index 1bcb68ac4b01..3fcb3e62dc56 100644
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
++++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -23,6 +23,7 @@ SECTIONS
+ *(.ARM.extab*)
+ *(.note.*)
+ *(.rel.*)
++ *(.printk_index)
+ /*
+ * Discard any r/w data - this produces a link error if we have any,
+ * which is required for PIC decompression. Local data generates
+@@ -57,6 +58,7 @@ SECTIONS
+ *(.rodata)
+ *(.rodata.*)
+ *(.data.rel.ro)
++ *(.data.rel.ro.*)
+ }
+ .piggydata : {
+ *(.piggydata)
+--
+2.35.1
+
--- /dev/null
+From fd23471f8cba678657f9a32abfc6a3a273ee32e7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 15:28:26 +0200
+Subject: ARM: Drop CMDLINE_* dependency on ATAGS
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+[ Upstream commit 136f4b1ec7c962ee37a787e095fd37b058d72bd3 ]
+
+On arm32, the configuration options to specify the kernel command line
+type depend on ATAGS. However, the actual CMDLINE cofiguration option
+does not depend on ATAGS, and the code that handles this is not specific
+to ATAGS (see drivers/of/fdt.c:early_init_dt_scan_chosen()).
+
+Hence users who desire to override the kernel command line on arm32 must
+enable support for ATAGS, even on a pure-DT system. Other architectures
+(arm64, loongarch, microblaze, nios2, powerpc, and riscv) do not impose
+such a restriction.
+
+Hence drop the dependency on ATAGS.
+
+Fixes: bd51e2f595580fb6 ("ARM: 7506/1: allow for ATAGS to be configured out when DT support is selected")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 4ebd512043be..a8ae17f5740d 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1741,7 +1741,6 @@ config CMDLINE
+ choice
+ prompt "Kernel command line type" if CMDLINE != ""
+ default CMDLINE_FROM_BOOTLOADER
+- depends on ATAGS
+
+ config CMDLINE_FROM_BOOTLOADER
+ bool "Use bootloader kernel arguments if available"
+--
+2.35.1
+
--- /dev/null
+From d55db56b0e3e58f06a4fe30c40c6b8fe9996832c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 12:43:53 +0200
+Subject: ARM: dts: exynos: correct s5k6a3 reset polarity on Midas family
+
+From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+
+[ Upstream commit 3ba2d4bb9592bf7a6a3fe3dbe711ecfc3d004bab ]
+
+According to s5k6a3 driver code, the reset line for the chip appears to
+be active low. This also matches the typical polarity of reset lines in
+general. Let's fix it up as having correct polarity in DTS is important
+when the driver will be switched over to gpiod API.
+
+Fixes: b4fec64758ab ("ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board")
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220913164104.203957-1-dmitry.torokhov@gmail.com
+Link: https://lore.kernel.org/r/20220926104354.118578-2-krzysztof.kozlowski@linaro.org'
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
+index 968c7943653e..49843e016828 100644
+--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
++++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
+@@ -585,7 +585,7 @@
+ clocks = <&camera 1>;
+ clock-names = "extclk";
+ samsung,camclk-out = <1>;
+- gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
++ gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
+
+ port {
+ is_s5k6a3_ep: endpoint {
+--
+2.35.1
+
--- /dev/null
+From 621a365dbeca6a086ed0213e4cdaf824d22127c1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 15:05:03 -0700
+Subject: ARM: dts: exynos: fix polarity of VBUS GPIO of Origen
+
+From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+
+[ Upstream commit a08137bd1e0a7ce951dce9ce4a83e39d379b6e1b ]
+
+EHCI Oxynos (drivers/usb/host/ehci-exynos.c) drives VBUS GPIO high when
+trying to power up the bus, therefore the GPIO in DTS must be marked as
+"active high". This will be important when EHCI driver is converted to
+gpiod API that respects declared polarities.
+
+Fixes: 4e8991def565 ("ARM: dts: exynos: Enable AX88760 USB hub on Origen board")
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Link: https://lore.kernel.org/r/20220927220504.3744878-1-dmitry.torokhov@gmail.com
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/exynos4412-origen.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
+index 5479ef09f9f3..0acb05f0a2b7 100644
+--- a/arch/arm/boot/dts/exynos4412-origen.dts
++++ b/arch/arm/boot/dts/exynos4412-origen.dts
+@@ -95,7 +95,7 @@
+ };
+
+ &ehci {
+- samsung,vbus-gpio = <&gpx3 5 1>;
++ samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
+ phy-names = "hsic0", "hsic1";
+--
+2.35.1
+
--- /dev/null
+From a704c94bac83bb239eaa039e815ab412970aa6a0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:32 +0200
+Subject: ARM: dts: imx6dl: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit f5848b95633d598bacf0500e0108dc5961af88c0 ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@900000: '#address-cells' is a required property
+sram@900000: '#size-cells' is a required property
+sram@900000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6dl.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
+index fdd81fdc3f35..cd3183c36488 100644
+--- a/arch/arm/boot/dts/imx6dl.dtsi
++++ b/arch/arm/boot/dts/imx6dl.dtsi
+@@ -84,6 +84,9 @@
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
++ ranges = <0 0x00900000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From b1cde90c8d355412168be2da8c1f7f9a8f531aa3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:31 +0200
+Subject: ARM: dts: imx6q: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit b11d083c5dcec7c42fe982c854706d404ddd3a5f ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@900000: '#address-cells' is a required property
+sram@900000: '#size-cells' is a required property
+sram@900000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6q.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
+index 9caba4529c71..a8069e0a8fe8 100644
+--- a/arch/arm/boot/dts/imx6q.dtsi
++++ b/arch/arm/boot/dts/imx6q.dtsi
+@@ -163,6 +163,9 @@
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x40000>;
++ ranges = <0 0x00900000 0x40000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 7743f45155e62cb05ee4169f69b9d1a837e42f37 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 26 Jul 2022 15:05:23 +0200
+Subject: ARM: dts: imx6qdl-kontron-samx6i: hook up DDC i2c bus
+
+From: Lucas Stach <l.stach@pengutronix.de>
+
+[ Upstream commit afd8f77957e3e83adf21d9229c61ff37f44a177a ]
+
+i2c2 is routed to the pins dedicated as DDC in the module standard.
+Reduce clock rate to 100kHz to be in line with VESA standard and hook
+this bus up to the HDMI node.
+
+Fixes: 708ed2649ad8 ("ARM: dts: imx6qdl-kontron-samx6i: increase i2c-frequency")
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+[m.felsch@pengutronix.de: add fixes line]
+Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+index 6b791d515e29..683f6e58ab23 100644
+--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+@@ -263,6 +263,10 @@
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ };
+
++&hdmi {
++ ddc-i2c-bus = <&i2c2>;
++};
++
+ &i2c_intern {
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+@@ -387,7 +391,7 @@
+
+ /* HDMI_CTRL */
+ &i2c2 {
+- clock-frequency = <375000>;
++ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ };
+--
+2.35.1
+
--- /dev/null
+From f71f57929d2d971ed0c8ce4b7cb55f7c39c86344 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:33 +0200
+Subject: ARM: dts: imx6qp: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit 088fe5237435ee2f7ed4450519b2ef58b94c832f ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@940000: '#address-cells' is a required property
+sram@940000: '#size-cells' is a required property
+sram@940000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6qp.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
+index b310f13a53f2..4d23c92aa8a6 100644
+--- a/arch/arm/boot/dts/imx6qp.dtsi
++++ b/arch/arm/boot/dts/imx6qp.dtsi
+@@ -9,12 +9,18 @@
+ ocram2: sram@940000 {
+ compatible = "mmio-sram";
+ reg = <0x00940000 0x20000>;
++ ranges = <0 0x00940000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ ocram3: sram@960000 {
+ compatible = "mmio-sram";
+ reg = <0x00960000 0x20000>;
++ ranges = <0 0x00960000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 70ccbbb2df4d40def6f47a48f94804b15d337ab0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:34 +0200
+Subject: ARM: dts: imx6sl: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit 60c9213a1d9941a8b33db570796c3f9be8984974 ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@900000: '#address-cells' is a required property
+sram@900000: '#size-cells' is a required property
+sram@900000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6sl.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
+index 997b96c1c47b..5b4dfc62030e 100644
+--- a/arch/arm/boot/dts/imx6sl.dtsi
++++ b/arch/arm/boot/dts/imx6sl.dtsi
+@@ -117,6 +117,9 @@
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
++ ranges = <0 0x00900000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6SL_CLK_OCRAM>;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 35495c8faa3131ebcd5501b1b95058e9a5b5a6e2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:35 +0200
+Subject: ARM: dts: imx6sll: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit 7492a83ed9b7a151e2dd11d64b06da7a7f0fa7f9 ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@900000: '#address-cells' is a required property
+sram@900000: '#size-cells' is a required property
+sram@900000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6sll.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
+index 04f8d637a501..eecb2f68a1c3 100644
+--- a/arch/arm/boot/dts/imx6sll.dtsi
++++ b/arch/arm/boot/dts/imx6sll.dtsi
+@@ -117,6 +117,9 @@
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
++ ranges = <0 0x00900000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ };
+
+ intc: interrupt-controller@a01000 {
+--
+2.35.1
+
--- /dev/null
+From a0941f5e05bc76ca9ff8adfe3370a2b45a9b2488 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 07:53:36 +0200
+Subject: ARM: dts: imx6sx: add missing properties for sram
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit 415432c008b2bce8138841356ba444631cabaa50 ]
+
+All 3 properties are required by sram.yaml. Fixes the dtbs_check warning:
+sram@900000: '#address-cells' is a required property
+sram@900000: '#size-cells' is a required property
+sram@900000: 'ranges' is a required property
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
+index 8516730778df..8bef5440278b 100644
+--- a/arch/arm/boot/dts/imx6sx.dtsi
++++ b/arch/arm/boot/dts/imx6sx.dtsi
+@@ -164,12 +164,18 @@
+ ocram_s: sram@8f8000 {
+ compatible = "mmio-sram";
+ reg = <0x008f8000 0x4000>;
++ ranges = <0 0x008f8000 0x4000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6SX_CLK_OCRAM_S>;
+ };
+
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
++ ranges = <0 0x00900000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ clocks = <&clks IMX6SX_CLK_OCRAM>;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 3ac783a34a8126c75f97ca84c053964b7270c54c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Jul 2022 18:16:22 +0800
+Subject: ARM: dts: imx7d-sdb: config the max pressure for tsc2046
+
+From: Haibo Chen <haibo.chen@nxp.com>
+
+[ Upstream commit e7c4ebe2f9cd68588eb24ba4ed122e696e2d5272 ]
+
+Use the general touchscreen method to config the max pressure for
+touch tsc2046(data sheet suggest 8 bit pressure), otherwise, for
+ABS_PRESSURE, when config the same max and min value, weston will
+meet the following issue,
+
+[17:19:39.183] event1 - ADS7846 Touchscreen: is tagged by udev as: Touchscreen
+[17:19:39.183] event1 - ADS7846 Touchscreen: kernel bug: device has min == max on ABS_PRESSURE
+[17:19:39.183] event1 - ADS7846 Touchscreen: was rejected
+[17:19:39.183] event1 - not using input device '/dev/input/event1'
+
+This will then cause the APP weston-touch-calibrator can't list touch devices.
+
+root@imx6ul7d:~# weston-touch-calibrator
+could not load cursor 'dnd-move'
+could not load cursor 'dnd-copy'
+could not load cursor 'dnd-none'
+No devices listed.
+
+And accroding to binding Doc, "ti,x-max", "ti,y-max", "ti,pressure-max"
+belong to the deprecated properties, so remove them. Also for "ti,x-min",
+"ti,y-min", "ti,x-plate-ohms", the value set in dts equal to the default
+value in driver, so are redundant, also remove here.
+
+Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx7d-sdb.dts | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
+index e5f1bdbe7992..4e1a6cde90fe 100644
+--- a/arch/arm/boot/dts/imx7d-sdb.dts
++++ b/arch/arm/boot/dts/imx7d-sdb.dts
+@@ -206,12 +206,7 @@
+ interrupt-parent = <&gpio2>;
+ interrupts = <29 0>;
+ pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+- ti,x-min = /bits/ 16 <0>;
+- ti,x-max = /bits/ 16 <0>;
+- ti,y-min = /bits/ 16 <0>;
+- ti,y-max = /bits/ 16 <0>;
+- ti,pressure-max = /bits/ 16 <0>;
+- ti,x-plate-ohms = /bits/ 16 <400>;
++ touchscreen-max-pressure = <255>;
+ wakeup-source;
+ };
+ };
+--
+2.35.1
+
--- /dev/null
+From 4859586548aa8f917ab773a26069fe4416dfb4c6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 02:10:24 +0200
+Subject: ARM: dts: kirkwood: lsxl: fix serial line
+
+From: Michael Walle <michael@walle.cc>
+
+[ Upstream commit 04eabc6ac10fda9424606d9a7ab6ab9a5d95350a ]
+
+Commit 327e15428977 ("ARM: dts: kirkwood: consolidate common pinctrl
+settings") unknowingly broke the serial output on this board. Before
+this commit, the pinmux was still configured by the bootloader and the
+kernel didn't reconfigured it again. This was an oversight by the
+initial board support where the pinmux for the serial line was never
+configured by the kernel. But with this commit, the serial line will be
+reconfigured to the wrong pins. This is especially confusing, because
+the output still works, but the input doesn't. Presumingly, the input is
+reconfigured to MPP10, but the output is connected to both MPP11 and
+MPP5.
+
+Override the pinmux in the board device tree.
+
+Fixes: 327e15428977 ("ARM: dts: kirkwood: consolidate common pinctrl settings")
+Signed-off-by: Michael Walle <michael@walle.cc>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/kirkwood-lsxl.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+index 7b151acb9984..321a40a98ed2 100644
+--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
++++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+@@ -10,6 +10,11 @@
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
++ /* Non-default UART pins */
++ pmx_uart0: pmx-uart0 {
++ marvell,pins = "mpp4", "mpp5";
++ };
++
+ pmx_power_hdd: pmx-power-hdd {
+ marvell,pins = "mpp10";
+ marvell,function = "gpo";
+--
+2.35.1
+
--- /dev/null
+From 919b50232363ebeaa615f7d3ac12380ad34da4a1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 02:10:25 +0200
+Subject: ARM: dts: kirkwood: lsxl: remove first ethernet port
+
+From: Michael Walle <michael@walle.cc>
+
+[ Upstream commit 2d528eda7c96ce5c70f895854ecd5684bd5d80b9 ]
+
+Both the Linkstation LS-CHLv2 and the LS-XHL have only one ethernet
+port. This has always been wrong, i.e. the board code used to set up
+both ports, but the driver will play nice and return -ENODEV if the
+assiciated PHY is not found. Nevertheless, it is wrong. Remove it.
+
+Fixes: 876e23333511 ("ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes")
+Signed-off-by: Michael Walle <michael@walle.cc>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/kirkwood-lsxl.dtsi | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+index 321a40a98ed2..88b70ba1c8fe 100644
+--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
++++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+@@ -218,22 +218,11 @@
+ &mdio {
+ status = "okay";
+
+- ethphy0: ethernet-phy@0 {
+- reg = <0>;
+- };
+-
+ ethphy1: ethernet-phy@8 {
+ reg = <8>;
+ };
+ };
+
+-ð0 {
+- status = "okay";
+- ethernet0-port@0 {
+- phy-handle = <ðphy0>;
+- };
+-};
+-
+ ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+--
+2.35.1
+
--- /dev/null
+From a094ef3016e3098ced5b78a836d76f846774648d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 14:56:10 +0200
+Subject: ARM: dts: turris-omnia: Fix mpp26 pin name and comment
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Marek Behún <kabel@kernel.org>
+
+[ Upstream commit 49e93898f0dc177e645c22d0664813567fd9ec00 ]
+
+There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
+which is routed to CN11 pin header, is documented as SPI CS1, but
+MPP[26] pin does not support this function. Instead it controls chip
+select 2 if in "spi0" mode.
+
+Fix the name of the pin node in pinctrl node and fix the comment in SPI
+node.
+
+Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
+Signed-off-by: Marek Behún <kabel@kernel.org>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
+index 5bd6a66d2c2b..01b0dfd55d70 100644
+--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
++++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
+@@ -471,7 +471,7 @@
+ marvell,function = "spi0";
+ };
+
+- spi0cs1_pins: spi0cs1-pins {
++ spi0cs2_pins: spi0cs2-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "spi0";
+ };
+@@ -506,7 +506,7 @@
+ };
+ };
+
+- /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
++ /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
+ };
+
+ &uart0 {
+--
+2.35.1
+
--- /dev/null
+From daccf502c8feda9f70fcd8de3301b7950479aa83 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Sep 2022 21:55:50 +0200
+Subject: ARM: orion: fix include path
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+[ Upstream commit 63872304bdb3decd5454f4dd210c25395278ed13 ]
+
+Now that CONFIG_ARCH_MULTIPLATFORM can be disabled anywhere,
+there is a build failure for plat-orion:
+
+arch/arm/plat-orion/irq.c:19:10: fatal error: plat/irq.h: No such file or directory
+
+Make the include path unconditional.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/plat-orion/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
+index 4e3f25de13c1..830b0be038c6 100644
+--- a/arch/arm/plat-orion/Makefile
++++ b/arch/arm/plat-orion/Makefile
+@@ -2,7 +2,7 @@
+ #
+ # Makefile for the linux kernel.
+ #
+-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
++ccflags-y := -I$(srctree)/$(src)/include
+
+ orion-gpio-$(CONFIG_GPIOLIB) += gpio.o
+ obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
+--
+2.35.1
+
--- /dev/null
+From f47c5966950293b14cd7ad02433a89c5b2b38a10 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 15 Sep 2022 08:28:54 +0200
+Subject: arm64: dts: imx8mp: Add snps,gfladj-refclk-lpm-sel quirk to USB nodes
+
+From: Alexander Stein <alexander.stein@ew.tq-group.com>
+
+[ Upstream commit 5c3d5ecf48ab06c709c012bf1e8f0c91e1fcd7ad ]
+
+With this set the SOF/ITP counter is based on ref_clk when 2.0 ports are
+suspended.
+snps,dis-u2-freeclk-exists-quirk can be removed as
+snps,gfladj-refclk-lpm-sel also clears the free running clock configuration
+bit.
+
+Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
+Link: https://lore.kernel.org/r/20220915062855.751881-4-alexander.stein@ew.tq-group.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+index 9b07b26230a1..664177ed38d3 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+@@ -912,7 +912,7 @@
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+- snps,dis-u2-freeclk-exists-quirk;
++ snps,gfladj-refclk-lpm-sel-quirk;
+ };
+
+ };
+@@ -953,7 +953,7 @@
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+- snps,dis-u2-freeclk-exists-quirk;
++ snps,gfladj-refclk-lpm-sel-quirk;
+ };
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 92addcb59a7ab8913ac18da71a24d96c7e828c72 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 10:42:13 +0200
+Subject: arm64: dts: imx8mq-librem5: Add bq25895 as max17055's power supply
+
+From: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
+
+[ Upstream commit 6effe295e1a87408033c29dbcea9d5a5c8b937d5 ]
+
+This allows the userspace to notice that there's not enough
+current provided to charge the battery, and also fixes issues
+with 0% SOC values being considered invalid.
+
+Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
+Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+index 460ef0d86540..c86cd20d4e70 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+@@ -967,6 +967,7 @@
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gauge>;
++ power-supplies = <&bq25895>;
+ maxim,over-heat-temp = <700>;
+ maxim,over-volt = <4500>;
+ maxim,rsns-microohm = <5000>;
+--
+2.35.1
+
--- /dev/null
+From fbd40c1cd9ba16a24ba64085b7d71c81c01ade89 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 Aug 2022 10:35:07 +0530
+Subject: arm64: dts: qcom: sc7280: Cleanup the lpasscc node
+
+From: Satya Priya <quic_c_skakit@quicinc.com>
+
+[ Upstream commit 8c7ebabd2e3f33ef24378d3cac00d3e59886cecb ]
+
+Remove "cc" regmap from lpasscc node which is overlapping
+with the lpass_aon regmap.
+
+Fixes: 422a295221bb ("arm64: dts: qcom: sc7280: Add clock controller nodes")
+Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
+Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/1660107909-27947-2-git-send-email-quic_c_skakit@quicinc.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
+index b795a9993cc1..9405b405b3fb 100644
+--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
+@@ -634,9 +634,8 @@
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+- <0 0x03c04000 0 0x4>,
+- <0 0x03389000 0 0x24>;
+- reg-names = "qdsp6ss", "top_cc", "cc";
++ <0 0x03c04000 0 0x4>;
++ reg-names = "qdsp6ss", "top_cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+--
+2.35.1
+
--- /dev/null
+From 01af1fb68d790b9e272142c8153123340ea68b64 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 28 Aug 2022 11:43:38 +0300
+Subject: arm64: dts: qcom: sc7280-idp: correct ADC channel node name and unit
+ address
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit 5589ffb2da2a66988ab3a68334dad3e68b42e3a9 ]
+
+Correct SPMI PMIC VADC channel node name:
+1. Use hyphens instead of underscores,
+2. Add missing unit address.
+
+This fixes `make dtbs_check` warnings like:
+
+ qcom/sc7280-idp.dtb: pmic@0: adc@3100: 'pmk8350_die_temp', 'pmr735a_die_temp' do not match any of the regexes: '^.*@[0-9a-f]+$', 'pinctrl-[0-9]+'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Stephen Boyd <sboyd@kernel.org>
+Reviewed-by: Vinod Koul <vkoul@kernel.org>
+Reviewed-by: David Heidelberg <david@ixit.cz>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220828084341.112146-12-krzysztof.kozlowski@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
+ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+index 64fc22aff33d..0b4bcc34b794 100644
+--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
++++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+@@ -62,7 +62,7 @@
+ };
+
+ &pmk8350_vadc {
+- pmr735a_die_temp {
++ pmr735a-die-temp@403 {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ label = "pmr735a_die_temp";
+ qcom,pre-scaling = <1 1>;
+diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+index 371a2a9dcf7a..1948b8011d2b 100644
+--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
++++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+@@ -200,7 +200,7 @@
+ };
+
+ &pmk8350_vadc {
+- pmk8350_die_temp {
++ pmk8350-die-temp@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+--
+2.35.1
+
--- /dev/null
+From b06496f6e669d25307e4015cecd8b2d40cf47341 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Jul 2022 13:37:47 +0200
+Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
+
+The Last Level Cache Controller (LLCC) device does not need to access
+entire LLCC address space. Currently driver uses only hardware info and
+status registers which both reside in LLCC0_COMMON range (offset
+0x30000, size 0x1000). Narrow the address space to allow binding other
+drivers to rest of LLCC address space.
+
+Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
+Cc: Sibi Sankar <quic_sibis@quicinc.com>
+Reported-by: Steev Klimaszewski <steev@kali.org>
+Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Tested-by: Steev Klimaszewski <steev@kali.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+index ea7a272d267a..ce523ec8dd28 100644
+--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+@@ -1968,7 +1968,7 @@
+
+ system-cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
++ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+--
+2.35.1
+
--- /dev/null
+From 4ccc11c6a998ed988bb4480db09d35a16aff830a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 13:57:23 -0700
+Subject: arm64: dts: ti: k3-j7200: fix main pinmux range
+
+From: Matt Ranostay <mranostay@ti.com>
+
+[ Upstream commit 0d0a0b4413460383331088b2203ba09a6971bc3a ]
+
+Range size of 0x2b4 was incorrect since there isn't 173 configurable
+pins for muxing. Additionally there is a non-addressable region in the
+mapping which requires splitting into two ranges.
+
+main_pmx0 -> 67 pins
+main_pmx1 -> 3 pins
+
+Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
+Signed-off-by: Matt Ranostay <mranostay@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
+Link: https://lore.kernel.org/r/20220919205723.8342-1-mranostay@ti.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 10 ++++++----
+ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 11 ++++++++++-
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+index d14f3c18b65f..c3406e7f10a9 100644
+--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
++++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+@@ -131,15 +131,17 @@
+ >;
+ };
+
+- main_usbss0_pins_default: main-usbss0-pins-default {
++ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
++ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
+ >;
+ };
++};
+
+- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
++&main_pmx1 {
++ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
++ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+ >;
+ };
+ };
+diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+index 000b5732ea0c..b1df17525dea 100644
+--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+@@ -295,7 +295,16 @@
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+- reg = <0x00 0x11c000 0x00 0x2b4>;
++ reg = <0x00 0x11c000 0x00 0x10c>;
++ #pinctrl-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <0xffffffff>;
++ };
++
++ main_pmx1: pinctrl@11c11c {
++ compatible = "pinctrl-single";
++ /* Proxy 0 addressing */
++ reg = <0x00 0x11c11c 0x00 0xc>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+--
+2.35.1
+
--- /dev/null
+From cf893ac7f2414bcf92b3b8a076db6850e30a664f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 13:23:18 +0900
+Subject: arm64: dts: uniphier: Add USB-device support for PXs3 reference board
+
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+[ Upstream commit 19fee1a1096d21ab1f1e712148b5417bda2939a2 ]
+
+PXs3 reference board can change each USB port 0 and 1 to device mode
+with jumpers. Prepare devicetree sources for USB port 0 and 1.
+
+This specifies dr_mode, pinctrl, and some quirks and removes nodes for
+unused phys and vbus-supply properties.
+
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Link: https://lore.kernel.org/r/20220913042321.4817-8-hayashi.kunihiko@socionext.com'
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/uniphier-pinctrl.dtsi | 10 +++++
+ arch/arm64/boot/dts/socionext/Makefile | 4 +-
+ .../socionext/uniphier-pxs3-ref-gadget0.dts | 41 +++++++++++++++++++
+ .../socionext/uniphier-pxs3-ref-gadget1.dts | 40 ++++++++++++++++++
+ 4 files changed, 94 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
+ create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
+
+diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+index c0fd029b37e5..f909ec2e5333 100644
+--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
++++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+@@ -196,11 +196,21 @@
+ function = "usb0";
+ };
+
++ pinctrl_usb0_device: usb0-device {
++ groups = "usb0_device";
++ function = "usb0";
++ };
++
+ pinctrl_usb1: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
++ pinctrl_usb1_device: usb1-device {
++ groups = "usb1_device";
++ function = "usb1";
++ };
++
+ pinctrl_usb2: usb2 {
+ groups = "usb2";
+ function = "usb2";
+diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
+index dda3da33614b..33989a9643ac 100644
+--- a/arch/arm64/boot/dts/socionext/Makefile
++++ b/arch/arm64/boot/dts/socionext/Makefile
+@@ -5,4 +5,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ld20-akebi96.dtb \
+ uniphier-ld20-global.dtb \
+ uniphier-ld20-ref.dtb \
+- uniphier-pxs3-ref.dtb
++ uniphier-pxs3-ref.dtb \
++ uniphier-pxs3-ref-gadget0.dtb \
++ uniphier-pxs3-ref-gadget1.dtb
+diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
+new file mode 100644
+index 000000000000..7069f51bc120
+--- /dev/null
++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
+@@ -0,0 +1,41 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++//
++// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #0)
++//
++// Copyright (C) 2021 Socionext Inc.
++// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
++
++/dts-v1/;
++#include "uniphier-pxs3-ref.dts"
++
++/ {
++ model = "UniPhier PXs3 Reference Board (USB-Device #0)";
++};
++
++/* I2C3 pinctrl is shared with USB*VBUSIN */
++&i2c3 {
++ status = "disabled";
++};
++
++&usb0 {
++ status = "okay";
++ dr_mode = "peripheral";
++ pinctrl-0 = <&pinctrl_usb0_device>;
++ snps,dis_enblslpm_quirk;
++ snps,dis_u2_susphy_quirk;
++ snps,dis_u3_susphy_quirk;
++ snps,usb2_gadget_lpm_disable;
++ phy-names = "usb2-phy", "usb3-phy";
++ phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
++};
++
++&usb0_hsphy0 {
++ /delete-property/ vbus-supply;
++};
++
++&usb0_ssphy0 {
++ /delete-property/ vbus-supply;
++};
++
++/delete-node/ &usb0_hsphy1;
++/delete-node/ &usb0_ssphy1;
+diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
+new file mode 100644
+index 000000000000..a3cfa8113ffb
+--- /dev/null
++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++//
++// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #1)
++//
++// Copyright (C) 2021 Socionext Inc.
++// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
++
++/dts-v1/;
++#include "uniphier-pxs3-ref.dts"
++
++/ {
++ model = "UniPhier PXs3 Reference Board (USB-Device #1)";
++};
++
++/* I2C3 pinctrl is shared with USB*VBUSIN */
++&i2c3 {
++ status = "disabled";
++};
++
++&usb1 {
++ status = "okay";
++ dr_mode = "peripheral";
++ pinctrl-0 = <&pinctrl_usb1_device>;
++ snps,dis_enblslpm_quirk;
++ snps,dis_u2_susphy_quirk;
++ snps,dis_u3_susphy_quirk;
++ snps,usb2_gadget_lpm_disable;
++ phy-names = "usb2-phy", "usb3-phy";
++ phys = <&usb1_hsphy0>, <&usb1_ssphy0>;
++};
++
++&usb1_hsphy0 {
++ /delete-property/ vbus-supply;
++};
++
++&usb1_ssphy0 {
++ /delete-property/ vbus-supply;
++};
++
++/delete-node/ &usb1_hsphy1;
+--
+2.35.1
+
--- /dev/null
+From 498a47d69b5073c9d35a6d70f8b9665dab049cf8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 14:45:25 +0100
+Subject: arm64: ftrace: fix module PLTs with mcount
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+[ Upstream commit 8cfb08575c6d4585f1ce0deeb189e5c824776b04 ]
+
+Li Huafei reports that mcount-based ftrace with module PLTs was broken
+by commit:
+
+ a6253579977e4c6f ("arm64: ftrace: consistently handle PLTs.")
+
+When a module PLTs are used and a module is loaded sufficiently far away
+from the kernel, we'll create PLTs for any branches which are
+out-of-range. These are separate from the special ftrace trampoline
+PLTs, which the module PLT code doesn't directly manipulate.
+
+When mcount is in use this is a problem, as each mcount callsite in a
+module will be initialized to point to a module PLT, but since commit
+a6253579977e4c6f ftrace_make_nop() will assume that the callsite has
+been initialized to point to the special ftrace trampoline PLT, and
+ftrace_find_callable_addr() rejects other cases.
+
+This means that when ftrace tries to initialize a callsite via
+ftrace_make_nop(), the call to ftrace_find_callable_addr() will find
+that the `_mcount` stub is out-of-range and is not handled by the ftrace
+PLT, resulting in a splat:
+
+| ftrace_test: loading out-of-tree module taints kernel.
+| ftrace: no module PLT for _mcount
+| ------------[ ftrace bug ]------------
+| ftrace failed to modify
+| [<ffff800029180014>] 0xffff800029180014
+| actual: 44:00:00:94
+| Initializing ftrace call sites
+| ftrace record flags: 2000000
+| (0)
+| expected tramp: ffff80000802eb3c
+| ------------[ cut here ]------------
+| WARNING: CPU: 3 PID: 157 at kernel/trace/ftrace.c:2120 ftrace_bug+0x94/0x270
+| Modules linked in:
+| CPU: 3 PID: 157 Comm: insmod Tainted: G O 6.0.0-rc6-00151-gcd722513a189-dirty #22
+| Hardware name: linux,dummy-virt (DT)
+| pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+| pc : ftrace_bug+0x94/0x270
+| lr : ftrace_bug+0x21c/0x270
+| sp : ffff80000b2bbaf0
+| x29: ffff80000b2bbaf0 x28: 0000000000000000 x27: ffff0000c4d38000
+| x26: 0000000000000001 x25: ffff800009d7e000 x24: ffff0000c4d86e00
+| x23: 0000000002000000 x22: ffff80000a62b000 x21: ffff8000098ebea8
+| x20: ffff0000c4d38000 x19: ffff80000aa24158 x18: ffffffffffffffff
+| x17: 0000000000000000 x16: 0a0d2d2d2d2d2d2d x15: ffff800009aa9118
+| x14: 0000000000000000 x13: 6333626532303830 x12: 3030303866666666
+| x11: 203a706d61727420 x10: 6465746365707865 x9 : 3362653230383030
+| x8 : c0000000ffffefff x7 : 0000000000017fe8 x6 : 000000000000bff4
+| x5 : 0000000000057fa8 x4 : 0000000000000000 x3 : 0000000000000001
+| x2 : ad2cb14bb5438900 x1 : 0000000000000000 x0 : 0000000000000022
+| Call trace:
+| ftrace_bug+0x94/0x270
+| ftrace_process_locs+0x308/0x430
+| ftrace_module_init+0x44/0x60
+| load_module+0x15b4/0x1ce8
+| __do_sys_init_module+0x1ec/0x238
+| __arm64_sys_init_module+0x24/0x30
+| invoke_syscall+0x54/0x118
+| el0_svc_common.constprop.4+0x84/0x100
+| do_el0_svc+0x3c/0xd0
+| el0_svc+0x1c/0x50
+| el0t_64_sync_handler+0x90/0xb8
+| el0t_64_sync+0x15c/0x160
+| ---[ end trace 0000000000000000 ]---
+| ---------test_init-----------
+
+Fix this by reverting to the old behaviour of ignoring the old
+instruction when initialising an mcount callsite in a module, which was
+the behaviour prior to commit a6253579977e4c6f.
+
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Fixes: a6253579977e ("arm64: ftrace: consistently handle PLTs.")
+Reported-by: Li Huafei <lihuafei1@huawei.com>
+Link: https://lore.kernel.org/linux-arm-kernel/20220929094134.99512-1-lihuafei1@huawei.com
+Cc: Ard Biesheuvel <ardb@kernel.org>
+Cc: Will Deacon <will@kernel.org>
+Link: https://lore.kernel.org/r/20220929134525.798593-1-mark.rutland@arm.com
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/kernel/ftrace.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
+index ae0248154981..dba774f3b8d7 100644
+--- a/arch/arm64/kernel/ftrace.c
++++ b/arch/arm64/kernel/ftrace.c
+@@ -217,11 +217,26 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
+ unsigned long pc = rec->ip;
+ u32 old = 0, new;
+
++ new = aarch64_insn_gen_nop();
++
++ /*
++ * When using mcount, callsites in modules may have been initalized to
++ * call an arbitrary module PLT (which redirects to the _mcount stub)
++ * rather than the ftrace PLT we'll use at runtime (which redirects to
++ * the ftrace trampoline). We can ignore the old PLT when initializing
++ * the callsite.
++ *
++ * Note: 'mod' is only set at module load time.
++ */
++ if (!IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS) &&
++ IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && mod) {
++ return aarch64_insn_patch_text_nosync((void *)pc, new);
++ }
++
+ if (!ftrace_find_callable_addr(rec, mod, &addr))
+ return -EINVAL;
+
+ old = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
+- new = aarch64_insn_gen_nop();
+
+ return ftrace_modify_code(pc, old, new, true);
+ }
+--
+2.35.1
+
--- /dev/null
+From d142e3103d8d9191fba4e1ffd56b2cb0f731f87d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 20:47:39 +0800
+Subject: arm64: run softirqs on the per-CPU IRQ stack
+
+From: Qi Zheng <zhengqi.arch@bytedance.com>
+
+[ Upstream commit 8eb858c44b98e0326bb32fca34ae671995cd73bb ]
+
+Currently arm64 supports per-CPU IRQ stack, but softirqs
+are still handled in the task context.
+
+Since any call to local_bh_enable() at any level in the task's
+call stack may trigger a softirq processing run, which could
+potentially cause a task stack overflow if the combined stack
+footprints exceed the stack's size, let's run these softirqs
+on the IRQ stack as well.
+
+Signed-off-by: Qi Zheng <zhengqi.arch@bytedance.com>
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Will Deacon <will@kernel.org>
+Link: https://lore.kernel.org/r/20220815124739.15948-1-zhengqi.arch@bytedance.com
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/Kconfig | 1 +
+ arch/arm64/kernel/irq.c | 14 ++++++++++++++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+index 1e5a03d51d46..73f411975357 100644
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -221,6 +221,7 @@ config ARM64
+ select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
+ select TRACE_IRQFLAGS_SUPPORT
+ select TRACE_IRQFLAGS_NMI_SUPPORT
++ select HAVE_SOFTIRQ_ON_OWN_STACK
+ help
+ ARM 64-bit (AArch64) Linux support.
+
+diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
+index bda49430c9ea..38dbd3828f13 100644
+--- a/arch/arm64/kernel/irq.c
++++ b/arch/arm64/kernel/irq.c
+@@ -21,7 +21,9 @@
+ #include <linux/seq_file.h>
+ #include <linux/vmalloc.h>
+ #include <asm/daifflags.h>
++#include <asm/exception.h>
+ #include <asm/vmap_stack.h>
++#include <asm/softirq_stack.h>
+
+ /* Only access this in an NMI enter/exit */
+ DEFINE_PER_CPU(struct nmi_ctx, nmi_contexts);
+@@ -71,6 +73,18 @@ static void init_irq_stacks(void)
+ }
+ #endif
+
++#ifndef CONFIG_PREEMPT_RT
++static void ____do_softirq(struct pt_regs *regs)
++{
++ __do_softirq();
++}
++
++void do_softirq_own_stack(void)
++{
++ call_on_irq_stack(NULL, ____do_softirq);
++}
++#endif
++
+ static void default_handle_irq(struct pt_regs *regs)
+ {
+ panic("IRQ taken without a root IRQ handler\n");
+--
+2.35.1
+
--- /dev/null
+From 88fdad486a8ec61ad3d5b02c94b9b8443761778f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 18:01:05 +0100
+Subject: ASoC: codecs: tx-macro: fix kcontrol put
+
+From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+[ Upstream commit c1057a08af438e0cf5450c1d977a3011198ed2f8 ]
+
+tx_macro_tx_mixer_put() and tx_macro_dec_mode_put() currently returns zero
+eventhough it changes the value.
+Fix this, so that change notifications are sent correctly.
+
+Fixes: d207bdea0ca9 ("ASoC: codecs: lpass-tx-macro: add dapm widgets and route")
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20220906170112.1984-6-srinivas.kandagatla@linaro.org
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/lpass-tx-macro.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
+index e4bbc6bd4925..feafb8a90ffe 100644
+--- a/sound/soc/codecs/lpass-tx-macro.c
++++ b/sound/soc/codecs/lpass-tx-macro.c
+@@ -815,17 +815,23 @@ static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
+ struct tx_macro *tx = snd_soc_component_get_drvdata(component);
+
+ if (enable) {
++ if (tx->active_decimator[dai_id] == dec_id)
++ return 0;
++
+ set_bit(dec_id, &tx->active_ch_mask[dai_id]);
+ tx->active_ch_cnt[dai_id]++;
+ tx->active_decimator[dai_id] = dec_id;
+ } else {
++ if (tx->active_decimator[dai_id] == -1)
++ return 0;
++
+ tx->active_ch_cnt[dai_id]--;
+ clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
+ tx->active_decimator[dai_id] = -1;
+ }
+ snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
+
+- return 0;
++ return 1;
+ }
+
+ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
+@@ -1011,9 +1017,12 @@ static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
+ int path = e->shift_l;
+ struct tx_macro *tx = snd_soc_component_get_drvdata(component);
+
++ if (tx->dec_mode[path] == value)
++ return 0;
++
+ tx->dec_mode[path] = value;
+
+- return 0;
++ return 1;
+ }
+
+ static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
+--
+2.35.1
+
--- /dev/null
+From ac54d29579e41cb74732cd0dc7327c77ba6fc36b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 21:44:57 +0200
+Subject: ASoC: da7219: Fix an error handling path in
+ da7219_register_dai_clks()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit abb4e4349afe7eecdb0499582f1c777031e3a7c8 ]
+
+If clk_hw_register() fails, the corresponding clk should not be
+unregistered.
+
+To handle errors from loops, clean up partial iterations before doing the
+goto. So add a clk_hw_unregister().
+Then use a while (--i >= 0) loop in the unwind section.
+
+Fixes: 78013a1cf297 ("ASoC: da7219: Fix clock handling around codec level probe")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
+Link: https://lore.kernel.org/r/e4acceab57a0d9e477a8d5890a45c5309e553e7c.1663875789.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/da7219.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
+index c7493549a9a5..da4c24b8dae5 100644
+--- a/sound/soc/codecs/da7219.c
++++ b/sound/soc/codecs/da7219.c
+@@ -2196,6 +2196,7 @@ static int da7219_register_dai_clks(struct snd_soc_component *component)
+ dai_clk_lookup = clkdev_hw_create(dai_clk_hw, init.name,
+ "%s", dev_name(dev));
+ if (!dai_clk_lookup) {
++ clk_hw_unregister(dai_clk_hw);
+ ret = -ENOMEM;
+ goto err;
+ } else {
+@@ -2217,12 +2218,12 @@ static int da7219_register_dai_clks(struct snd_soc_component *component)
+ return 0;
+
+ err:
+- do {
++ while (--i >= 0) {
+ if (da7219->dai_clks_lookup[i])
+ clkdev_drop(da7219->dai_clks_lookup[i]);
+
+ clk_hw_unregister(&da7219->dai_clks_hw[i]);
+- } while (i-- > 0);
++ }
+
+ if (np)
+ kfree(da7219->clk_hw_data);
+--
+2.35.1
+
--- /dev/null
+From a27c6fff0bd3646f06086a74171e4caac5c5454c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 21:43:54 +0800
+Subject: ASoC: eureka-tlv320: Hold reference returned from of_find_xxx API
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit bfb735a3ceff0bab6473bac275da96f9b2a06dec ]
+
+In eukrea_tlv320_probe(), we need to hold the reference returned
+from of_find_compatible_node() which has increased the refcount
+and then call of_node_put() with it when done.
+
+Fixes: 66f232908de2 ("ASoC: eukrea-tlv320: Add DT support.")
+Co-authored-by: Kelin Wang <wangkelin2023@163.com>
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220914134354.3995587-1-windhl@126.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/fsl/eukrea-tlv320.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/fsl/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
+index e13271ea84de..29cf9234984d 100644
+--- a/sound/soc/fsl/eukrea-tlv320.c
++++ b/sound/soc/fsl/eukrea-tlv320.c
+@@ -86,7 +86,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev)
+ int ret;
+ int int_port = 0, ext_port;
+ struct device_node *np = pdev->dev.of_node;
+- struct device_node *ssi_np = NULL, *codec_np = NULL;
++ struct device_node *ssi_np = NULL, *codec_np = NULL, *tmp_np = NULL;
+
+ eukrea_tlv320.dev = &pdev->dev;
+ if (np) {
+@@ -143,7 +143,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev)
+ }
+
+ if (machine_is_eukrea_cpuimx27() ||
+- of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux")) {
++ (tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux"))) {
+ imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+ IMX_AUDMUX_V1_PCR_SYN |
+ IMX_AUDMUX_V1_PCR_TFSDIR |
+@@ -158,10 +158,11 @@ static int eukrea_tlv320_probe(struct platform_device *pdev)
+ IMX_AUDMUX_V1_PCR_SYN |
+ IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+ );
++ of_node_put(tmp_np);
+ } else if (machine_is_eukrea_cpuimx25sd() ||
+ machine_is_eukrea_cpuimx35sd() ||
+ machine_is_eukrea_cpuimx51sd() ||
+- of_find_compatible_node(NULL, NULL, "fsl,imx31-audmux")) {
++ (tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx31-audmux"))) {
+ if (!np)
+ ext_port = machine_is_eukrea_cpuimx25sd() ?
+ 4 : 3;
+@@ -178,6 +179,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev)
+ IMX_AUDMUX_V2_PTCR_SYN,
+ IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)
+ );
++ of_node_put(tmp_np);
+ } else {
+ if (np) {
+ /* The eukrea,asoc-tlv320 driver was explicitly
+--
+2.35.1
+
--- /dev/null
+From 661c6eca65ed508882d4532a0934a82ff9a23e3a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Aug 2022 14:01:26 +0300
+Subject: ASoC: mt6359: fix tests for platform_get_irq() failure
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 51eea3a6fb4d39c2cc71824e6eee5949d7ae4d1c ]
+
+The platform_get_irq() returns negative error codes. It can't actually
+return zero, but if it did that should be treated as success.
+
+Fixes: eef07b9e0925 ("ASoC: mediatek: mt6359: add MT6359 accdet jack driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Link: https://lore.kernel.org/r/YvThhr86N3qQM2EO@kili
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/mt6359-accdet.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c
+index c190628e2905..7f624854948c 100644
+--- a/sound/soc/codecs/mt6359-accdet.c
++++ b/sound/soc/codecs/mt6359-accdet.c
+@@ -965,7 +965,7 @@ static int mt6359_accdet_probe(struct platform_device *pdev)
+ mutex_init(&priv->res_lock);
+
+ priv->accdet_irq = platform_get_irq(pdev, 0);
+- if (priv->accdet_irq) {
++ if (priv->accdet_irq >= 0) {
+ ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq,
+ NULL, mt6359_accdet_irq,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+@@ -979,7 +979,7 @@ static int mt6359_accdet_probe(struct platform_device *pdev)
+
+ if (priv->caps & ACCDET_PMIC_EINT0) {
+ priv->accdet_eint0 = platform_get_irq(pdev, 1);
+- if (priv->accdet_eint0) {
++ if (priv->accdet_eint0 >= 0) {
+ ret = devm_request_threaded_irq(&pdev->dev,
+ priv->accdet_eint0,
+ NULL, mt6359_accdet_irq,
+@@ -994,7 +994,7 @@ static int mt6359_accdet_probe(struct platform_device *pdev)
+ }
+ } else if (priv->caps & ACCDET_PMIC_EINT1) {
+ priv->accdet_eint1 = platform_get_irq(pdev, 2);
+- if (priv->accdet_eint1) {
++ if (priv->accdet_eint1 >= 0) {
+ ret = devm_request_threaded_irq(&pdev->dev,
+ priv->accdet_eint1,
+ NULL, mt6359_accdet_irq,
+--
+2.35.1
+
--- /dev/null
+From bc0c8583cd464602b108bc9f94f8c7d65cad8bd2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 00:01:16 +0800
+Subject: ASoC: mt6660: Fix PM disable depth imbalance in mt6660_i2c_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit b73f11e895e140537e7f8c7251211ccd3ce0782b ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context. We fix it by moving
+pm_runtime_enable to the endding of mt6660_i2c_probe.
+
+Fixes:f289e55c6eeb4 ("ASoC: Add MediaTek MT6660 Speaker Amp Driver")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220928160116.125020-5-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/mt6660.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/codecs/mt6660.c b/sound/soc/codecs/mt6660.c
+index 358c500377df..a0a3fd60e93a 100644
+--- a/sound/soc/codecs/mt6660.c
++++ b/sound/soc/codecs/mt6660.c
+@@ -504,13 +504,17 @@ static int mt6660_i2c_probe(struct i2c_client *client,
+ dev_err(chip->dev, "read chip revision fail\n");
+ goto probe_fail;
+ }
+- pm_runtime_set_active(chip->dev);
+- pm_runtime_enable(chip->dev);
+
+ ret = devm_snd_soc_register_component(chip->dev,
+ &mt6660_component_driver,
+ &mt6660_codec_dai, 1);
++ if (!ret) {
++ pm_runtime_set_active(chip->dev);
++ pm_runtime_enable(chip->dev);
++ }
++
+ return ret;
++
+ probe_fail:
+ _mt6660_chip_power_on(chip, 0);
+ mutex_destroy(&chip->io_lock);
+--
+2.35.1
+
--- /dev/null
+From 840bc2b7b007fdf0cde7d43ea9a603fef5a820b4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 09:30:30 +0800
+Subject: ASoC: rsnd: Add check for rsnd_mod_power_on
+
+From: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+
+[ Upstream commit 376be51caf8871419bbcbb755e1e615d30dc3153 ]
+
+As rsnd_mod_power_on() can return negative numbers,
+it should be better to check the return value and
+deal with the exception.
+
+Fixes: e7d850dd10f4 ("ASoC: rsnd: use mod base common method on SSI-parent")
+Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Link: https://lore.kernel.org/r/20220902013030.3691266-1-jiasheng@iscas.ac.cn
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/sh/rcar/ctu.c | 6 +++++-
+ sound/soc/sh/rcar/dvc.c | 6 +++++-
+ sound/soc/sh/rcar/mix.c | 6 +++++-
+ sound/soc/sh/rcar/src.c | 5 ++++-
+ sound/soc/sh/rcar/ssi.c | 4 +++-
+ 5 files changed, 22 insertions(+), 5 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c
+index 6156445bcb69..e39eb2ac7e95 100644
+--- a/sound/soc/sh/rcar/ctu.c
++++ b/sound/soc/sh/rcar/ctu.c
+@@ -171,7 +171,11 @@ static int rsnd_ctu_init(struct rsnd_mod *mod,
+ struct rsnd_dai_stream *io,
+ struct rsnd_priv *priv)
+ {
+- rsnd_mod_power_on(mod);
++ int ret;
++
++ ret = rsnd_mod_power_on(mod);
++ if (ret < 0)
++ return ret;
+
+ rsnd_ctu_activation(mod);
+
+diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c
+index 5137e03a9d7c..16befcbc312c 100644
+--- a/sound/soc/sh/rcar/dvc.c
++++ b/sound/soc/sh/rcar/dvc.c
+@@ -186,7 +186,11 @@ static int rsnd_dvc_init(struct rsnd_mod *mod,
+ struct rsnd_dai_stream *io,
+ struct rsnd_priv *priv)
+ {
+- rsnd_mod_power_on(mod);
++ int ret;
++
++ ret = rsnd_mod_power_on(mod);
++ if (ret < 0)
++ return ret;
+
+ rsnd_dvc_activation(mod);
+
+diff --git a/sound/soc/sh/rcar/mix.c b/sound/soc/sh/rcar/mix.c
+index 3572c2c5686c..1de0e085804c 100644
+--- a/sound/soc/sh/rcar/mix.c
++++ b/sound/soc/sh/rcar/mix.c
+@@ -146,7 +146,11 @@ static int rsnd_mix_init(struct rsnd_mod *mod,
+ struct rsnd_dai_stream *io,
+ struct rsnd_priv *priv)
+ {
+- rsnd_mod_power_on(mod);
++ int ret;
++
++ ret = rsnd_mod_power_on(mod);
++ if (ret < 0)
++ return ret;
+
+ rsnd_mix_activation(mod);
+
+diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c
+index 0ea84ae57c6a..f832165e46bc 100644
+--- a/sound/soc/sh/rcar/src.c
++++ b/sound/soc/sh/rcar/src.c
+@@ -463,11 +463,14 @@ static int rsnd_src_init(struct rsnd_mod *mod,
+ struct rsnd_priv *priv)
+ {
+ struct rsnd_src *src = rsnd_mod_to_src(mod);
++ int ret;
+
+ /* reset sync convert_rate */
+ src->sync.val = 0;
+
+- rsnd_mod_power_on(mod);
++ ret = rsnd_mod_power_on(mod);
++ if (ret < 0)
++ return ret;
+
+ rsnd_src_activation(mod);
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index 43c5e27dc5c8..7ade6c5ed96f 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -480,7 +480,9 @@ static int rsnd_ssi_init(struct rsnd_mod *mod,
+
+ ssi->usrcnt++;
+
+- rsnd_mod_power_on(mod);
++ ret = rsnd_mod_power_on(mod);
++ if (ret < 0)
++ return ret;
+
+ rsnd_ssi_config_init(mod, io);
+
+--
+2.35.1
+
--- /dev/null
+From b61927883be5ebbfe9d7ca375e742c52a910461d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 13:44:29 +0200
+Subject: ASoC: SOF: pci: Change DMI match info to support all Chrome platforms
+
+From: Jairaj Arava <jairaj.arava@intel.com>
+
+[ Upstream commit c1c1fc8103f794a10c5c15e3c17879caf4f42c8f ]
+
+In some Chrome platforms if OEM's use their own string as SYS_VENDOR than
+"Google", it leads to firmware load failure from intel/sof/community path.
+
+Hence, changing SYS_VENDOR to PRODUCT_FAMILY in which "Google" is used
+as common prefix and is supported in all Chrome platforms.
+
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+Reviewed-by: Chao Song <chao.song@intel.com>
+Reviewed-by: Curtis Malainey <curtis@malainey.com>
+Signed-off-by: Jairaj Arava <jairaj.arava@intel.com>
+Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
+Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Link: https://lore.kernel.org/r/20220919114429.42700-1-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/sof/sof-pci-dev.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c
+index b773289c928d..3b4c011e0283 100644
+--- a/sound/soc/sof/sof-pci-dev.c
++++ b/sound/soc/sof/sof-pci-dev.c
+@@ -80,7 +80,7 @@ static const struct dmi_system_id community_key_platforms[] = {
+ {
+ .ident = "Google Chromebooks",
+ .matches = {
+- DMI_MATCH(DMI_SYS_VENDOR, "Google"),
++ DMI_MATCH(DMI_PRODUCT_FAMILY, "Google"),
+ }
+ },
+ {},
+--
+2.35.1
+
--- /dev/null
+From fa2c06562186170ebab4c12353761d442b98f7a2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 16:02:37 +0200
+Subject: ASoC: tas2764: Allow mono streams
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Martin Povišer <povik+lin@cutebit.org>
+
+[ Upstream commit 23204d928a27146d13e11c9383632775345ecca8 ]
+
+The part is a mono speaker amp, but it can do downmix and switch between
+left and right channel, so the right channel range is 1 to 2.
+
+(This mirrors commit bf54d97a835d ("ASoC: tas2770: Allow mono streams")
+which was a fix to the tas2770 driver.)
+
+Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764")
+Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
+Link: https://lore.kernel.org/r/20220825140241.53963-2-povik+lin@cutebit.org
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/tas2764.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
+index ec13ba01e522..d0b6c174186d 100644
+--- a/sound/soc/codecs/tas2764.c
++++ b/sound/soc/codecs/tas2764.c
+@@ -485,7 +485,7 @@ static struct snd_soc_dai_driver tas2764_dai_driver[] = {
+ .id = 0,
+ .playback = {
+ .stream_name = "ASI1 Playback",
+- .channels_min = 2,
++ .channels_min = 1,
+ .channels_max = 2,
+ .rates = TAS2764_RATES,
+ .formats = TAS2764_FORMATS,
+--
+2.35.1
+
--- /dev/null
+From 2680df1cf83722480dc1ad6d792e8b54728c309c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 16:02:38 +0200
+Subject: ASoC: tas2764: Drop conflicting set_bias_level power setting
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Martin Povišer <povik+lin@cutebit.org>
+
+[ Upstream commit 09273f38832406db19a8907a934687cc10660a6b ]
+
+The driver is setting the PWR_CTRL field in both the set_bias_level
+callback and on DAPM events of the DAC widget (and also in the
+mute_stream method). Drop the set_bias_level callback altogether as the
+power setting it does is in conflict with the other code paths.
+
+(This mirrors commit c8a6ae3fe1c8 ("ASoC: tas2770: Drop conflicting
+set_bias_level power setting") which was a fix to the tas2770 driver.)
+
+Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764")
+Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
+Link: https://lore.kernel.org/r/20220825140241.53963-3-povik+lin@cutebit.org
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/tas2764.c | 33 ---------------------------------
+ 1 file changed, 33 deletions(-)
+
+diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
+index d0b6c174186d..e76ce90c787f 100644
+--- a/sound/soc/codecs/tas2764.c
++++ b/sound/soc/codecs/tas2764.c
+@@ -50,38 +50,6 @@ static void tas2764_reset(struct tas2764_priv *tas2764)
+ usleep_range(1000, 2000);
+ }
+
+-static int tas2764_set_bias_level(struct snd_soc_component *component,
+- enum snd_soc_bias_level level)
+-{
+- struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+-
+- switch (level) {
+- case SND_SOC_BIAS_ON:
+- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_ACTIVE);
+- break;
+- case SND_SOC_BIAS_STANDBY:
+- case SND_SOC_BIAS_PREPARE:
+- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_MUTE);
+- break;
+- case SND_SOC_BIAS_OFF:
+- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_SHUTDOWN);
+- break;
+-
+- default:
+- dev_err(tas2764->dev,
+- "wrong power level setting %d\n", level);
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+ #ifdef CONFIG_PM
+ static int tas2764_codec_suspend(struct snd_soc_component *component)
+ {
+@@ -549,7 +517,6 @@ static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
+ .probe = tas2764_codec_probe,
+ .suspend = tas2764_codec_suspend,
+ .resume = tas2764_codec_resume,
+- .set_bias_level = tas2764_set_bias_level,
+ .controls = tas2764_snd_controls,
+ .num_controls = ARRAY_SIZE(tas2764_snd_controls),
+ .dapm_widgets = tas2764_dapm_widgets,
+--
+2.35.1
+
--- /dev/null
+From 099f3ff66e7a1a6d1cca7c0f02e0550c48c5c683 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 16:02:39 +0200
+Subject: ASoC: tas2764: Fix mute/unmute
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Martin Povišer <povik+lin@cutebit.org>
+
+[ Upstream commit f5ad67f13623548e5aff847f89700c178aaf2a98 ]
+
+Because the PWR_CTRL field is modeled as the power state of the DAC
+widget, and at the same time it is used to implement mute/unmute, we
+need some additional book-keeping to have the right end result no matter
+the sequence of calls. Without this fix, one permanently mutes an
+ongoing stream by toggling the associated speaker pin control.
+
+(This mirrors commit 1e5907bcb3a3 ("ASoC: tas2770: Fix handling of
+mute/unmute") which was a fix to the tas2770 driver.)
+
+Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764")
+Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
+Link: https://lore.kernel.org/r/20220825140241.53963-4-povik+lin@cutebit.org
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/tas2764.c | 57 +++++++++++++++++++++-----------------
+ 1 file changed, 32 insertions(+), 25 deletions(-)
+
+diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
+index e76ce90c787f..afb4c0d7e714 100644
+--- a/sound/soc/codecs/tas2764.c
++++ b/sound/soc/codecs/tas2764.c
+@@ -34,6 +34,9 @@ struct tas2764_priv {
+
+ int v_sense_slot;
+ int i_sense_slot;
++
++ bool dac_powered;
++ bool unmuted;
+ };
+
+ static void tas2764_reset(struct tas2764_priv *tas2764)
+@@ -50,6 +53,26 @@ static void tas2764_reset(struct tas2764_priv *tas2764)
+ usleep_range(1000, 2000);
+ }
+
++static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764)
++{
++ struct snd_soc_component *component = tas2764->component;
++ unsigned int val;
++ int ret;
++
++ if (tas2764->dac_powered)
++ val = tas2764->unmuted ?
++ TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE;
++ else
++ val = TAS2764_PWR_CTRL_SHUTDOWN;
++
++ ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
++ TAS2764_PWR_CTRL_MASK, val);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
+ #ifdef CONFIG_PM
+ static int tas2764_codec_suspend(struct snd_soc_component *component)
+ {
+@@ -82,9 +105,7 @@ static int tas2764_codec_resume(struct snd_soc_component *component)
+ usleep_range(1000, 2000);
+ }
+
+- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_ACTIVE);
++ ret = tas2764_update_pwr_ctrl(tas2764);
+
+ if (ret < 0)
+ return ret;
+@@ -118,14 +139,12 @@ static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_MUTE);
++ tas2764->dac_powered = true;
++ ret = tas2764_update_pwr_ctrl(tas2764);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_SHUTDOWN);
++ tas2764->dac_powered = false;
++ ret = tas2764_update_pwr_ctrl(tas2764);
+ break;
+ default:
+ dev_err(tas2764->dev, "Unsupported event\n");
+@@ -170,17 +189,11 @@ static const struct snd_soc_dapm_route tas2764_audio_map[] = {
+
+ static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
+ {
+- struct snd_soc_component *component = dai->component;
+- int ret;
+-
+- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- mute ? TAS2764_PWR_CTRL_MUTE : 0);
++ struct tas2764_priv *tas2764 =
++ snd_soc_component_get_drvdata(dai->component);
+
+- if (ret < 0)
+- return ret;
+-
+- return 0;
++ tas2764->unmuted = !mute;
++ return tas2764_update_pwr_ctrl(tas2764);
+ }
+
+ static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
+@@ -494,12 +507,6 @@ static int tas2764_codec_probe(struct snd_soc_component *component)
+ if (ret < 0)
+ return ret;
+
+- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+- TAS2764_PWR_CTRL_MASK,
+- TAS2764_PWR_CTRL_MUTE);
+- if (ret < 0)
+- return ret;
+-
+ return 0;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 241686b29f3f21f68e15d5c4accc52326f9b6d3a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 00:01:15 +0800
+Subject: ASoC: wm5102: Fix PM disable depth imbalance in wm5102_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit fcbb60820cd3008bb44334a0395e5e57ccb77329 ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context. We fix it by moving
+pm_runtime_enable to the endding of wm5102_probe.
+
+Fixes:93e8791dd34ca ("ASoC: wm5102: Initial driver")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220928160116.125020-4-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/wm5102.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
+index 621598608bf0..c8adce8936bc 100644
+--- a/sound/soc/codecs/wm5102.c
++++ b/sound/soc/codecs/wm5102.c
+@@ -2087,9 +2087,6 @@ static int wm5102_probe(struct platform_device *pdev)
+ regmap_update_bits(arizona->regmap, wm5102_digital_vu[i],
+ WM5102_DIG_VU, WM5102_DIG_VU);
+
+- pm_runtime_enable(&pdev->dev);
+- pm_runtime_idle(&pdev->dev);
+-
+ ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
+ "ADSP2 Compressed IRQ", wm5102_adsp2_irq,
+ wm5102);
+@@ -2122,6 +2119,9 @@ static int wm5102_probe(struct platform_device *pdev)
+ goto err_spk_irqs;
+ }
+
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_idle(&pdev->dev);
++
+ return ret;
+
+ err_spk_irqs:
+--
+2.35.1
+
--- /dev/null
+From d0bfcc6b0863627159721cd4f586670ff645786d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 00:01:14 +0800
+Subject: ASoC: wm5110: Fix PM disable depth imbalance in wm5110_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit 86b46bf1feb83898d89a2b4a8d08d21e9ea277a7 ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context. We fix it by moving
+pm_runtime_enable to the endding of wm5110_probe.
+
+Fixes:5c6af635fd772 ("ASoC: wm5110: Add audio CODEC driver")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220928160116.125020-3-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/wm5110.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
+index 7c6e01720d65..66a4827c16bd 100644
+--- a/sound/soc/codecs/wm5110.c
++++ b/sound/soc/codecs/wm5110.c
+@@ -2458,9 +2458,6 @@ static int wm5110_probe(struct platform_device *pdev)
+ regmap_update_bits(arizona->regmap, wm5110_digital_vu[i],
+ WM5110_DIG_VU, WM5110_DIG_VU);
+
+- pm_runtime_enable(&pdev->dev);
+- pm_runtime_idle(&pdev->dev);
+-
+ ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
+ "ADSP2 Compressed IRQ", wm5110_adsp2_irq,
+ wm5110);
+@@ -2493,6 +2490,9 @@ static int wm5110_probe(struct platform_device *pdev)
+ goto err_spk_irqs;
+ }
+
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_idle(&pdev->dev);
++
+ return ret;
+
+ err_spk_irqs:
+--
+2.35.1
+
--- /dev/null
+From d9068f95feba023e61c09a741a4e05844659058d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 00:01:13 +0800
+Subject: ASoC: wm8997: Fix PM disable depth imbalance in wm8997_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit 41a736ac20602f64773e80f0f5b32cde1830a44a ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context. We fix it by moving
+pm_runtime_enable to the endding of wm8997_probe
+
+Fixes:40843aea5a9bd ("ASoC: wm8997: Initial CODEC driver")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220928160116.125020-2-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/wm8997.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/codecs/wm8997.c b/sound/soc/codecs/wm8997.c
+index 38ef631d1a1f..c8c711e555c0 100644
+--- a/sound/soc/codecs/wm8997.c
++++ b/sound/soc/codecs/wm8997.c
+@@ -1162,9 +1162,6 @@ static int wm8997_probe(struct platform_device *pdev)
+ regmap_update_bits(arizona->regmap, wm8997_digital_vu[i],
+ WM8997_DIG_VU, WM8997_DIG_VU);
+
+- pm_runtime_enable(&pdev->dev);
+- pm_runtime_idle(&pdev->dev);
+-
+ arizona_init_common(arizona);
+
+ ret = arizona_init_vol_limit(arizona);
+@@ -1183,6 +1180,9 @@ static int wm8997_probe(struct platform_device *pdev)
+ goto err_spk_irqs;
+ }
+
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_idle(&pdev->dev);
++
+ return ret;
+
+ err_spk_irqs:
+--
+2.35.1
+
--- /dev/null
+From 99902ba2d8be77a798143961b6bd90db933bff36 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 14:28:33 +0200
+Subject: ata: fix ata_id_has_devslp()
+
+From: Niklas Cassel <niklas.cassel@wdc.com>
+
+[ Upstream commit 9c6e09a434e1317e09b78b3b69cd384022ec9a03 ]
+
+ACS-5 section
+7.13.6.36 Word 78: Serial ATA features supported
+states that:
+
+If word 76 is not 0000h or FFFFh, word 78 reports the features supported
+by the device. If this word is not supported, the word shall be cleared
+to zero.
+
+(This text also exists in really old ACS standards, e.g. ACS-3.)
+
+Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros
+(which already have this check), thus making it more likely that the
+next ATA_ID_FEATURE_SUPP macro that is added will include this check.
+
+Fixes: 65fe1f0f66a5 ("ahci: implement aggressive SATA device sleep support")
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/ata.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/include/linux/ata.h b/include/linux/ata.h
+index 5d43716e5047..0dab64eb5cbc 100644
+--- a/include/linux/ata.h
++++ b/include/linux/ata.h
+@@ -565,6 +565,10 @@ struct ata_bmdma_prd {
+ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
+ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
+ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 2)))
++#define ata_id_has_devslp(id) \
++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8)))
+ #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10))
+ #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11))
+ #define ata_id_u32(id,n) \
+@@ -577,7 +581,6 @@ struct ata_bmdma_prd {
+
+ #define ata_id_cdb_intr(id) (((id)[ATA_ID_CONFIG] & 0x60) == 0x20)
+ #define ata_id_has_da(id) ((id)[ATA_ID_SATA_CAPABILITY_2] & (1 << 4))
+-#define ata_id_has_devslp(id) ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8))
+ #define ata_id_has_ncq_autosense(id) \
+ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7))
+
+--
+2.35.1
+
--- /dev/null
+From 841d29a2eb64a91aa96b0b351bacf9c6af687269 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 14:28:35 +0200
+Subject: ata: fix ata_id_has_dipm()
+
+From: Niklas Cassel <niklas.cassel@wdc.com>
+
+[ Upstream commit 630624cb1b5826d753ac8e01a0e42de43d66dedf ]
+
+ACS-5 section
+7.13.6.36 Word 78: Serial ATA features supported
+states that:
+
+If word 76 is not 0000h or FFFFh, word 78 reports the features supported
+by the device. If this word is not supported, the word shall be cleared
+to zero.
+
+(This text also exists in really old ACS standards, e.g. ACS-3.)
+
+The problem with ata_id_has_dipm() is that the while it performs a
+check against 0 and 0xffff, it performs the check against
+ATA_ID_FEATURE_SUPP (word 78), the same word where the feature bit
+is stored.
+
+Fix this by performing the check against ATA_ID_SATA_CAPABILITY
+(word 76), like required by the spec. The feature bit check itself
+is of course still performed against ATA_ID_FEATURE_SUPP (word 78).
+
+Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros
+(which already have this check), thus making it more likely that the
+next ATA_ID_FEATURE_SUPP macro that is added will include this check.
+
+Fixes: ca77329fb713 ("[libata] Link power management infrastructure")
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/ata.h | 15 ++++-----------
+ 1 file changed, 4 insertions(+), 11 deletions(-)
+
+diff --git a/include/linux/ata.h b/include/linux/ata.h
+index 295a6c6b506d..3b1ad57d0e01 100644
+--- a/include/linux/ata.h
++++ b/include/linux/ata.h
+@@ -573,6 +573,10 @@ struct ata_bmdma_prd {
+ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
+ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
+ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7)))
++#define ata_id_has_dipm(id) \
++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 3)))
+ #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10))
+ #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11))
+ #define ata_id_u32(id,n) \
+@@ -596,17 +600,6 @@ static inline bool ata_id_has_hipm(const u16 *id)
+ return val & (1 << 9);
+ }
+
+-static inline bool ata_id_has_dipm(const u16 *id)
+-{
+- u16 val = id[ATA_ID_FEATURE_SUPP];
+-
+- if (val == 0 || val == 0xffff)
+- return false;
+-
+- return val & (1 << 3);
+-}
+-
+-
+ static inline bool ata_id_has_fua(const u16 *id)
+ {
+ if ((id[ATA_ID_CFSSE] & 0xC000) != 0x4000)
+--
+2.35.1
+
--- /dev/null
+From 7faf5964de5a1e31ef42aa369c47ebb737683db8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 14:28:34 +0200
+Subject: ata: fix ata_id_has_ncq_autosense()
+
+From: Niklas Cassel <niklas.cassel@wdc.com>
+
+[ Upstream commit a5fb6bf853148974dbde092ec1bde553bea5e49f ]
+
+ACS-5 section
+7.13.6.36 Word 78: Serial ATA features supported
+states that:
+
+If word 76 is not 0000h or FFFFh, word 78 reports the features supported
+by the device. If this word is not supported, the word shall be cleared
+to zero.
+
+(This text also exists in really old ACS standards, e.g. ACS-3.)
+
+Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros
+(which already have this check), thus making it more likely that the
+next ATA_ID_FEATURE_SUPP macro that is added will include this check.
+
+Fixes: 5b01e4b9efa0 ("libata: Implement NCQ autosense")
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/ata.h | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/include/linux/ata.h b/include/linux/ata.h
+index 0dab64eb5cbc..295a6c6b506d 100644
+--- a/include/linux/ata.h
++++ b/include/linux/ata.h
+@@ -569,6 +569,10 @@ struct ata_bmdma_prd {
+ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
+ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
+ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8)))
++#define ata_id_has_ncq_autosense(id) \
++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \
++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \
++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7)))
+ #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10))
+ #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11))
+ #define ata_id_u32(id,n) \
+@@ -581,8 +585,6 @@ struct ata_bmdma_prd {
+
+ #define ata_id_cdb_intr(id) (((id)[ATA_ID_CONFIG] & 0x60) == 0x20)
+ #define ata_id_has_da(id) ((id)[ATA_ID_SATA_CAPABILITY_2] & (1 << 4))
+-#define ata_id_has_ncq_autosense(id) \
+- ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7))
+
+ static inline bool ata_id_has_hipm(const u16 *id)
+ {
+--
+2.35.1
+
--- /dev/null
+From 5a7f6c184070389302fb66de0c01a614ac43fd10 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 14:28:32 +0200
+Subject: ata: fix ata_id_sense_reporting_enabled() and
+ ata_id_has_sense_reporting()
+
+From: Niklas Cassel <niklas.cassel@wdc.com>
+
+[ Upstream commit 690aa8c3ae308bc696ec8b1b357b995193927083 ]
+
+ACS-5 section
+7.13.6.41 Words 85..87, 120: Commands and feature sets supported or enabled
+states that:
+
+If bit 15 of word 86 is set to one, bit 14 of word 119 is set to one,
+and bit 15 of word 119 is cleared to zero, then word 119 is valid.
+
+If bit 15 of word 86 is set to one, bit 14 of word 120 is set to one,
+and bit 15 of word 120 is cleared to zero, then word 120 is valid.
+
+(This text also exists in really old ACS standards, e.g. ACS-3.)
+
+Currently, ata_id_sense_reporting_enabled() and
+ata_id_has_sense_reporting() both check bit 15 of word 86,
+but neither of them check that bit 14 of word 119 is set to one,
+or that bit 15 of word 119 is cleared to zero.
+
+Additionally, make ata_id_sense_reporting_enabled() return false
+if !ata_id_has_sense_reporting(), similar to how e.g.
+ata_id_flush_ext_enabled() returns false if !ata_id_has_flush_ext().
+
+Fixes: e87fd28cf9a2 ("libata: Implement support for sense data reporting")
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/ata.h | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/include/linux/ata.h b/include/linux/ata.h
+index 1b44f40c7700..5d43716e5047 100644
+--- a/include/linux/ata.h
++++ b/include/linux/ata.h
+@@ -770,16 +770,21 @@ static inline bool ata_id_has_read_log_dma_ext(const u16 *id)
+
+ static inline bool ata_id_has_sense_reporting(const u16 *id)
+ {
+- if (!(id[ATA_ID_CFS_ENABLE_2] & (1 << 15)))
++ if (!(id[ATA_ID_CFS_ENABLE_2] & BIT(15)))
++ return false;
++ if ((id[ATA_ID_COMMAND_SET_3] & (BIT(15) | BIT(14))) != BIT(14))
+ return false;
+- return id[ATA_ID_COMMAND_SET_3] & (1 << 6);
++ return id[ATA_ID_COMMAND_SET_3] & BIT(6);
+ }
+
+ static inline bool ata_id_sense_reporting_enabled(const u16 *id)
+ {
+- if (!(id[ATA_ID_CFS_ENABLE_2] & (1 << 15)))
++ if (!ata_id_has_sense_reporting(id))
++ return false;
++ /* ata_id_has_sense_reporting() == true, word 86 must have bit 15 set */
++ if ((id[ATA_ID_COMMAND_SET_4] & (BIT(15) | BIT(14))) != BIT(14))
+ return false;
+- return id[ATA_ID_COMMAND_SET_4] & (1 << 6);
++ return id[ATA_ID_COMMAND_SET_4] & BIT(6);
+ }
+
+ /**
+--
+2.35.1
+
--- /dev/null
+From c23ecfd5f913789c9a7cde6b6862b4fa7895a2d0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 22:36:06 +0300
+Subject: ata: libahci_platform: Sanity check the DT child nodes number
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit 3c132ea6508b34956e5ed88d04936983ec230601 ]
+
+Having greater than AHCI_MAX_PORTS (32) ports detected isn't that critical
+from the further AHCI-platform initialization point of view since
+exceeding the ports upper limit will cause allocating more resources than
+will be used afterwards. But detecting too many child DT-nodes doesn't
+seem right since it's very unlikely to have it on an ordinary platform. In
+accordance with the AHCI specification there can't be more than 32 ports
+implemented at least due to having the CAP.NP field of 5 bits wide and the
+PI register of dword size. Thus if such situation is found the DTB must
+have been corrupted and the data read from it shouldn't be reliable. Let's
+consider that as an erroneous situation and halt further resources
+allocation.
+
+Note it's logically more correct to have the nports set only after the
+initialization value is checked for being sane. So while at it let's make
+sure nports is assigned with a correct value.
+
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Reviewed-by: Hannes Reinecke <hare@suse.de>
+Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ata/libahci_platform.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
+index 0910441321f7..64d6da0a5303 100644
+--- a/drivers/ata/libahci_platform.c
++++ b/drivers/ata/libahci_platform.c
+@@ -451,14 +451,24 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
+ }
+ }
+
+- hpriv->nports = child_nodes = of_get_child_count(dev->of_node);
++ /*
++ * Too many sub-nodes most likely means having something wrong with
++ * the firmware.
++ */
++ child_nodes = of_get_child_count(dev->of_node);
++ if (child_nodes > AHCI_MAX_PORTS) {
++ rc = -EINVAL;
++ goto err_out;
++ }
+
+ /*
+ * If no sub-node was found, we still need to set nports to
+ * one in order to be able to use the
+ * ahci_platform_[en|dis]able_[phys|regulators] functions.
+ */
+- if (!child_nodes)
++ if (child_nodes)
++ hpriv->nports = child_nodes;
++ else
+ hpriv->nports = 1;
+
+ hpriv->phys = devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GFP_KERNEL);
+--
+2.35.1
+
--- /dev/null
+From 9ac7042da0309994f6f057cde364a6d04fd011a0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 00:16:47 +0800
+Subject: bcache: fix set_at_max_writeback_rate() for multiple attached devices
+
+From: Coly Li <colyli@suse.de>
+
+[ Upstream commit d2d05b88035d2d51a5bb6c5afec88a0880c73df4 ]
+
+Inside set_at_max_writeback_rate() the calculation in following if()
+check is wrong,
+ if (atomic_inc_return(&c->idle_counter) <
+ atomic_read(&c->attached_dev_nr) * 6)
+
+Because each attached backing device has its own writeback thread
+running and increasing c->idle_counter, the counter increates much
+faster than expected. The correct calculation should be,
+ (counter / dev_nr) < dev_nr * 6
+which equals to,
+ counter < dev_nr * dev_nr * 6
+
+This patch fixes the above mistake with correct calculation, and helper
+routine idle_counter_exceeded() is added to make code be more clear.
+
+Reported-by: Mingzhe Zou <mingzhe.zou@easystack.cn>
+Signed-off-by: Coly Li <colyli@suse.de>
+Acked-by: Mingzhe Zou <mingzhe.zou@easystack.cn>
+Link: https://lore.kernel.org/r/20220919161647.81238-6-colyli@suse.de
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/bcache/writeback.c | 73 +++++++++++++++++++++++++----------
+ 1 file changed, 52 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c
+index 96a07839864b..ee7ad999e924 100644
+--- a/drivers/md/bcache/writeback.c
++++ b/drivers/md/bcache/writeback.c
+@@ -157,6 +157,53 @@ static void __update_writeback_rate(struct cached_dev *dc)
+ dc->writeback_rate_target = target;
+ }
+
++static bool idle_counter_exceeded(struct cache_set *c)
++{
++ int counter, dev_nr;
++
++ /*
++ * If c->idle_counter is overflow (idel for really long time),
++ * reset as 0 and not set maximum rate this time for code
++ * simplicity.
++ */
++ counter = atomic_inc_return(&c->idle_counter);
++ if (counter <= 0) {
++ atomic_set(&c->idle_counter, 0);
++ return false;
++ }
++
++ dev_nr = atomic_read(&c->attached_dev_nr);
++ if (dev_nr == 0)
++ return false;
++
++ /*
++ * c->idle_counter is increased by writeback thread of all
++ * attached backing devices, in order to represent a rough
++ * time period, counter should be divided by dev_nr.
++ * Otherwise the idle time cannot be larger with more backing
++ * device attached.
++ * The following calculation equals to checking
++ * (counter / dev_nr) < (dev_nr * 6)
++ */
++ if (counter < (dev_nr * dev_nr * 6))
++ return false;
++
++ return true;
++}
++
++/*
++ * Idle_counter is increased every time when update_writeback_rate() is
++ * called. If all backing devices attached to the same cache set have
++ * identical dc->writeback_rate_update_seconds values, it is about 6
++ * rounds of update_writeback_rate() on each backing device before
++ * c->at_max_writeback_rate is set to 1, and then max wrteback rate set
++ * to each dc->writeback_rate.rate.
++ * In order to avoid extra locking cost for counting exact dirty cached
++ * devices number, c->attached_dev_nr is used to calculate the idle
++ * throushold. It might be bigger if not all cached device are in write-
++ * back mode, but it still works well with limited extra rounds of
++ * update_writeback_rate().
++ */
+ static bool set_at_max_writeback_rate(struct cache_set *c,
+ struct cached_dev *dc)
+ {
+@@ -167,21 +214,8 @@ static bool set_at_max_writeback_rate(struct cache_set *c,
+ /* Don't set max writeback rate if gc is running */
+ if (!c->gc_mark_valid)
+ return false;
+- /*
+- * Idle_counter is increased everytime when update_writeback_rate() is
+- * called. If all backing devices attached to the same cache set have
+- * identical dc->writeback_rate_update_seconds values, it is about 6
+- * rounds of update_writeback_rate() on each backing device before
+- * c->at_max_writeback_rate is set to 1, and then max wrteback rate set
+- * to each dc->writeback_rate.rate.
+- * In order to avoid extra locking cost for counting exact dirty cached
+- * devices number, c->attached_dev_nr is used to calculate the idle
+- * throushold. It might be bigger if not all cached device are in write-
+- * back mode, but it still works well with limited extra rounds of
+- * update_writeback_rate().
+- */
+- if (atomic_inc_return(&c->idle_counter) <
+- atomic_read(&c->attached_dev_nr) * 6)
++
++ if (!idle_counter_exceeded(c))
+ return false;
+
+ if (atomic_read(&c->at_max_writeback_rate) != 1)
+@@ -195,13 +229,10 @@ static bool set_at_max_writeback_rate(struct cache_set *c,
+ dc->writeback_rate_change = 0;
+
+ /*
+- * Check c->idle_counter and c->at_max_writeback_rate agagain in case
+- * new I/O arrives during before set_at_max_writeback_rate() returns.
+- * Then the writeback rate is set to 1, and its new value should be
+- * decided via __update_writeback_rate().
++ * In case new I/O arrives during before
++ * set_at_max_writeback_rate() returns.
+ */
+- if ((atomic_read(&c->idle_counter) <
+- atomic_read(&c->attached_dev_nr) * 6) ||
++ if (!idle_counter_exceeded(c) ||
+ !atomic_read(&c->at_max_writeback_rate))
+ return false;
+
+--
+2.35.1
+
--- /dev/null
+From f7d3731607fdd8ec30b4568ca2734691ba307fca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 10:22:38 +0800
+Subject: blk-throttle: prevent overflow while calculating wait time
+
+From: Yu Kuai <yukuai3@huawei.com>
+
+[ Upstream commit 8d6bbaada2e0a65f9012ac4c2506460160e7237a ]
+
+There is a problem found by code review in tg_with_in_bps_limit() that
+'bps_limit * jiffy_elapsed_rnd' might overflow. Fix the problem by
+calling mul_u64_u64_div_u64() instead.
+
+Signed-off-by: Yu Kuai <yukuai3@huawei.com>
+Acked-by: Tejun Heo <tj@kernel.org>
+Link: https://lore.kernel.org/r/20220829022240.3348319-3-yukuai1@huaweicloud.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ block/blk-throttle.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/block/blk-throttle.c b/block/blk-throttle.c
+index 7c4e7993ba97..68cf8dbb4c67 100644
+--- a/block/blk-throttle.c
++++ b/block/blk-throttle.c
+@@ -950,7 +950,7 @@ static bool tg_with_in_bps_limit(struct throtl_grp *tg, struct bio *bio,
+ u64 bps_limit, unsigned long *wait)
+ {
+ bool rw = bio_data_dir(bio);
+- u64 bytes_allowed, extra_bytes, tmp;
++ u64 bytes_allowed, extra_bytes;
+ unsigned long jiffy_elapsed, jiffy_wait, jiffy_elapsed_rnd;
+ unsigned int bio_size = throtl_bio_data_size(bio);
+
+@@ -967,10 +967,8 @@ static bool tg_with_in_bps_limit(struct throtl_grp *tg, struct bio *bio,
+ jiffy_elapsed_rnd = tg->td->throtl_slice;
+
+ jiffy_elapsed_rnd = roundup(jiffy_elapsed_rnd, tg->td->throtl_slice);
+-
+- tmp = bps_limit * jiffy_elapsed_rnd;
+- do_div(tmp, HZ);
+- bytes_allowed = tmp;
++ bytes_allowed = mul_u64_u64_div_u64(bps_limit, (u64)jiffy_elapsed_rnd,
++ (u64)HZ);
+
+ if (tg->bytes_disp[rw] + bio_size <= bytes_allowed) {
+ if (wait)
+--
+2.35.1
+
--- /dev/null
+From 14b080f1259fd56a8a2ba4803404423a6677c6bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 12:49:45 +0530
+Subject: Bluetooth: btintel: Mark Intel controller to support LE_STATES quirk
+
+From: Kiran K <kiran.k@intel.com>
+
+[ Upstream commit dd0a1794f4334ddbf9b7c5e7d642aaffff38c69b ]
+
+HarrrisonPeak, CyclonePeak, SnowFieldPeak and SandyPeak controllers
+are marked to support HCI_QUIRK_LE_STATES.
+
+Signed-off-by: Kiran K <kiran.k@intel.com>
+Signed-off-by: Chethan T N <chethan.tumkur.narayan@intel.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bluetooth/btintel.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/bluetooth/btintel.c b/drivers/bluetooth/btintel.c
+index d122cc973917..de3d851d85e7 100644
+--- a/drivers/bluetooth/btintel.c
++++ b/drivers/bluetooth/btintel.c
+@@ -2274,15 +2274,20 @@ static int btintel_setup_combined(struct hci_dev *hdev)
+ INTEL_ROM_LEGACY_NO_WBS_SUPPORT))
+ set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED,
+ &hdev->quirks);
++ if (ver.hw_variant == 0x08 && ver.fw_variant == 0x22)
++ set_bit(HCI_QUIRK_VALID_LE_STATES,
++ &hdev->quirks);
+
+ err = btintel_legacy_rom_setup(hdev, &ver);
+ break;
+ case 0x0b: /* SfP */
+- case 0x0c: /* WsP */
+ case 0x11: /* JfP */
+ case 0x12: /* ThP */
+ case 0x13: /* HrP */
+ case 0x14: /* CcP */
++ set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks);
++ fallthrough;
++ case 0x0c: /* WsP */
+ /* Apply the device specific HCI quirks
+ *
+ * All Legacy bootloader devices support WBS
+@@ -2290,11 +2295,6 @@ static int btintel_setup_combined(struct hci_dev *hdev)
+ set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED,
+ &hdev->quirks);
+
+- /* Valid LE States quirk for JfP/ThP familiy */
+- if (ver.hw_variant == 0x11 || ver.hw_variant == 0x12)
+- set_bit(HCI_QUIRK_VALID_LE_STATES,
+- &hdev->quirks);
+-
+ /* Setup MSFT Extension support */
+ btintel_set_msft_opcode(hdev, ver.hw_variant);
+
+@@ -2361,9 +2361,8 @@ static int btintel_setup_combined(struct hci_dev *hdev)
+ */
+ set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED, &hdev->quirks);
+
+- /* Valid LE States quirk for JfP/ThP familiy */
+- if (ver.hw_variant == 0x11 || ver.hw_variant == 0x12)
+- set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks);
++ /* Set Valid LE States quirk */
++ set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks);
+
+ /* Setup MSFT Extension support */
+ btintel_set_msft_opcode(hdev, ver.hw_variant);
+--
+2.35.1
+
--- /dev/null
+From b43077f72dc7a739b99c46ebc23fdc782a02533e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Aug 2022 08:49:07 +0800
+Subject: Bluetooth: btusb: mediatek: fix WMT failure during runtime suspend
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+[ Upstream commit fd3f106677bac70437dc12e76c827294ed495a44 ]
+
+WMT cmd/event doesn't follow up the generic HCI cmd/event handling, it
+needs constantly polling control pipe until the host received the WMT
+event, thus, we should require to specifically acquire PM counter on the
+USB to prevent the interface from entering auto suspended while WMT
+cmd/event in progress.
+
+Fixes: a1c49c434e15 ("Bluetooth: btusb: Add protocol support for MediaTek MT7668U USB devices")
+Co-developed-by: Jing Cai <jing.cai@mediatek.com>
+Signed-off-by: Jing Cai <jing.cai@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bluetooth/btusb.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
+index 627436329b50..64d72ea0c310 100644
+--- a/drivers/bluetooth/btusb.c
++++ b/drivers/bluetooth/btusb.c
+@@ -2435,15 +2435,29 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev,
+
+ set_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags);
+
++ /* WMT cmd/event doesn't follow up the generic HCI cmd/event handling,
++ * it needs constantly polling control pipe until the host received the
++ * WMT event, thus, we should require to specifically acquire PM counter
++ * on the USB to prevent the interface from entering auto suspended
++ * while WMT cmd/event in progress.
++ */
++ err = usb_autopm_get_interface(data->intf);
++ if (err < 0)
++ goto err_free_wc;
++
+ err = __hci_cmd_send(hdev, 0xfc6f, hlen, wc);
+
+ if (err < 0) {
+ clear_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags);
++ usb_autopm_put_interface(data->intf);
+ goto err_free_wc;
+ }
+
+ /* Submit control IN URB on demand to process the WMT event */
+ err = btusb_mtk_submit_wmt_recv_urb(hdev);
++
++ usb_autopm_put_interface(data->intf);
++
+ if (err < 0)
+ goto err_free_wc;
+
+--
+2.35.1
+
--- /dev/null
+From bc1988ab7d1a5e6f7402016ba85aeb74ff934496 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 23:58:12 +0900
+Subject: Bluetooth: hci_{ldisc,serdev}: check percpu_init_rwsem() failure
+
+From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+
+[ Upstream commit 3124d320c22f3f4388d9ac5c8f37eaad0cefd6b1 ]
+
+syzbot is reporting NULL pointer dereference at hci_uart_tty_close() [1],
+for rcu_sync_enter() is called without rcu_sync_init() due to
+hci_uart_tty_open() ignoring percpu_init_rwsem() failure.
+
+While we are at it, fix that hci_uart_register_device() ignores
+percpu_init_rwsem() failure and hci_uart_unregister_device() does not
+call percpu_free_rwsem().
+
+Link: https://syzkaller.appspot.com/bug?extid=576dfca25381fb6fbc5f [1]
+Reported-by: syzbot <syzbot+576dfca25381fb6fbc5f@syzkaller.appspotmail.com>
+Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+Fixes: 67d2f8781b9f00d1 ("Bluetooth: hci_ldisc: Allow sleeping while proto locks are held.")
+Fixes: d73e172816652772 ("Bluetooth: hci_serdev: Init hci_uart proto_lock to avoid oops")
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bluetooth/hci_ldisc.c | 7 +++++--
+ drivers/bluetooth/hci_serdev.c | 10 +++++++---
+ 2 files changed, 12 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
+index 5ed2cfa7da1d..2d960a5e3679 100644
+--- a/drivers/bluetooth/hci_ldisc.c
++++ b/drivers/bluetooth/hci_ldisc.c
+@@ -490,6 +490,11 @@ static int hci_uart_tty_open(struct tty_struct *tty)
+ BT_ERR("Can't allocate control structure");
+ return -ENFILE;
+ }
++ if (percpu_init_rwsem(&hu->proto_lock)) {
++ BT_ERR("Can't allocate semaphore structure");
++ kfree(hu);
++ return -ENOMEM;
++ }
+
+ tty->disc_data = hu;
+ hu->tty = tty;
+@@ -502,8 +507,6 @@ static int hci_uart_tty_open(struct tty_struct *tty)
+ INIT_WORK(&hu->init_ready, hci_uart_init_work);
+ INIT_WORK(&hu->write_work, hci_uart_write_work);
+
+- percpu_init_rwsem(&hu->proto_lock);
+-
+ /* Flush any pending characters in the driver */
+ tty_driver_flush_buffer(tty);
+
+diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c
+index 4cda890ce647..649d112eea78 100644
+--- a/drivers/bluetooth/hci_serdev.c
++++ b/drivers/bluetooth/hci_serdev.c
+@@ -301,11 +301,12 @@ int hci_uart_register_device(struct hci_uart *hu,
+
+ serdev_device_set_client_ops(hu->serdev, &hci_serdev_client_ops);
+
++ if (percpu_init_rwsem(&hu->proto_lock))
++ return -ENOMEM;
++
+ err = serdev_device_open(hu->serdev);
+ if (err)
+- return err;
+-
+- percpu_init_rwsem(&hu->proto_lock);
++ goto err_rwsem;
+
+ err = p->open(hu);
+ if (err)
+@@ -378,6 +379,8 @@ int hci_uart_register_device(struct hci_uart *hu,
+ p->close(hu);
+ err_open:
+ serdev_device_close(hu->serdev);
++err_rwsem:
++ percpu_free_rwsem(&hu->proto_lock);
+ return err;
+ }
+ EXPORT_SYMBOL_GPL(hci_uart_register_device);
+@@ -399,5 +402,6 @@ void hci_uart_unregister_device(struct hci_uart *hu)
+ clear_bit(HCI_UART_PROTO_READY, &hu->flags);
+ serdev_device_close(hu->serdev);
+ }
++ percpu_free_rwsem(&hu->proto_lock);
+ }
+ EXPORT_SYMBOL_GPL(hci_uart_unregister_device);
+--
+2.35.1
+
--- /dev/null
+From 132f65e06d879582e0649db31d09360fa7bfba83 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 15:44:42 -0700
+Subject: Bluetooth: hci_core: Fix not handling link timeouts propertly
+
+From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+
+[ Upstream commit 116523c8fac05d1d26f748fee7919a4ec5df67ea ]
+
+Change that introduced the use of __check_timeout did not account for
+link types properly, it always assumes ACL_LINK is used thus causing
+hdev->acl_last_tx to be used even in case of LE_LINK and then again
+uses ACL_LINK with hci_link_tx_to.
+
+To fix this __check_timeout now takes the link type as parameter and
+then procedure to use the right last_tx based on the link type and pass
+it to hci_link_tx_to.
+
+Fixes: 1b1d29e51499 ("Bluetooth: Make use of __check_timeout on hci_sched_le")
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Tested-by: David Beinder <david@beinder.at>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/hci_core.c | 34 +++++++++++++++++++++++-----------
+ 1 file changed, 23 insertions(+), 11 deletions(-)
+
+diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
+index cdca53732304..396696241d17 100644
+--- a/net/bluetooth/hci_core.c
++++ b/net/bluetooth/hci_core.c
+@@ -4673,15 +4673,27 @@ static inline int __get_blocks(struct hci_dev *hdev, struct sk_buff *skb)
+ return DIV_ROUND_UP(skb->len - HCI_ACL_HDR_SIZE, hdev->block_len);
+ }
+
+-static void __check_timeout(struct hci_dev *hdev, unsigned int cnt)
++static void __check_timeout(struct hci_dev *hdev, unsigned int cnt, u8 type)
+ {
+- if (!hci_dev_test_flag(hdev, HCI_UNCONFIGURED)) {
+- /* ACL tx timeout must be longer than maximum
+- * link supervision timeout (40.9 seconds) */
+- if (!cnt && time_after(jiffies, hdev->acl_last_tx +
+- HCI_ACL_TX_TIMEOUT))
+- hci_link_tx_to(hdev, ACL_LINK);
++ unsigned long last_tx;
++
++ if (hci_dev_test_flag(hdev, HCI_UNCONFIGURED))
++ return;
++
++ switch (type) {
++ case LE_LINK:
++ last_tx = hdev->le_last_tx;
++ break;
++ default:
++ last_tx = hdev->acl_last_tx;
++ break;
+ }
++
++ /* tx timeout must be longer than maximum link supervision timeout
++ * (40.9 seconds)
++ */
++ if (!cnt && time_after(jiffies, last_tx + HCI_ACL_TX_TIMEOUT))
++ hci_link_tx_to(hdev, type);
+ }
+
+ /* Schedule SCO */
+@@ -4739,7 +4751,7 @@ static void hci_sched_acl_pkt(struct hci_dev *hdev)
+ struct sk_buff *skb;
+ int quote;
+
+- __check_timeout(hdev, cnt);
++ __check_timeout(hdev, cnt, ACL_LINK);
+
+ while (hdev->acl_cnt &&
+ (chan = hci_chan_sent(hdev, ACL_LINK, "e))) {
+@@ -4782,8 +4794,6 @@ static void hci_sched_acl_blk(struct hci_dev *hdev)
+ int quote;
+ u8 type;
+
+- __check_timeout(hdev, cnt);
+-
+ BT_DBG("%s", hdev->name);
+
+ if (hdev->dev_type == HCI_AMP)
+@@ -4791,6 +4801,8 @@ static void hci_sched_acl_blk(struct hci_dev *hdev)
+ else
+ type = ACL_LINK;
+
++ __check_timeout(hdev, cnt, type);
++
+ while (hdev->block_cnt > 0 &&
+ (chan = hci_chan_sent(hdev, type, "e))) {
+ u32 priority = (skb_peek(&chan->data_q))->priority;
+@@ -4864,7 +4876,7 @@ static void hci_sched_le(struct hci_dev *hdev)
+
+ cnt = hdev->le_pkts ? hdev->le_cnt : hdev->acl_cnt;
+
+- __check_timeout(hdev, cnt);
++ __check_timeout(hdev, cnt, LE_LINK);
+
+ tmp = cnt;
+ while (cnt && (chan = hci_chan_sent(hdev, LE_LINK, "e))) {
+--
+2.35.1
+
--- /dev/null
+From 403c19ed32e3561b99d5c37f8885fd15539cdf1e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 10:56:59 -0700
+Subject: Bluetooth: hci_sysfs: Fix attempting to call device_add multiple
+ times
+
+From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+
+[ Upstream commit 448a496f760664d3e2e79466aa1787e6abc922b5 ]
+
+device_add shall not be called multiple times as stated in its
+documentation:
+
+ 'Do not call this routine or device_register() more than once for
+ any device structure'
+
+Syzkaller reports a bug as follows [1]:
+------------[ cut here ]------------
+kernel BUG at lib/list_debug.c:33!
+invalid opcode: 0000 [#1] PREEMPT SMP KASAN
+[...]
+Call Trace:
+ <TASK>
+ __list_add include/linux/list.h:69 [inline]
+ list_add_tail include/linux/list.h:102 [inline]
+ kobj_kset_join lib/kobject.c:164 [inline]
+ kobject_add_internal+0x18f/0x8f0 lib/kobject.c:214
+ kobject_add_varg lib/kobject.c:358 [inline]
+ kobject_add+0x150/0x1c0 lib/kobject.c:410
+ device_add+0x368/0x1e90 drivers/base/core.c:3452
+ hci_conn_add_sysfs+0x9b/0x1b0 net/bluetooth/hci_sysfs.c:53
+ hci_le_cis_estabilished_evt+0x57c/0xae0 net/bluetooth/hci_event.c:6799
+ hci_le_meta_evt+0x2b8/0x510 net/bluetooth/hci_event.c:7110
+ hci_event_func net/bluetooth/hci_event.c:7440 [inline]
+ hci_event_packet+0x63d/0xfd0 net/bluetooth/hci_event.c:7495
+ hci_rx_work+0xae7/0x1230 net/bluetooth/hci_core.c:4007
+ process_one_work+0x991/0x1610 kernel/workqueue.c:2289
+ worker_thread+0x665/0x1080 kernel/workqueue.c:2436
+ kthread+0x2e4/0x3a0 kernel/kthread.c:376
+ ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:306
+ </TASK>
+
+Link: https://syzkaller.appspot.com/bug?id=da3246e2d33afdb92d66bc166a0934c5b146404a
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Tested-by: Hawkins Jiawei <yin31149@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/hci_sysfs.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/net/bluetooth/hci_sysfs.c b/net/bluetooth/hci_sysfs.c
+index 4e3e0451b08c..08542dfc2dc5 100644
+--- a/net/bluetooth/hci_sysfs.c
++++ b/net/bluetooth/hci_sysfs.c
+@@ -48,6 +48,9 @@ void hci_conn_add_sysfs(struct hci_conn *conn)
+
+ BT_DBG("conn %p", conn);
+
++ if (device_is_registered(&conn->dev))
++ return;
++
+ dev_set_name(&conn->dev, "%s:%d", hdev->name, conn->handle);
+
+ if (device_add(&conn->dev) < 0) {
+--
+2.35.1
+
--- /dev/null
+From d91c3ab9e38f9ed163c86dc2acce820823350f1b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 13:27:13 -0700
+Subject: Bluetooth: L2CAP: Fix user-after-free
+
+From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+
+[ Upstream commit 35fcbc4243aad7e7d020b7c1dfb14bb888b20a4f ]
+
+This uses l2cap_chan_hold_unless_zero() after calling
+__l2cap_get_chan_blah() to prevent the following trace:
+
+Bluetooth: l2cap_core.c:static void l2cap_chan_destroy(struct kref
+*kref)
+Bluetooth: chan 0000000023c4974d
+Bluetooth: parent 00000000ae861c08
+==================================================================
+BUG: KASAN: use-after-free in __mutex_waiter_is_first
+kernel/locking/mutex.c:191 [inline]
+BUG: KASAN: use-after-free in __mutex_lock_common
+kernel/locking/mutex.c:671 [inline]
+BUG: KASAN: use-after-free in __mutex_lock+0x278/0x400
+kernel/locking/mutex.c:729
+Read of size 8 at addr ffff888006a49b08 by task kworker/u3:2/389
+
+Link: https://lore.kernel.org/lkml/20220622082716.478486-1-lee.jones@linaro.org
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sungwoo Kim <iam@sung-woo.kim>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/l2cap_core.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
+index 4e7dd41a8314..8f1a95b9d320 100644
+--- a/net/bluetooth/l2cap_core.c
++++ b/net/bluetooth/l2cap_core.c
+@@ -4309,6 +4309,12 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
+ }
+ }
+
++ chan = l2cap_chan_hold_unless_zero(chan);
++ if (!chan) {
++ err = -EBADSLT;
++ goto unlock;
++ }
++
+ err = 0;
+
+ l2cap_chan_lock(chan);
+@@ -4338,6 +4344,7 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
+ }
+
+ l2cap_chan_unlock(chan);
++ l2cap_chan_put(chan);
+
+ unlock:
+ mutex_unlock(&conn->chan_lock);
+--
+2.35.1
+
--- /dev/null
+From a61f02d64bcd9684ddc601da2c7fcce09a8c9621 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 00:32:56 +0900
+Subject: Bluetooth: L2CAP: initialize delayed works at l2cap_chan_create()
+
+From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+
+[ Upstream commit 2d2cb3066f2c90cd8ca540b36ba7a55e7f2406e0 ]
+
+syzbot is reporting cancel_delayed_work() without INIT_DELAYED_WORK() at
+l2cap_chan_del() [1], for CONF_NOT_COMPLETE flag (which meant to prevent
+l2cap_chan_del() from calling cancel_delayed_work()) is cleared by timer
+which fires before l2cap_chan_del() is called by closing file descriptor
+created by socket(AF_BLUETOOTH, SOCK_STREAM, BTPROTO_L2CAP).
+
+l2cap_bredr_sig_cmd(L2CAP_CONF_REQ) and l2cap_bredr_sig_cmd(L2CAP_CONF_RSP)
+are calling l2cap_ertm_init(chan), and they call l2cap_chan_ready() (which
+clears CONF_NOT_COMPLETE flag) only when l2cap_ertm_init(chan) succeeded.
+
+l2cap_sock_init() does not call l2cap_ertm_init(chan), and it instead sets
+CONF_NOT_COMPLETE flag by calling l2cap_chan_set_defaults(). However, when
+connect() is requested, "command 0x0409 tx timeout" happens after 2 seconds
+ from connect() request, and CONF_NOT_COMPLETE flag is cleared after 4
+seconds from connect() request, for l2cap_conn_start() from
+l2cap_info_timeout() callback scheduled by
+
+ schedule_delayed_work(&conn->info_timer, L2CAP_INFO_TIMEOUT);
+
+in l2cap_connect() is calling l2cap_chan_ready().
+
+Fix this problem by initializing delayed works used by L2CAP_MODE_ERTM
+mode as soon as l2cap_chan_create() allocates a channel, like I did in
+commit be8597239379f0f5 ("Bluetooth: initialize skb_queue_head at
+l2cap_chan_create()").
+
+Link: https://syzkaller.appspot.com/bug?extid=83672956c7aa6af698b3 [1]
+Reported-by: syzbot <syzbot+83672956c7aa6af698b3@syzkaller.appspotmail.com>
+Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/l2cap_core.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
+index e8de1e7d6ff4..4e7dd41a8314 100644
+--- a/net/bluetooth/l2cap_core.c
++++ b/net/bluetooth/l2cap_core.c
+@@ -61,6 +61,9 @@ static void l2cap_send_disconn_req(struct l2cap_chan *chan, int err);
+
+ static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control,
+ struct sk_buff_head *skbs, u8 event);
++static void l2cap_retrans_timeout(struct work_struct *work);
++static void l2cap_monitor_timeout(struct work_struct *work);
++static void l2cap_ack_timeout(struct work_struct *work);
+
+ static inline u8 bdaddr_type(u8 link_type, u8 bdaddr_type)
+ {
+@@ -476,6 +479,9 @@ struct l2cap_chan *l2cap_chan_create(void)
+ write_unlock(&chan_list_lock);
+
+ INIT_DELAYED_WORK(&chan->chan_timer, l2cap_chan_timeout);
++ INIT_DELAYED_WORK(&chan->retrans_timer, l2cap_retrans_timeout);
++ INIT_DELAYED_WORK(&chan->monitor_timer, l2cap_monitor_timeout);
++ INIT_DELAYED_WORK(&chan->ack_timer, l2cap_ack_timeout);
+
+ chan->state = BT_OPEN;
+
+@@ -3320,10 +3326,6 @@ int l2cap_ertm_init(struct l2cap_chan *chan)
+ chan->rx_state = L2CAP_RX_STATE_RECV;
+ chan->tx_state = L2CAP_TX_STATE_XMIT;
+
+- INIT_DELAYED_WORK(&chan->retrans_timer, l2cap_retrans_timeout);
+- INIT_DELAYED_WORK(&chan->monitor_timer, l2cap_monitor_timeout);
+- INIT_DELAYED_WORK(&chan->ack_timer, l2cap_ack_timeout);
+-
+ skb_queue_head_init(&chan->srej_q);
+
+ err = l2cap_seq_list_init(&chan->srej_list, chan->tx_win);
+--
+2.35.1
+
--- /dev/null
+From 52990c1855a74086aaee681f18de1562d2e18767 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 16:08:13 -0700
+Subject: Bluetooth: RFCOMM: Fix possible deadlock on socket shutdown/release
+
+From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+
+[ Upstream commit 812e92b824c1db16c9519f8624d48a9901a0d38f ]
+
+Due to change to switch to use lock_sock inside rfcomm_sk_state_change
+the socket shutdown/release procedure can cause a deadlock:
+
+ rfcomm_sock_shutdown():
+ lock_sock();
+ __rfcomm_sock_close():
+ rfcomm_dlc_close():
+ __rfcomm_dlc_close():
+ rfcomm_dlc_lock();
+ rfcomm_sk_state_change():
+ lock_sock();
+
+To fix this when the call __rfcomm_sock_close is now done without
+holding the lock_sock since rfcomm_dlc_lock exists to protect
+the dlc data there is no need to use lock_sock in that code path.
+
+Link: https://lore.kernel.org/all/CAD+dNTsbuU4w+Y_P7o+VEN7BYCAbZuwZx2+tH+OTzCdcZF82YA@mail.gmail.com/
+Fixes: b7ce436a5d79 ("Bluetooth: switch to lock_sock in RFCOMM")
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/rfcomm/sock.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/net/bluetooth/rfcomm/sock.c b/net/bluetooth/rfcomm/sock.c
+index 4bf4ea6cbb5e..21e24da4847f 100644
+--- a/net/bluetooth/rfcomm/sock.c
++++ b/net/bluetooth/rfcomm/sock.c
+@@ -902,7 +902,10 @@ static int rfcomm_sock_shutdown(struct socket *sock, int how)
+ lock_sock(sk);
+ if (!sk->sk_shutdown) {
+ sk->sk_shutdown = SHUTDOWN_MASK;
++
++ release_sock(sk);
+ __rfcomm_sock_close(sk);
++ lock_sock(sk);
+
+ if (sock_flag(sk, SOCK_LINGER) && sk->sk_lingertime &&
+ !(current->flags & PF_EXITING))
+--
+2.35.1
+
--- /dev/null
+From c23900081ae0b940585fd617a27b5184b11bd2df Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 14:28:43 +0800
+Subject: bnx2x: fix potential memory leak in bnx2x_tpa_stop()
+
+From: Jianglei Nie <niejianglei2021@163.com>
+
+[ Upstream commit b43f9acbb8942b05252be83ac25a81cec70cc192 ]
+
+bnx2x_tpa_stop() allocates a memory chunk from new_data with
+bnx2x_frag_alloc(). The new_data should be freed when gets some error.
+But when "pad + len > fp->rx_buf_size" is true, bnx2x_tpa_stop() returns
+without releasing the new_data, which will lead to a memory leak.
+
+We should free the new_data with bnx2x_frag_free() when "pad + len >
+fp->rx_buf_size" is true.
+
+Fixes: 07b0f00964def8af9321cfd6c4a7e84f6362f728 ("bnx2x: fix possible panic under memory stress")
+Signed-off-by: Jianglei Nie <niejianglei2021@163.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+index 198e041d8410..4f669e7c7558 100644
+--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+@@ -788,6 +788,7 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+ BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
+ pad, len, fp->rx_buf_size);
+ bnx2x_panic();
++ bnx2x_frag_free(fp, new_data);
+ return;
+ }
+ #endif
+--
+2.35.1
+
--- /dev/null
+From 48adb5a94c109855651c2af51e95376e4438c583 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 10 Sep 2022 11:01:20 +0000
+Subject: bpf: btf: fix truncated last_member_type_id in btf_struct_resolve
+
+From: Lorenz Bauer <oss@lmb.io>
+
+[ Upstream commit a37a32583e282d8d815e22add29bc1e91e19951a ]
+
+When trying to finish resolving a struct member, btf_struct_resolve
+saves the member type id in a u16 temporary variable. This truncates
+the 32 bit type id value if it exceeds UINT16_MAX.
+
+As a result, structs that have members with type ids > UINT16_MAX and
+which need resolution will fail with a message like this:
+
+ [67414] STRUCT ff_device size=120 vlen=12
+ effect_owners type_id=67434 bits_offset=960 Member exceeds struct_size
+
+Fix this by changing the type of last_member_type_id to u32.
+
+Fixes: a0791f0df7d2 ("bpf: fix BTF limits")
+Reviewed-by: Stanislav Fomichev <sdf@google.com>
+Signed-off-by: Lorenz Bauer <oss@lmb.io>
+Link: https://lore.kernel.org/r/20220910110120.339242-1-oss@lmb.io
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/btf.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c
+index 3cfba41a0829..7cb13b9f69a6 100644
+--- a/kernel/bpf/btf.c
++++ b/kernel/bpf/btf.c
+@@ -2983,7 +2983,7 @@ static int btf_struct_resolve(struct btf_verifier_env *env,
+ if (v->next_member) {
+ const struct btf_type *last_member_type;
+ const struct btf_member *last_member;
+- u16 last_member_type_id;
++ u32 last_member_type_id;
+
+ last_member = btf_type_member(v->t) + v->next_member - 1;
+ last_member_type_id = last_member->type;
+--
+2.35.1
+
--- /dev/null
+From 7434ad3b9214ac030b312619e72b8db2d43f2b97 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 12:26:27 +0800
+Subject: bpf: Disable preemption when increasing per-cpu map_locked
+
+From: Hou Tao <houtao1@huawei.com>
+
+[ Upstream commit 2775da21628738ce073a3a6a806adcbaada0f091 ]
+
+Per-cpu htab->map_locked is used to prohibit the concurrent accesses
+from both NMI and non-NMI contexts. But since commit 74d862b682f5
+("sched: Make migrate_disable/enable() independent of RT"),
+migrate_disable() is also preemptible under CONFIG_PREEMPT case, so now
+map_locked also disallows concurrent updates from normal contexts
+(e.g. userspace processes) unexpectedly as shown below:
+
+process A process B
+
+htab_map_update_elem()
+ htab_lock_bucket()
+ migrate_disable()
+ /* return 1 */
+ __this_cpu_inc_return()
+ /* preempted by B */
+
+ htab_map_update_elem()
+ /* the same bucket as A */
+ htab_lock_bucket()
+ migrate_disable()
+ /* return 2, so lock fails */
+ __this_cpu_inc_return()
+ return -EBUSY
+
+A fix that seems feasible is using in_nmi() in htab_lock_bucket() and
+only checking the value of map_locked for nmi context. But it will
+re-introduce dead-lock on bucket lock if htab_lock_bucket() is re-entered
+through non-tracing program (e.g. fentry program).
+
+One cannot use preempt_disable() to fix this issue as htab_use_raw_lock
+being false causes the bucket lock to be a spin lock which can sleep and
+does not work with preempt_disable().
+
+Therefore, use migrate_disable() when using the spinlock instead of
+preempt_disable() and defer fixing concurrent updates to when the kernel
+has its own BPF memory allocator.
+
+Fixes: 74d862b682f5 ("sched: Make migrate_disable/enable() independent of RT")
+Reviewed-by: Hao Luo <haoluo@google.com>
+Signed-off-by: Hou Tao <houtao1@huawei.com>
+Link: https://lore.kernel.org/r/20220831042629.130006-2-houtao@huaweicloud.com
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/hashtab.c | 23 ++++++++++++++++++-----
+ 1 file changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c
+index 47eebb88695e..cae858985f0c 100644
+--- a/kernel/bpf/hashtab.c
++++ b/kernel/bpf/hashtab.c
+@@ -161,17 +161,25 @@ static inline int htab_lock_bucket(const struct bpf_htab *htab,
+ unsigned long *pflags)
+ {
+ unsigned long flags;
++ bool use_raw_lock;
+
+ hash = hash & HASHTAB_MAP_LOCK_MASK;
+
+- migrate_disable();
++ use_raw_lock = htab_use_raw_lock(htab);
++ if (use_raw_lock)
++ preempt_disable();
++ else
++ migrate_disable();
+ if (unlikely(__this_cpu_inc_return(*(htab->map_locked[hash])) != 1)) {
+ __this_cpu_dec(*(htab->map_locked[hash]));
+- migrate_enable();
++ if (use_raw_lock)
++ preempt_enable();
++ else
++ migrate_enable();
+ return -EBUSY;
+ }
+
+- if (htab_use_raw_lock(htab))
++ if (use_raw_lock)
+ raw_spin_lock_irqsave(&b->raw_lock, flags);
+ else
+ spin_lock_irqsave(&b->lock, flags);
+@@ -184,13 +192,18 @@ static inline void htab_unlock_bucket(const struct bpf_htab *htab,
+ struct bucket *b, u32 hash,
+ unsigned long flags)
+ {
++ bool use_raw_lock = htab_use_raw_lock(htab);
++
+ hash = hash & HASHTAB_MAP_LOCK_MASK;
+- if (htab_use_raw_lock(htab))
++ if (use_raw_lock)
+ raw_spin_unlock_irqrestore(&b->raw_lock, flags);
+ else
+ spin_unlock_irqrestore(&b->lock, flags);
+ __this_cpu_dec(*(htab->map_locked[hash]));
+- migrate_enable();
++ if (use_raw_lock)
++ preempt_enable();
++ else
++ migrate_enable();
+ }
+
+ static bool htab_lru_map_delete_node(void *arg, struct bpf_lru_node *node);
+--
+2.35.1
+
--- /dev/null
+From facd366e221c1ad5c618014a5ebbdaa17b1889a5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 14:38:55 +0100
+Subject: bpf: Ensure correct locking around vulnerable function find_vpid()
+
+From: Lee Jones <lee@kernel.org>
+
+[ Upstream commit 83c10cc362d91c0d8d25e60779ee52fdbbf3894d ]
+
+The documentation for find_vpid() clearly states:
+
+ "Must be called with the tasklist_lock or rcu_read_lock() held."
+
+Presently we do neither for find_vpid() instance in bpf_task_fd_query().
+Add proper rcu_read_lock/unlock() to fix the issue.
+
+Fixes: 41bdc4b40ed6f ("bpf: introduce bpf subcommand BPF_TASK_FD_QUERY")
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: Yonghong Song <yhs@fb.com>
+Link: https://lore.kernel.org/bpf/20220912133855.1218900-1-lee@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/syscall.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c
+index 99ce46f51889..aea9852f1c22 100644
+--- a/kernel/bpf/syscall.c
++++ b/kernel/bpf/syscall.c
+@@ -4100,7 +4100,9 @@ static int bpf_task_fd_query(const union bpf_attr *attr,
+ if (attr->task_fd_query.flags != 0)
+ return -EINVAL;
+
++ rcu_read_lock();
+ task = get_pid_task(find_vpid(pid), PIDTYPE_PID);
++ rcu_read_unlock();
+ if (!task)
+ return -ENOENT;
+
+--
+2.35.1
+
--- /dev/null
+From f6cf753c1c068223d5ee46d7eb1937fcf25a672a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Aug 2022 03:31:25 +0200
+Subject: bpf: Fix reference state management for synchronous callbacks
+
+From: Kumar Kartikeya Dwivedi <memxor@gmail.com>
+
+[ Upstream commit 9d9d00ac29d0ef7ce426964de46fa6b380357d0a ]
+
+Currently, verifier verifies callback functions (sync and async) as if
+they will be executed once, (i.e. it explores execution state as if the
+function was being called once). The next insn to explore is set to
+start of subprog and the exit from nested frame is handled using
+curframe > 0 and prepare_func_exit. In case of async callback it uses a
+customized variant of push_stack simulating a kind of branch to set up
+custom state and execution context for the async callback.
+
+While this approach is simple and works when callback really will be
+executed only once, it is unsafe for all of our current helpers which
+are for_each style, i.e. they execute the callback multiple times.
+
+A callback releasing acquired references of the caller may do so
+multiple times, but currently verifier sees it as one call inside the
+frame, which then returns to caller. Hence, it thinks it released some
+reference that the cb e.g. got access through callback_ctx (register
+filled inside cb from spilled typed register on stack).
+
+Similarly, it may see that an acquire call is unpaired inside the
+callback, so the caller will copy the reference state of callback and
+then will have to release the register with new ref_obj_ids. But again,
+the callback may execute multiple times, but the verifier will only
+account for acquired references for a single symbolic execution of the
+callback, which will cause leaks.
+
+Note that for async callback case, things are different. While currently
+we have bpf_timer_set_callback which only executes it once, even for
+multiple executions it would be safe, as reference state is NULL and
+check_reference_leak would force program to release state before
+BPF_EXIT. The state is also unaffected by analysis for the caller frame.
+Hence async callback is safe.
+
+Since we want the reference state to be accessible, e.g. for pointers
+loaded from stack through callback_ctx's PTR_TO_STACK, we still have to
+copy caller's reference_state to callback's bpf_func_state, but we
+enforce that whatever references it adds to that reference_state has
+been released before it hits BPF_EXIT. This requires introducing a new
+callback_ref member in the reference state to distinguish between caller
+vs callee references. Hence, check_reference_leak now errors out if it
+sees we are in callback_fn and we have not released callback_ref refs.
+Since there can be multiple nested callbacks, like frame 0 -> cb1 -> cb2
+etc. we need to also distinguish between whether this particular ref
+belongs to this callback frame or parent, and only error for our own, so
+we store state->frameno (which is always non-zero for callbacks).
+
+In short, callbacks can read parent reference_state, but cannot mutate
+it, to be able to use pointers acquired by the caller. They must only
+undo their changes (by releasing their own acquired_refs before
+BPF_EXIT) on top of caller reference_state before returning (at which
+point the caller and callback state will match anyway, so no need to
+copy it back to caller).
+
+Fixes: 69c087ba6225 ("bpf: Add bpf_for_each_map_elem() helper")
+Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
+Link: https://lore.kernel.org/r/20220823013125.24938-1-memxor@gmail.com
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/bpf_verifier.h | 11 ++++++++++
+ kernel/bpf/verifier.c | 42 ++++++++++++++++++++++++++++--------
+ 2 files changed, 44 insertions(+), 9 deletions(-)
+
+diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h
+index bb1cc3fbc4ba..5625e19ae95b 100644
+--- a/include/linux/bpf_verifier.h
++++ b/include/linux/bpf_verifier.h
+@@ -192,6 +192,17 @@ struct bpf_reference_state {
+ * is used purely to inform the user of a reference leak.
+ */
+ int insn_idx;
++ /* There can be a case like:
++ * main (frame 0)
++ * cb (frame 1)
++ * func (frame 3)
++ * cb (frame 4)
++ * Hence for frame 4, if callback_ref just stored boolean, it would be
++ * impossible to distinguish nested callback refs. Hence store the
++ * frameno and compare that to callback_ref in check_reference_leak when
++ * exiting a callback function.
++ */
++ int callback_ref;
+ };
+
+ /* state of the program:
+diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
+index 5c9ebcbf6f5f..c3a4158e838e 100644
+--- a/kernel/bpf/verifier.c
++++ b/kernel/bpf/verifier.c
+@@ -851,6 +851,7 @@ static int acquire_reference_state(struct bpf_verifier_env *env, int insn_idx)
+ id = ++env->id_gen;
+ state->refs[new_ofs].id = id;
+ state->refs[new_ofs].insn_idx = insn_idx;
++ state->refs[new_ofs].callback_ref = state->in_callback_fn ? state->frameno : 0;
+
+ return id;
+ }
+@@ -863,6 +864,9 @@ static int release_reference_state(struct bpf_func_state *state, int ptr_id)
+ last_idx = state->acquired_refs - 1;
+ for (i = 0; i < state->acquired_refs; i++) {
+ if (state->refs[i].id == ptr_id) {
++ /* Cannot release caller references in callbacks */
++ if (state->in_callback_fn && state->refs[i].callback_ref != state->frameno)
++ return -EINVAL;
+ if (last_idx && i != last_idx)
+ memcpy(&state->refs[i], &state->refs[last_idx],
+ sizeof(*state->refs));
+@@ -6005,10 +6009,17 @@ static int prepare_func_exit(struct bpf_verifier_env *env, int *insn_idx)
+ caller->regs[BPF_REG_0] = *r0;
+ }
+
+- /* Transfer references to the caller */
+- err = copy_reference_state(caller, callee);
+- if (err)
+- return err;
++ /* callback_fn frame should have released its own additions to parent's
++ * reference state at this point, or check_reference_leak would
++ * complain, hence it must be the same as the caller. There is no need
++ * to copy it back.
++ */
++ if (!callee->in_callback_fn) {
++ /* Transfer references to the caller */
++ err = copy_reference_state(caller, callee);
++ if (err)
++ return err;
++ }
+
+ *insn_idx = callee->callsite + 1;
+ if (env->log.level & BPF_LOG_LEVEL) {
+@@ -6129,13 +6140,20 @@ record_func_key(struct bpf_verifier_env *env, struct bpf_call_arg_meta *meta,
+ static int check_reference_leak(struct bpf_verifier_env *env)
+ {
+ struct bpf_func_state *state = cur_func(env);
++ bool refs_lingering = false;
+ int i;
+
++ if (state->frameno && !state->in_callback_fn)
++ return 0;
++
+ for (i = 0; i < state->acquired_refs; i++) {
++ if (state->in_callback_fn && state->refs[i].callback_ref != state->frameno)
++ continue;
+ verbose(env, "Unreleased reference id=%d alloc_insn=%d\n",
+ state->refs[i].id, state->refs[i].insn_idx);
++ refs_lingering = true;
+ }
+- return state->acquired_refs ? -EINVAL : 0;
++ return refs_lingering ? -EINVAL : 0;
+ }
+
+ static int check_bpf_snprintf_call(struct bpf_verifier_env *env,
+@@ -11150,6 +11168,16 @@ static int do_check(struct bpf_verifier_env *env)
+ return -EINVAL;
+ }
+
++ /* We must do check_reference_leak here before
++ * prepare_func_exit to handle the case when
++ * state->curframe > 0, it may be a callback
++ * function, for which reference_state must
++ * match caller reference state when it exits.
++ */
++ err = check_reference_leak(env);
++ if (err)
++ return err;
++
+ if (state->curframe) {
+ /* exit from nested function */
+ err = prepare_func_exit(env, &env->insn_idx);
+@@ -11159,10 +11187,6 @@ static int do_check(struct bpf_verifier_env *env)
+ continue;
+ }
+
+- err = check_reference_leak(env);
+- if (err)
+- return err;
+-
+ err = check_return_code(env);
+ if (err)
+ return err;
+--
+2.35.1
+
--- /dev/null
+From 0965e6d482781e84a222a4c60bba8c3ca598e746 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 12:26:28 +0800
+Subject: bpf: Propagate error from htab_lock_bucket() to userspace
+
+From: Hou Tao <houtao1@huawei.com>
+
+[ Upstream commit 66a7a92e4d0d091e79148a4c6ec15d1da65f4280 ]
+
+In __htab_map_lookup_and_delete_batch() if htab_lock_bucket() returns
+-EBUSY, it will go to next bucket. Going to next bucket may not only
+skip the elements in current bucket silently, but also incur
+out-of-bound memory access or expose kernel memory to userspace if
+current bucket_cnt is greater than bucket_size or zero.
+
+Fixing it by stopping batch operation and returning -EBUSY when
+htab_lock_bucket() fails, and the application can retry or skip the busy
+batch as needed.
+
+Fixes: 20b6cc34ea74 ("bpf: Avoid hashtab deadlock with map_locked")
+Reported-by: Hao Sun <sunhao.th@gmail.com>
+Signed-off-by: Hou Tao <houtao1@huawei.com>
+Link: https://lore.kernel.org/r/20220831042629.130006-3-houtao@huaweicloud.com
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/hashtab.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c
+index cae858985f0c..e7f45a966e6b 100644
+--- a/kernel/bpf/hashtab.c
++++ b/kernel/bpf/hashtab.c
+@@ -1671,8 +1671,11 @@ __htab_map_lookup_and_delete_batch(struct bpf_map *map,
+ /* do not grab the lock unless need it (bucket_cnt > 0). */
+ if (locked) {
+ ret = htab_lock_bucket(htab, b, batch, &flags);
+- if (ret)
+- goto next_batch;
++ if (ret) {
++ rcu_read_unlock();
++ bpf_enable_instrumentation();
++ goto after_loop;
++ }
+ }
+
+ bucket_cnt = 0;
+--
+2.35.1
+
--- /dev/null
+From 215338d3fadc32e403b3bf151edfd0da83948f93 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Jan 2022 10:54:12 -0800
+Subject: bpf: remove unused static inlines
+
+From: Jakub Kicinski <kuba@kernel.org>
+
+[ Upstream commit 8033c6c2fed235b3d571b5a5ede302b752bc5c7d ]
+
+Remove two dead stubs, sk_msg_clear_meta() was never
+used, use of xskq_cons_is_full() got replaced by
+xsk_tx_writeable() in v5.10.
+
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Link: https://lore.kernel.org/r/20220126185412.2776254-1-kuba@kernel.org
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Stable-dep-of: c00c4461689e ("xsk: Fix backpressure mechanism on Tx")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/bpf.h | 10 ----------
+ include/linux/skmsg.h | 5 -----
+ net/xdp/xsk_queue.h | 7 -------
+ 3 files changed, 22 deletions(-)
+
+diff --git a/include/linux/bpf.h b/include/linux/bpf.h
+index 818cd594e922..2463c2ed5922 100644
+--- a/include/linux/bpf.h
++++ b/include/linux/bpf.h
+@@ -1800,11 +1800,6 @@ static inline int bpf_obj_get_user(const char __user *pathname, int flags)
+ return -EOPNOTSUPP;
+ }
+
+-static inline bool dev_map_can_have_prog(struct bpf_map *map)
+-{
+- return false;
+-}
+-
+ static inline void __dev_flush(void)
+ {
+ }
+@@ -1868,11 +1863,6 @@ static inline int cpu_map_generic_redirect(struct bpf_cpu_map_entry *rcpu,
+ return -EOPNOTSUPP;
+ }
+
+-static inline bool cpu_map_prog_allowed(struct bpf_map *map)
+-{
+- return false;
+-}
+-
+ static inline struct bpf_prog *bpf_prog_get_type_path(const char *name,
+ enum bpf_prog_type type)
+ {
+diff --git a/include/linux/skmsg.h b/include/linux/skmsg.h
+index 0c742cdf413c..13652d225b81 100644
+--- a/include/linux/skmsg.h
++++ b/include/linux/skmsg.h
+@@ -171,11 +171,6 @@ static inline u32 sk_msg_iter_dist(u32 start, u32 end)
+ #define sk_msg_iter_next(msg, which) \
+ sk_msg_iter_var_next(msg->sg.which)
+
+-static inline void sk_msg_clear_meta(struct sk_msg *msg)
+-{
+- memset(&msg->sg, 0, offsetofend(struct sk_msg_sg, copy));
+-}
+-
+ static inline void sk_msg_init(struct sk_msg *msg)
+ {
+ BUILD_BUG_ON(ARRAY_SIZE(msg->sg.data) - 1 != NR_MSG_FRAG_IDS);
+diff --git a/net/xdp/xsk_queue.h b/net/xdp/xsk_queue.h
+index 491a18c1f786..0e59b4611f18 100644
+--- a/net/xdp/xsk_queue.h
++++ b/net/xdp/xsk_queue.h
+@@ -292,13 +292,6 @@ static inline void xskq_cons_release_n(struct xsk_queue *q, u32 cnt)
+ q->cached_cons += cnt;
+ }
+
+-static inline bool xskq_cons_is_full(struct xsk_queue *q)
+-{
+- /* No barriers needed since data is not accessed */
+- return READ_ONCE(q->ring->producer) - READ_ONCE(q->ring->consumer) ==
+- q->nentries;
+-}
+-
+ static inline u32 xskq_cons_present_entries(struct xsk_queue *q)
+ {
+ /* No barriers needed since data is not accessed */
+--
+2.35.1
+
--- /dev/null
+From 9cc57db8711eb7d4e369a04e19491706312f7cc8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 14:19:35 +0800
+Subject: bpf: Use this_cpu_{inc|dec|inc_return} for bpf_task_storage_busy
+
+From: Hou Tao <houtao1@huawei.com>
+
+[ Upstream commit 197827a05e13808c60f52632e9887eede63f1c16 ]
+
+Now migrate_disable() does not disable preemption and under some
+architectures (e.g. arm64) __this_cpu_{inc|dec|inc_return} are neither
+preemption-safe nor IRQ-safe, so for fully preemptible kernel concurrent
+lookups or updates on the same task local storage and on the same CPU
+may make bpf_task_storage_busy be imbalanced, and
+bpf_task_storage_trylock() on the specific cpu will always fail.
+
+Fixing it by using this_cpu_{inc|dec|inc_return} when manipulating
+bpf_task_storage_busy.
+
+Fixes: bc235cdb423a ("bpf: Prevent deadlock from recursive bpf_task_storage_[get|delete]")
+Signed-off-by: Hou Tao <houtao1@huawei.com>
+Acked-by: Alexei Starovoitov <ast@kernel.org>
+Link: https://lore.kernel.org/r/20220901061938.3789460-2-houtao@huaweicloud.com
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/bpf_local_storage.c | 4 ++--
+ kernel/bpf/bpf_task_storage.c | 8 ++++----
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/kernel/bpf/bpf_local_storage.c b/kernel/bpf/bpf_local_storage.c
+index b305270b7a4b..de4d741d99a3 100644
+--- a/kernel/bpf/bpf_local_storage.c
++++ b/kernel/bpf/bpf_local_storage.c
+@@ -506,11 +506,11 @@ void bpf_local_storage_map_free(struct bpf_local_storage_map *smap,
+ struct bpf_local_storage_elem, map_node))) {
+ if (busy_counter) {
+ migrate_disable();
+- __this_cpu_inc(*busy_counter);
++ this_cpu_inc(*busy_counter);
+ }
+ bpf_selem_unlink(selem);
+ if (busy_counter) {
+- __this_cpu_dec(*busy_counter);
++ this_cpu_dec(*busy_counter);
+ migrate_enable();
+ }
+ cond_resched_rcu();
+diff --git a/kernel/bpf/bpf_task_storage.c b/kernel/bpf/bpf_task_storage.c
+index ebfa8bc90892..6b7bfce23915 100644
+--- a/kernel/bpf/bpf_task_storage.c
++++ b/kernel/bpf/bpf_task_storage.c
+@@ -25,20 +25,20 @@ static DEFINE_PER_CPU(int, bpf_task_storage_busy);
+ static void bpf_task_storage_lock(void)
+ {
+ migrate_disable();
+- __this_cpu_inc(bpf_task_storage_busy);
++ this_cpu_inc(bpf_task_storage_busy);
+ }
+
+ static void bpf_task_storage_unlock(void)
+ {
+- __this_cpu_dec(bpf_task_storage_busy);
++ this_cpu_dec(bpf_task_storage_busy);
+ migrate_enable();
+ }
+
+ static bool bpf_task_storage_trylock(void)
+ {
+ migrate_disable();
+- if (unlikely(__this_cpu_inc_return(bpf_task_storage_busy) != 1)) {
+- __this_cpu_dec(bpf_task_storage_busy);
++ if (unlikely(this_cpu_inc_return(bpf_task_storage_busy) != 1)) {
++ this_cpu_dec(bpf_task_storage_busy);
+ migrate_enable();
+ return false;
+ }
+--
+2.35.1
+
--- /dev/null
+From f9e6be85686879800e7334362982b50446f4e8f7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 17:22:05 +0100
+Subject: bpftool: Clear errno after libcap's checks
+
+From: Quentin Monnet <quentin@isovalent.com>
+
+[ Upstream commit cea558855c39b7f1f02ff50dcf701ca6596bc964 ]
+
+When bpftool is linked against libcap, the library runs a "constructor"
+function to compute the number of capabilities of the running kernel
+[0], at the beginning of the execution of the program. As part of this,
+it performs multiple calls to prctl(). Some of these may fail, and set
+errno to a non-zero value:
+
+ # strace -e prctl ./bpftool version
+ prctl(PR_CAPBSET_READ, CAP_MAC_OVERRIDE) = 1
+ prctl(PR_CAPBSET_READ, 0x30 /* CAP_??? */) = -1 EINVAL (Invalid argument)
+ prctl(PR_CAPBSET_READ, CAP_CHECKPOINT_RESTORE) = 1
+ prctl(PR_CAPBSET_READ, 0x2c /* CAP_??? */) = -1 EINVAL (Invalid argument)
+ prctl(PR_CAPBSET_READ, 0x2a /* CAP_??? */) = -1 EINVAL (Invalid argument)
+ prctl(PR_CAPBSET_READ, 0x29 /* CAP_??? */) = -1 EINVAL (Invalid argument)
+ ** fprintf added at the top of main(): we have errno == 1
+ ./bpftool v7.0.0
+ using libbpf v1.0
+ features: libbfd, libbpf_strict, skeletons
+ +++ exited with 0 +++
+
+This has been addressed in libcap 2.63 [1], but until this version is
+available everywhere, we can fix it on bpftool side.
+
+Let's clean errno at the beginning of the main() function, to make sure
+that these checks do not interfere with the batch mode, where we error
+out if errno is set after a bpftool command.
+
+ [0] https://git.kernel.org/pub/scm/libs/libcap/libcap.git/tree/libcap/cap_alloc.c?h=libcap-2.65#n20
+ [1] https://git.kernel.org/pub/scm/libs/libcap/libcap.git/commit/?id=f25a1b7e69f7b33e6afb58b3e38f3450b7d2d9a0
+
+Signed-off-by: Quentin Monnet <quentin@isovalent.com>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Link: https://lore.kernel.org/bpf/20220815162205.45043-1-quentin@isovalent.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/bpf/bpftool/main.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c
+index d27ec4f852bb..b70c023f3a57 100644
+--- a/tools/bpf/bpftool/main.c
++++ b/tools/bpf/bpftool/main.c
+@@ -404,6 +404,16 @@ int main(int argc, char **argv)
+
+ setlinebuf(stdout);
+
++#ifdef USE_LIBCAP
++ /* Libcap < 2.63 hooks before main() to compute the number of
++ * capabilities of the running kernel, and doing so it calls prctl()
++ * which may fail and set errno to non-zero.
++ * Let's reset errno to make sure this does not interfere with the
++ * batch mode.
++ */
++ errno = 0;
++#endif
++
+ last_do_help = do_help;
+ pretty_output = false;
+ json_output = false;
+--
+2.35.1
+
--- /dev/null
+From e34588998f3bd2f4205570f19538099503969284 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 15:59:00 -0700
+Subject: bpftool: Fix a wrong type cast in btf_dumper_int
+
+From: Lam Thai <lamthai@arista.com>
+
+[ Upstream commit 7184aef9c0f7a81db8fd18d183ee42481d89bf35 ]
+
+When `data` points to a boolean value, casting it to `int *` is problematic
+and could lead to a wrong value being passed to `jsonw_bool`. Change the
+cast to `bool *` instead.
+
+Fixes: b12d6ec09730 ("bpf: btf: add btf print functionality")
+Signed-off-by: Lam Thai <lamthai@arista.com>
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Reviewed-by: Quentin Monnet <quentin@isovalent.com>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Link: https://lore.kernel.org/bpf/20220824225859.9038-1-lamthai@arista.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/bpf/bpftool/btf_dumper.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/bpf/bpftool/btf_dumper.c b/tools/bpf/bpftool/btf_dumper.c
+index 9c25286a5c73..70fb26a3dfa8 100644
+--- a/tools/bpf/bpftool/btf_dumper.c
++++ b/tools/bpf/bpftool/btf_dumper.c
+@@ -418,7 +418,7 @@ static int btf_dumper_int(const struct btf_type *t, __u8 bit_offset,
+ *(char *)data);
+ break;
+ case BTF_INT_BOOL:
+- jsonw_bool(jw, *(int *)data);
++ jsonw_bool(jw, *(bool *)data);
+ break;
+ default:
+ /* shouldn't happen */
+--
+2.35.1
+
--- /dev/null
+From 4524d3949d0bf4877bf901de76095f3818c3f1dc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 18:32:23 +0200
+Subject: btrfs: add KCSAN annotations for unlocked access to block_rsv->full
+
+From: David Sterba <dsterba@suse.com>
+
+[ Upstream commit 748f553c3c4c4f175c6c834358632aff802d72cf ]
+
+KCSAN reports that there's unlocked access mixed with locked access,
+which is technically correct but is not a bug. To avoid false alerts at
+least from KCSAN, add annotation and use a wrapper whenever ->full is
+accessed for read outside of lock.
+
+It is used as a fast check and only advisory. In the worst case the
+block reserve is found !full and becomes full in the meantime, but
+properly handled.
+
+Depending on the value of ->full, btrfs_block_rsv_release decides
+where to return the reservation, and block_rsv_release_bytes handles a
+NULL pointer for block_rsv and if it's not NULL then it double checks
+the full status under a lock.
+
+Link: https://lore.kernel.org/linux-btrfs/CAAwBoOJDjei5Hnem155N_cJwiEkVwJYvgN-tQrwWbZQGhFU=cA@mail.gmail.com/
+Link: https://lore.kernel.org/linux-btrfs/YvHU/vsXd7uz5V6j@hungrycats.org
+Reported-by: Zygo Blaxell <ce3g8jdj@umail.furryterror.org>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/block-rsv.c | 2 +-
+ fs/btrfs/block-rsv.h | 9 +++++++++
+ fs/btrfs/transaction.c | 4 ++--
+ 3 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/fs/btrfs/block-rsv.c b/fs/btrfs/block-rsv.c
+index 04a6226e0388..3e0eb69b6d4e 100644
+--- a/fs/btrfs/block-rsv.c
++++ b/fs/btrfs/block-rsv.c
+@@ -285,7 +285,7 @@ u64 btrfs_block_rsv_release(struct btrfs_fs_info *fs_info,
+ */
+ if (block_rsv == delayed_rsv)
+ target = global_rsv;
+- else if (block_rsv != global_rsv && !delayed_rsv->full)
++ else if (block_rsv != global_rsv && !btrfs_block_rsv_full(delayed_rsv))
+ target = delayed_rsv;
+
+ if (target && block_rsv->space_info != target->space_info)
+diff --git a/fs/btrfs/block-rsv.h b/fs/btrfs/block-rsv.h
+index 0b6ae5302837..f0431547acf2 100644
+--- a/fs/btrfs/block-rsv.h
++++ b/fs/btrfs/block-rsv.h
+@@ -90,4 +90,13 @@ static inline void btrfs_unuse_block_rsv(struct btrfs_fs_info *fs_info,
+ btrfs_block_rsv_release(fs_info, block_rsv, 0, NULL);
+ }
+
++/*
++ * Fast path to check if the reserve is full, may be carefully used outside of
++ * locks.
++ */
++static inline bool btrfs_block_rsv_full(const struct btrfs_block_rsv *rsv)
++{
++ return data_race(rsv->full);
++}
++
+ #endif /* BTRFS_BLOCK_RSV_H */
+diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c
+index 642cd2b55fa0..6b6a1a277f01 100644
+--- a/fs/btrfs/transaction.c
++++ b/fs/btrfs/transaction.c
+@@ -619,7 +619,7 @@ start_transaction(struct btrfs_root *root, unsigned int num_items,
+ */
+ num_bytes = btrfs_calc_insert_metadata_size(fs_info, num_items);
+ if (flush == BTRFS_RESERVE_FLUSH_ALL &&
+- delayed_refs_rsv->full == 0) {
++ btrfs_block_rsv_full(delayed_refs_rsv) == 0) {
+ delayed_refs_bytes = num_bytes;
+ num_bytes <<= 1;
+ }
+@@ -644,7 +644,7 @@ start_transaction(struct btrfs_root *root, unsigned int num_items,
+ if (rsv->space_info->force_alloc)
+ do_chunk_alloc = true;
+ } else if (num_items == 0 && flush == BTRFS_RESERVE_FLUSH_ALL &&
+- !delayed_refs_rsv->full) {
++ !btrfs_block_rsv_full(delayed_refs_rsv)) {
+ /*
+ * Some people call with btrfs_start_transaction(root, 0)
+ * because they can be throttled, but have some other mechanism
+--
+2.35.1
+
--- /dev/null
+From 1587253bfd3c2e90d8659abd8093396881f622fc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Jul 2022 15:11:46 -0700
+Subject: btrfs: add macros for annotating wait events with lockdep
+
+From: Ioannis Angelakopoulos <iangelak@fb.com>
+
+[ Upstream commit ab9a323f9ab576000795285dd7ac6afeedf29e32 ]
+
+Introduce four macros that are used to annotate wait events in btrfs code
+with lockdep;
+
+ 1) the btrfs_lockdep_init_map
+ 2) the btrfs_lockdep_acquire,
+ 3) the btrfs_lockdep_release
+ 4) the btrfs_might_wait_for_event macros.
+
+The btrfs_lockdep_init_map macro is used to initialize a lockdep map.
+
+The btrfs_lockdep_<acquire,release> macros are used by threads to take
+the lockdep map as readers (shared lock) and release it, respectively.
+
+The btrfs_might_wait_for_event macro is used by threads to take the
+lockdep map as writers (exclusive lock) and release it.
+
+In general, the lockdep annotation for wait events work as follows:
+
+The condition for a wait event can be modified and signaled at the same
+time by multiple threads. These threads hold the lockdep map as readers
+when they enter a context in which blocking would prevent signaling the
+condition. Frequently, this occurs when a thread violates a condition
+(lockdep map acquire), before restoring it and signaling it at a later
+point (lockdep map release).
+
+The threads that block on the wait event take the lockdep map as writers
+(exclusive lock). These threads have to block until all the threads that
+hold the lockdep map as readers signal the condition for the wait event
+and release the lockdep map.
+
+The lockdep annotation is used to warn about potential deadlock scenarios
+that involve the threads that modify and signal the wait event condition
+and threads that block on the wait event. A simple example is illustrated
+below:
+
+Without lockdep:
+
+TA TB
+cond = false
+ lock(A)
+ wait_event(w, cond)
+ unlock(A)
+lock(A)
+cond = true
+signal(w)
+unlock(A)
+
+With lockdep:
+
+TA TB
+rwsem_acquire_read(lockdep_map)
+cond = false
+ lock(A)
+ rwsem_acquire(lockdep_map)
+ rwsem_release(lockdep_map)
+ wait_event(w, cond)
+ unlock(A)
+lock(A)
+cond = true
+signal(w)
+unlock(A)
+rwsem_release(lockdep_map)
+
+In the second case, with the lockdep annotation, lockdep would warn about
+an ABBA deadlock, while the first case would just deadlock at some point.
+
+Reviewed-by: Josef Bacik <josef@toxicpanda.com>
+Signed-off-by: Ioannis Angelakopoulos <iangelak@fb.com>
+Reviewed-by: David Sterba <dsterba@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/ctree.h | 45 +++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
+index 02d3ee6c7d9b..3ab1219db32e 100644
+--- a/fs/btrfs/ctree.h
++++ b/fs/btrfs/ctree.h
+@@ -1108,6 +1108,51 @@ enum {
+ BTRFS_ROOT_RESET_LOCKDEP_CLASS,
+ };
+
++/*
++ * Lockdep annotation for wait events.
++ *
++ * @owner: The struct where the lockdep map is defined
++ * @lock: The lockdep map corresponding to a wait event
++ *
++ * This macro is used to annotate a wait event. In this case a thread acquires
++ * the lockdep map as writer (exclusive lock) because it has to block until all
++ * the threads that hold the lock as readers signal the condition for the wait
++ * event and release their locks.
++ */
++#define btrfs_might_wait_for_event(owner, lock) \
++ do { \
++ rwsem_acquire(&owner->lock##_map, 0, 0, _THIS_IP_); \
++ rwsem_release(&owner->lock##_map, _THIS_IP_); \
++ } while (0)
++
++/*
++ * Protection for the resource/condition of a wait event.
++ *
++ * @owner: The struct where the lockdep map is defined
++ * @lock: The lockdep map corresponding to a wait event
++ *
++ * Many threads can modify the condition for the wait event at the same time
++ * and signal the threads that block on the wait event. The threads that modify
++ * the condition and do the signaling acquire the lock as readers (shared
++ * lock).
++ */
++#define btrfs_lockdep_acquire(owner, lock) \
++ rwsem_acquire_read(&owner->lock##_map, 0, 0, _THIS_IP_)
++
++/*
++ * Used after signaling the condition for a wait event to release the lockdep
++ * map held by a reader thread.
++ */
++#define btrfs_lockdep_release(owner, lock) \
++ rwsem_release(&owner->lock##_map, _THIS_IP_)
++
++/* Initialization of the lockdep map */
++#define btrfs_lockdep_init_map(owner, lock) \
++ do { \
++ static struct lock_class_key lock##_key; \
++ lockdep_init_map(&owner->lock##_map, #lock, &lock##_key, 0); \
++ } while (0)
++
+ static inline void btrfs_wake_unfinished_drop(struct btrfs_fs_info *fs_info)
+ {
+ clear_and_wake_up_bit(BTRFS_FS_UNFINISHED_DROPS, &fs_info->flags);
+--
+2.35.1
+
--- /dev/null
+From 28946141bf21e5e533d472b762e7a4dac31be136 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Jul 2022 15:11:57 -0700
+Subject: btrfs: change the lockdep class of free space inode's invalidate_lock
+
+From: Ioannis Angelakopoulos <iangelak@fb.com>
+
+[ Upstream commit 9d7464c87b159bbf763c24faeb7a2dcaac96e4a1 ]
+
+Reinitialize the class of the lockdep map for struct inode's
+mapping->invalidate_lock in load_free_space_cache() function in
+fs/btrfs/free-space-cache.c. This will prevent lockdep from producing
+false positives related to execution paths that make use of free space
+inodes and paths that make use of normal inodes.
+
+Specifically, with this change lockdep will create separate lock
+dependencies that include the invalidate_lock, in the case that free
+space inodes are used and in the case that normal inodes are used.
+
+The lockdep class for this lock was first initialized in
+inode_init_always() in fs/inode.c.
+
+Reviewed-by: Josef Bacik <josef@toxicpanda.com>
+Signed-off-by: Ioannis Angelakopoulos <iangelak@fb.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/free-space-cache.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c
+index 529907ea3825..456da08feccd 100644
+--- a/fs/btrfs/free-space-cache.c
++++ b/fs/btrfs/free-space-cache.c
+@@ -899,6 +899,8 @@ static int copy_free_space_cache(struct btrfs_block_group *block_group,
+ return ret;
+ }
+
++static struct lock_class_key btrfs_free_space_inode_key;
++
+ int load_free_space_cache(struct btrfs_block_group *block_group)
+ {
+ struct btrfs_fs_info *fs_info = block_group->fs_info;
+@@ -968,6 +970,14 @@ int load_free_space_cache(struct btrfs_block_group *block_group)
+ }
+ spin_unlock(&block_group->lock);
+
++ /*
++ * Reinitialize the class of struct inode's mapping->invalidate_lock for
++ * free space inodes to prevent false positives related to locks for normal
++ * inodes.
++ */
++ lockdep_set_class(&(&inode->i_data)->invalidate_lock,
++ &btrfs_free_space_inode_key);
++
+ ret = __load_free_space_cache(fs_info->tree_root, inode, &tmp_ctl,
+ path, block_group->start);
+ btrfs_free_path(path);
+--
+2.35.1
+
--- /dev/null
+From d490034decc9adb54e82e9804e5dfac7bb746315 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 20:16:22 +0800
+Subject: btrfs: check superblock to ensure the fs was not modified at thaw
+ time
+
+From: Qu Wenruo <wqu@suse.com>
+
+[ Upstream commit a05d3c9153145283ce9c58a1d7a9056fbb85f6a1 ]
+
+[BACKGROUND]
+There is an incident report that, one user hibernated the system, with
+one btrfs on removable device still mounted.
+
+Then by some incident, the btrfs got mounted and modified by another
+system/OS, then back to the hibernated system.
+
+After resuming from the hibernation, new write happened into the victim btrfs.
+
+Now the fs is completely broken, since the underlying btrfs is no longer
+the same one before the hibernation, and the user lost their data due to
+various transid mismatch.
+
+[REPRODUCER]
+We can emulate the situation using the following small script:
+
+ truncate -s 1G $dev
+ mkfs.btrfs -f $dev
+ mount $dev $mnt
+ fsstress -w -d $mnt -n 500
+ sync
+ xfs_freeze -f $mnt
+ cp $dev $dev.backup
+
+ # There is no way to mount the same cloned fs on the same system,
+ # as the conflicting fsid will be rejected by btrfs.
+ # Thus here we have to wipe the fs using a different btrfs.
+ mkfs.btrfs -f $dev.backup
+
+ dd if=$dev.backup of=$dev bs=1M
+ xfs_freeze -u $mnt
+ fsstress -w -d $mnt -n 20
+ umount $mnt
+ btrfs check $dev
+
+The final fsck will fail due to some tree blocks has incorrect fsid.
+
+This is enough to emulate the problem hit by the unfortunate user.
+
+[ENHANCEMENT]
+Although such case should not be that common, it can still happen from
+time to time.
+
+From the view of btrfs, we can detect any unexpected super block change,
+and if there is any unexpected change, we just mark the fs read-only,
+and thaw the fs.
+
+By this we can limit the damage to minimal, and I hope no one would lose
+their data by this anymore.
+
+Suggested-by: Goffredo Baroncelli <kreijack@libero.it>
+Link: https://lore.kernel.org/linux-btrfs/83bf3b4b-7f4c-387a-b286-9251e3991e34@bluemole.com/
+Reviewed-by: Anand Jain <anand.jain@oracle.com>
+Signed-off-by: Qu Wenruo <wqu@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/disk-io.c | 25 ++++++++++++++-----
+ fs/btrfs/disk-io.h | 4 +++-
+ fs/btrfs/super.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
+ fs/btrfs/volumes.c | 2 +-
+ 4 files changed, 83 insertions(+), 8 deletions(-)
+
+diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
+index f4015556cafa..c812aff63e1b 100644
+--- a/fs/btrfs/disk-io.c
++++ b/fs/btrfs/disk-io.c
+@@ -2489,8 +2489,8 @@ static int btrfs_read_roots(struct btrfs_fs_info *fs_info)
+ * 1, 2 2nd and 3rd backup copy
+ * -1 skip bytenr check
+ */
+-static int validate_super(struct btrfs_fs_info *fs_info,
+- struct btrfs_super_block *sb, int mirror_num)
++int btrfs_validate_super(struct btrfs_fs_info *fs_info,
++ struct btrfs_super_block *sb, int mirror_num)
+ {
+ u64 nodesize = btrfs_super_nodesize(sb);
+ u64 sectorsize = btrfs_super_sectorsize(sb);
+@@ -2673,7 +2673,7 @@ static int validate_super(struct btrfs_fs_info *fs_info,
+ */
+ static int btrfs_validate_mount_super(struct btrfs_fs_info *fs_info)
+ {
+- return validate_super(fs_info, fs_info->super_copy, 0);
++ return btrfs_validate_super(fs_info, fs_info->super_copy, 0);
+ }
+
+ /*
+@@ -2687,7 +2687,7 @@ static int btrfs_validate_write_super(struct btrfs_fs_info *fs_info,
+ {
+ int ret;
+
+- ret = validate_super(fs_info, sb, -1);
++ ret = btrfs_validate_super(fs_info, sb, -1);
+ if (ret < 0)
+ goto out;
+ if (!btrfs_supported_super_csum(btrfs_super_csum_type(sb))) {
+@@ -3701,7 +3701,7 @@ static void btrfs_end_super_write(struct bio *bio)
+ }
+
+ struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev,
+- int copy_num)
++ int copy_num, bool drop_cache)
+ {
+ struct btrfs_super_block *super;
+ struct page *page;
+@@ -3719,6 +3719,19 @@ struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev,
+ if (bytenr + BTRFS_SUPER_INFO_SIZE >= i_size_read(bdev->bd_inode))
+ return ERR_PTR(-EINVAL);
+
++ if (drop_cache) {
++ /* This should only be called with the primary sb. */
++ ASSERT(copy_num == 0);
++
++ /*
++ * Drop the page of the primary superblock, so later read will
++ * always read from the device.
++ */
++ invalidate_inode_pages2_range(mapping,
++ bytenr >> PAGE_SHIFT,
++ (bytenr + BTRFS_SUPER_INFO_SIZE) >> PAGE_SHIFT);
++ }
++
+ page = read_cache_page_gfp(mapping, bytenr >> PAGE_SHIFT, GFP_NOFS);
+ if (IS_ERR(page))
+ return ERR_CAST(page);
+@@ -3750,7 +3763,7 @@ struct btrfs_super_block *btrfs_read_dev_super(struct block_device *bdev)
+ * later supers, using BTRFS_SUPER_MIRROR_MAX instead
+ */
+ for (i = 0; i < 1; i++) {
+- super = btrfs_read_dev_one_super(bdev, i);
++ super = btrfs_read_dev_one_super(bdev, i, false);
+ if (IS_ERR(super))
+ continue;
+
+diff --git a/fs/btrfs/disk-io.h b/fs/btrfs/disk-io.h
+index 1b8fd3deafc9..9de0c39f63a2 100644
+--- a/fs/btrfs/disk-io.h
++++ b/fs/btrfs/disk-io.h
+@@ -56,10 +56,12 @@ int __cold open_ctree(struct super_block *sb,
+ struct btrfs_fs_devices *fs_devices,
+ char *options);
+ void __cold close_ctree(struct btrfs_fs_info *fs_info);
++int btrfs_validate_super(struct btrfs_fs_info *fs_info,
++ struct btrfs_super_block *sb, int mirror_num);
+ int write_all_supers(struct btrfs_fs_info *fs_info, int max_mirrors);
+ struct btrfs_super_block *btrfs_read_dev_super(struct block_device *bdev);
+ struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev,
+- int copy_num);
++ int copy_num, bool drop_cache);
+ int btrfs_commit_super(struct btrfs_fs_info *fs_info);
+ struct btrfs_root *btrfs_read_tree_root(struct btrfs_root *tree_root,
+ struct btrfs_key *key);
+diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
+index 442fcd1b14a6..135ddfb47b39 100644
+--- a/fs/btrfs/super.c
++++ b/fs/btrfs/super.c
+@@ -2488,11 +2488,71 @@ static int btrfs_freeze(struct super_block *sb)
+ return btrfs_commit_transaction(trans);
+ }
+
++static int check_dev_super(struct btrfs_device *dev)
++{
++ struct btrfs_fs_info *fs_info = dev->fs_info;
++ struct btrfs_super_block *sb;
++ int ret = 0;
++
++ /* This should be called with fs still frozen. */
++ ASSERT(test_bit(BTRFS_FS_FROZEN, &fs_info->flags));
++
++ /* Missing dev, no need to check. */
++ if (!dev->bdev)
++ return 0;
++
++ /* Only need to check the primary super block. */
++ sb = btrfs_read_dev_one_super(dev->bdev, 0, true);
++ if (IS_ERR(sb))
++ return PTR_ERR(sb);
++
++ /* Btrfs_validate_super() includes fsid check against super->fsid. */
++ ret = btrfs_validate_super(fs_info, sb, 0);
++ if (ret < 0)
++ goto out;
++
++ if (btrfs_super_generation(sb) != fs_info->last_trans_committed) {
++ btrfs_err(fs_info, "transid mismatch, has %llu expect %llu",
++ btrfs_super_generation(sb),
++ fs_info->last_trans_committed);
++ ret = -EUCLEAN;
++ goto out;
++ }
++out:
++ btrfs_release_disk_super(sb);
++ return ret;
++}
++
+ static int btrfs_unfreeze(struct super_block *sb)
+ {
+ struct btrfs_fs_info *fs_info = btrfs_sb(sb);
++ struct btrfs_device *device;
++ int ret = 0;
+
++ /*
++ * Make sure the fs is not changed by accident (like hibernation then
++ * modified by other OS).
++ * If we found anything wrong, we mark the fs error immediately.
++ *
++ * And since the fs is frozen, no one can modify the fs yet, thus
++ * we don't need to hold device_list_mutex.
++ */
++ list_for_each_entry(device, &fs_info->fs_devices->devices, dev_list) {
++ ret = check_dev_super(device);
++ if (ret < 0) {
++ btrfs_handle_fs_error(fs_info, ret,
++ "super block on devid %llu got modified unexpectedly",
++ device->devid);
++ break;
++ }
++ }
+ clear_bit(BTRFS_FS_FROZEN, &fs_info->flags);
++
++ /*
++ * We still return 0, to allow VFS layer to unfreeze the fs even the
++ * above checks failed. Since the fs is either fine or read-only, we're
++ * safe to continue, without causing further damage.
++ */
+ return 0;
+ }
+
+diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
+index 0f22d91e2392..82db36019a3d 100644
+--- a/fs/btrfs/volumes.c
++++ b/fs/btrfs/volumes.c
+@@ -2074,7 +2074,7 @@ void btrfs_scratch_superblocks(struct btrfs_fs_info *fs_info,
+ struct page *page;
+ int ret;
+
+- disk_super = btrfs_read_dev_one_super(bdev, copy_num);
++ disk_super = btrfs_read_dev_one_super(bdev, copy_num, false);
+ if (IS_ERR(disk_super))
+ continue;
+
+--
+2.35.1
+
--- /dev/null
+From f475dc0e22e857051dc33200584a8be522bf9895 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Aug 2022 17:28:20 +0200
+Subject: btrfs: don't print information about space cache or tree every
+ remount
+
+From: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
+
+[ Upstream commit dbecac26630014d336a8e5ea67096ff18210fb9c ]
+
+btrfs currently prints information about space cache or free space tree
+being in use on every remount, regardless whether such remount actually
+enabled or disabled one of these features.
+
+This is actually unnecessary since providing remount options changing the
+state of these features will explicitly print the appropriate notice.
+
+Let's instead print such unconditional information just on an initial mount
+to avoid filling the kernel log when, for example, laptop-mode-tools
+remount the fs on some events.
+
+Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
+Reviewed-by: David Sterba <dsterba@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/super.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
+index 969bf0724fdf..442fcd1b14a6 100644
+--- a/fs/btrfs/super.c
++++ b/fs/btrfs/super.c
+@@ -574,6 +574,7 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
+ int saved_compress_level;
+ bool saved_compress_force;
+ int no_compress = 0;
++ const bool remounting = test_bit(BTRFS_FS_STATE_REMOUNTING, &info->fs_state);
+
+ if (btrfs_fs_compat_ro(info, FREE_SPACE_TREE))
+ btrfs_set_opt(info->mount_opt, FREE_SPACE_TREE);
+@@ -1065,10 +1066,12 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
+ }
+ if (!ret)
+ ret = btrfs_check_mountopts_zoned(info);
+- if (!ret && btrfs_test_opt(info, SPACE_CACHE))
+- btrfs_info(info, "disk space caching is enabled");
+- if (!ret && btrfs_test_opt(info, FREE_SPACE_TREE))
+- btrfs_info(info, "using free space tree");
++ if (!ret && !remounting) {
++ if (btrfs_test_opt(info, SPACE_CACHE))
++ btrfs_info(info, "disk space caching is enabled");
++ if (btrfs_test_opt(info, FREE_SPACE_TREE))
++ btrfs_info(info, "using free space tree");
++ }
+ return ret;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From e2536c83905ef62006039df009bba4aae0eb7d46 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Aug 2022 09:35:57 +0800
+Subject: btrfs: dump extra info if one free space cache has more bitmaps than
+ it should
+
+From: Qu Wenruo <wqu@suse.com>
+
+[ Upstream commit 62cd9d4474282a1eb84f945955c56cbfc42e1ffe ]
+
+There is an internal report on hitting the following ASSERT() in
+recalculate_thresholds():
+
+ ASSERT(ctl->total_bitmaps <= max_bitmaps);
+
+Above @max_bitmaps is calculated using the following variables:
+
+- bytes_per_bg
+ 8 * 4096 * 4096 (128M) for x86_64/x86.
+
+- block_group->length
+ The length of the block group.
+
+@max_bitmaps is the rounded up value of block_group->length / 128M.
+
+Normally one free space cache should not have more bitmaps than above
+value, but when it happens the ASSERT() can be triggered if
+CONFIG_BTRFS_ASSERT is also enabled.
+
+But the ASSERT() itself won't provide enough info to know which is going
+wrong.
+Is the bg too small thus it only allows one bitmap?
+Or is there something else wrong?
+
+So although I haven't found extra reports or crash dump to do further
+investigation, add the extra info to make it more helpful to debug.
+
+Reviewed-by: Anand Jain <anand.jain@oracle.com>
+Signed-off-by: Qu Wenruo <wqu@suse.com>
+Reviewed-by: David Sterba <dsterba@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/free-space-cache.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c
+index da0eee7c9e5f..529907ea3825 100644
+--- a/fs/btrfs/free-space-cache.c
++++ b/fs/btrfs/free-space-cache.c
+@@ -672,6 +672,12 @@ static void recalculate_thresholds(struct btrfs_free_space_ctl *ctl)
+
+ max_bitmaps = max_t(u64, max_bitmaps, 1);
+
++ if (ctl->total_bitmaps > max_bitmaps)
++ btrfs_err(block_group->fs_info,
++"invalid free space control: bg start=%llu len=%llu total_bitmaps=%u unit=%u max_bitmaps=%llu bytes_per_bg=%llu",
++ block_group->start, block_group->length,
++ ctl->total_bitmaps, ctl->unit, max_bitmaps,
++ bytes_per_bg);
+ ASSERT(ctl->total_bitmaps <= max_bitmaps);
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From ee562d8d8306f72f89eb93844e86a405d7f3f990 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 Aug 2022 14:53:03 +0800
+Subject: btrfs: scrub: try to fix super block errors
+
+From: Qu Wenruo <wqu@suse.com>
+
+[ Upstream commit f9eab5f0bba76742af654f33d517bf62a0db8f12 ]
+
+[BUG]
+The following script shows that, although scrub can detect super block
+errors, it never tries to fix it:
+
+ mkfs.btrfs -f -d raid1 -m raid1 $dev1 $dev2
+ xfs_io -c "pwrite 67108864 4k" $dev2
+
+ mount $dev1 $mnt
+ btrfs scrub start -B $dev2
+ btrfs scrub start -Br $dev2
+ umount $mnt
+
+The first scrub reports the super error correctly:
+
+ scrub done for f3289218-abd3-41ac-a630-202f766c0859
+ Scrub started: Tue Aug 2 14:44:11 2022
+ Status: finished
+ Duration: 0:00:00
+ Total to scrub: 1.26GiB
+ Rate: 0.00B/s
+ Error summary: super=1
+ Corrected: 0
+ Uncorrectable: 0
+ Unverified: 0
+
+But the second read-only scrub still reports the same super error:
+
+ Scrub started: Tue Aug 2 14:44:11 2022
+ Status: finished
+ Duration: 0:00:00
+ Total to scrub: 1.26GiB
+ Rate: 0.00B/s
+ Error summary: super=1
+ Corrected: 0
+ Uncorrectable: 0
+ Unverified: 0
+
+[CAUSE]
+The comments already shows that super block can be easily fixed by
+committing a transaction:
+
+ /*
+ * If we find an error in a super block, we just report it.
+ * They will get written with the next transaction commit
+ * anyway
+ */
+
+But the truth is, such assumption is not always true, and since scrub
+should try to repair every error it found (except for read-only scrub),
+we should really actively commit a transaction to fix this.
+
+[FIX]
+Just commit a transaction if we found any super block errors, after
+everything else is done.
+
+We cannot do this just after scrub_supers(), as
+btrfs_commit_transaction() will try to pause and wait for the running
+scrub, thus we can not call it with scrub_lock hold.
+
+Signed-off-by: Qu Wenruo <wqu@suse.com>
+Reviewed-by: David Sterba <dsterba@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/scrub.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/fs/btrfs/scrub.c b/fs/btrfs/scrub.c
+index 0785d9d645fc..ca8d6979c788 100644
+--- a/fs/btrfs/scrub.c
++++ b/fs/btrfs/scrub.c
+@@ -4072,6 +4072,7 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start,
+ int ret;
+ struct btrfs_device *dev;
+ unsigned int nofs_flag;
++ bool need_commit = false;
+
+ if (btrfs_fs_closing(fs_info))
+ return -EAGAIN;
+@@ -4177,6 +4178,12 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start,
+ */
+ nofs_flag = memalloc_nofs_save();
+ if (!is_dev_replace) {
++ u64 old_super_errors;
++
++ spin_lock(&sctx->stat_lock);
++ old_super_errors = sctx->stat.super_errors;
++ spin_unlock(&sctx->stat_lock);
++
+ btrfs_info(fs_info, "scrub: started on devid %llu", devid);
+ /*
+ * by holding device list mutex, we can
+@@ -4185,6 +4192,16 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start,
+ mutex_lock(&fs_info->fs_devices->device_list_mutex);
+ ret = scrub_supers(sctx, dev);
+ mutex_unlock(&fs_info->fs_devices->device_list_mutex);
++
++ spin_lock(&sctx->stat_lock);
++ /*
++ * Super block errors found, but we can not commit transaction
++ * at current context, since btrfs_commit_transaction() needs
++ * to pause the current running scrub (hold by ourselves).
++ */
++ if (sctx->stat.super_errors > old_super_errors && !sctx->readonly)
++ need_commit = true;
++ spin_unlock(&sctx->stat_lock);
+ }
+
+ if (!ret)
+@@ -4211,6 +4228,25 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start,
+ scrub_workers_put(fs_info);
+ scrub_put_ctx(sctx);
+
++ /*
++ * We found some super block errors before, now try to force a
++ * transaction commit, as scrub has finished.
++ */
++ if (need_commit) {
++ struct btrfs_trans_handle *trans;
++
++ trans = btrfs_start_transaction(fs_info->tree_root, 0);
++ if (IS_ERR(trans)) {
++ ret = PTR_ERR(trans);
++ btrfs_err(fs_info,
++ "scrub: failed to start transaction to fix super block errors: %d", ret);
++ return ret;
++ }
++ ret = btrfs_commit_transaction(trans);
++ if (ret < 0)
++ btrfs_err(fs_info,
++ "scrub: failed to commit transaction to fix super block errors: %d", ret);
++ }
+ return ret;
+ out:
+ scrub_workers_put(fs_info);
+--
+2.35.1
+
--- /dev/null
+From 4166032c305d5875eff9fd43b703db64df3ce3d2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 17:53:19 -0400
+Subject: btrfs: separate out the eb and extent state leak helpers
+
+From: Josef Bacik <josef@toxicpanda.com>
+
+[ Upstream commit a40246e8afc0af3ffdee21854fb755c9364b8346 ]
+
+Currently we have the add/del functions generic so that we can use them
+for both extent buffers and extent states. We want to separate this
+code however, so separate these helpers into per-object helpers in
+anticipation of the split.
+
+Signed-off-by: Josef Bacik <josef@toxicpanda.com>
+Reviewed-by: David Sterba <dsterba@suse.com>
+Signed-off-by: David Sterba <dsterba@suse.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/btrfs/extent_io.c | 58 +++++++++++++++++++++++++++++---------------
+ 1 file changed, 38 insertions(+), 20 deletions(-)
+
+diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
+index 7bd704779a99..eef6e38915ab 100644
+--- a/fs/btrfs/extent_io.c
++++ b/fs/btrfs/extent_io.c
+@@ -43,25 +43,42 @@ static inline bool extent_state_in_tree(const struct extent_state *state)
+ static LIST_HEAD(states);
+ static DEFINE_SPINLOCK(leak_lock);
+
+-static inline void btrfs_leak_debug_add(spinlock_t *lock,
+- struct list_head *new,
+- struct list_head *head)
++static inline void btrfs_leak_debug_add_eb(struct extent_buffer *eb)
++{
++ struct btrfs_fs_info *fs_info = eb->fs_info;
++ unsigned long flags;
++
++ spin_lock_irqsave(&fs_info->eb_leak_lock, flags);
++ list_add(&eb->leak_list, &fs_info->allocated_ebs);
++ spin_unlock_irqrestore(&fs_info->eb_leak_lock, flags);
++}
++
++static inline void btrfs_leak_debug_add_state(struct extent_state *state)
+ {
+ unsigned long flags;
+
+- spin_lock_irqsave(lock, flags);
+- list_add(new, head);
+- spin_unlock_irqrestore(lock, flags);
++ spin_lock_irqsave(&leak_lock, flags);
++ list_add(&state->leak_list, &states);
++ spin_unlock_irqrestore(&leak_lock, flags);
++}
++
++static inline void btrfs_leak_debug_del_eb(struct extent_buffer *eb)
++{
++ struct btrfs_fs_info *fs_info = eb->fs_info;
++ unsigned long flags;
++
++ spin_lock_irqsave(&fs_info->eb_leak_lock, flags);
++ list_del(&eb->leak_list);
++ spin_unlock_irqrestore(&fs_info->eb_leak_lock, flags);
+ }
+
+-static inline void btrfs_leak_debug_del(spinlock_t *lock,
+- struct list_head *entry)
++static inline void btrfs_leak_debug_del_state(struct extent_state *state)
+ {
+ unsigned long flags;
+
+- spin_lock_irqsave(lock, flags);
+- list_del(entry);
+- spin_unlock_irqrestore(lock, flags);
++ spin_lock_irqsave(&leak_lock, flags);
++ list_del(&state->leak_list);
++ spin_unlock_irqrestore(&leak_lock, flags);
+ }
+
+ void btrfs_extent_buffer_leak_debug_check(struct btrfs_fs_info *fs_info)
+@@ -124,9 +141,11 @@ static inline void __btrfs_debug_check_extent_io_range(const char *caller,
+ }
+ }
+ #else
+-#define btrfs_leak_debug_add(lock, new, head) do {} while (0)
+-#define btrfs_leak_debug_del(lock, entry) do {} while (0)
+-#define btrfs_extent_state_leak_debug_check() do {} while (0)
++#define btrfs_leak_debug_add_eb(eb) do {} while (0)
++#define btrfs_leak_debug_add_state(state) do {} while (0)
++#define btrfs_leak_debug_del_eb(eb) do {} while (0)
++#define btrfs_leak_debug_del_state(state) do {} while (0)
++#define btrfs_extent_state_leak_debug_check() do {} while (0)
+ #define btrfs_debug_check_extent_io_range(c, s, e) do {} while (0)
+ #endif
+
+@@ -343,7 +362,7 @@ static struct extent_state *alloc_extent_state(gfp_t mask)
+ state->state = 0;
+ state->failrec = NULL;
+ RB_CLEAR_NODE(&state->rb_node);
+- btrfs_leak_debug_add(&leak_lock, &state->leak_list, &states);
++ btrfs_leak_debug_add_state(state);
+ refcount_set(&state->refs, 1);
+ init_waitqueue_head(&state->wq);
+ trace_alloc_extent_state(state, mask, _RET_IP_);
+@@ -356,7 +375,7 @@ void free_extent_state(struct extent_state *state)
+ return;
+ if (refcount_dec_and_test(&state->refs)) {
+ WARN_ON(extent_state_in_tree(state));
+- btrfs_leak_debug_del(&leak_lock, &state->leak_list);
++ btrfs_leak_debug_del_state(state);
+ trace_free_extent_state(state, _RET_IP_);
+ kmem_cache_free(extent_state_cache, state);
+ }
+@@ -5830,7 +5849,7 @@ static void btrfs_release_extent_buffer_pages(struct extent_buffer *eb)
+ static inline void btrfs_release_extent_buffer(struct extent_buffer *eb)
+ {
+ btrfs_release_extent_buffer_pages(eb);
+- btrfs_leak_debug_del(&eb->fs_info->eb_leak_lock, &eb->leak_list);
++ btrfs_leak_debug_del_eb(eb);
+ __free_extent_buffer(eb);
+ }
+
+@@ -5847,8 +5866,7 @@ __alloc_extent_buffer(struct btrfs_fs_info *fs_info, u64 start,
+ eb->bflags = 0;
+ init_rwsem(&eb->lock);
+
+- btrfs_leak_debug_add(&fs_info->eb_leak_lock, &eb->leak_list,
+- &fs_info->allocated_ebs);
++ btrfs_leak_debug_add_eb(eb);
+ INIT_LIST_HEAD(&eb->release_list);
+
+ spin_lock_init(&eb->refs_lock);
+@@ -6294,7 +6312,7 @@ static int release_extent_buffer(struct extent_buffer *eb)
+ spin_unlock(&eb->refs_lock);
+ }
+
+- btrfs_leak_debug_del(&eb->fs_info->eb_leak_lock, &eb->leak_list);
++ btrfs_leak_debug_del_eb(eb);
+ /* Should be safe to release our pages at this point */
+ btrfs_release_extent_buffer_pages(eb);
+ #ifdef CONFIG_BTRFS_FS_RUN_SANITY_TESTS
+--
+2.35.1
+
--- /dev/null
+From 8e37e4efecf98026a8c2f2efe352fa941fb1acd5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 15 Sep 2022 09:55:56 +0800
+Subject: can: bcm: check the result of can_send() in bcm_can_tx()
+
+From: Ziyang Xuan <william.xuanziyang@huawei.com>
+
+[ Upstream commit 3fd7bfd28cfd68ae80a2fe92ea1615722cc2ee6e ]
+
+If can_send() fail, it should not update frames_abs counter
+in bcm_can_tx(). Add the result check for can_send() in bcm_can_tx().
+
+Suggested-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Suggested-by: Oliver Hartkopp <socketcan@hartkopp.net>
+Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com>
+Link: https://lore.kernel.org/all/9851878e74d6d37aee2f1ee76d68361a46f89458.1663206163.git.william.xuanziyang@huawei.com
+Acked-by: Oliver Hartkopp <socketcan@hartkopp.net>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/can/bcm.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/net/can/bcm.c b/net/can/bcm.c
+index e5ffd2bd62ab..aab3a18f4a90 100644
+--- a/net/can/bcm.c
++++ b/net/can/bcm.c
+@@ -274,6 +274,7 @@ static void bcm_can_tx(struct bcm_op *op)
+ struct sk_buff *skb;
+ struct net_device *dev;
+ struct canfd_frame *cf = op->frames + op->cfsiz * op->currframe;
++ int err;
+
+ /* no target device? => exit */
+ if (!op->ifindex)
+@@ -298,11 +299,11 @@ static void bcm_can_tx(struct bcm_op *op)
+ /* send with loopback */
+ skb->dev = dev;
+ can_skb_set_owner(skb, op->sk);
+- can_send(skb, 1);
++ err = can_send(skb, 1);
++ if (!err)
++ op->frames_abs++;
+
+- /* update statistics */
+ op->currframe++;
+- op->frames_abs++;
+
+ /* reached last frame? */
+ if (op->currframe >= op->nframes)
+--
+2.35.1
+
--- /dev/null
+From 944840c81463d967d2ee59a3322f596501b7ac33 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 Aug 2022 21:38:00 +0200
+Subject: can: rx-offload: can_rx_offload_init_queue(): fix typo
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+
+[ Upstream commit 766108d91246530d31b42765046f7ec2d1e42581 ]
+
+Fix typo "rounted" -> "rounded".
+
+Link: https://lore.kernel.org/all/20220811093617.1861938-2-mkl@pengutronix.de
+Fixes: d254586c3453 ("can: rx-offload: Add support for HW fifo based irq offloading")
+Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/can/dev/rx-offload.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/can/dev/rx-offload.c b/drivers/net/can/dev/rx-offload.c
+index 37b0cc65237b..90ef0429fda3 100644
+--- a/drivers/net/can/dev/rx-offload.c
++++ b/drivers/net/can/dev/rx-offload.c
+@@ -328,7 +328,7 @@ static int can_rx_offload_init_queue(struct net_device *dev,
+ {
+ offload->dev = dev;
+
+- /* Limit queue len to 4x the weight (rounted to next power of two) */
++ /* Limit queue len to 4x the weight (rounded to next power of two) */
+ offload->skb_queue_len_max = 2 << fls(weight);
+ offload->skb_queue_len_max *= 4;
+ skb_queue_head_init(&offload->skb_queue);
+--
+2.35.1
+
--- /dev/null
+From 628368732769b513e4a4ff23d24a95f7827f6666 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 16:57:36 -0400
+Subject: cgroup/cpuset: Enable update_tasks_cpumask() on top_cpuset
+
+From: Waiman Long <longman@redhat.com>
+
+[ Upstream commit ec5fbdfb99d18482619ac42605cb80fbb56068ee ]
+
+Previously, update_tasks_cpumask() is not supposed to be called with
+top cpuset. With cpuset partition that takes CPUs away from the top
+cpuset, adjusting the cpus_mask of the tasks in the top cpuset is
+necessary. Percpu kthreads, however, are ignored.
+
+Fixes: ee8dde0cd2ce ("cpuset: Add new v2 cpuset.sched.partition flag")
+Signed-off-by: Waiman Long <longman@redhat.com>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/cgroup/cpuset.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c
+index 3213d3c8ea0a..428820bf141d 100644
+--- a/kernel/cgroup/cpuset.c
++++ b/kernel/cgroup/cpuset.c
+@@ -33,6 +33,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+ #include <linux/kmod.h>
++#include <linux/kthread.h>
+ #include <linux/list.h>
+ #include <linux/mempolicy.h>
+ #include <linux/mm.h>
+@@ -1087,10 +1088,18 @@ static void update_tasks_cpumask(struct cpuset *cs)
+ {
+ struct css_task_iter it;
+ struct task_struct *task;
++ bool top_cs = cs == &top_cpuset;
+
+ css_task_iter_start(&cs->css, 0, &it);
+- while ((task = css_task_iter_next(&it)))
++ while ((task = css_task_iter_next(&it))) {
++ /*
++ * Percpu kthreads in top_cpuset are ignored
++ */
++ if (top_cs && (task->flags & PF_KTHREAD) &&
++ kthread_is_per_cpu(task))
++ continue;
+ set_cpus_allowed_ptr(task, cs->effective_cpus);
++ }
+ css_task_iter_end(&it);
+ }
+
+@@ -2052,12 +2061,7 @@ static int update_prstate(struct cpuset *cs, int new_prs)
+ update_flag(CS_CPU_EXCLUSIVE, cs, 0);
+ }
+
+- /*
+- * Update cpumask of parent's tasks except when it is the top
+- * cpuset as some system daemons cannot be mapped to other CPUs.
+- */
+- if (parent != &top_cpuset)
+- update_tasks_cpumask(parent);
++ update_tasks_cpumask(parent);
+
+ if (parent->child_ecpus_count)
+ update_sibling_cpumasks(parent, cs, &tmpmask);
+--
+2.35.1
+
--- /dev/null
+From 4dc00b9078bdb4e46894e8e84dd3f54b1b0f7173 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 18:52:35 +0200
+Subject: cgroup: Honor caller's cgroup NS when resolving path
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Michal Koutný <mkoutny@suse.com>
+
+[ Upstream commit 74e4b956eb1cac0e4c10c240339b1bbfbc9a4c48 ]
+
+cgroup_get_from_path() is not widely used function. Its callers presume
+the path is resolved under cgroup namespace. (There is one caller
+currently and resolving in init NS won't make harm (netfilter). However,
+future users may be subject to different effects when resolving
+globally.)
+Since, there's currently no use for the global resolution, modify the
+existing function to take cgroup NS into account.
+
+Fixes: a79a908fd2b0 ("cgroup: introduce cgroup namespaces")
+Signed-off-by: Michal Koutný <mkoutny@suse.com>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/cgroup/cgroup.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
+index 4b19f7fc4deb..a92990f070d1 100644
+--- a/kernel/cgroup/cgroup.c
++++ b/kernel/cgroup/cgroup.c
+@@ -6598,8 +6598,12 @@ struct cgroup *cgroup_get_from_path(const char *path)
+ {
+ struct kernfs_node *kn;
+ struct cgroup *cgrp = ERR_PTR(-ENOENT);
++ struct cgroup *root_cgrp;
+
+- kn = kernfs_walk_and_get(cgrp_dfl_root.cgrp.kn, path);
++ spin_lock_irq(&css_set_lock);
++ root_cgrp = current_cgns_cgroup_from_root(&cgrp_dfl_root);
++ kn = kernfs_walk_and_get(root_cgrp->kn, path);
++ spin_unlock_irq(&css_set_lock);
+ if (!kn)
+ goto out;
+
+--
+2.35.1
+
--- /dev/null
+From 05f8551778b6a9bb80094575b82ff7f17605392a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 5 Nov 2021 08:39:01 +0900
+Subject: cifs: Create a new shared file holding smb2 pdu definitions
+
+From: Ronnie Sahlberg <lsahlber@redhat.com>
+
+[ Upstream commit 0d35e382e4e96a4fd97a1438bc1b11a91d2d85a6 ]
+
+This file will contain all the definitions we need for SMB2 packets
+and will follow the naming convention of MS-SMB2.PDF as closely
+as possible to make it easier to cross-reference beween the definitions
+and the standard.
+
+The content of this file will mostly consist of migration of existing
+definitions in the cifs/smb2.pdu.h and ksmbd/smb2pdu.h files
+with some additional tweaks as the two files have diverged.
+
+This patch introduces the new smbfs_common/smb2pdu.h file
+and migrates the SMB2 header as well as TREE_CONNECT and TREE_DISCONNECT
+to the shared file.
+
+Signed-off-by: Ronnie Sahlberg <lsahlber@redhat.com>
+Reviewed-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Stable-dep-of: 09a1f9a168ae ("cifs: return correct error in ->calc_signature()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/cifs/cifsfs.c | 1 -
+ fs/cifs/cifsglob.h | 3 +-
+ fs/cifs/connect.c | 4 +-
+ fs/cifs/misc.c | 2 +-
+ fs/cifs/smb2maperror.c | 16 +-
+ fs/cifs/smb2misc.c | 43 +++--
+ fs/cifs/smb2ops.c | 65 +++----
+ fs/cifs/smb2pdu.c | 106 ++++++-----
+ fs/cifs/smb2pdu.h | 373 ++++----------------------------------
+ fs/cifs/smb2proto.h | 2 +-
+ fs/cifs/smb2transport.c | 36 ++--
+ fs/smbfs_common/smb2pdu.h | 318 ++++++++++++++++++++++++++++++++
+ 12 files changed, 493 insertions(+), 476 deletions(-)
+ create mode 100644 fs/smbfs_common/smb2pdu.h
+
+diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c
+index 8ec55bbd705d..482dc5e50852 100644
+--- a/fs/cifs/cifsfs.c
++++ b/fs/cifs/cifsfs.c
+@@ -38,7 +38,6 @@
+ #include <linux/key-type.h>
+ #include "cifs_spnego.h"
+ #include "fscache.h"
+-#include "smb2pdu.h"
+ #ifdef CONFIG_CIFS_DFS_UPCALL
+ #include "dfs_cache.h"
+ #endif
+diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
+index a97ed30843cf..24ea63590d8d 100644
+--- a/fs/cifs/cifsglob.h
++++ b/fs/cifs/cifsglob.h
+@@ -20,6 +20,7 @@
+ #include <crypto/internal/hash.h>
+ #include <linux/scatterlist.h>
+ #include <uapi/linux/cifs/cifs_mount.h>
++#include "../smbfs_common/smb2pdu.h"
+ #include "smb2pdu.h"
+
+ #define CIFS_MAGIC_NUMBER 0xFF534D42 /* the first four bytes of SMB PDUs */
+@@ -778,7 +779,7 @@ revert_current_mid(struct TCP_Server_Info *server, const unsigned int val)
+
+ static inline void
+ revert_current_mid_from_hdr(struct TCP_Server_Info *server,
+- const struct smb2_sync_hdr *shdr)
++ const struct smb2_hdr *shdr)
+ {
+ unsigned int num = le16_to_cpu(shdr->CreditCharge);
+
+diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
+index 278634a63895..05f32cd8435d 100644
+--- a/fs/cifs/connect.c
++++ b/fs/cifs/connect.c
+@@ -672,7 +672,7 @@ dequeue_mid(struct mid_q_entry *mid, bool malformed)
+ static unsigned int
+ smb2_get_credits_from_hdr(char *buffer, struct TCP_Server_Info *server)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buffer;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buffer;
+
+ /*
+ * SMB1 does not use credits.
+@@ -872,7 +872,7 @@ cifs_handle_standard(struct TCP_Server_Info *server, struct mid_q_entry *mid)
+ static void
+ smb2_add_credits_from_hdr(char *buffer, struct TCP_Server_Info *server)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buffer;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buffer;
+ int scredits, in_flight;
+
+ /*
+diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c
+index 699f676ded47..ff8684512171 100644
+--- a/fs/cifs/misc.c
++++ b/fs/cifs/misc.c
+@@ -153,7 +153,7 @@ cifs_buf_get(void)
+ * SMB2 header is bigger than CIFS one - no problems to clean some
+ * more bytes for CIFS.
+ */
+- size_t buf_size = sizeof(struct smb2_sync_hdr);
++ size_t buf_size = sizeof(struct smb2_hdr);
+
+ /*
+ * We could use negotiated size instead of max_msgsize -
+diff --git a/fs/cifs/smb2maperror.c b/fs/cifs/smb2maperror.c
+index 181514b8770d..194799ddd382 100644
+--- a/fs/cifs/smb2maperror.c
++++ b/fs/cifs/smb2maperror.c
+@@ -2439,14 +2439,16 @@ smb2_print_status(__le32 status)
+ int
+ map_smb2_to_linux_error(char *buf, bool log_err)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+ unsigned int i;
+ int rc = -EIO;
+ __le32 smb2err = shdr->Status;
+
+ if (smb2err == 0) {
+- trace_smb3_cmd_done(shdr->TreeId, shdr->SessionId,
+- le16_to_cpu(shdr->Command), le64_to_cpu(shdr->MessageId));
++ trace_smb3_cmd_done(le32_to_cpu(shdr->Id.SyncId.TreeId),
++ le64_to_cpu(shdr->SessionId),
++ le16_to_cpu(shdr->Command),
++ le64_to_cpu(shdr->MessageId));
+ return 0;
+ }
+
+@@ -2470,8 +2472,10 @@ map_smb2_to_linux_error(char *buf, bool log_err)
+ cifs_dbg(FYI, "Mapping SMB2 status code 0x%08x to POSIX err %d\n",
+ __le32_to_cpu(smb2err), rc);
+
+- trace_smb3_cmd_err(shdr->TreeId, shdr->SessionId,
+- le16_to_cpu(shdr->Command),
+- le64_to_cpu(shdr->MessageId), le32_to_cpu(smb2err), rc);
++ trace_smb3_cmd_err(le32_to_cpu(shdr->Id.SyncId.TreeId),
++ le64_to_cpu(shdr->SessionId),
++ le16_to_cpu(shdr->Command),
++ le64_to_cpu(shdr->MessageId),
++ le32_to_cpu(smb2err), rc);
+ return rc;
+ }
+diff --git a/fs/cifs/smb2misc.c b/fs/cifs/smb2misc.c
+index 29b5554f6263..ce7d6cc652b3 100644
+--- a/fs/cifs/smb2misc.c
++++ b/fs/cifs/smb2misc.c
+@@ -8,7 +8,6 @@
+ *
+ */
+ #include <linux/ctype.h>
+-#include "smb2pdu.h"
+ #include "cifsglob.h"
+ #include "cifsproto.h"
+ #include "smb2proto.h"
+@@ -19,7 +18,7 @@
+ #include "nterr.h"
+
+ static int
+-check_smb2_hdr(struct smb2_sync_hdr *shdr, __u64 mid)
++check_smb2_hdr(struct smb2_hdr *shdr, __u64 mid)
+ {
+ __u64 wire_mid = le64_to_cpu(shdr->MessageId);
+
+@@ -81,9 +80,9 @@ static const __le16 smb2_rsp_struct_sizes[NUMBER_OF_SMB2_COMMANDS] = {
+ /* SMB2_OPLOCK_BREAK */ cpu_to_le16(24)
+ };
+
+-#define SMB311_NEGPROT_BASE_SIZE (sizeof(struct smb2_sync_hdr) + sizeof(struct smb2_negotiate_rsp))
++#define SMB311_NEGPROT_BASE_SIZE (sizeof(struct smb2_hdr) + sizeof(struct smb2_negotiate_rsp))
+
+-static __u32 get_neg_ctxt_len(struct smb2_sync_hdr *hdr, __u32 len,
++static __u32 get_neg_ctxt_len(struct smb2_hdr *hdr, __u32 len,
+ __u32 non_ctxlen)
+ {
+ __u16 neg_count;
+@@ -135,13 +134,13 @@ static __u32 get_neg_ctxt_len(struct smb2_sync_hdr *hdr, __u32 len,
+ int
+ smb2_check_message(char *buf, unsigned int len, struct TCP_Server_Info *srvr)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
+- struct smb2_sync_pdu *pdu = (struct smb2_sync_pdu *)shdr;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
++ struct smb2_pdu *pdu = (struct smb2_pdu *)shdr;
+ __u64 mid;
+ __u32 clc_len; /* calculated length */
+ int command;
+- int pdu_size = sizeof(struct smb2_sync_pdu);
+- int hdr_size = sizeof(struct smb2_sync_hdr);
++ int pdu_size = sizeof(struct smb2_pdu);
++ int hdr_size = sizeof(struct smb2_hdr);
+
+ /*
+ * Add function to do table lookup of StructureSize by command
+@@ -155,7 +154,7 @@ smb2_check_message(char *buf, unsigned int len, struct TCP_Server_Info *srvr)
+ /* decrypt frame now that it is completely read in */
+ spin_lock(&cifs_tcp_ses_lock);
+ list_for_each_entry(ses, &srvr->smb_ses_list, smb_ses_list) {
+- if (ses->Suid == thdr->SessionId)
++ if (ses->Suid == le64_to_cpu(thdr->SessionId))
+ break;
+ }
+ spin_unlock(&cifs_tcp_ses_lock);
+@@ -296,7 +295,7 @@ static const bool has_smb2_data_area[NUMBER_OF_SMB2_COMMANDS] = {
+ * area and the offset to it (from the beginning of the smb are also returned.
+ */
+ char *
+-smb2_get_data_area_len(int *off, int *len, struct smb2_sync_hdr *shdr)
++smb2_get_data_area_len(int *off, int *len, struct smb2_hdr *shdr)
+ {
+ *off = 0;
+ *len = 0;
+@@ -401,8 +400,8 @@ smb2_get_data_area_len(int *off, int *len, struct smb2_sync_hdr *shdr)
+ unsigned int
+ smb2_calc_size(void *buf, struct TCP_Server_Info *srvr)
+ {
+- struct smb2_sync_pdu *pdu = (struct smb2_sync_pdu *)buf;
+- struct smb2_sync_hdr *shdr = &pdu->sync_hdr;
++ struct smb2_pdu *pdu = (struct smb2_pdu *)buf;
++ struct smb2_hdr *shdr = &pdu->hdr;
+ int offset; /* the offset from the beginning of SMB to data area */
+ int data_length; /* the length of the variable length data area */
+ /* Structure Size has already been checked to make sure it is 64 */
+@@ -669,7 +668,7 @@ smb2_is_valid_oplock_break(char *buffer, struct TCP_Server_Info *server)
+
+ cifs_dbg(FYI, "Checking for oplock break\n");
+
+- if (rsp->sync_hdr.Command != SMB2_OPLOCK_BREAK)
++ if (rsp->hdr.Command != SMB2_OPLOCK_BREAK)
+ return false;
+
+ if (rsp->StructureSize !=
+@@ -816,23 +815,23 @@ smb2_handle_cancelled_close(struct cifs_tcon *tcon, __u64 persistent_fid,
+ int
+ smb2_handle_cancelled_mid(struct mid_q_entry *mid, struct TCP_Server_Info *server)
+ {
+- struct smb2_sync_hdr *sync_hdr = mid->resp_buf;
++ struct smb2_hdr *hdr = mid->resp_buf;
+ struct smb2_create_rsp *rsp = mid->resp_buf;
+ struct cifs_tcon *tcon;
+ int rc;
+
+- if ((mid->optype & CIFS_CP_CREATE_CLOSE_OP) || sync_hdr->Command != SMB2_CREATE ||
+- sync_hdr->Status != STATUS_SUCCESS)
++ if ((mid->optype & CIFS_CP_CREATE_CLOSE_OP) || hdr->Command != SMB2_CREATE ||
++ hdr->Status != STATUS_SUCCESS)
+ return 0;
+
+- tcon = smb2_find_smb_tcon(server, sync_hdr->SessionId,
+- sync_hdr->TreeId);
++ tcon = smb2_find_smb_tcon(server, le64_to_cpu(hdr->SessionId),
++ le32_to_cpu(hdr->Id.SyncId.TreeId));
+ if (!tcon)
+ return -ENOENT;
+
+ rc = __smb2_handle_cancelled_cmd(tcon,
+- le16_to_cpu(sync_hdr->Command),
+- le64_to_cpu(sync_hdr->MessageId),
++ le16_to_cpu(hdr->Command),
++ le64_to_cpu(hdr->MessageId),
+ rsp->PersistentFileId,
+ rsp->VolatileFileId);
+ if (rc)
+@@ -856,10 +855,10 @@ smb311_update_preauth_hash(struct cifs_ses *ses, struct kvec *iov, int nvec)
+ {
+ int i, rc;
+ struct sdesc *d;
+- struct smb2_sync_hdr *hdr;
++ struct smb2_hdr *hdr;
+ struct TCP_Server_Info *server = cifs_ses_server(ses);
+
+- hdr = (struct smb2_sync_hdr *)iov[0].iov_base;
++ hdr = (struct smb2_hdr *)iov[0].iov_base;
+ /* neg prot are always taken */
+ if (hdr->Command == SMB2_NEGOTIATE)
+ goto ok;
+diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
+index 2d31860d56e9..b13d0ce3b876 100644
+--- a/fs/cifs/smb2ops.c
++++ b/fs/cifs/smb2ops.c
+@@ -325,7 +325,7 @@ static struct mid_q_entry *
+ __smb2_find_mid(struct TCP_Server_Info *server, char *buf, bool dequeue)
+ {
+ struct mid_q_entry *mid;
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+ __u64 wire_mid = le64_to_cpu(shdr->MessageId);
+
+ if (shdr->ProtocolId == SMB2_TRANSFORM_PROTO_NUM) {
+@@ -367,11 +367,11 @@ static void
+ smb2_dump_detail(void *buf, struct TCP_Server_Info *server)
+ {
+ #ifdef CONFIG_CIFS_DEBUG2
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+
+ cifs_server_dbg(VFS, "Cmd: %d Err: 0x%x Flags: 0x%x Mid: %llu Pid: %d\n",
+ shdr->Command, shdr->Status, shdr->Flags, shdr->MessageId,
+- shdr->ProcessId);
++ shdr->Id.SyncId.ProcessId);
+ cifs_server_dbg(VFS, "smb buf %p len %u\n", buf,
+ server->ops->calc_smb_size(buf, server));
+ #endif
+@@ -891,7 +891,7 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon,
+ oparms.fid->persistent_fid = o_rsp->PersistentFileId;
+ oparms.fid->volatile_fid = o_rsp->VolatileFileId;
+ #ifdef CONFIG_CIFS_DEBUG2
+- oparms.fid->mid = le64_to_cpu(o_rsp->sync_hdr.MessageId);
++ oparms.fid->mid = le64_to_cpu(o_rsp->hdr.MessageId);
+ #endif /* CIFS_DEBUG2 */
+
+ tcon->crfid.tcon = tcon;
+@@ -2413,7 +2413,7 @@ smb2_query_dir_first(const unsigned int xid, struct cifs_tcon *tcon,
+
+ /* If the open failed there is nothing to do */
+ op_rsp = (struct smb2_create_rsp *)rsp_iov[0].iov_base;
+- if (op_rsp == NULL || op_rsp->sync_hdr.Status != STATUS_SUCCESS) {
++ if (op_rsp == NULL || op_rsp->hdr.Status != STATUS_SUCCESS) {
+ cifs_dbg(FYI, "query_dir_first: open failed rc=%d\n", rc);
+ goto qdf_free;
+ }
+@@ -2432,7 +2432,7 @@ smb2_query_dir_first(const unsigned int xid, struct cifs_tcon *tcon,
+ atomic_inc(&tcon->num_remote_opens);
+
+ qd_rsp = (struct smb2_query_directory_rsp *)rsp_iov[1].iov_base;
+- if (qd_rsp->sync_hdr.Status == STATUS_NO_MORE_FILES) {
++ if (qd_rsp->hdr.Status == STATUS_NO_MORE_FILES) {
+ trace_smb3_query_dir_done(xid, fid->persistent_fid,
+ tcon->tid, tcon->ses->Suid, 0, 0);
+ srch_inf->endOfSearch = true;
+@@ -2484,7 +2484,7 @@ smb2_close_dir(const unsigned int xid, struct cifs_tcon *tcon,
+ static bool
+ smb2_is_status_pending(char *buf, struct TCP_Server_Info *server)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+ int scredits, in_flight;
+
+ if (shdr->Status != STATUS_PENDING)
+@@ -2511,13 +2511,14 @@ smb2_is_status_pending(char *buf, struct TCP_Server_Info *server)
+ static bool
+ smb2_is_session_expired(char *buf)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+
+ if (shdr->Status != STATUS_NETWORK_SESSION_EXPIRED &&
+ shdr->Status != STATUS_USER_SESSION_DELETED)
+ return false;
+
+- trace_smb3_ses_expired(shdr->TreeId, shdr->SessionId,
++ trace_smb3_ses_expired(le32_to_cpu(shdr->Id.SyncId.TreeId),
++ le64_to_cpu(shdr->SessionId),
+ le16_to_cpu(shdr->Command),
+ le64_to_cpu(shdr->MessageId));
+ cifs_dbg(FYI, "Session expired or deleted\n");
+@@ -2528,7 +2529,7 @@ smb2_is_session_expired(char *buf)
+ static bool
+ smb2_is_status_io_timeout(char *buf)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+
+ if (shdr->Status == STATUS_IO_TIMEOUT)
+ return true;
+@@ -2539,7 +2540,7 @@ smb2_is_status_io_timeout(char *buf)
+ static void
+ smb2_is_network_name_deleted(char *buf, struct TCP_Server_Info *server)
+ {
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+ struct list_head *tmp, *tmp1;
+ struct cifs_ses *ses;
+ struct cifs_tcon *tcon;
+@@ -2552,7 +2553,7 @@ smb2_is_network_name_deleted(char *buf, struct TCP_Server_Info *server)
+ ses = list_entry(tmp, struct cifs_ses, smb_ses_list);
+ list_for_each(tmp1, &ses->tcon_list) {
+ tcon = list_entry(tmp1, struct cifs_tcon, tcon_list);
+- if (tcon->tid == shdr->TreeId) {
++ if (tcon->tid == le32_to_cpu(shdr->Id.SyncId.TreeId)) {
+ tcon->need_reconnect = true;
+ spin_unlock(&cifs_tcp_ses_lock);
+ pr_warn_once("Server share %s deleted.\n",
+@@ -2580,9 +2581,9 @@ smb2_oplock_response(struct cifs_tcon *tcon, struct cifs_fid *fid,
+ void
+ smb2_set_related(struct smb_rqst *rqst)
+ {
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+
+- shdr = (struct smb2_sync_hdr *)(rqst->rq_iov[0].iov_base);
++ shdr = (struct smb2_hdr *)(rqst->rq_iov[0].iov_base);
+ if (shdr == NULL) {
+ cifs_dbg(FYI, "shdr NULL in smb2_set_related\n");
+ return;
+@@ -2595,13 +2596,13 @@ char smb2_padding[7] = {0, 0, 0, 0, 0, 0, 0};
+ void
+ smb2_set_next_command(struct cifs_tcon *tcon, struct smb_rqst *rqst)
+ {
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ struct cifs_ses *ses = tcon->ses;
+ struct TCP_Server_Info *server = ses->server;
+ unsigned long len = smb_rqst_len(server, rqst);
+ int i, num_padding;
+
+- shdr = (struct smb2_sync_hdr *)(rqst->rq_iov[0].iov_base);
++ shdr = (struct smb2_hdr *)(rqst->rq_iov[0].iov_base);
+ if (shdr == NULL) {
+ cifs_dbg(FYI, "shdr NULL in smb2_set_next_command\n");
+ return;
+@@ -3146,7 +3147,7 @@ smb2_query_symlink(const unsigned int xid, struct cifs_tcon *tcon,
+ resp_buftype, rsp_iov);
+
+ create_rsp = rsp_iov[0].iov_base;
+- if (create_rsp && create_rsp->sync_hdr.Status)
++ if (create_rsp && create_rsp->hdr.Status)
+ err_iov = rsp_iov[0];
+ ioctl_rsp = rsp_iov[1].iov_base;
+
+@@ -4393,8 +4394,8 @@ static void
+ fill_transform_hdr(struct smb2_transform_hdr *tr_hdr, unsigned int orig_len,
+ struct smb_rqst *old_rq, __le16 cipher_type)
+ {
+- struct smb2_sync_hdr *shdr =
+- (struct smb2_sync_hdr *)old_rq->rq_iov[0].iov_base;
++ struct smb2_hdr *shdr =
++ (struct smb2_hdr *)old_rq->rq_iov[0].iov_base;
+
+ memset(tr_hdr, 0, sizeof(struct smb2_transform_hdr));
+ tr_hdr->ProtocolId = SMB2_TRANSFORM_PROTO_NUM;
+@@ -4520,7 +4521,7 @@ crypt_message(struct TCP_Server_Info *server, int num_rqst,
+ struct crypto_aead *tfm;
+ unsigned int crypt_len = le32_to_cpu(tr_hdr->OriginalMessageSize);
+
+- rc = smb2_get_enc_key(server, tr_hdr->SessionId, enc, key);
++ rc = smb2_get_enc_key(server, le64_to_cpu(tr_hdr->SessionId), enc, key);
+ if (rc) {
+ cifs_server_dbg(VFS, "%s: Could not get %scryption key\n", __func__,
+ enc ? "en" : "de");
+@@ -4812,7 +4813,7 @@ handle_read_data(struct TCP_Server_Info *server, struct mid_q_entry *mid,
+ unsigned int cur_page_idx;
+ unsigned int pad_len;
+ struct cifs_readdata *rdata = mid->callback_data;
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)buf;
+ struct bio_vec *bvec = NULL;
+ struct iov_iter iter;
+ struct kvec iov;
+@@ -5141,7 +5142,7 @@ receive_encrypted_standard(struct TCP_Server_Info *server,
+ {
+ int ret, length;
+ char *buf = server->smallbuf;
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ unsigned int pdu_length = server->pdu_size;
+ unsigned int buf_size;
+ struct mid_q_entry *mid_entry;
+@@ -5171,7 +5172,7 @@ receive_encrypted_standard(struct TCP_Server_Info *server,
+
+ next_is_large = server->large_buf;
+ one_more:
+- shdr = (struct smb2_sync_hdr *)buf;
++ shdr = (struct smb2_hdr *)buf;
+ if (shdr->NextCommand) {
+ if (next_is_large)
+ next_buffer = (char *)cifs_buf_get();
+@@ -5237,7 +5238,7 @@ smb3_receive_transform(struct TCP_Server_Info *server,
+ unsigned int orig_len = le32_to_cpu(tr_hdr->OriginalMessageSize);
+
+ if (pdu_length < sizeof(struct smb2_transform_hdr) +
+- sizeof(struct smb2_sync_hdr)) {
++ sizeof(struct smb2_hdr)) {
+ cifs_server_dbg(VFS, "Transform message is too small (%u)\n",
+ pdu_length);
+ cifs_reconnect(server);
+@@ -5270,7 +5271,7 @@ smb3_handle_read_data(struct TCP_Server_Info *server, struct mid_q_entry *mid)
+ static int
+ smb2_next_header(char *buf)
+ {
+- struct smb2_sync_hdr *hdr = (struct smb2_sync_hdr *)buf;
++ struct smb2_hdr *hdr = (struct smb2_hdr *)buf;
+ struct smb2_transform_hdr *t_hdr = (struct smb2_transform_hdr *)buf;
+
+ if (hdr->ProtocolId == SMB2_TRANSFORM_PROTO_NUM)
+@@ -5814,7 +5815,7 @@ struct smb_version_values smb20_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5836,7 +5837,7 @@ struct smb_version_values smb21_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5857,7 +5858,7 @@ struct smb_version_values smb3any_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5878,7 +5879,7 @@ struct smb_version_values smbdefault_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5899,7 +5900,7 @@ struct smb_version_values smb30_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5920,7 +5921,7 @@ struct smb_version_values smb302_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+@@ -5941,7 +5942,7 @@ struct smb_version_values smb311_values = {
+ .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE_LOCK,
+ .shared_lock_type = SMB2_LOCKFLAG_SHARED_LOCK,
+ .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK,
+- .header_size = sizeof(struct smb2_sync_hdr),
++ .header_size = sizeof(struct smb2_hdr),
+ .header_preamble_size = 0,
+ .max_header_size = MAX_SMB2_HDR_SIZE,
+ .read_rsp_size = sizeof(struct smb2_read_rsp) - 1,
+diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
+index 8aa0372141f5..4790499c1a22 100644
+--- a/fs/cifs/smb2pdu.c
++++ b/fs/cifs/smb2pdu.c
+@@ -23,7 +23,6 @@
+ #include <linux/uuid.h>
+ #include <linux/pagemap.h>
+ #include <linux/xattr.h>
+-#include "smb2pdu.h"
+ #include "cifsglob.h"
+ #include "cifsacl.h"
+ #include "cifsproto.h"
+@@ -84,7 +83,7 @@ int smb3_encryption_required(const struct cifs_tcon *tcon)
+ }
+
+ static void
+-smb2_hdr_assemble(struct smb2_sync_hdr *shdr, __le16 smb2_cmd,
++smb2_hdr_assemble(struct smb2_hdr *shdr, __le16 smb2_cmd,
+ const struct cifs_tcon *tcon,
+ struct TCP_Server_Info *server)
+ {
+@@ -104,7 +103,7 @@ smb2_hdr_assemble(struct smb2_sync_hdr *shdr, __le16 smb2_cmd,
+ } else {
+ shdr->CreditRequest = cpu_to_le16(2);
+ }
+- shdr->ProcessId = cpu_to_le32((__u16)current->tgid);
++ shdr->Id.SyncId.ProcessId = cpu_to_le32((__u16)current->tgid);
+
+ if (!tcon)
+ goto out;
+@@ -115,10 +114,10 @@ smb2_hdr_assemble(struct smb2_sync_hdr *shdr, __le16 smb2_cmd,
+ shdr->CreditCharge = cpu_to_le16(1);
+ /* else CreditCharge MBZ */
+
+- shdr->TreeId = tcon->tid;
++ shdr->Id.SyncId.TreeId = cpu_to_le32(tcon->tid);
+ /* Uid is not converted */
+ if (tcon->ses)
+- shdr->SessionId = tcon->ses->Suid;
++ shdr->SessionId = cpu_to_le64(tcon->ses->Suid);
+
+ /*
+ * If we would set SMB2_FLAGS_DFS_OPERATIONS on open we also would have
+@@ -334,7 +333,7 @@ fill_small_buf(__le16 smb2_command, struct cifs_tcon *tcon,
+ void *buf,
+ unsigned int *total_len)
+ {
+- struct smb2_sync_pdu *spdu = (struct smb2_sync_pdu *)buf;
++ struct smb2_pdu *spdu = (struct smb2_pdu *)buf;
+ /* lookup word count ie StructureSize from table */
+ __u16 parmsize = smb2_req_struct_sizes[le16_to_cpu(smb2_command)];
+
+@@ -344,10 +343,10 @@ fill_small_buf(__le16 smb2_command, struct cifs_tcon *tcon,
+ */
+ memset(buf, 0, 256);
+
+- smb2_hdr_assemble(&spdu->sync_hdr, smb2_command, tcon, server);
++ smb2_hdr_assemble(&spdu->hdr, smb2_command, tcon, server);
+ spdu->StructureSize2 = cpu_to_le16(parmsize);
+
+- *total_len = parmsize + sizeof(struct smb2_sync_hdr);
++ *total_len = parmsize + sizeof(struct smb2_hdr);
+ }
+
+ /*
+@@ -370,7 +369,7 @@ static int __smb2_plain_req_init(__le16 smb2_command, struct cifs_tcon *tcon,
+ }
+
+ fill_small_buf(smb2_command, tcon, server,
+- (struct smb2_sync_hdr *)(*request_buf),
++ (struct smb2_hdr *)(*request_buf),
+ total_len);
+
+ if (tcon != NULL) {
+@@ -860,7 +859,7 @@ SMB2_negotiate(const unsigned int xid, struct cifs_ses *ses)
+ if (rc)
+ return rc;
+
+- req->sync_hdr.SessionId = 0;
++ req->hdr.SessionId = 0;
+
+ memset(server->preauth_sha_hash, 0, SMB2_PREAUTH_HASH_SIZE);
+ memset(ses->preauth_sha_hash, 0, SMB2_PREAUTH_HASH_SIZE);
+@@ -1023,7 +1022,7 @@ SMB2_negotiate(const unsigned int xid, struct cifs_ses *ses)
+ server->cipher_type = SMB2_ENCRYPTION_AES128_CCM;
+
+ security_blob = smb2_get_data_area_len(&blob_offset, &blob_length,
+- (struct smb2_sync_hdr *)rsp);
++ (struct smb2_hdr *)rsp);
+ /*
+ * See MS-SMB2 section 2.2.4: if no blob, client picks default which
+ * for us will be
+@@ -1255,13 +1254,13 @@ SMB2_sess_alloc_buffer(struct SMB2_sess_data *sess_data)
+ return rc;
+
+ if (sess_data->ses->binding) {
+- req->sync_hdr.SessionId = sess_data->ses->Suid;
+- req->sync_hdr.Flags |= SMB2_FLAGS_SIGNED;
++ req->hdr.SessionId = cpu_to_le64(sess_data->ses->Suid);
++ req->hdr.Flags |= SMB2_FLAGS_SIGNED;
+ req->PreviousSessionId = 0;
+ req->Flags = SMB2_SESSION_REQ_FLAG_BINDING;
+ } else {
+ /* First session, not a reauthenticate */
+- req->sync_hdr.SessionId = 0;
++ req->hdr.SessionId = 0;
+ /*
+ * if reconnect, we need to send previous sess id
+ * otherwise it is 0
+@@ -1271,7 +1270,7 @@ SMB2_sess_alloc_buffer(struct SMB2_sess_data *sess_data)
+ }
+
+ /* enough to enable echos and oplocks and one max size write */
+- req->sync_hdr.CreditRequest = cpu_to_le16(130);
++ req->hdr.CreditRequest = cpu_to_le16(130);
+
+ /* only one of SMB2 signing flags may be set in SMB2 request */
+ if (server->sign)
+@@ -1430,7 +1429,7 @@ SMB2_auth_kerberos(struct SMB2_sess_data *sess_data)
+ rsp = (struct smb2_sess_setup_rsp *)sess_data->iov[0].iov_base;
+ /* keep session id and flags if binding */
+ if (!ses->binding) {
+- ses->Suid = rsp->sync_hdr.SessionId;
++ ses->Suid = le64_to_cpu(rsp->hdr.SessionId);
+ ses->session_flags = le16_to_cpu(rsp->SessionFlags);
+ }
+
+@@ -1506,7 +1505,7 @@ SMB2_sess_auth_rawntlmssp_negotiate(struct SMB2_sess_data *sess_data)
+
+ /* If true, rc here is expected and not an error */
+ if (sess_data->buf0_type != CIFS_NO_BUFFER &&
+- rsp->sync_hdr.Status == STATUS_MORE_PROCESSING_REQUIRED)
++ rsp->hdr.Status == STATUS_MORE_PROCESSING_REQUIRED)
+ rc = 0;
+
+ if (rc)
+@@ -1528,7 +1527,7 @@ SMB2_sess_auth_rawntlmssp_negotiate(struct SMB2_sess_data *sess_data)
+
+ /* keep existing ses id and flags if binding */
+ if (!ses->binding) {
+- ses->Suid = rsp->sync_hdr.SessionId;
++ ses->Suid = le64_to_cpu(rsp->hdr.SessionId);
+ ses->session_flags = le16_to_cpu(rsp->SessionFlags);
+ }
+
+@@ -1563,7 +1562,7 @@ SMB2_sess_auth_rawntlmssp_authenticate(struct SMB2_sess_data *sess_data)
+ goto out;
+
+ req = (struct smb2_sess_setup_req *) sess_data->iov[0].iov_base;
+- req->sync_hdr.SessionId = ses->Suid;
++ req->hdr.SessionId = cpu_to_le64(ses->Suid);
+
+ rc = build_ntlmssp_auth_blob(&ntlmssp_blob, &blob_length, ses,
+ sess_data->nls_cp);
+@@ -1589,7 +1588,7 @@ SMB2_sess_auth_rawntlmssp_authenticate(struct SMB2_sess_data *sess_data)
+
+ /* keep existing ses id and flags if binding */
+ if (!ses->binding) {
+- ses->Suid = rsp->sync_hdr.SessionId;
++ ses->Suid = le64_to_cpu(rsp->hdr.SessionId);
+ ses->session_flags = le16_to_cpu(rsp->SessionFlags);
+ }
+
+@@ -1720,12 +1719,12 @@ SMB2_logoff(const unsigned int xid, struct cifs_ses *ses)
+ return rc;
+
+ /* since no tcon, smb2_init can not do this, so do here */
+- req->sync_hdr.SessionId = ses->Suid;
++ req->hdr.SessionId = cpu_to_le64(ses->Suid);
+
+ if (ses->session_flags & SMB2_SESSION_FLAG_ENCRYPT_DATA)
+ flags |= CIFS_TRANSFORM_REQ;
+ else if (server->sign)
+- req->sync_hdr.Flags |= SMB2_FLAGS_SIGNED;
++ req->hdr.Flags |= SMB2_FLAGS_SIGNED;
+
+ flags |= CIFS_NO_RSP_BUF;
+
+@@ -1833,14 +1832,14 @@ SMB2_tcon(const unsigned int xid, struct cifs_ses *ses, const char *tree,
+ !(ses->session_flags &
+ (SMB2_SESSION_FLAG_IS_GUEST|SMB2_SESSION_FLAG_IS_NULL)) &&
+ ((ses->user_name != NULL) || (ses->sectype == Kerberos)))
+- req->sync_hdr.Flags |= SMB2_FLAGS_SIGNED;
++ req->hdr.Flags |= SMB2_FLAGS_SIGNED;
+
+ memset(&rqst, 0, sizeof(struct smb_rqst));
+ rqst.rq_iov = iov;
+ rqst.rq_nvec = 2;
+
+ /* Need 64 for max size write so ask for more in case not there yet */
+- req->sync_hdr.CreditRequest = cpu_to_le16(64);
++ req->hdr.CreditRequest = cpu_to_le16(64);
+
+ rc = cifs_send_recv(xid, ses, server,
+ &rqst, &resp_buftype, flags, &rsp_iov);
+@@ -1876,7 +1875,7 @@ SMB2_tcon(const unsigned int xid, struct cifs_ses *ses, const char *tree,
+ tcon->maximal_access = le32_to_cpu(rsp->MaximalAccess);
+ tcon->tidStatus = CifsGood;
+ tcon->need_reconnect = false;
+- tcon->tid = rsp->sync_hdr.TreeId;
++ tcon->tid = le32_to_cpu(rsp->hdr.Id.SyncId.TreeId);
+ strlcpy(tcon->treeName, tree, sizeof(tcon->treeName));
+
+ if ((rsp->Capabilities & SMB2_SHARE_CAP_DFS) &&
+@@ -1897,9 +1896,8 @@ SMB2_tcon(const unsigned int xid, struct cifs_ses *ses, const char *tree,
+ return rc;
+
+ tcon_error_exit:
+- if (rsp && rsp->sync_hdr.Status == STATUS_BAD_NETWORK_NAME) {
++ if (rsp && rsp->hdr.Status == STATUS_BAD_NETWORK_NAME)
+ cifs_tcon_dbg(VFS, "BAD_NETWORK_NAME: %s\n", tree);
+- }
+ goto tcon_exit;
+ }
+
+@@ -2614,7 +2612,7 @@ int smb311_posix_mkdir(const unsigned int xid, struct inode *inode,
+ if (tcon->share_flags & SHI1005_FLAGS_DFS) {
+ int name_len;
+
+- req->sync_hdr.Flags |= SMB2_FLAGS_DFS_OPERATIONS;
++ req->hdr.Flags |= SMB2_FLAGS_DFS_OPERATIONS;
+ rc = alloc_path_with_tree_prefix(©_path, ©_size,
+ &name_len,
+ tcon->treeName, utf16_path);
+@@ -2746,7 +2744,7 @@ SMB2_open_init(struct cifs_tcon *tcon, struct TCP_Server_Info *server,
+ if (tcon->share_flags & SHI1005_FLAGS_DFS) {
+ int name_len;
+
+- req->sync_hdr.Flags |= SMB2_FLAGS_DFS_OPERATIONS;
++ req->hdr.Flags |= SMB2_FLAGS_DFS_OPERATIONS;
+ rc = alloc_path_with_tree_prefix(©_path, ©_size,
+ &name_len,
+ tcon->treeName, path);
+@@ -2958,7 +2956,7 @@ SMB2_open(const unsigned int xid, struct cifs_open_parms *oparms, __le16 *path,
+ oparms->fid->volatile_fid = rsp->VolatileFileId;
+ oparms->fid->access = oparms->desired_access;
+ #ifdef CONFIG_CIFS_DEBUG2
+- oparms->fid->mid = le64_to_cpu(rsp->sync_hdr.MessageId);
++ oparms->fid->mid = le64_to_cpu(rsp->hdr.MessageId);
+ #endif /* CIFS_DEBUG2 */
+
+ if (buf) {
+@@ -3058,7 +3056,7 @@ SMB2_ioctl_init(struct cifs_tcon *tcon, struct TCP_Server_Info *server,
+ * response size smaller.
+ */
+ req->MaxOutputResponse = cpu_to_le32(max_response_size);
+- req->sync_hdr.CreditCharge =
++ req->hdr.CreditCharge =
+ cpu_to_le16(DIV_ROUND_UP(max(indatalen, max_response_size),
+ SMB2_MAX_BUFFER_SIZE));
+ if (is_fsctl)
+@@ -3068,7 +3066,7 @@ SMB2_ioctl_init(struct cifs_tcon *tcon, struct TCP_Server_Info *server,
+
+ /* validate negotiate request must be signed - see MS-SMB2 3.2.5.5 */
+ if (opcode == FSCTL_VALIDATE_NEGOTIATE_INFO)
+- req->sync_hdr.Flags |= SMB2_FLAGS_SIGNED;
++ req->hdr.Flags |= SMB2_FLAGS_SIGNED;
+
+ return 0;
+ }
+@@ -3693,7 +3691,7 @@ smb2_echo_callback(struct mid_q_entry *mid)
+
+ if (mid->mid_state == MID_RESPONSE_RECEIVED
+ || mid->mid_state == MID_RESPONSE_MALFORMED) {
+- credits.value = le16_to_cpu(rsp->sync_hdr.CreditRequest);
++ credits.value = le16_to_cpu(rsp->hdr.CreditRequest);
+ credits.instance = server->reconnect_instance;
+ }
+
+@@ -3793,7 +3791,7 @@ SMB2_echo(struct TCP_Server_Info *server)
+ if (rc)
+ return rc;
+
+- req->sync_hdr.CreditRequest = cpu_to_le16(1);
++ req->hdr.CreditRequest = cpu_to_le16(1);
+
+ iov[0].iov_len = total_len;
+ iov[0].iov_base = (char *)req;
+@@ -3897,7 +3895,7 @@ smb2_new_read_req(void **buf, unsigned int *total_len,
+ {
+ int rc = -EACCES;
+ struct smb2_read_plain_req *req = NULL;
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ struct TCP_Server_Info *server = io_parms->server;
+
+ rc = smb2_plain_req_init(SMB2_READ, io_parms->tcon, server,
+@@ -3908,8 +3906,8 @@ smb2_new_read_req(void **buf, unsigned int *total_len,
+ if (server == NULL)
+ return -ECONNABORTED;
+
+- shdr = &req->sync_hdr;
+- shdr->ProcessId = cpu_to_le32(io_parms->pid);
++ shdr = &req->hdr;
++ shdr->Id.SyncId.ProcessId = cpu_to_le32(io_parms->pid);
+
+ req->PersistentFileId = io_parms->persistent_fid;
+ req->VolatileFileId = io_parms->volatile_fid;
+@@ -3970,8 +3968,8 @@ smb2_new_read_req(void **buf, unsigned int *total_len,
+ * Related requests use info from previous read request
+ * in chain.
+ */
+- shdr->SessionId = 0xFFFFFFFFFFFFFFFF;
+- shdr->TreeId = 0xFFFFFFFF;
++ shdr->SessionId = cpu_to_le64(0xFFFFFFFFFFFFFFFF);
++ shdr->Id.SyncId.TreeId = cpu_to_le32(0xFFFFFFFF);
+ req->PersistentFileId = 0xFFFFFFFFFFFFFFFF;
+ req->VolatileFileId = 0xFFFFFFFFFFFFFFFF;
+ }
+@@ -3991,8 +3989,8 @@ smb2_readv_callback(struct mid_q_entry *mid)
+ struct cifs_readdata *rdata = mid->callback_data;
+ struct cifs_tcon *tcon = tlink_tcon(rdata->cfile->tlink);
+ struct TCP_Server_Info *server = rdata->server;
+- struct smb2_sync_hdr *shdr =
+- (struct smb2_sync_hdr *)rdata->iov[0].iov_base;
++ struct smb2_hdr *shdr =
++ (struct smb2_hdr *)rdata->iov[0].iov_base;
+ struct cifs_credits credits = { .value = 0, .instance = 0 };
+ struct smb_rqst rqst = { .rq_iov = &rdata->iov[1],
+ .rq_nvec = 1,
+@@ -4078,7 +4076,7 @@ smb2_async_readv(struct cifs_readdata *rdata)
+ {
+ int rc, flags = 0;
+ char *buf;
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ struct cifs_io_parms io_parms;
+ struct smb_rqst rqst = { .rq_iov = rdata->iov,
+ .rq_nvec = 1 };
+@@ -4111,7 +4109,7 @@ smb2_async_readv(struct cifs_readdata *rdata)
+ rdata->iov[0].iov_base = buf;
+ rdata->iov[0].iov_len = total_len;
+
+- shdr = (struct smb2_sync_hdr *)buf;
++ shdr = (struct smb2_hdr *)buf;
+
+ if (rdata->credits.value > 0) {
+ shdr->CreditCharge = cpu_to_le16(DIV_ROUND_UP(rdata->bytes,
+@@ -4244,7 +4242,7 @@ smb2_writev_callback(struct mid_q_entry *mid)
+
+ switch (mid->mid_state) {
+ case MID_RESPONSE_RECEIVED:
+- credits.value = le16_to_cpu(rsp->sync_hdr.CreditRequest);
++ credits.value = le16_to_cpu(rsp->hdr.CreditRequest);
+ credits.instance = server->reconnect_instance;
+ wdata->result = smb2_check_receive(mid, server, 0);
+ if (wdata->result != 0)
+@@ -4270,7 +4268,7 @@ smb2_writev_callback(struct mid_q_entry *mid)
+ wdata->result = -EAGAIN;
+ break;
+ case MID_RESPONSE_MALFORMED:
+- credits.value = le16_to_cpu(rsp->sync_hdr.CreditRequest);
++ credits.value = le16_to_cpu(rsp->hdr.CreditRequest);
+ credits.instance = server->reconnect_instance;
+ fallthrough;
+ default:
+@@ -4317,7 +4315,7 @@ smb2_async_writev(struct cifs_writedata *wdata,
+ {
+ int rc = -EACCES, flags = 0;
+ struct smb2_write_req *req = NULL;
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ struct cifs_tcon *tcon = tlink_tcon(wdata->cfile->tlink);
+ struct TCP_Server_Info *server = wdata->server;
+ struct kvec iov[1];
+@@ -4335,8 +4333,8 @@ smb2_async_writev(struct cifs_writedata *wdata,
+ if (smb3_encryption_required(tcon))
+ flags |= CIFS_TRANSFORM_REQ;
+
+- shdr = (struct smb2_sync_hdr *)req;
+- shdr->ProcessId = cpu_to_le32(wdata->cfile->pid);
++ shdr = (struct smb2_hdr *)req;
++ shdr->Id.SyncId.ProcessId = cpu_to_le32(wdata->cfile->pid);
+
+ req->PersistentFileId = wdata->cfile->fid.persistent_fid;
+ req->VolatileFileId = wdata->cfile->fid.volatile_fid;
+@@ -4487,7 +4485,7 @@ SMB2_write(const unsigned int xid, struct cifs_io_parms *io_parms,
+ if (smb3_encryption_required(io_parms->tcon))
+ flags |= CIFS_TRANSFORM_REQ;
+
+- req->sync_hdr.ProcessId = cpu_to_le32(io_parms->pid);
++ req->hdr.Id.SyncId.ProcessId = cpu_to_le32(io_parms->pid);
+
+ req->PersistentFileId = io_parms->persistent_fid;
+ req->VolatileFileId = io_parms->volatile_fid;
+@@ -4872,7 +4870,7 @@ SMB2_query_directory(const unsigned int xid, struct cifs_tcon *tcon,
+
+ if (rc) {
+ if (rc == -ENODATA &&
+- rsp->sync_hdr.Status == STATUS_NO_MORE_FILES) {
++ rsp->hdr.Status == STATUS_NO_MORE_FILES) {
+ trace_smb3_query_dir_done(xid, persistent_fid,
+ tcon->tid, tcon->ses->Suid, index, 0);
+ srch_inf->endOfSearch = true;
+@@ -4920,7 +4918,7 @@ SMB2_set_info_init(struct cifs_tcon *tcon, struct TCP_Server_Info *server,
+ if (rc)
+ return rc;
+
+- req->sync_hdr.ProcessId = cpu_to_le32(pid);
++ req->hdr.Id.SyncId.ProcessId = cpu_to_le32(pid);
+ req->InfoType = info_type;
+ req->FileInfoClass = info_class;
+ req->PersistentFileId = persistent_fid;
+@@ -5080,7 +5078,7 @@ SMB2_oplock_break(const unsigned int xid, struct cifs_tcon *tcon,
+ req->VolatileFid = volatile_fid;
+ req->PersistentFid = persistent_fid;
+ req->OplockLevel = oplock_level;
+- req->sync_hdr.CreditRequest = cpu_to_le16(1);
++ req->hdr.CreditRequest = cpu_to_le16(1);
+
+ flags |= CIFS_NO_RSP_BUF;
+
+@@ -5382,7 +5380,7 @@ smb2_lockv(const unsigned int xid, struct cifs_tcon *tcon,
+ if (smb3_encryption_required(tcon))
+ flags |= CIFS_TRANSFORM_REQ;
+
+- req->sync_hdr.ProcessId = cpu_to_le32(pid);
++ req->hdr.Id.SyncId.ProcessId = cpu_to_le32(pid);
+ req->LockCount = cpu_to_le16(num_lock);
+
+ req->PersistentFileId = persist_fid;
+@@ -5458,7 +5456,7 @@ SMB2_lease_break(const unsigned int xid, struct cifs_tcon *tcon,
+ if (smb3_encryption_required(tcon))
+ flags |= CIFS_TRANSFORM_REQ;
+
+- req->sync_hdr.CreditRequest = cpu_to_le16(1);
++ req->hdr.CreditRequest = cpu_to_le16(1);
+ req->StructureSize = cpu_to_le16(36);
+ total_len += 12;
+
+diff --git a/fs/cifs/smb2pdu.h b/fs/cifs/smb2pdu.h
+index f32c99c9ba13..739e98d117ed 100644
+--- a/fs/cifs/smb2pdu.h
++++ b/fs/cifs/smb2pdu.h
+@@ -14,156 +14,12 @@
+ #include <net/sock.h>
+ #include "cifsacl.h"
+
+-/*
+- * Note that, due to trying to use names similar to the protocol specifications,
+- * there are many mixed case field names in the structures below. Although
+- * this does not match typical Linux kernel style, it is necessary to be
+- * able to match against the protocol specfication.
+- *
+- * SMB2 commands
+- * Some commands have minimal (wct=0,bcc=0), or uninteresting, responses
+- * (ie no useful data other than the SMB error code itself) and are marked such.
+- * Knowing this helps avoid response buffer allocations and copy in some cases.
+- */
+-
+-/* List of commands in host endian */
+-#define SMB2_NEGOTIATE_HE 0x0000
+-#define SMB2_SESSION_SETUP_HE 0x0001
+-#define SMB2_LOGOFF_HE 0x0002 /* trivial request/resp */
+-#define SMB2_TREE_CONNECT_HE 0x0003
+-#define SMB2_TREE_DISCONNECT_HE 0x0004 /* trivial req/resp */
+-#define SMB2_CREATE_HE 0x0005
+-#define SMB2_CLOSE_HE 0x0006
+-#define SMB2_FLUSH_HE 0x0007 /* trivial resp */
+-#define SMB2_READ_HE 0x0008
+-#define SMB2_WRITE_HE 0x0009
+-#define SMB2_LOCK_HE 0x000A
+-#define SMB2_IOCTL_HE 0x000B
+-#define SMB2_CANCEL_HE 0x000C
+-#define SMB2_ECHO_HE 0x000D
+-#define SMB2_QUERY_DIRECTORY_HE 0x000E
+-#define SMB2_CHANGE_NOTIFY_HE 0x000F
+-#define SMB2_QUERY_INFO_HE 0x0010
+-#define SMB2_SET_INFO_HE 0x0011
+-#define SMB2_OPLOCK_BREAK_HE 0x0012
+-
+-/* The same list in little endian */
+-#define SMB2_NEGOTIATE cpu_to_le16(SMB2_NEGOTIATE_HE)
+-#define SMB2_SESSION_SETUP cpu_to_le16(SMB2_SESSION_SETUP_HE)
+-#define SMB2_LOGOFF cpu_to_le16(SMB2_LOGOFF_HE)
+-#define SMB2_TREE_CONNECT cpu_to_le16(SMB2_TREE_CONNECT_HE)
+-#define SMB2_TREE_DISCONNECT cpu_to_le16(SMB2_TREE_DISCONNECT_HE)
+-#define SMB2_CREATE cpu_to_le16(SMB2_CREATE_HE)
+-#define SMB2_CLOSE cpu_to_le16(SMB2_CLOSE_HE)
+-#define SMB2_FLUSH cpu_to_le16(SMB2_FLUSH_HE)
+-#define SMB2_READ cpu_to_le16(SMB2_READ_HE)
+-#define SMB2_WRITE cpu_to_le16(SMB2_WRITE_HE)
+-#define SMB2_LOCK cpu_to_le16(SMB2_LOCK_HE)
+-#define SMB2_IOCTL cpu_to_le16(SMB2_IOCTL_HE)
+-#define SMB2_CANCEL cpu_to_le16(SMB2_CANCEL_HE)
+-#define SMB2_ECHO cpu_to_le16(SMB2_ECHO_HE)
+-#define SMB2_QUERY_DIRECTORY cpu_to_le16(SMB2_QUERY_DIRECTORY_HE)
+-#define SMB2_CHANGE_NOTIFY cpu_to_le16(SMB2_CHANGE_NOTIFY_HE)
+-#define SMB2_QUERY_INFO cpu_to_le16(SMB2_QUERY_INFO_HE)
+-#define SMB2_SET_INFO cpu_to_le16(SMB2_SET_INFO_HE)
+-#define SMB2_OPLOCK_BREAK cpu_to_le16(SMB2_OPLOCK_BREAK_HE)
+-
+-#define SMB2_INTERNAL_CMD cpu_to_le16(0xFFFF)
+-
+-#define NUMBER_OF_SMB2_COMMANDS 0x0013
+-
+ /* 52 transform hdr + 64 hdr + 88 create rsp */
+ #define SMB2_TRANSFORM_HEADER_SIZE 52
+ #define MAX_SMB2_HDR_SIZE 204
+
+-#define SMB2_PROTO_NUMBER cpu_to_le32(0x424d53fe)
+-#define SMB2_TRANSFORM_PROTO_NUM cpu_to_le32(0x424d53fd)
+-#define SMB2_COMPRESSION_TRANSFORM_ID cpu_to_le32(0x424d53fc)
+-
+-/*
+- * SMB2 Header Definition
+- *
+- * "MBZ" : Must be Zero
+- * "BB" : BugBug, Something to check/review/analyze later
+- * "PDU" : "Protocol Data Unit" (ie a network "frame")
+- *
+- */
+-
+-#define SMB2_HEADER_STRUCTURE_SIZE cpu_to_le16(64)
+-
+-struct smb2_sync_hdr {
+- __le32 ProtocolId; /* 0xFE 'S' 'M' 'B' */
+- __le16 StructureSize; /* 64 */
+- __le16 CreditCharge; /* MBZ */
+- __le32 Status; /* Error from server */
+- __le16 Command;
+- __le16 CreditRequest; /* CreditResponse */
+- __le32 Flags;
+- __le32 NextCommand;
+- __le64 MessageId;
+- __le32 ProcessId;
+- __u32 TreeId; /* opaque - so do not make little endian */
+- __u64 SessionId; /* opaque - so do not make little endian */
+- __u8 Signature[16];
+-} __packed;
+-
+ /* The total header size for SMB2 read and write */
+-#define SMB2_READWRITE_PDU_HEADER_SIZE (48 + sizeof(struct smb2_sync_hdr))
+-
+-struct smb2_sync_pdu {
+- struct smb2_sync_hdr sync_hdr;
+- __le16 StructureSize2; /* size of wct area (varies, request specific) */
+-} __packed;
+-
+-#define SMB3_AES_CCM_NONCE 11
+-#define SMB3_AES_GCM_NONCE 12
+-
+-/* Transform flags (for 3.0 dialect this flag indicates CCM */
+-#define TRANSFORM_FLAG_ENCRYPTED 0x0001
+-struct smb2_transform_hdr {
+- __le32 ProtocolId; /* 0xFD 'S' 'M' 'B' */
+- __u8 Signature[16];
+- __u8 Nonce[16];
+- __le32 OriginalMessageSize;
+- __u16 Reserved1;
+- __le16 Flags; /* EncryptionAlgorithm for 3.0, enc enabled for 3.1.1 */
+- __u64 SessionId;
+-} __packed;
+-
+-/* See MS-SMB2 2.2.42 */
+-struct smb2_compression_transform_hdr_unchained {
+- __le32 ProtocolId; /* 0xFC 'S' 'M' 'B' */
+- __le32 OriginalCompressedSegmentSize;
+- __le16 CompressionAlgorithm;
+- __le16 Flags;
+- __le16 Length; /* if chained it is length, else offset */
+-} __packed;
+-
+-/* See MS-SMB2 2.2.42.1 */
+-#define SMB2_COMPRESSION_FLAG_NONE 0x0000
+-#define SMB2_COMPRESSION_FLAG_CHAINED 0x0001
+-
+-struct compression_payload_header {
+- __le16 CompressionAlgorithm;
+- __le16 Flags;
+- __le32 Length; /* length of compressed playload including field below if present */
+- /* __le32 OriginalPayloadSize; */ /* optional, present when LZNT1, LZ77, LZ77+Huffman */
+-} __packed;
+-
+-/* See MS-SMB2 2.2.42.2 */
+-struct smb2_compression_transform_hdr_chained {
+- __le32 ProtocolId; /* 0xFC 'S' 'M' 'B' */
+- __le32 OriginalCompressedSegmentSize;
+- /* struct compression_payload_header[] */
+-} __packed;
+-
+-/* See MS-SMB2 2.2.42.2.2 */
+-struct compression_pattern_payload_v1 {
+- __le16 Pattern;
+- __le16 Reserved1;
+- __le16 Reserved2;
+- __le32 Repetitions;
+-} __packed;
++#define SMB2_READWRITE_PDU_HEADER_SIZE (48 + sizeof(struct smb2_hdr))
+
+ /* See MS-SMB2 2.2.43 */
+ struct smb2_rdma_transform {
+@@ -189,17 +45,6 @@ struct smb2_rdma_crypto_transform {
+ /* followed by padding */
+ } __packed;
+
+-/*
+- * SMB2 flag definitions
+- */
+-#define SMB2_FLAGS_SERVER_TO_REDIR cpu_to_le32(0x00000001)
+-#define SMB2_FLAGS_ASYNC_COMMAND cpu_to_le32(0x00000002)
+-#define SMB2_FLAGS_RELATED_OPERATIONS cpu_to_le32(0x00000004)
+-#define SMB2_FLAGS_SIGNED cpu_to_le32(0x00000008)
+-#define SMB2_FLAGS_PRIORITY_MASK cpu_to_le32(0x00000070) /* SMB3.1.1 */
+-#define SMB2_FLAGS_DFS_OPERATIONS cpu_to_le32(0x10000000)
+-#define SMB2_FLAGS_REPLAY_OPERATION cpu_to_le32(0x20000000) /* SMB3 & up */
+-
+ /*
+ * Definitions for SMB2 Protocol Data Units (network frames)
+ *
+@@ -214,7 +59,7 @@ struct smb2_rdma_crypto_transform {
+ #define SMB2_ERROR_STRUCTURE_SIZE2 cpu_to_le16(9)
+
+ struct smb2_err_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize;
+ __le16 Reserved; /* MBZ */
+ __le32 ByteCount; /* even if zero, at least one byte follows */
+@@ -273,7 +118,7 @@ struct share_redirect_error_context_rsp {
+ #define SMB2_CLIENT_GUID_SIZE 16
+
+ struct smb2_negotiate_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 36 */
+ __le16 DialectCount;
+ __le16 SecurityMode;
+@@ -472,7 +317,7 @@ struct smb2_posix_neg_context {
+ } __packed;
+
+ struct smb2_negotiate_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 65 */
+ __le16 SecurityMode;
+ __le16 DialectRevision;
+@@ -495,7 +340,7 @@ struct smb2_negotiate_rsp {
+ #define SMB2_SESSION_REQ_FLAG_ENCRYPT_DATA 0x04
+
+ struct smb2_sess_setup_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 25 */
+ __u8 Flags;
+ __u8 SecurityMode;
+@@ -512,7 +357,7 @@ struct smb2_sess_setup_req {
+ #define SMB2_SESSION_FLAG_IS_NULL 0x0002
+ #define SMB2_SESSION_FLAG_ENCRYPT_DATA 0x0004
+ struct smb2_sess_setup_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 9 */
+ __le16 SessionFlags;
+ __le16 SecurityBufferOffset;
+@@ -521,161 +366,13 @@ struct smb2_sess_setup_rsp {
+ } __packed;
+
+ struct smb2_logoff_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 4 */
+ __le16 Reserved;
+ } __packed;
+
+ struct smb2_logoff_rsp {
+- struct smb2_sync_hdr sync_hdr;
+- __le16 StructureSize; /* Must be 4 */
+- __le16 Reserved;
+-} __packed;
+-
+-/* Flags/Reserved for SMB3.1.1 */
+-#define SMB2_TREE_CONNECT_FLAG_CLUSTER_RECONNECT cpu_to_le16(0x0001)
+-#define SMB2_TREE_CONNECT_FLAG_REDIRECT_TO_OWNER cpu_to_le16(0x0002)
+-#define SMB2_TREE_CONNECT_FLAG_EXTENSION_PRESENT cpu_to_le16(0x0004)
+-
+-struct smb2_tree_connect_req {
+- struct smb2_sync_hdr sync_hdr;
+- __le16 StructureSize; /* Must be 9 */
+- __le16 Flags; /* Reserved MBZ for dialects prior to SMB3.1.1 */
+- __le16 PathOffset;
+- __le16 PathLength;
+- __u8 Buffer[1]; /* variable length */
+-} __packed;
+-
+-/* See MS-SMB2 section 2.2.9.2 */
+-/* Context Types */
+-#define SMB2_RESERVED_TREE_CONNECT_CONTEXT_ID 0x0000
+-#define SMB2_REMOTED_IDENTITY_TREE_CONNECT_CONTEXT_ID cpu_to_le16(0x0001)
+-
+-struct tree_connect_contexts {
+- __le16 ContextType;
+- __le16 DataLength;
+- __le32 Reserved;
+- __u8 Data[];
+-} __packed;
+-
+-/* Remoted identity tree connect context structures - see MS-SMB2 2.2.9.2.1 */
+-struct smb3_blob_data {
+- __le16 BlobSize;
+- __u8 BlobData[];
+-} __packed;
+-
+-/* Valid values for Attr */
+-#define SE_GROUP_MANDATORY 0x00000001
+-#define SE_GROUP_ENABLED_BY_DEFAULT 0x00000002
+-#define SE_GROUP_ENABLED 0x00000004
+-#define SE_GROUP_OWNER 0x00000008
+-#define SE_GROUP_USE_FOR_DENY_ONLY 0x00000010
+-#define SE_GROUP_INTEGRITY 0x00000020
+-#define SE_GROUP_INTEGRITY_ENABLED 0x00000040
+-#define SE_GROUP_RESOURCE 0x20000000
+-#define SE_GROUP_LOGON_ID 0xC0000000
+-
+-/* struct sid_attr_data is SidData array in BlobData format then le32 Attr */
+-
+-struct sid_array_data {
+- __le16 SidAttrCount;
+- /* SidAttrList - array of sid_attr_data structs */
+-} __packed;
+-
+-struct luid_attr_data {
+-
+-} __packed;
+-
+-/*
+- * struct privilege_data is the same as BLOB_DATA - see MS-SMB2 2.2.9.2.1.5
+- * but with size of LUID_ATTR_DATA struct and BlobData set to LUID_ATTR DATA
+- */
+-
+-struct privilege_array_data {
+- __le16 PrivilegeCount;
+- /* array of privilege_data structs */
+-} __packed;
+-
+-struct remoted_identity_tcon_context {
+- __le16 TicketType; /* must be 0x0001 */
+- __le16 TicketSize; /* total size of this struct */
+- __le16 User; /* offset to SID_ATTR_DATA struct with user info */
+- __le16 UserName; /* offset to null terminated Unicode username string */
+- __le16 Domain; /* offset to null terminated Unicode domain name */
+- __le16 Groups; /* offset to SID_ARRAY_DATA struct with group info */
+- __le16 RestrictedGroups; /* similar to above */
+- __le16 Privileges; /* offset to PRIVILEGE_ARRAY_DATA struct */
+- __le16 PrimaryGroup; /* offset to SID_ARRAY_DATA struct */
+- __le16 Owner; /* offset to BLOB_DATA struct */
+- __le16 DefaultDacl; /* offset to BLOB_DATA struct */
+- __le16 DeviceGroups; /* offset to SID_ARRAY_DATA struct */
+- __le16 UserClaims; /* offset to BLOB_DATA struct */
+- __le16 DeviceClaims; /* offset to BLOB_DATA struct */
+- __u8 TicketInfo[]; /* variable length buf - remoted identity data */
+-} __packed;
+-
+-struct smb2_tree_connect_req_extension {
+- __le32 TreeConnectContextOffset;
+- __le16 TreeConnectContextCount;
+- __u8 Reserved[10];
+- __u8 PathName[]; /* variable sized array */
+- /* followed by array of TreeConnectContexts */
+-} __packed;
+-
+-struct smb2_tree_connect_rsp {
+- struct smb2_sync_hdr sync_hdr;
+- __le16 StructureSize; /* Must be 16 */
+- __u8 ShareType; /* see below */
+- __u8 Reserved;
+- __le32 ShareFlags; /* see below */
+- __le32 Capabilities; /* see below */
+- __le32 MaximalAccess;
+-} __packed;
+-
+-/* Possible ShareType values */
+-#define SMB2_SHARE_TYPE_DISK 0x01
+-#define SMB2_SHARE_TYPE_PIPE 0x02
+-#define SMB2_SHARE_TYPE_PRINT 0x03
+-
+-/*
+- * Possible ShareFlags - exactly one and only one of the first 4 caching flags
+- * must be set (any of the remaining, SHI1005, flags may be set individually
+- * or in combination.
+- */
+-#define SMB2_SHAREFLAG_MANUAL_CACHING 0x00000000
+-#define SMB2_SHAREFLAG_AUTO_CACHING 0x00000010
+-#define SMB2_SHAREFLAG_VDO_CACHING 0x00000020
+-#define SMB2_SHAREFLAG_NO_CACHING 0x00000030
+-#define SHI1005_FLAGS_DFS 0x00000001
+-#define SHI1005_FLAGS_DFS_ROOT 0x00000002
+-#define SHI1005_FLAGS_RESTRICT_EXCLUSIVE_OPENS 0x00000100
+-#define SHI1005_FLAGS_FORCE_SHARED_DELETE 0x00000200
+-#define SHI1005_FLAGS_ALLOW_NAMESPACE_CACHING 0x00000400
+-#define SHI1005_FLAGS_ACCESS_BASED_DIRECTORY_ENUM 0x00000800
+-#define SHI1005_FLAGS_FORCE_LEVELII_OPLOCK 0x00001000
+-#define SHI1005_FLAGS_ENABLE_HASH_V1 0x00002000
+-#define SHI1005_FLAGS_ENABLE_HASH_V2 0x00004000
+-#define SHI1005_FLAGS_ENCRYPT_DATA 0x00008000
+-#define SMB2_SHAREFLAG_IDENTITY_REMOTING 0x00040000 /* 3.1.1 */
+-#define SMB2_SHAREFLAG_COMPRESS_DATA 0x00100000 /* 3.1.1 */
+-#define SHI1005_FLAGS_ALL 0x0014FF33
+-
+-/* Possible share capabilities */
+-#define SMB2_SHARE_CAP_DFS cpu_to_le32(0x00000008) /* all dialects */
+-#define SMB2_SHARE_CAP_CONTINUOUS_AVAILABILITY cpu_to_le32(0x00000010) /* 3.0 */
+-#define SMB2_SHARE_CAP_SCALEOUT cpu_to_le32(0x00000020) /* 3.0 */
+-#define SMB2_SHARE_CAP_CLUSTER cpu_to_le32(0x00000040) /* 3.0 */
+-#define SMB2_SHARE_CAP_ASYMMETRIC cpu_to_le32(0x00000080) /* 3.02 */
+-#define SMB2_SHARE_CAP_REDIRECT_TO_OWNER cpu_to_le32(0x00000100) /* 3.1.1 */
+-
+-struct smb2_tree_disconnect_req {
+- struct smb2_sync_hdr sync_hdr;
+- __le16 StructureSize; /* Must be 4 */
+- __le16 Reserved;
+-} __packed;
+-
+-struct smb2_tree_disconnect_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 4 */
+ __le16 Reserved;
+ } __packed;
+@@ -808,7 +505,7 @@ struct smb2_tree_disconnect_rsp {
+ #define SMB2_CREATE_IOV_SIZE 8
+
+ struct smb2_create_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 57 */
+ __u8 SecurityFlags;
+ __u8 RequestedOplockLevel;
+@@ -835,7 +532,7 @@ struct smb2_create_req {
+ #define MAX_SMB2_CREATE_RESPONSE_SIZE 880
+
+ struct smb2_create_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 89 */
+ __u8 OplockLevel;
+ __u8 Flag; /* 0x01 if reparse point */
+@@ -1210,7 +907,7 @@ struct duplicate_extents_to_file {
+ #define SMB2_IOCTL_IOV_SIZE 2
+
+ struct smb2_ioctl_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 57 */
+ __u16 Reserved;
+ __le32 CtlCode;
+@@ -1228,7 +925,7 @@ struct smb2_ioctl_req {
+ } __packed;
+
+ struct smb2_ioctl_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 57 */
+ __u16 Reserved;
+ __le32 CtlCode;
+@@ -1246,7 +943,7 @@ struct smb2_ioctl_rsp {
+ /* Currently defined values for close flags */
+ #define SMB2_CLOSE_FLAG_POSTQUERY_ATTRIB cpu_to_le16(0x0001)
+ struct smb2_close_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 24 */
+ __le16 Flags;
+ __le32 Reserved;
+@@ -1260,7 +957,7 @@ struct smb2_close_req {
+ #define MAX_SMB2_CLOSE_RESPONSE_SIZE 124
+
+ struct smb2_close_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* 60 */
+ __le16 Flags;
+ __le32 Reserved;
+@@ -1274,7 +971,7 @@ struct smb2_close_rsp {
+ } __packed;
+
+ struct smb2_flush_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 24 */
+ __le16 Reserved1;
+ __le32 Reserved2;
+@@ -1283,7 +980,7 @@ struct smb2_flush_req {
+ } __packed;
+
+ struct smb2_flush_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize;
+ __le16 Reserved;
+ } __packed;
+@@ -1300,7 +997,7 @@ struct smb2_flush_rsp {
+
+ /* SMB2 read request without RFC1001 length at the beginning */
+ struct smb2_read_plain_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 49 */
+ __u8 Padding; /* offset from start of SMB2 header to place read */
+ __u8 Flags; /* MBZ unless SMB3.02 or later */
+@@ -1321,7 +1018,7 @@ struct smb2_read_plain_req {
+ #define SMB2_READFLAG_RESPONSE_RDMA_TRANSFORM 0x00000001
+
+ struct smb2_read_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 17 */
+ __u8 DataOffset;
+ __u8 Reserved;
+@@ -1336,7 +1033,7 @@ struct smb2_read_rsp {
+ #define SMB2_WRITEFLAG_WRITE_UNBUFFERED 0x00000002 /* SMB3.02 or later */
+
+ struct smb2_write_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 49 */
+ __le16 DataOffset; /* offset from start of SMB2 header to write data */
+ __le32 Length;
+@@ -1352,7 +1049,7 @@ struct smb2_write_req {
+ } __packed;
+
+ struct smb2_write_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 17 */
+ __u8 DataOffset;
+ __u8 Reserved;
+@@ -1380,7 +1077,7 @@ struct smb2_write_rsp {
+ #define FILE_NOTIFY_CHANGE_STREAM_WRITE 0x00000800
+
+ struct smb2_change_notify_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize;
+ __le16 Flags;
+ __le32 OutputBufferLength;
+@@ -1391,7 +1088,7 @@ struct smb2_change_notify_req {
+ } __packed;
+
+ struct smb2_change_notify_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 9 */
+ __le16 OutputBufferOffset;
+ __le32 OutputBufferLength;
+@@ -1411,7 +1108,7 @@ struct smb2_lock_element {
+ } __packed;
+
+ struct smb2_lock_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 48 */
+ __le16 LockCount;
+ /*
+@@ -1426,19 +1123,19 @@ struct smb2_lock_req {
+ } __packed;
+
+ struct smb2_lock_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 4 */
+ __le16 Reserved;
+ } __packed;
+
+ struct smb2_echo_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 4 */
+ __u16 Reserved;
+ } __packed;
+
+ struct smb2_echo_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 4 */
+ __u16 Reserved;
+ } __packed;
+@@ -1468,7 +1165,7 @@ struct smb2_echo_rsp {
+ */
+
+ struct smb2_query_directory_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 33 */
+ __u8 FileInformationClass;
+ __u8 Flags;
+@@ -1482,7 +1179,7 @@ struct smb2_query_directory_req {
+ } __packed;
+
+ struct smb2_query_directory_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 9 */
+ __le16 OutputBufferOffset;
+ __le32 OutputBufferLength;
+@@ -1515,7 +1212,7 @@ struct smb2_query_directory_rsp {
+ #define SL_INDEX_SPECIFIED 0x00000004
+
+ struct smb2_query_info_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 41 */
+ __u8 InfoType;
+ __u8 FileInfoClass;
+@@ -1531,7 +1228,7 @@ struct smb2_query_info_req {
+ } __packed;
+
+ struct smb2_query_info_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 9 */
+ __le16 OutputBufferOffset;
+ __le32 OutputBufferLength;
+@@ -1548,7 +1245,7 @@ struct smb2_query_info_rsp {
+ #define SMB2_SET_INFO_IOV_SIZE 3
+
+ struct smb2_set_info_req {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 33 */
+ __u8 InfoType;
+ __u8 FileInfoClass;
+@@ -1562,12 +1259,12 @@ struct smb2_set_info_req {
+ } __packed;
+
+ struct smb2_set_info_rsp {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 2 */
+ } __packed;
+
+ struct smb2_oplock_break {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 24 */
+ __u8 OplockLevel;
+ __u8 Reserved;
+@@ -1579,7 +1276,7 @@ struct smb2_oplock_break {
+ #define SMB2_NOTIFY_BREAK_LEASE_FLAG_ACK_REQUIRED cpu_to_le32(0x01)
+
+ struct smb2_lease_break {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 44 */
+ __le16 Epoch;
+ __le32 Flags;
+@@ -1592,7 +1289,7 @@ struct smb2_lease_break {
+ } __packed;
+
+ struct smb2_lease_ack {
+- struct smb2_sync_hdr sync_hdr;
++ struct smb2_hdr hdr;
+ __le16 StructureSize; /* Must be 36 */
+ __le16 Reserved;
+ __le32 Flags;
+diff --git a/fs/cifs/smb2proto.h b/fs/cifs/smb2proto.h
+index 547945443fa7..096fada16ebd 100644
+--- a/fs/cifs/smb2proto.h
++++ b/fs/cifs/smb2proto.h
+@@ -25,7 +25,7 @@ extern int smb2_check_message(char *buf, unsigned int length,
+ struct TCP_Server_Info *server);
+ extern unsigned int smb2_calc_size(void *buf, struct TCP_Server_Info *server);
+ extern char *smb2_get_data_area_len(int *off, int *len,
+- struct smb2_sync_hdr *shdr);
++ struct smb2_hdr *shdr);
+ extern __le16 *cifs_convert_path_to_utf16(const char *from,
+ struct cifs_sb_info *cifs_sb);
+
+diff --git a/fs/cifs/smb2transport.c b/fs/cifs/smb2transport.c
+index f59b956f9d25..2bf047b390a9 100644
+--- a/fs/cifs/smb2transport.c
++++ b/fs/cifs/smb2transport.c
+@@ -19,7 +19,6 @@
+ #include <linux/mempool.h>
+ #include <linux/highmem.h>
+ #include <crypto/aead.h>
+-#include "smb2pdu.h"
+ #include "cifsglob.h"
+ #include "cifsproto.h"
+ #include "smb2proto.h"
+@@ -213,14 +212,14 @@ smb2_calc_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server,
+ unsigned char smb2_signature[SMB2_HMACSHA256_SIZE];
+ unsigned char *sigptr = smb2_signature;
+ struct kvec *iov = rqst->rq_iov;
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)iov[0].iov_base;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)iov[0].iov_base;
+ struct cifs_ses *ses;
+ struct shash_desc *shash;
+ struct crypto_shash *hash;
+ struct sdesc *sdesc = NULL;
+ struct smb_rqst drqst;
+
+- ses = smb2_find_smb_ses(server, shdr->SessionId);
++ ses = smb2_find_smb_ses(server, le64_to_cpu(shdr->SessionId));
+ if (!ses) {
+ cifs_server_dbg(VFS, "%s: Could not find session\n", __func__);
+ return 0;
+@@ -534,14 +533,14 @@ smb3_calc_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server,
+ unsigned char smb3_signature[SMB2_CMACAES_SIZE];
+ unsigned char *sigptr = smb3_signature;
+ struct kvec *iov = rqst->rq_iov;
+- struct smb2_sync_hdr *shdr = (struct smb2_sync_hdr *)iov[0].iov_base;
++ struct smb2_hdr *shdr = (struct smb2_hdr *)iov[0].iov_base;
+ struct shash_desc *shash;
+ struct crypto_shash *hash;
+ struct sdesc *sdesc = NULL;
+ struct smb_rqst drqst;
+ u8 key[SMB3_SIGN_KEY_SIZE];
+
+- rc = smb2_get_sign_key(shdr->SessionId, server, key);
++ rc = smb2_get_sign_key(le64_to_cpu(shdr->SessionId), server, key);
+ if (rc)
+ return 0;
+
+@@ -611,12 +610,12 @@ static int
+ smb2_sign_rqst(struct smb_rqst *rqst, struct TCP_Server_Info *server)
+ {
+ int rc = 0;
+- struct smb2_sync_hdr *shdr;
++ struct smb2_hdr *shdr;
+ struct smb2_sess_setup_req *ssr;
+ bool is_binding;
+ bool is_signed;
+
+- shdr = (struct smb2_sync_hdr *)rqst->rq_iov[0].iov_base;
++ shdr = (struct smb2_hdr *)rqst->rq_iov[0].iov_base;
+ ssr = (struct smb2_sess_setup_req *)shdr;
+
+ is_binding = shdr->Command == SMB2_SESSION_SETUP &&
+@@ -642,8 +641,8 @@ smb2_verify_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server)
+ {
+ unsigned int rc;
+ char server_response_sig[SMB2_SIGNATURE_SIZE];
+- struct smb2_sync_hdr *shdr =
+- (struct smb2_sync_hdr *)rqst->rq_iov[0].iov_base;
++ struct smb2_hdr *shdr =
++ (struct smb2_hdr *)rqst->rq_iov[0].iov_base;
+
+ if ((shdr->Command == SMB2_NEGOTIATE) ||
+ (shdr->Command == SMB2_SESSION_SETUP) ||
+@@ -689,7 +688,7 @@ smb2_verify_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server)
+ */
+ static inline void
+ smb2_seq_num_into_buf(struct TCP_Server_Info *server,
+- struct smb2_sync_hdr *shdr)
++ struct smb2_hdr *shdr)
+ {
+ unsigned int i, num = le16_to_cpu(shdr->CreditCharge);
+
+@@ -700,7 +699,7 @@ smb2_seq_num_into_buf(struct TCP_Server_Info *server,
+ }
+
+ static struct mid_q_entry *
+-smb2_mid_entry_alloc(const struct smb2_sync_hdr *shdr,
++smb2_mid_entry_alloc(const struct smb2_hdr *shdr,
+ struct TCP_Server_Info *server)
+ {
+ struct mid_q_entry *temp;
+@@ -732,14 +731,15 @@ smb2_mid_entry_alloc(const struct smb2_sync_hdr *shdr,
+
+ atomic_inc(&midCount);
+ temp->mid_state = MID_REQUEST_ALLOCATED;
+- trace_smb3_cmd_enter(shdr->TreeId, shdr->SessionId,
+- le16_to_cpu(shdr->Command), temp->mid);
++ trace_smb3_cmd_enter(le32_to_cpu(shdr->Id.SyncId.TreeId),
++ le64_to_cpu(shdr->SessionId),
++ le16_to_cpu(shdr->Command), temp->mid);
+ return temp;
+ }
+
+ static int
+ smb2_get_mid_entry(struct cifs_ses *ses, struct TCP_Server_Info *server,
+- struct smb2_sync_hdr *shdr, struct mid_q_entry **mid)
++ struct smb2_hdr *shdr, struct mid_q_entry **mid)
+ {
+ if (server->tcpStatus == CifsExiting)
+ return -ENOENT;
+@@ -807,8 +807,8 @@ smb2_setup_request(struct cifs_ses *ses, struct TCP_Server_Info *server,
+ struct smb_rqst *rqst)
+ {
+ int rc;
+- struct smb2_sync_hdr *shdr =
+- (struct smb2_sync_hdr *)rqst->rq_iov[0].iov_base;
++ struct smb2_hdr *shdr =
++ (struct smb2_hdr *)rqst->rq_iov[0].iov_base;
+ struct mid_q_entry *mid;
+
+ smb2_seq_num_into_buf(server, shdr);
+@@ -833,8 +833,8 @@ struct mid_q_entry *
+ smb2_setup_async_request(struct TCP_Server_Info *server, struct smb_rqst *rqst)
+ {
+ int rc;
+- struct smb2_sync_hdr *shdr =
+- (struct smb2_sync_hdr *)rqst->rq_iov[0].iov_base;
++ struct smb2_hdr *shdr =
++ (struct smb2_hdr *)rqst->rq_iov[0].iov_base;
+ struct mid_q_entry *mid;
+
+ if (server->tcpStatus == CifsNeedNegotiate &&
+diff --git a/fs/smbfs_common/smb2pdu.h b/fs/smbfs_common/smb2pdu.h
+new file mode 100644
+index 000000000000..f191ed64c1ee
+--- /dev/null
++++ b/fs/smbfs_common/smb2pdu.h
+@@ -0,0 +1,318 @@
++/* SPDX-License-Identifier: LGPL-2.1 */
++#ifndef _COMMON_SMB2PDU_H
++#define _COMMON_SMB2PDU_H
++
++/*
++ * Note that, due to trying to use names similar to the protocol specifications,
++ * there are many mixed case field names in the structures below. Although
++ * this does not match typical Linux kernel style, it is necessary to be
++ * able to match against the protocol specfication.
++ *
++ * SMB2 commands
++ * Some commands have minimal (wct=0,bcc=0), or uninteresting, responses
++ * (ie no useful data other than the SMB error code itself) and are marked such.
++ * Knowing this helps avoid response buffer allocations and copy in some cases.
++ */
++
++/* List of commands in host endian */
++#define SMB2_NEGOTIATE_HE 0x0000
++#define SMB2_SESSION_SETUP_HE 0x0001
++#define SMB2_LOGOFF_HE 0x0002 /* trivial request/resp */
++#define SMB2_TREE_CONNECT_HE 0x0003
++#define SMB2_TREE_DISCONNECT_HE 0x0004 /* trivial req/resp */
++#define SMB2_CREATE_HE 0x0005
++#define SMB2_CLOSE_HE 0x0006
++#define SMB2_FLUSH_HE 0x0007 /* trivial resp */
++#define SMB2_READ_HE 0x0008
++#define SMB2_WRITE_HE 0x0009
++#define SMB2_LOCK_HE 0x000A
++#define SMB2_IOCTL_HE 0x000B
++#define SMB2_CANCEL_HE 0x000C
++#define SMB2_ECHO_HE 0x000D
++#define SMB2_QUERY_DIRECTORY_HE 0x000E
++#define SMB2_CHANGE_NOTIFY_HE 0x000F
++#define SMB2_QUERY_INFO_HE 0x0010
++#define SMB2_SET_INFO_HE 0x0011
++#define SMB2_OPLOCK_BREAK_HE 0x0012
++
++/* The same list in little endian */
++#define SMB2_NEGOTIATE cpu_to_le16(SMB2_NEGOTIATE_HE)
++#define SMB2_SESSION_SETUP cpu_to_le16(SMB2_SESSION_SETUP_HE)
++#define SMB2_LOGOFF cpu_to_le16(SMB2_LOGOFF_HE)
++#define SMB2_TREE_CONNECT cpu_to_le16(SMB2_TREE_CONNECT_HE)
++#define SMB2_TREE_DISCONNECT cpu_to_le16(SMB2_TREE_DISCONNECT_HE)
++#define SMB2_CREATE cpu_to_le16(SMB2_CREATE_HE)
++#define SMB2_CLOSE cpu_to_le16(SMB2_CLOSE_HE)
++#define SMB2_FLUSH cpu_to_le16(SMB2_FLUSH_HE)
++#define SMB2_READ cpu_to_le16(SMB2_READ_HE)
++#define SMB2_WRITE cpu_to_le16(SMB2_WRITE_HE)
++#define SMB2_LOCK cpu_to_le16(SMB2_LOCK_HE)
++#define SMB2_IOCTL cpu_to_le16(SMB2_IOCTL_HE)
++#define SMB2_CANCEL cpu_to_le16(SMB2_CANCEL_HE)
++#define SMB2_ECHO cpu_to_le16(SMB2_ECHO_HE)
++#define SMB2_QUERY_DIRECTORY cpu_to_le16(SMB2_QUERY_DIRECTORY_HE)
++#define SMB2_CHANGE_NOTIFY cpu_to_le16(SMB2_CHANGE_NOTIFY_HE)
++#define SMB2_QUERY_INFO cpu_to_le16(SMB2_QUERY_INFO_HE)
++#define SMB2_SET_INFO cpu_to_le16(SMB2_SET_INFO_HE)
++#define SMB2_OPLOCK_BREAK cpu_to_le16(SMB2_OPLOCK_BREAK_HE)
++
++#define SMB2_INTERNAL_CMD cpu_to_le16(0xFFFF)
++
++#define NUMBER_OF_SMB2_COMMANDS 0x0013
++
++/*
++ * SMB2 Header Definition
++ *
++ * "MBZ" : Must be Zero
++ * "BB" : BugBug, Something to check/review/analyze later
++ * "PDU" : "Protocol Data Unit" (ie a network "frame")
++ *
++ */
++
++#define __SMB2_HEADER_STRUCTURE_SIZE 64
++#define SMB2_HEADER_STRUCTURE_SIZE \
++ cpu_to_le16(__SMB2_HEADER_STRUCTURE_SIZE)
++
++#define SMB2_PROTO_NUMBER cpu_to_le32(0x424d53fe)
++#define SMB2_TRANSFORM_PROTO_NUM cpu_to_le32(0x424d53fd)
++#define SMB2_COMPRESSION_TRANSFORM_ID cpu_to_le32(0x424d53fc)
++
++/*
++ * SMB2 flag definitions
++ */
++#define SMB2_FLAGS_SERVER_TO_REDIR cpu_to_le32(0x00000001)
++#define SMB2_FLAGS_ASYNC_COMMAND cpu_to_le32(0x00000002)
++#define SMB2_FLAGS_RELATED_OPERATIONS cpu_to_le32(0x00000004)
++#define SMB2_FLAGS_SIGNED cpu_to_le32(0x00000008)
++#define SMB2_FLAGS_PRIORITY_MASK cpu_to_le32(0x00000070) /* SMB3.1.1 */
++#define SMB2_FLAGS_DFS_OPERATIONS cpu_to_le32(0x10000000)
++#define SMB2_FLAGS_REPLAY_OPERATION cpu_to_le32(0x20000000) /* SMB3 & up */
++
++/* See MS-SMB2 section 2.2.1 */
++struct smb2_hdr {
++ __le32 ProtocolId; /* 0xFE 'S' 'M' 'B' */
++ __le16 StructureSize; /* 64 */
++ __le16 CreditCharge; /* MBZ */
++ __le32 Status; /* Error from server */
++ __le16 Command;
++ __le16 CreditRequest; /* CreditResponse */
++ __le32 Flags;
++ __le32 NextCommand;
++ __le64 MessageId;
++ union {
++ struct {
++ __le32 ProcessId;
++ __le32 TreeId;
++ } __packed SyncId;
++ __le64 AsyncId;
++ } __packed Id;
++ __le64 SessionId;
++ __u8 Signature[16];
++} __packed;
++
++struct smb2_pdu {
++ struct smb2_hdr hdr;
++ __le16 StructureSize2; /* size of wct area (varies, request specific) */
++} __packed;
++
++#define SMB3_AES_CCM_NONCE 11
++#define SMB3_AES_GCM_NONCE 12
++
++/* Transform flags (for 3.0 dialect this flag indicates CCM */
++#define TRANSFORM_FLAG_ENCRYPTED 0x0001
++struct smb2_transform_hdr {
++ __le32 ProtocolId; /* 0xFD 'S' 'M' 'B' */
++ __u8 Signature[16];
++ __u8 Nonce[16];
++ __le32 OriginalMessageSize;
++ __u16 Reserved1;
++ __le16 Flags; /* EncryptionAlgorithm for 3.0, enc enabled for 3.1.1 */
++ __le64 SessionId;
++} __packed;
++
++
++/* See MS-SMB2 2.2.42 */
++struct smb2_compression_transform_hdr_unchained {
++ __le32 ProtocolId; /* 0xFC 'S' 'M' 'B' */
++ __le32 OriginalCompressedSegmentSize;
++ __le16 CompressionAlgorithm;
++ __le16 Flags;
++ __le16 Length; /* if chained it is length, else offset */
++} __packed;
++
++/* See MS-SMB2 2.2.42.1 */
++#define SMB2_COMPRESSION_FLAG_NONE 0x0000
++#define SMB2_COMPRESSION_FLAG_CHAINED 0x0001
++
++struct compression_payload_header {
++ __le16 CompressionAlgorithm;
++ __le16 Flags;
++ __le32 Length; /* length of compressed playload including field below if present */
++ /* __le32 OriginalPayloadSize; */ /* optional, present when LZNT1, LZ77, LZ77+Huffman */
++} __packed;
++
++/* See MS-SMB2 2.2.42.2 */
++struct smb2_compression_transform_hdr_chained {
++ __le32 ProtocolId; /* 0xFC 'S' 'M' 'B' */
++ __le32 OriginalCompressedSegmentSize;
++ /* struct compression_payload_header[] */
++} __packed;
++
++/* See MS-SMB2 2.2.42.2.2 */
++struct compression_pattern_payload_v1 {
++ __le16 Pattern;
++ __le16 Reserved1;
++ __le16 Reserved2;
++ __le32 Repetitions;
++} __packed;
++
++/* See MS-SMB2 section 2.2.9.2 */
++/* Context Types */
++#define SMB2_RESERVED_TREE_CONNECT_CONTEXT_ID 0x0000
++#define SMB2_REMOTED_IDENTITY_TREE_CONNECT_CONTEXT_ID cpu_to_le16(0x0001)
++
++struct tree_connect_contexts {
++ __le16 ContextType;
++ __le16 DataLength;
++ __le32 Reserved;
++ __u8 Data[];
++} __packed;
++
++/* Remoted identity tree connect context structures - see MS-SMB2 2.2.9.2.1 */
++struct smb3_blob_data {
++ __le16 BlobSize;
++ __u8 BlobData[];
++} __packed;
++
++/* Valid values for Attr */
++#define SE_GROUP_MANDATORY 0x00000001
++#define SE_GROUP_ENABLED_BY_DEFAULT 0x00000002
++#define SE_GROUP_ENABLED 0x00000004
++#define SE_GROUP_OWNER 0x00000008
++#define SE_GROUP_USE_FOR_DENY_ONLY 0x00000010
++#define SE_GROUP_INTEGRITY 0x00000020
++#define SE_GROUP_INTEGRITY_ENABLED 0x00000040
++#define SE_GROUP_RESOURCE 0x20000000
++#define SE_GROUP_LOGON_ID 0xC0000000
++
++/* struct sid_attr_data is SidData array in BlobData format then le32 Attr */
++
++struct sid_array_data {
++ __le16 SidAttrCount;
++ /* SidAttrList - array of sid_attr_data structs */
++} __packed;
++
++struct luid_attr_data {
++
++} __packed;
++
++/*
++ * struct privilege_data is the same as BLOB_DATA - see MS-SMB2 2.2.9.2.1.5
++ * but with size of LUID_ATTR_DATA struct and BlobData set to LUID_ATTR DATA
++ */
++
++struct privilege_array_data {
++ __le16 PrivilegeCount;
++ /* array of privilege_data structs */
++} __packed;
++
++struct remoted_identity_tcon_context {
++ __le16 TicketType; /* must be 0x0001 */
++ __le16 TicketSize; /* total size of this struct */
++ __le16 User; /* offset to SID_ATTR_DATA struct with user info */
++ __le16 UserName; /* offset to null terminated Unicode username string */
++ __le16 Domain; /* offset to null terminated Unicode domain name */
++ __le16 Groups; /* offset to SID_ARRAY_DATA struct with group info */
++ __le16 RestrictedGroups; /* similar to above */
++ __le16 Privileges; /* offset to PRIVILEGE_ARRAY_DATA struct */
++ __le16 PrimaryGroup; /* offset to SID_ARRAY_DATA struct */
++ __le16 Owner; /* offset to BLOB_DATA struct */
++ __le16 DefaultDacl; /* offset to BLOB_DATA struct */
++ __le16 DeviceGroups; /* offset to SID_ARRAY_DATA struct */
++ __le16 UserClaims; /* offset to BLOB_DATA struct */
++ __le16 DeviceClaims; /* offset to BLOB_DATA struct */
++ __u8 TicketInfo[]; /* variable length buf - remoted identity data */
++} __packed;
++
++struct smb2_tree_connect_req_extension {
++ __le32 TreeConnectContextOffset;
++ __le16 TreeConnectContextCount;
++ __u8 Reserved[10];
++ __u8 PathName[]; /* variable sized array */
++ /* followed by array of TreeConnectContexts */
++} __packed;
++
++/* Flags/Reserved for SMB3.1.1 */
++#define SMB2_TREE_CONNECT_FLAG_CLUSTER_RECONNECT cpu_to_le16(0x0001)
++#define SMB2_TREE_CONNECT_FLAG_REDIRECT_TO_OWNER cpu_to_le16(0x0002)
++#define SMB2_TREE_CONNECT_FLAG_EXTENSION_PRESENT cpu_to_le16(0x0004)
++
++struct smb2_tree_connect_req {
++ struct smb2_hdr hdr;
++ __le16 StructureSize; /* Must be 9 */
++ __le16 Flags; /* Flags in SMB3.1.1 */
++ __le16 PathOffset;
++ __le16 PathLength;
++ __u8 Buffer[1]; /* variable length */
++} __packed;
++
++/* Possible ShareType values */
++#define SMB2_SHARE_TYPE_DISK 0x01
++#define SMB2_SHARE_TYPE_PIPE 0x02
++#define SMB2_SHARE_TYPE_PRINT 0x03
++
++/*
++ * Possible ShareFlags - exactly one and only one of the first 4 caching flags
++ * must be set (any of the remaining, SHI1005, flags may be set individually
++ * or in combination.
++ */
++#define SMB2_SHAREFLAG_MANUAL_CACHING 0x00000000
++#define SMB2_SHAREFLAG_AUTO_CACHING 0x00000010
++#define SMB2_SHAREFLAG_VDO_CACHING 0x00000020
++#define SMB2_SHAREFLAG_NO_CACHING 0x00000030
++#define SHI1005_FLAGS_DFS 0x00000001
++#define SHI1005_FLAGS_DFS_ROOT 0x00000002
++#define SHI1005_FLAGS_RESTRICT_EXCLUSIVE_OPENS 0x00000100
++#define SHI1005_FLAGS_FORCE_SHARED_DELETE 0x00000200
++#define SHI1005_FLAGS_ALLOW_NAMESPACE_CACHING 0x00000400
++#define SHI1005_FLAGS_ACCESS_BASED_DIRECTORY_ENUM 0x00000800
++#define SHI1005_FLAGS_FORCE_LEVELII_OPLOCK 0x00001000
++#define SHI1005_FLAGS_ENABLE_HASH_V1 0x00002000
++#define SHI1005_FLAGS_ENABLE_HASH_V2 0x00004000
++#define SHI1005_FLAGS_ENCRYPT_DATA 0x00008000
++#define SMB2_SHAREFLAG_IDENTITY_REMOTING 0x00040000 /* 3.1.1 */
++#define SMB2_SHAREFLAG_COMPRESS_DATA 0x00100000 /* 3.1.1 */
++#define SHI1005_FLAGS_ALL 0x0014FF33
++
++/* Possible share capabilities */
++#define SMB2_SHARE_CAP_DFS cpu_to_le32(0x00000008) /* all dialects */
++#define SMB2_SHARE_CAP_CONTINUOUS_AVAILABILITY cpu_to_le32(0x00000010) /* 3.0 */
++#define SMB2_SHARE_CAP_SCALEOUT cpu_to_le32(0x00000020) /* 3.0 */
++#define SMB2_SHARE_CAP_CLUSTER cpu_to_le32(0x00000040) /* 3.0 */
++#define SMB2_SHARE_CAP_ASYMMETRIC cpu_to_le32(0x00000080) /* 3.02 */
++#define SMB2_SHARE_CAP_REDIRECT_TO_OWNER cpu_to_le32(0x00000100) /* 3.1.1 */
++
++struct smb2_tree_connect_rsp {
++ struct smb2_hdr hdr;
++ __le16 StructureSize; /* Must be 16 */
++ __u8 ShareType; /* see below */
++ __u8 Reserved;
++ __le32 ShareFlags; /* see below */
++ __le32 Capabilities; /* see below */
++ __le32 MaximalAccess;
++} __packed;
++
++struct smb2_tree_disconnect_req {
++ struct smb2_hdr hdr;
++ __le16 StructureSize; /* Must be 4 */
++ __le16 Reserved;
++} __packed;
++
++struct smb2_tree_disconnect_rsp {
++ struct smb2_hdr hdr;
++ __le16 StructureSize; /* Must be 4 */
++ __le16 Reserved;
++} __packed;
++
++
++#endif /* _COMMON_SMB2PDU_H */
+--
+2.35.1
+
--- /dev/null
+From f5cb1d0d42ed22d528d84ad36b560bfa6ab5ef9c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 20:57:05 -0300
+Subject: cifs: return correct error in ->calc_signature()
+
+From: Enzo Matsumiya <ematsumiya@suse.de>
+
+[ Upstream commit 09a1f9a168ae1f69f701689429871793174417d2 ]
+
+If an error happens while getting the key or session in the
+->calc_signature implementations, 0 (success) is returned. Fix it by
+returning a proper error code.
+
+Since it seems to be highly unlikely to happen wrap the rc check in
+unlikely() too.
+
+Reviewed-by: Ronnie Sahlberg <lsahlber@redhat.com>
+Fixes: 32811d242ff6 ("cifs: Start using per session key for smb2/3 for signature generation")
+Signed-off-by: Enzo Matsumiya <ematsumiya@suse.de>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/cifs/smb2transport.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/fs/cifs/smb2transport.c b/fs/cifs/smb2transport.c
+index 2bf047b390a9..0f1c8dccbae8 100644
+--- a/fs/cifs/smb2transport.c
++++ b/fs/cifs/smb2transport.c
+@@ -220,9 +220,9 @@ smb2_calc_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server,
+ struct smb_rqst drqst;
+
+ ses = smb2_find_smb_ses(server, le64_to_cpu(shdr->SessionId));
+- if (!ses) {
++ if (unlikely(!ses)) {
+ cifs_server_dbg(VFS, "%s: Could not find session\n", __func__);
+- return 0;
++ return -ENOENT;
+ }
+
+ memset(smb2_signature, 0x0, SMB2_HMACSHA256_SIZE);
+@@ -541,8 +541,10 @@ smb3_calc_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server,
+ u8 key[SMB3_SIGN_KEY_SIZE];
+
+ rc = smb2_get_sign_key(le64_to_cpu(shdr->SessionId), server, key);
+- if (rc)
+- return 0;
++ if (unlikely(rc)) {
++ cifs_server_dbg(VFS, "%s: Could not get signing key\n", __func__);
++ return rc;
++ }
+
+ if (allocate_crypto) {
+ rc = cifs_alloc_hash("cmac(aes)", &hash, &sdesc);
+--
+2.35.1
+
--- /dev/null
+From 7f8234cfe60a574edbf9622921299e57802f49ce Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Apr 2022 13:34:26 +0930
+Subject: clk: ast2600: BCLK comes from EPLL
+
+From: Joel Stanley <joel@jms.id.au>
+
+[ Upstream commit b8c1dc9c00b252b3be853720a71b05ed451ddd9f ]
+
+This correction was made in the u-boot SDK recently. There are no
+in-tree users of this clock so the impact is minimal.
+
+Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
+Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.au
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-ast2600.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
+index 24dab2312bc6..9c3305bcb27a 100644
+--- a/drivers/clk/clk-ast2600.c
++++ b/drivers/clk/clk-ast2600.c
+@@ -622,7 +622,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
+ regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
+
+ /* P-Bus (BCLK) clock divider */
+- hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
++ hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+ ast2600_div_table,
+ &aspeed_g6_clk_lock);
+--
+2.35.1
+
--- /dev/null
+From b8ef93dd49d8bb43e87eef3c8c85b220512f9041 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 01:53:58 +0300
+Subject: clk: baikal-t1: Add SATA internal ref clock buffer
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit 081a9b7c74eae4e12b2cb1b86720f836a8f29247 ]
+
+It turns out the internal SATA reference clock signal will stay
+unavailable for the SATA interface consumer until the buffer on it's way
+is ungated. So aside with having the actual clock divider enabled we need
+to ungate a buffer placed on the signal way to the SATA controller (most
+likely some rudiment from the initial SoC release). Seeing the switch flag
+is placed in the same register as the SATA-ref clock divider at a
+non-standard ffset, let's implement it as a separate clock controller with
+the set-rate propagation to the parental clock divider wrapper. As such
+we'll be able to disable/enable and still change the original clock source
+rate.
+
+Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/baikal-t1/ccu-div.c | 64 +++++++++++++++++++++++++++++
+ drivers/clk/baikal-t1/ccu-div.h | 4 ++
+ drivers/clk/baikal-t1/clk-ccu-div.c | 18 +++++++-
+ 3 files changed, 85 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
+index bbfa3526ee10..a6642f3d33d4 100644
+--- a/drivers/clk/baikal-t1/ccu-div.c
++++ b/drivers/clk/baikal-t1/ccu-div.c
+@@ -34,6 +34,7 @@
+ #define CCU_DIV_CTL_CLKDIV_MASK(_width) \
+ GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
+ #define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
++#define CCU_DIV_CTL_GATE_REF_BUF BIT(28)
+ #define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
+
+ #define CCU_DIV_RST_DELAY_US 1
+@@ -170,6 +171,40 @@ static int ccu_div_gate_is_enabled(struct clk_hw *hw)
+ return !!(val & CCU_DIV_CTL_EN);
+ }
+
++static int ccu_div_buf_enable(struct clk_hw *hw)
++{
++ struct ccu_div *div = to_ccu_div(hw);
++ unsigned long flags;
++
++ spin_lock_irqsave(&div->lock, flags);
++ regmap_update_bits(div->sys_regs, div->reg_ctl,
++ CCU_DIV_CTL_GATE_REF_BUF, 0);
++ spin_unlock_irqrestore(&div->lock, flags);
++
++ return 0;
++}
++
++static void ccu_div_buf_disable(struct clk_hw *hw)
++{
++ struct ccu_div *div = to_ccu_div(hw);
++ unsigned long flags;
++
++ spin_lock_irqsave(&div->lock, flags);
++ regmap_update_bits(div->sys_regs, div->reg_ctl,
++ CCU_DIV_CTL_GATE_REF_BUF, CCU_DIV_CTL_GATE_REF_BUF);
++ spin_unlock_irqrestore(&div->lock, flags);
++}
++
++static int ccu_div_buf_is_enabled(struct clk_hw *hw)
++{
++ struct ccu_div *div = to_ccu_div(hw);
++ u32 val = 0;
++
++ regmap_read(div->sys_regs, div->reg_ctl, &val);
++
++ return !(val & CCU_DIV_CTL_GATE_REF_BUF);
++}
++
+ static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
+@@ -323,6 +358,7 @@ static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
+ CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
+ CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
+ CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
++ CCU_DIV_DBGFS_BIT_ATTR("div_buf", CCU_DIV_CTL_GATE_REF_BUF),
+ CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
+ };
+
+@@ -441,6 +477,9 @@ static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
+ continue;
+ }
+
++ if (!strcmp("div_buf", name))
++ continue;
++
+ bits[didx] = ccu_div_bits[bidx];
+ bits[didx].div = div;
+
+@@ -477,6 +516,21 @@ static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
+ &ccu_div_dbgfs_fixed_clkdiv_fops);
+ }
+
++static void ccu_div_buf_debug_init(struct clk_hw *hw, struct dentry *dentry)
++{
++ struct ccu_div *div = to_ccu_div(hw);
++ struct ccu_div_dbgfs_bit *bit;
++
++ bit = kmalloc(sizeof(*bit), GFP_KERNEL);
++ if (!bit)
++ return;
++
++ *bit = ccu_div_bits[3];
++ bit->div = div;
++ debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
++ &ccu_div_dbgfs_bit_fops);
++}
++
+ static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
+ {
+ struct ccu_div *div = to_ccu_div(hw);
+@@ -489,6 +543,7 @@ static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
+
+ #define ccu_div_var_debug_init NULL
+ #define ccu_div_gate_debug_init NULL
++#define ccu_div_buf_debug_init NULL
+ #define ccu_div_fixed_debug_init NULL
+
+ #endif /* !CONFIG_DEBUG_FS */
+@@ -520,6 +575,13 @@ static const struct clk_ops ccu_div_gate_ops = {
+ .debug_init = ccu_div_gate_debug_init
+ };
+
++static const struct clk_ops ccu_div_buf_ops = {
++ .enable = ccu_div_buf_enable,
++ .disable = ccu_div_buf_disable,
++ .is_enabled = ccu_div_buf_is_enabled,
++ .debug_init = ccu_div_buf_debug_init
++};
++
+ static const struct clk_ops ccu_div_fixed_ops = {
+ .recalc_rate = ccu_div_fixed_recalc_rate,
+ .round_rate = ccu_div_fixed_round_rate,
+@@ -566,6 +628,8 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
+ } else if (div_init->type == CCU_DIV_GATE) {
+ hw_init.ops = &ccu_div_gate_ops;
+ div->divider = div_init->divider;
++ } else if (div_init->type == CCU_DIV_BUF) {
++ hw_init.ops = &ccu_div_buf_ops;
+ } else if (div_init->type == CCU_DIV_FIXED) {
+ hw_init.ops = &ccu_div_fixed_ops;
+ div->divider = div_init->divider;
+diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
+index b6a9c8e45318..4eb49ff4803c 100644
+--- a/drivers/clk/baikal-t1/ccu-div.h
++++ b/drivers/clk/baikal-t1/ccu-div.h
+@@ -15,8 +15,10 @@
+
+ /*
+ * CCU Divider private clock IDs
++ * @CCU_SYS_SATA_CLK: CCU SATA internal clock
+ * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
+ */
++#define CCU_SYS_SATA_CLK -1
+ #define CCU_SYS_XGMAC_CLK -2
+
+ /*
+@@ -37,11 +39,13 @@
+ * enum ccu_div_type - CCU Divider types
+ * @CCU_DIV_VAR: Clocks gate with variable divider.
+ * @CCU_DIV_GATE: Clocks gate with fixed divider.
++ * @CCU_DIV_BUF: Clock gate with no divider.
+ * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
+ */
+ enum ccu_div_type {
+ CCU_DIV_VAR,
+ CCU_DIV_GATE,
++ CCU_DIV_BUF,
+ CCU_DIV_FIXED
+ };
+
+diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
+index 3953ae5664be..90f4fda406ee 100644
+--- a/drivers/clk/baikal-t1/clk-ccu-div.c
++++ b/drivers/clk/baikal-t1/clk-ccu-div.c
+@@ -76,6 +76,16 @@
+ .divider = _divider \
+ }
+
++#define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags) \
++ { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _pname, \
++ .base = _base, \
++ .type = CCU_DIV_BUF, \
++ .flags = _flags \
++ }
++
+ #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
+ { \
+ .id = _id, \
+@@ -188,11 +198,14 @@ static const struct ccu_div_rst_map axi_rst_map[] = {
+ * for the SoC devices registers IO-operations.
+ */
+ static const struct ccu_div_info sys_info[] = {
+- CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
++ CCU_DIV_VAR_INFO(CCU_SYS_SATA_CLK, "sys_sata_clk",
+ "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
+ CLK_SET_RATE_GATE,
+ CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
+ CCU_DIV_RESET_DOMAIN),
++ CCU_DIV_BUF_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
++ "sys_sata_clk", CCU_SYS_SATA_REF_BASE,
++ CLK_SET_RATE_PARENT),
+ CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
+ "pcie_clk", CCU_SYS_APB_BASE, 5,
+ CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
+@@ -398,6 +411,9 @@ static int ccu_div_clk_register(struct ccu_div_data *data)
+ init.base = info->base;
+ init.sys_regs = data->sys_regs;
+ init.divider = info->divider;
++ } else if (init.type == CCU_DIV_BUF) {
++ init.base = info->base;
++ init.sys_regs = data->sys_regs;
+ } else {
+ init.divider = info->divider;
+ }
+--
+2.35.1
+
--- /dev/null
+From 3a6c95175a25a0d2196eda3120ad515b82df8b4f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 01:53:57 +0300
+Subject: clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit e2eef312762e0b5a5a70d29fe59a245c0a3cffa0 ]
+
+Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
+PTP clocks are generated by two different wrappers with the same constant
+divider thus each producing a 156.25 MHz signal. But for some reason both
+of these clock sources are gated by a single switch-flag in the CCU
+registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
+handled independently we need to define a shared parental gate so the base
+clock signal would be switched off only if both of the child-clocks are
+disabled.
+
+Note the ID is intentionally set to -2 since we are going to add a one
+more internal clock identifier in the next commit.
+
+Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Link: https://lore.kernel.org/r/20220929225402.9696-4-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/baikal-t1/ccu-div.c | 1 +
+ drivers/clk/baikal-t1/ccu-div.h | 6 ++++++
+ drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++---
+ 3 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
+index 4062092d67f9..bbfa3526ee10 100644
+--- a/drivers/clk/baikal-t1/ccu-div.c
++++ b/drivers/clk/baikal-t1/ccu-div.c
+@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
+ goto err_free_div;
+ }
+ parent_data.fw_name = div_init->parent_name;
++ parent_data.name = div_init->parent_name;
+ hw_init.parent_data = &parent_data;
+ hw_init.num_parents = 1;
+
+diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
+index 795665caefbd..b6a9c8e45318 100644
+--- a/drivers/clk/baikal-t1/ccu-div.h
++++ b/drivers/clk/baikal-t1/ccu-div.h
+@@ -13,6 +13,12 @@
+ #include <linux/bits.h>
+ #include <linux/of.h>
+
++/*
++ * CCU Divider private clock IDs
++ * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
++ */
++#define CCU_SYS_XGMAC_CLK -2
++
+ /*
+ * CCU Divider private flags
+ * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
+diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
+index ea77eec40ddd..3953ae5664be 100644
+--- a/drivers/clk/baikal-t1/clk-ccu-div.c
++++ b/drivers/clk/baikal-t1/clk-ccu-div.c
+@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = {
+ "eth_clk", CCU_SYS_GMAC1_BASE, 5),
+ CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
+ "eth_clk", 10),
+- CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+- "eth_clk", CCU_SYS_XGMAC_BASE, 8),
++ CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",
++ "eth_clk", CCU_SYS_XGMAC_BASE, 1),
++ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
++ "sys_xgmac_clk", 8),
+ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
+- "eth_clk", 8),
++ "sys_xgmac_clk", 8),
+ CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
+ "eth_clk", CCU_SYS_USB_BASE, 10),
+ CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
+--
+2.35.1
+
--- /dev/null
+From 649f0bba1d1374541d21a0b25456b266674bf7bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 01:53:56 +0300
+Subject: clk: baikal-t1: Fix invalid xGMAC PTP clock divider
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit 3c742088686ce922704aec5b11d09bcc5a396589 ]
+
+Most likely due to copy-paste mistake the divider has been set to 10 while
+according to the SoC reference manual it's supposed to be 8 thus having
+PTP clock frequency of 156.25 MHz.
+
+Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Link: https://lore.kernel.org/r/20220929225402.9696-3-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/baikal-t1/clk-ccu-div.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
+index f141fda12b09..ea77eec40ddd 100644
+--- a/drivers/clk/baikal-t1/clk-ccu-div.c
++++ b/drivers/clk/baikal-t1/clk-ccu-div.c
+@@ -207,7 +207,7 @@ static const struct ccu_div_info sys_info[] = {
+ CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+ "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
+- "eth_clk", 10),
++ "eth_clk", 8),
+ CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
+ "eth_clk", CCU_SYS_USB_BASE, 10),
+ CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
+--
+2.35.1
+
--- /dev/null
+From 4fa78111c42196ac31d980c026f8eab3a1a80019 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 16:10:37 +0200
+Subject: clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration
+
+From: Stefan Wahren <stefan.wahren@i2se.com>
+
+[ Upstream commit 0b919a3728691c172312dee99ba654055ccd8c84 ]
+
+The return value of bcm2835_clock_rate_from_divisor is always unsigned
+and also all caller expect this. So fix the declaration accordingly.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+Link: https://lore.kernel.org/r/20220904141037.38816-1-stefan.wahren@i2se.com
+Reviewed-by: Ivan T. Ivanov <iivanov@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index 3667b4d731e7..2200305a722d 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -967,9 +967,9 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
+ return div;
+ }
+
+-static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
+- unsigned long parent_rate,
+- u32 div)
++static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
++ unsigned long parent_rate,
++ u32 div)
+ {
+ const struct bcm2835_clock_data *data = clock->data;
+ u64 temp;
+--
+2.35.1
+
--- /dev/null
+From 08f556567b3551ffc8c591cf31c7318f829f0cbc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 10:45:09 +0200
+Subject: clk: bcm2835: Make peripheral PLLC critical
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Maxime Ripard <maxime@cerno.tech>
+
+[ Upstream commit 6c5422851d8be8c7451e968fd2e6da41b6109e17 ]
+
+When testing for a series affecting the VEC, it was discovered that
+turning off and on the VEC clock is crashing the system.
+
+It turns out that, when disabling the VEC clock, it's the only child of
+the PLLC-per clock which will also get disabled. The source of the crash
+is PLLC-per being disabled.
+
+It's likely that some other device might not take a clock reference that
+it actually needs, but it's unclear which at this point. Let's make
+PLLC-per critical so that we don't have that crash.
+
+Reported-by: Noralf Trønnes <noralf@tronnes.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+Link: https://lore.kernel.org/r/20220926084509.12233-1-maxime@cerno.tech
+Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
+Acked-by: Noralf Trønnes <noralf@tronnes.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index 2200305a722d..f17b65d546e9 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1785,7 +1785,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
+ .load_mask = CM_PLLC_LOADPER,
+ .hold_mask = CM_PLLC_HOLDPER,
+ .fixed_divider = 1,
+- .flags = CLK_SET_RATE_PARENT),
++ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+
+ /*
+ * PLLD is the display PLL, used to drive DSI display panels.
+--
+2.35.1
+
--- /dev/null
+From 1c79fd2058db4c22b326f76e6a6cca876e06ab1d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 11:13:04 +0300
+Subject: clk: bcm2835: Round UART input clock up
+
+From: Ivan T. Ivanov <iivanov@suse.de>
+
+[ Upstream commit f690a4d7a8f66430662975511c86819dc9965bcc ]
+
+It was reported that RPi3[1] and RPi Zero 2W boards have issues with
+the Bluetooth. It turns out that when switching from initial to
+operation speed host and device no longer can talk each other because
+host uses incorrect UART baud rate.
+
+The UART driver used in this case is amba-pl011. Original fix, see
+below Github link[2], was inside pl011 module, but somehow it didn't
+look as the right place to fix. Beside that this original rounding
+function is not exactly perfect for all possible clock values. So I
+deiced to move the hack to the platform which actually need it.
+
+The UART clock is initialised to be as close to the requested
+frequency as possible without exceeding it. Now that there is a
+clock manager that returns the actual frequencies, an expected
+48MHz clock is reported as 47999625. If the requested baud rate
+== requested clock/16, there is no headroom and the slight
+reduction in actual clock rate results in failure.
+
+If increasing a clock by less than 0.1% changes it from ..999..
+to ..000.., round it up.
+
+[1] https://bugzilla.suse.com/show_bug.cgi?id=1188238
+[2] https://github.com/raspberrypi/linux/commit/ab3f1b39537f6d3825b8873006fbe2fc5ff057b7
+
+Cc: Phil Elwell <phil@raspberrypi.com>
+Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
+Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
+Link: https://lore.kernel.org/r/20220912081306.24662-1-iivanov@suse.de
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 35 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 33 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index f17b65d546e9..141ce19bc570 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -30,6 +30,7 @@
+ #include <linux/debugfs.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
++#include <linux/math.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+@@ -502,6 +503,8 @@ struct bcm2835_clock_data {
+ bool low_jitter;
+
+ u32 tcnt_mux;
++
++ bool round_up;
+ };
+
+ struct bcm2835_gate_data {
+@@ -994,12 +997,34 @@ static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock
+ return temp;
+ }
+
++static unsigned long bcm2835_round_rate(unsigned long rate)
++{
++ unsigned long scaler;
++ unsigned long limit;
++
++ limit = rate / 100000;
++
++ scaler = 1;
++ while (scaler < limit)
++ scaler *= 10;
++
++ /*
++ * If increasing a clock by less than 0.1% changes it
++ * from ..999.. to ..000.., round up.
++ */
++ if ((rate + scaler - 1) / scaler % 1000 == 0)
++ rate = roundup(rate, scaler);
++
++ return rate;
++}
++
+ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct bcm2835_cprman *cprman = clock->cprman;
+ const struct bcm2835_clock_data *data = clock->data;
++ unsigned long rate;
+ u32 div;
+
+ if (data->int_bits == 0 && data->frac_bits == 0)
+@@ -1007,7 +1032,12 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
+
+ div = cprman_read(cprman, data->div_reg);
+
+- return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
++ rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
++
++ if (data->round_up)
++ rate = bcm2835_round_rate(rate);
++
++ return rate;
+ }
+
+ static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
+@@ -2144,7 +2174,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
+ .div_reg = CM_UARTDIV,
+ .int_bits = 10,
+ .frac_bits = 12,
+- .tcnt_mux = 28),
++ .tcnt_mux = 28,
++ .round_up = true),
+
+ /* TV encoder clock. Only operating frequency is 108Mhz. */
+ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
+--
+2.35.1
+
--- /dev/null
+From 143ac992ccc2d68af149d198914841474a7ad6c3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 Jul 2022 16:49:00 +0800
+Subject: clk: berlin: Add of_node_put() for of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 37c381b812dcbfde9c3f1f3d3e75fdfc1b40d5bc ]
+
+In berlin2_clock_setup() and berlin2q_clock_setup(), we need to
+call of_node_put() for the reference returned by of_get_parent()
+which has increased the refcount. We should call *_put() in fail
+path or when it is not used anymore.
+
+Fixes: 26b3b6b959b2 ("clk: berlin: prepare simple-mfd conversion")
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220708084900.311684-1-windhl@126.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/berlin/bg2.c | 5 ++++-
+ drivers/clk/berlin/bg2q.c | 6 +++++-
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
+index bccdfa00fd37..67a9edbba29c 100644
+--- a/drivers/clk/berlin/bg2.c
++++ b/drivers/clk/berlin/bg2.c
+@@ -500,12 +500,15 @@ static void __init berlin2_clock_setup(struct device_node *np)
+ int n, ret;
+
+ clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
+- if (!clk_data)
++ if (!clk_data) {
++ of_node_put(parent_np);
+ return;
++ }
+ clk_data->num = MAX_CLKS;
+ hws = clk_data->hws;
+
+ gbase = of_iomap(parent_np, 0);
++ of_node_put(parent_np);
+ if (!gbase)
+ return;
+
+diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
+index e9518d35f262..dd2784bb75b6 100644
+--- a/drivers/clk/berlin/bg2q.c
++++ b/drivers/clk/berlin/bg2q.c
+@@ -286,19 +286,23 @@ static void __init berlin2q_clock_setup(struct device_node *np)
+ int n, ret;
+
+ clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
+- if (!clk_data)
++ if (!clk_data) {
++ of_node_put(parent_np);
+ return;
++ }
+ clk_data->num = MAX_CLKS;
+ hws = clk_data->hws;
+
+ gbase = of_iomap(parent_np, 0);
+ if (!gbase) {
++ of_node_put(parent_np);
+ pr_err("%pOF: Unable to map global base\n", np);
+ return;
+ }
+
+ /* BG2Q CPU PLL is not part of global registers */
+ cpupll_base = of_iomap(parent_np, 1);
++ of_node_put(parent_np);
+ if (!cpupll_base) {
+ pr_err("%pOF: Unable to map cpupll base\n", np);
+ iounmap(gbase);
+--
+2.35.1
+
--- /dev/null
+From 90f211f7712a91e96b004695da40fb739c2daf12 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 May 2022 09:57:35 +0200
+Subject: clk: generalize devm_clk_get() a bit
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+[ Upstream commit abae8e57e49aa75f6db76aa866c775721523908f ]
+
+Allow to add an exit hook to devm managed clocks. Also use
+clk_get_optional() in devm_clk_get_optional instead of open coding it.
+The generalisation will be used in the next commit to add some more
+devm_clk helpers.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Reviewed-by: Alexandru Ardelean <aardelean@deviqon.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Link: https://lore.kernel.org/r/20220520075737.758761-3-u.kleine-koenig@pengutronix.de
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-devres.c | 66 +++++++++++++++++++++++++++++-----------
+ 1 file changed, 49 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
+index f9d5b7334341..c822f4ef1584 100644
+--- a/drivers/clk/clk-devres.c
++++ b/drivers/clk/clk-devres.c
+@@ -4,39 +4,71 @@
+ #include <linux/export.h>
+ #include <linux/gfp.h>
+
++struct devm_clk_state {
++ struct clk *clk;
++ void (*exit)(struct clk *clk);
++};
++
+ static void devm_clk_release(struct device *dev, void *res)
+ {
+- clk_put(*(struct clk **)res);
++ struct devm_clk_state *state = *(struct devm_clk_state **)res;
++
++ if (state->exit)
++ state->exit(state->clk);
++
++ clk_put(state->clk);
+ }
+
+-struct clk *devm_clk_get(struct device *dev, const char *id)
++static struct clk *__devm_clk_get(struct device *dev, const char *id,
++ struct clk *(*get)(struct device *dev, const char *id),
++ int (*init)(struct clk *clk),
++ void (*exit)(struct clk *clk))
+ {
+- struct clk **ptr, *clk;
++ struct devm_clk_state *state;
++ struct clk *clk;
++ int ret;
+
+- ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
+- if (!ptr)
++ state = devres_alloc(devm_clk_release, sizeof(*state), GFP_KERNEL);
++ if (!state)
+ return ERR_PTR(-ENOMEM);
+
+- clk = clk_get(dev, id);
+- if (!IS_ERR(clk)) {
+- *ptr = clk;
+- devres_add(dev, ptr);
+- } else {
+- devres_free(ptr);
++ clk = get(dev, id);
++ if (IS_ERR(clk)) {
++ ret = PTR_ERR(clk);
++ goto err_clk_get;
+ }
+
++ if (init) {
++ ret = init(clk);
++ if (ret)
++ goto err_clk_init;
++ }
++
++ state->clk = clk;
++ state->exit = exit;
++
++ devres_add(dev, state);
++
+ return clk;
++
++err_clk_init:
++
++ clk_put(clk);
++err_clk_get:
++
++ devres_free(state);
++ return ERR_PTR(ret);
++}
++
++struct clk *devm_clk_get(struct device *dev, const char *id)
++{
++ return __devm_clk_get(dev, id, clk_get, NULL, NULL);
+ }
+ EXPORT_SYMBOL(devm_clk_get);
+
+ struct clk *devm_clk_get_optional(struct device *dev, const char *id)
+ {
+- struct clk *clk = devm_clk_get(dev, id);
+-
+- if (clk == ERR_PTR(-ENOENT))
+- return NULL;
+-
+- return clk;
++ return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL);
+ }
+ EXPORT_SYMBOL(devm_clk_get_optional);
+
+--
+2.35.1
+
--- /dev/null
+From 1346618e626cce39460bae55c305805db9728346 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 11:32:06 +0800
+Subject: clk: imx: scu: fix memleak on platform_device_add() fails
+
+From: Lin Yujun <linyujun809@huawei.com>
+
+[ Upstream commit 855ae87a2073ebf1b395e020de54fdf9ce7d166f ]
+
+No error handling is performed when platform_device_add()
+fails. Add error processing before return, and modified
+the return value.
+
+Fixes: 77d8f3068c63 ("clk: imx: scu: add two cells binding support")
+Signed-off-by: Lin Yujun <linyujun809@huawei.com>
+Link: https://lore.kernel.org/r/20220914033206.98046-1-linyujun809@huawei.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/imx/clk-scu.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
+index 083da31dc3ea..dc933fd5d5a0 100644
+--- a/drivers/clk/imx/clk-scu.c
++++ b/drivers/clk/imx/clk-scu.c
+@@ -690,7 +690,11 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
+ pr_warn("%s: failed to attached the power domain %d\n",
+ name, ret);
+
+- platform_device_add(pdev);
++ ret = platform_device_add(pdev);
++ if (ret) {
++ platform_device_put(pdev);
++ return ERR_PTR(ret);
++ }
+
+ /* For API backwards compatiblilty, simply return NULL for success */
+ return NULL;
+--
+2.35.1
+
--- /dev/null
+From 38b1a381eee20d9adcf3600b2e162a18800474d0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 12:11:20 +0200
+Subject: clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
+
+From: Chen-Yu Tsai <wenst@chromium.org>
+
+[ Upstream commit 9f94f545f258b15bfa6357eb62e1e307b712851e ]
+
+The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
+rate change requests to its parent, so that DVFS for the GPU can work
+properly.
+
+Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+index 37b4162c5882..3a33014eee7f 100644
+--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
++++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+@@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = {
+ .sta_ofs = 0x0,
+ };
+
+-#define GATE_MFG(_id, _name, _parent, _shift) \
+- GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
+- &mtk_clk_gate_ops_setclr)
++#define GATE_MFG(_id, _name, _parent, _shift) \
++ GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
++ &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
+
+ static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
+--
+2.35.1
+
--- /dev/null
+From 29e50b85feddefa64e8be3aed8f5994459348dac Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jun 2022 22:10:38 +0800
+Subject: clk: meson: Hold reference returned by of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 89ab396d712f7c91fe94f55cff23460426f5fc81 ]
+
+We should hold the reference returned by of_get_parent() and use it
+to call of_node_put() for refcount balance.
+
+Fixes: 88e2da81241e ("clk: meson: aoclk: refactor common code into dedicated file")
+Fixes: 6682bd4d443f ("clk: meson: factorise meson64 peripheral clock controller drivers")
+Fixes: bb6eddd1d28c ("clk: meson: meson8b: use the HHI syscon if available")
+
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220628141038.168383-1-windhl@126.com
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/meson/meson-aoclk.c | 5 ++++-
+ drivers/clk/meson/meson-eeclk.c | 5 ++++-
+ drivers/clk/meson/meson8b.c | 5 ++++-
+ 3 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
+index 27cd2c1f3f61..434cd8f9de82 100644
+--- a/drivers/clk/meson/meson-aoclk.c
++++ b/drivers/clk/meson/meson-aoclk.c
+@@ -38,6 +38,7 @@ int meson_aoclkc_probe(struct platform_device *pdev)
+ struct meson_aoclk_reset_controller *rstc;
+ struct meson_aoclk_data *data;
+ struct device *dev = &pdev->dev;
++ struct device_node *np;
+ struct regmap *regmap;
+ int ret, clkid;
+
+@@ -49,7 +50,9 @@ int meson_aoclkc_probe(struct platform_device *pdev)
+ if (!rstc)
+ return -ENOMEM;
+
+- regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
++ np = of_get_parent(dev->of_node);
++ regmap = syscon_node_to_regmap(np);
++ of_node_put(np);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "failed to get regmap\n");
+ return PTR_ERR(regmap);
+diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
+index 8d5a5dab955a..0e5e6b57eb20 100644
+--- a/drivers/clk/meson/meson-eeclk.c
++++ b/drivers/clk/meson/meson-eeclk.c
+@@ -18,6 +18,7 @@ int meson_eeclkc_probe(struct platform_device *pdev)
+ {
+ const struct meson_eeclkc_data *data;
+ struct device *dev = &pdev->dev;
++ struct device_node *np;
+ struct regmap *map;
+ int ret, i;
+
+@@ -26,7 +27,9 @@ int meson_eeclkc_probe(struct platform_device *pdev)
+ return -EINVAL;
+
+ /* Get the hhi system controller node */
+- map = syscon_node_to_regmap(of_get_parent(dev->of_node));
++ np = of_get_parent(dev->of_node);
++ map = syscon_node_to_regmap(np);
++ of_node_put(np);
+ if (IS_ERR(map)) {
+ dev_err(dev,
+ "failed to get HHI regmap\n");
+diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
+index a844d35b553a..809a0bfb670d 100644
+--- a/drivers/clk/meson/meson8b.c
++++ b/drivers/clk/meson/meson8b.c
+@@ -3717,12 +3717,15 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
+ struct clk_hw_onecell_data *clk_hw_onecell_data)
+ {
+ struct meson8b_clk_reset *rstc;
++ struct device_node *parent_np;
+ const char *notifier_clk_name;
+ struct clk *notifier_clk;
+ struct regmap *map;
+ int i, ret;
+
+- map = syscon_node_to_regmap(of_get_parent(np));
++ parent_np = of_get_parent(np);
++ map = syscon_node_to_regmap(parent_np);
++ of_node_put(parent_np);
+ if (IS_ERR(map)) {
+ pr_err("failed to get HHI regmap - Trying obsolete regs\n");
+ return;
+--
+2.35.1
+
--- /dev/null
+From 7c9c50913a10510c641904a2d843150b6344371c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jun 2022 22:31:55 +0800
+Subject: clk: oxnas: Hold reference returned by of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 1d6aa08c54cd0e005210ab8e3b1e92ede70f8a4f ]
+
+In oxnas_stdclk_probe(), we need to hold the reference returned by
+of_get_parent() and use it to call of_node_put() for refcount
+balance.
+
+Fixes: 0bbd72b4c64f ("clk: Add Oxford Semiconductor OXNAS Standard Clocks")
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220628143155.170550-1-windhl@126.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-oxnas.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
+index 78d5ea669fea..2fe36f579ac5 100644
+--- a/drivers/clk/clk-oxnas.c
++++ b/drivers/clk/clk-oxnas.c
+@@ -207,7 +207,7 @@ static const struct of_device_id oxnas_stdclk_dt_ids[] = {
+
+ static int oxnas_stdclk_probe(struct platform_device *pdev)
+ {
+- struct device_node *np = pdev->dev.of_node;
++ struct device_node *np = pdev->dev.of_node, *parent_np;
+ const struct oxnas_stdclk_data *data;
+ const struct of_device_id *id;
+ struct regmap *regmap;
+@@ -219,7 +219,9 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
+ return -ENODEV;
+ data = id->data;
+
+- regmap = syscon_node_to_regmap(of_get_parent(np));
++ parent_np = of_get_parent(np);
++ regmap = syscon_node_to_regmap(parent_np);
++ of_node_put(parent_np);
+ if (IS_ERR(regmap)) {
+ dev_err(&pdev->dev, "failed to have parent regmap\n");
+ return PTR_ERR(regmap);
+--
+2.35.1
+
--- /dev/null
+From 94b670190d8ed6d1a3fd9aad041f8ad631c92b0b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 May 2022 09:57:36 +0200
+Subject: clk: Provide new devm_clk helpers for prepared and enabled clocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+[ Upstream commit 7ef9651e9792b08eb310c6beb202cbc947f43cab ]
+
+When a driver keeps a clock prepared (or enabled) during the whole
+lifetime of the driver, these helpers allow to simplify the drivers.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Reviewed-by: Alexandru Ardelean <aardelean@deviqon.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Link: https://lore.kernel.org/r/20220520075737.758761-4-u.kleine-koenig@pengutronix.de
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-devres.c | 27 ++++++++++
+ include/linux/clk.h | 109 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 136 insertions(+)
+
+diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
+index c822f4ef1584..43ccd20e0298 100644
+--- a/drivers/clk/clk-devres.c
++++ b/drivers/clk/clk-devres.c
+@@ -66,12 +66,39 @@ struct clk *devm_clk_get(struct device *dev, const char *id)
+ }
+ EXPORT_SYMBOL(devm_clk_get);
+
++struct clk *devm_clk_get_prepared(struct device *dev, const char *id)
++{
++ return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare);
++}
++EXPORT_SYMBOL_GPL(devm_clk_get_prepared);
++
++struct clk *devm_clk_get_enabled(struct device *dev, const char *id)
++{
++ return __devm_clk_get(dev, id, clk_get,
++ clk_prepare_enable, clk_disable_unprepare);
++}
++EXPORT_SYMBOL_GPL(devm_clk_get_enabled);
++
+ struct clk *devm_clk_get_optional(struct device *dev, const char *id)
+ {
+ return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL);
+ }
+ EXPORT_SYMBOL(devm_clk_get_optional);
+
++struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id)
++{
++ return __devm_clk_get(dev, id, clk_get_optional,
++ clk_prepare, clk_unprepare);
++}
++EXPORT_SYMBOL_GPL(devm_clk_get_optional_prepared);
++
++struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id)
++{
++ return __devm_clk_get(dev, id, clk_get_optional,
++ clk_prepare_enable, clk_disable_unprepare);
++}
++EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled);
++
+ struct clk_bulk_devres {
+ struct clk_bulk_data *clks;
+ int num_clks;
+diff --git a/include/linux/clk.h b/include/linux/clk.h
+index 266e8de3cb51..e280e0acb55c 100644
+--- a/include/linux/clk.h
++++ b/include/linux/clk.h
+@@ -458,6 +458,47 @@ int __must_check devm_clk_bulk_get_all(struct device *dev,
+ */
+ struct clk *devm_clk_get(struct device *dev, const char *id);
+
++/**
++ * devm_clk_get_prepared - devm_clk_get() + clk_prepare()
++ * @dev: device for clock "consumer"
++ * @id: clock consumer ID
++ *
++ * Context: May sleep.
++ *
++ * Return: a struct clk corresponding to the clock producer, or
++ * valid IS_ERR() condition containing errno. The implementation
++ * uses @dev and @id to determine the clock consumer, and thereby
++ * the clock producer. (IOW, @id may be identical strings, but
++ * clk_get may return different clock producers depending on @dev.)
++ *
++ * The returned clk (if valid) is prepared. Drivers must however assume
++ * that the clock is not enabled.
++ *
++ * The clock will automatically be unprepared and freed when the device
++ * is unbound from the bus.
++ */
++struct clk *devm_clk_get_prepared(struct device *dev, const char *id);
++
++/**
++ * devm_clk_get_enabled - devm_clk_get() + clk_prepare_enable()
++ * @dev: device for clock "consumer"
++ * @id: clock consumer ID
++ *
++ * Context: May sleep.
++ *
++ * Return: a struct clk corresponding to the clock producer, or
++ * valid IS_ERR() condition containing errno. The implementation
++ * uses @dev and @id to determine the clock consumer, and thereby
++ * the clock producer. (IOW, @id may be identical strings, but
++ * clk_get may return different clock producers depending on @dev.)
++ *
++ * The returned clk (if valid) is prepared and enabled.
++ *
++ * The clock will automatically be disabled, unprepared and freed
++ * when the device is unbound from the bus.
++ */
++struct clk *devm_clk_get_enabled(struct device *dev, const char *id);
++
+ /**
+ * devm_clk_get_optional - lookup and obtain a managed reference to an optional
+ * clock producer.
+@@ -469,6 +510,50 @@ struct clk *devm_clk_get(struct device *dev, const char *id);
+ */
+ struct clk *devm_clk_get_optional(struct device *dev, const char *id);
+
++/**
++ * devm_clk_get_optional_prepared - devm_clk_get_optional() + clk_prepare()
++ * @dev: device for clock "consumer"
++ * @id: clock consumer ID
++ *
++ * Context: May sleep.
++ *
++ * Return: a struct clk corresponding to the clock producer, or
++ * valid IS_ERR() condition containing errno. The implementation
++ * uses @dev and @id to determine the clock consumer, and thereby
++ * the clock producer. If no such clk is found, it returns NULL
++ * which serves as a dummy clk. That's the only difference compared
++ * to devm_clk_get_prepared().
++ *
++ * The returned clk (if valid) is prepared. Drivers must however
++ * assume that the clock is not enabled.
++ *
++ * The clock will automatically be unprepared and freed when the
++ * device is unbound from the bus.
++ */
++struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id);
++
++/**
++ * devm_clk_get_optional_enabled - devm_clk_get_optional() +
++ * clk_prepare_enable()
++ * @dev: device for clock "consumer"
++ * @id: clock consumer ID
++ *
++ * Context: May sleep.
++ *
++ * Return: a struct clk corresponding to the clock producer, or
++ * valid IS_ERR() condition containing errno. The implementation
++ * uses @dev and @id to determine the clock consumer, and thereby
++ * the clock producer. If no such clk is found, it returns NULL
++ * which serves as a dummy clk. That's the only difference compared
++ * to devm_clk_get_enabled().
++ *
++ * The returned clk (if valid) is prepared and enabled.
++ *
++ * The clock will automatically be disabled, unprepared and freed
++ * when the device is unbound from the bus.
++ */
++struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id);
++
+ /**
+ * devm_get_clk_from_child - lookup and obtain a managed reference to a
+ * clock producer from child node.
+@@ -813,12 +898,36 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id)
+ return NULL;
+ }
+
++static inline struct clk *devm_clk_get_prepared(struct device *dev,
++ const char *id)
++{
++ return NULL;
++}
++
++static inline struct clk *devm_clk_get_enabled(struct device *dev,
++ const char *id)
++{
++ return NULL;
++}
++
+ static inline struct clk *devm_clk_get_optional(struct device *dev,
+ const char *id)
+ {
+ return NULL;
+ }
+
++static inline struct clk *devm_clk_get_optional_prepared(struct device *dev,
++ const char *id)
++{
++ return NULL;
++}
++
++static inline struct clk *devm_clk_get_optional_enabled(struct device *dev,
++ const char *id)
++{
++ return NULL;
++}
++
+ static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
+ struct clk_bulk_data *clks)
+ {
+--
+2.35.1
+
--- /dev/null
+From da12f6c12a5451f31557ef3890da206b345074b7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 00:06:21 +0200
+Subject: clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
+
+From: Robert Marko <robimarko@gmail.com>
+
+[ Upstream commit 43a56cbf2a38170b02db29654607575b1b4b5bc0 ]
+
+While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
+IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
+currently broken.
+
+More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
+clock.
+However after debugging why it was always stuck at 800Mhz, it was figured
+out that its not regmap_mux compatible at all.
+It is a simple mux but it uses RCG2 register layout and control bits, so
+utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
+having to provide a dummy frequency table.
+
+While we are here, use ARRAY_SIZE for number of parents.
+
+Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
+
+Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
+index d78ff2f310bf..be952d417ded 100644
+--- a/drivers/clk/qcom/apss-ipq6018.c
++++ b/drivers/clk/qcom/apss-ipq6018.c
+@@ -16,7 +16,7 @@
+ #include "clk-regmap.h"
+ #include "clk-branch.h"
+ #include "clk-alpha-pll.h"
+-#include "clk-regmap-mux.h"
++#include "clk-rcg.h"
+
+ enum {
+ P_XO,
+@@ -33,16 +33,15 @@ static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_APSS_PLL_EARLY, 5 },
+ };
+
+-static struct clk_regmap_mux apcs_alias0_clk_src = {
+- .reg = 0x0050,
+- .width = 3,
+- .shift = 7,
++static struct clk_rcg2 apcs_alias0_clk_src = {
++ .cmd_rcgr = 0x0050,
++ .hid_width = 5,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+- .num_parents = 2,
+- .ops = &clk_regmap_mux_closest_ops,
++ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
++ .ops = &clk_rcg2_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ };
+--
+2.35.1
+
--- /dev/null
+From c0c705081c3e51d17687bb538216d02b788c2865 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 00:06:22 +0200
+Subject: clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as critical
+
+From: Robert Marko <robimarko@gmail.com>
+
+[ Upstream commit 86e78995c93ee182433f965babfccd48417d4dcf ]
+
+While fixing up the driver I noticed that my IPQ8074 board was hanging
+after CPUFreq switched the frequency during boot, WDT would eventually
+reset it.
+
+So mark apcs_alias0_core_clk as critical since its the clock feeding the
+CPU cluster and must never be disabled.
+
+Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/apss-ipq6018.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
+index be952d417ded..f2f502e2d5a4 100644
+--- a/drivers/clk/qcom/apss-ipq6018.c
++++ b/drivers/clk/qcom/apss-ipq6018.c
+@@ -56,7 +56,7 @@ static struct clk_branch apcs_alias0_core_clk = {
+ .parent_hws = (const struct clk_hw *[]){
+ &apcs_alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT,
++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+--
+2.35.1
+
--- /dev/null
+From 17f9bdb3638b4bbdcff8366c2afcfb8a22cb2db4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 00:06:20 +0200
+Subject: clk: qcom: clk-rcg2: add rcg2 mux ops
+
+From: Christian Marangi <ansuelsmth@gmail.com>
+
+[ Upstream commit c5d2c96b3a7bd8987fad9957510034130037fccf ]
+
+An RCG may act as a mux that switch between 2 parents.
+This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
+the CPU cluster clock just switches between XO and the PLL that feeds it.
+
+Add the required ops to add support for this special configuration and use
+the generic mux function to determine the rate.
+
+This way we dont have to keep a essentially dummy frequency table to use
+RCG2 as a mux.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
+Stable-dep-of: 43a56cbf2a38 ("clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/clk-rcg.h | 1 +
+ drivers/clk/qcom/clk-rcg2.c | 7 +++++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
+index 99efcc7f8d88..248115a018bc 100644
+--- a/drivers/clk/qcom/clk-rcg.h
++++ b/drivers/clk/qcom/clk-rcg.h
+@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
+
+ extern const struct clk_ops clk_rcg2_ops;
+ extern const struct clk_ops clk_rcg2_floor_ops;
++extern const struct clk_ops clk_rcg2_mux_closest_ops;
+ extern const struct clk_ops clk_edp_pixel_ops;
+ extern const struct clk_ops clk_byte_ops;
+ extern const struct clk_ops clk_byte2_ops;
+diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
+index c3823cc32edc..fdbbda1f2ba4 100644
+--- a/drivers/clk/qcom/clk-rcg2.c
++++ b/drivers/clk/qcom/clk-rcg2.c
+@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops = {
+ };
+ EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
+
++const struct clk_ops clk_rcg2_mux_closest_ops = {
++ .determine_rate = __clk_mux_determine_rate_closest,
++ .get_parent = clk_rcg2_get_parent,
++ .set_parent = clk_rcg2_set_parent,
++};
++EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
++
+ struct frac_entry {
+ int num;
+ int den;
+--
+2.35.1
+
--- /dev/null
+From ca42e146223b8f5a5ff4538b467c232f58a358cc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 29 Aug 2021 22:48:19 +0200
+Subject: clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parents
+
+From: Marijn Suijten <marijn.suijten@somainline.org>
+
+[ Upstream commit 00ff818888fd436b687dbef457ea5a9135c60b15 ]
+
+Where possible, use ARRAY_SIZE to determine the number of parents in
+clk_parent_data instead of hardcoding a number that relies on an array
+defined hundreds of lines above.
+
+Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
+Link: https://lore.kernel.org/r/20210829204822.289829-2-marijn.suijten@somainline.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Stable-dep-of: 6956c18f4ad9 ("clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/gcc-sdm660.c | 80 +++++++++++++++++------------------
+ 1 file changed, 40 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
+index 4d36f96e9ae2..9b97425008ce 100644
+--- a/drivers/clk/qcom/gcc-sdm660.c
++++ b/drivers/clk/qcom/gcc-sdm660.c
+@@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -309,7 +309,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -323,7 +323,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -337,7 +337,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -379,7 +379,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -393,7 +393,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -454,7 +454,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -468,7 +468,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -482,7 +482,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -496,7 +496,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -510,7 +510,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -524,7 +524,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -538,7 +538,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -552,7 +552,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -566,7 +566,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -580,7 +580,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -601,7 +601,7 @@ static struct clk_rcg2 gp1_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
+- .num_parents = 4,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -615,7 +615,7 @@ static struct clk_rcg2 gp2_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
+- .num_parents = 4,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -629,7 +629,7 @@ static struct clk_rcg2 gp3_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
+- .num_parents = 4,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -649,7 +649,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -670,7 +670,7 @@ static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll4,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -689,7 +689,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -708,7 +708,7 @@ static struct clk_rcg2 pdm2_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -730,7 +730,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+- .num_parents = 6,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -756,7 +756,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
+- .num_parents = 4,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -778,7 +778,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -804,7 +804,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,
+- .num_parents = 4,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4),
+ .ops = &clk_rcg2_floor_ops,
+ },
+ };
+@@ -827,7 +827,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -848,7 +848,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -862,7 +862,7 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_xo_sleep_clk,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -883,7 +883,7 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -904,7 +904,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -924,7 +924,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -949,7 +949,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -970,7 +970,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
+- .num_parents = 3,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -990,7 +990,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_xo_sleep_clk,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+--
+2.35.1
+
--- /dev/null
+From c24001c4744ea9e1f02b9c24e8e0ab85281e3804 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 14 Jul 2022 22:38:22 +0200
+Subject: clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock
+
+From: Marijn Suijten <marijn.suijten@somainline.org>
+
+[ Upstream commit 6956c18f4ad9200aa945f7ea37d65a05afc49d51 ]
+
+In commit 3f905469c8ce ("clk: qcom: gcc: Use floor ops for SDCC clocks")
+floor ops were applied to SDCC2 only, but flooring is also required on
+the SDCC1 apps clock which is used by the eMMC card on Sony's Nile
+platform, and otherwise result in the typicial "Card appears
+overclocked" warnings observed on many other platforms before:
+
+ mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
+ mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
+ mmc0: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz
+
+Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
+Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
+Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
+Reviewed-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220714203822.186448-1-marijn.suijten@somainline.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/gcc-sdm660.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
+index 9b97425008ce..db918c92a522 100644
+--- a/drivers/clk/qcom/gcc-sdm660.c
++++ b/drivers/clk/qcom/gcc-sdm660.c
+@@ -757,7 +757,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .name = "sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
+- .ops = &clk_rcg2_ops,
++ .ops = &clk_rcg2_floor_ops,
+ },
+ };
+
+--
+2.35.1
+
--- /dev/null
+From b0085c6214c33d5384f2abd37da5097aac760807 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 10:56:18 +0300
+Subject: clk: qcom: gcc-sm6115: Override default Alpha PLL regs
+
+From: Adam Skladowski <a_skl39@protonmail.com>
+
+[ Upstream commit 068a0605ef5a6b430e7278c169bfcd25b680b28f ]
+
+The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but
+currently only BRAMMO ones are overridden. Override DEFAULT ones too.
+
+A very similar thing is happening in gcc-qcm2290 driver.
+
+Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
+Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
+Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/gcc-sm6115.c | 46 +++++++++++++++++++++++------------
+ 1 file changed, 30 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
+index 68fe9f6f0d2f..e24a977c2580 100644
+--- a/drivers/clk/qcom/gcc-sm6115.c
++++ b/drivers/clk/qcom/gcc-sm6115.c
+@@ -53,11 +53,25 @@ static struct pll_vco gpll10_vco[] = {
+ { 750000000, 1500000000, 1 },
+ };
+
++static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
++ [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
++ [PLL_OFF_L_VAL] = 0x04,
++ [PLL_OFF_ALPHA_VAL] = 0x08,
++ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
++ [PLL_OFF_TEST_CTL] = 0x10,
++ [PLL_OFF_TEST_CTL_U] = 0x14,
++ [PLL_OFF_USER_CTL] = 0x18,
++ [PLL_OFF_USER_CTL_U] = 0x1c,
++ [PLL_OFF_CONFIG_CTL] = 0x20,
++ [PLL_OFF_STATUS] = 0x24,
++ },
++};
++
+ static struct clk_alpha_pll gpll0 = {
+ .offset = 0x0,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(0),
+@@ -83,7 +97,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
+ .post_div_table = post_div_table_gpll0_out_aux2,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_aux2",
+ .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
+@@ -115,7 +129,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_main = {
+ .post_div_table = post_div_table_gpll0_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
+@@ -137,7 +151,7 @@ static struct clk_alpha_pll gpll10 = {
+ .offset = 0xa000,
+ .vco_table = gpll10_vco,
+ .num_vco = ARRAY_SIZE(gpll10_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(10),
+@@ -163,7 +177,7 @@ static struct clk_alpha_pll_postdiv gpll10_out_main = {
+ .post_div_table = post_div_table_gpll10_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll10_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
+@@ -189,7 +203,7 @@ static struct clk_alpha_pll gpll11 = {
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(11),
+@@ -215,7 +229,7 @@ static struct clk_alpha_pll_postdiv gpll11_out_main = {
+ .post_div_table = post_div_table_gpll11_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll11_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
+@@ -229,7 +243,7 @@ static struct clk_alpha_pll gpll3 = {
+ .offset = 0x3000,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(3),
+@@ -248,7 +262,7 @@ static struct clk_alpha_pll gpll4 = {
+ .offset = 0x4000,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(4),
+@@ -274,7 +288,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_main = {
+ .post_div_table = post_div_table_gpll4_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
+@@ -287,7 +301,7 @@ static struct clk_alpha_pll gpll6 = {
+ .offset = 0x6000,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(6),
+@@ -313,7 +327,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
+ .post_div_table = post_div_table_gpll6_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll6_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
+@@ -326,7 +340,7 @@ static struct clk_alpha_pll gpll7 = {
+ .offset = 0x7000,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x79000,
+ .enable_mask = BIT(7),
+@@ -352,7 +366,7 @@ static struct clk_alpha_pll_postdiv gpll7_out_main = {
+ .post_div_table = post_div_table_gpll7_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll7_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
+@@ -380,7 +394,7 @@ static struct clk_alpha_pll gpll8 = {
+ .offset = 0x8000,
+ .vco_table = default_vco,
+ .num_vco = ARRAY_SIZE(default_vco),
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x79000,
+@@ -407,7 +421,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
+ .post_div_table = post_div_table_gpll8_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
+ .width = 4,
+- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
++ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll8_out_main",
+ .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
+--
+2.35.1
+
--- /dev/null
+From f64e1e1539b78a2a935afb6caf069f8636fe56c1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 11 Sep 2022 00:02:07 +0700
+Subject: clk: qcom: sm6115: Select QCOM_GDSC
+
+From: Dang Huynh <danct12@riseup.net>
+
+[ Upstream commit 50ee65dc512b9b5c4de354cf3b4dded34f46c571 ]
+
+While working on the Fxtec Pro1X device, this error shows up with
+my own minimal configuration:
+
+gcc-sm6115: probe of 1400000.clock-controller failed with error -38
+
+The clock driver depends on CONFIG_QCOM_GDSC and after enabling
+that, the driver probes successfully.
+
+Signed-off-by: Dang Huynh <danct12@riseup.net>
+Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC)
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220910170207.1592220-1-danct12@riseup.net
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/qcom/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
+index 9ef007b3cf9b..6ba86cffc413 100644
+--- a/drivers/clk/qcom/Kconfig
++++ b/drivers/clk/qcom/Kconfig
+@@ -550,6 +550,7 @@ config SM_DISPCC_8250
+
+ config SM_GCC_6115
+ tristate "SM6115 and SM4250 Global Clock Controller"
++ select QCOM_GDSC
+ help
+ Support for the global clock controller on SM6115 and SM4250 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+--
+2.35.1
+
--- /dev/null
+From 5f7c6416247f9ce6ecee17a23d1671437abcc23c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jun 2022 22:38:51 +0800
+Subject: clk: qoriq: Hold reference returned by of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit a8ea4273bc26256ce3cce83164f0f51c5bf6e127 ]
+
+In legacy_init_clockgen(), we need to hold the reference returned
+by of_get_parent() and use it to call of_node_put() for refcount
+balance.
+
+Beside, in create_sysclk(), we need to call of_node_put() on 'sysclk'
+also for refcount balance.
+
+Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver")
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220628143851.171299-1-windhl@126.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-qoriq.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
+index 88898b97a443..5eddb9f0d6bd 100644
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -1063,8 +1063,13 @@ static void __init _clockgen_init(struct device_node *np, bool legacy);
+ */
+ static void __init legacy_init_clockgen(struct device_node *np)
+ {
+- if (!clockgen.node)
+- _clockgen_init(of_get_parent(np), true);
++ if (!clockgen.node) {
++ struct device_node *parent_np;
++
++ parent_np = of_get_parent(np);
++ _clockgen_init(parent_np, true);
++ of_node_put(parent_np);
++ }
+ }
+
+ /* Legacy node */
+@@ -1159,6 +1164,7 @@ static struct clk * __init create_sysclk(const char *name)
+ sysclk = of_get_child_by_name(clockgen.node, "sysclk");
+ if (sysclk) {
+ clk = sysclk_from_fixed(sysclk, name);
++ of_node_put(sysclk);
+ if (!IS_ERR(clk))
+ return clk;
+ }
+--
+2.35.1
+
--- /dev/null
+From 93fbe8062979af18e5c8dcd24db982ba0d0e518c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Jul 2022 08:47:29 +0800
+Subject: clk: sprd: Hold reference returned by of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 91e6455bf715fb1558a0bf8f645ec1c131254a3c ]
+
+We should hold the reference returned by of_get_parent() and use it
+to call of_node_put() for refcount balance.
+
+Fixes: f95e8c7923d1 ("clk: sprd: support to get regmap from parent node")
+Signed-off-by: Liang He <windhl@126.com>
+Link: https://lore.kernel.org/r/20220704004729.272481-1-windhl@126.com
+Reviewed-by: Orson Zhai <orsonzhai@gmail.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/sprd/common.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c
+index d620bbbcdfc8..ce81e4087a8f 100644
+--- a/drivers/clk/sprd/common.c
++++ b/drivers/clk/sprd/common.c
+@@ -41,7 +41,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
+ {
+ void __iomem *base;
+ struct device *dev = &pdev->dev;
+- struct device_node *node = dev->of_node;
++ struct device_node *node = dev->of_node, *np;
+ struct regmap *regmap;
+
+ if (of_find_property(node, "sprd,syscon", NULL)) {
+@@ -50,9 +50,10 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
+ pr_err("%s: failed to get syscon regmap\n", __func__);
+ return PTR_ERR(regmap);
+ }
+- } else if (of_device_is_compatible(of_get_parent(dev->of_node),
+- "syscon")) {
+- regmap = device_node_to_regmap(of_get_parent(dev->of_node));
++ } else if (of_device_is_compatible(np = of_get_parent(node), "syscon") ||
++ (of_node_put(np), 0)) {
++ regmap = device_node_to_regmap(np);
++ of_node_put(np);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "failed to get regmap from its parent.\n");
+ return PTR_ERR(regmap);
+--
+2.35.1
+
--- /dev/null
+From 6c281aff69d1cd36150378d4a765e9bd53a45a61 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 18:38:34 +0400
+Subject: clk: tegra: Fix refcount leak in tegra114_clock_init
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit db16a80c76ea395766913082b1e3f939dde29b2c ]
+
+of_find_matching_node() returns a node pointer with refcount
+incremented, we should use of_node_put() on it when not need anymore.
+Add missing of_node_put() to avoid refcount leak.
+
+Fixes: 2cb5efefd6f7 ("clk: tegra: Implement clocks for Tegra114")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Link: https://lore.kernel.org/r/20220523143834.7587-1-linmq006@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/tegra/clk-tegra114.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
+index bc9e47a4cb60..4e2b26e3e573 100644
+--- a/drivers/clk/tegra/clk-tegra114.c
++++ b/drivers/clk/tegra/clk-tegra114.c
+@@ -1317,6 +1317,7 @@ static void __init tegra114_clock_init(struct device_node *np)
+ }
+
+ pmc_base = of_iomap(node, 0);
++ of_node_put(node);
+ if (!pmc_base) {
+ pr_err("Can't map pmc registers\n");
+ WARN_ON(1);
+--
+2.35.1
+
--- /dev/null
+From 9073c0b97351ec7dfda433cbf9d3e1933c32423f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 18:26:08 +0400
+Subject: clk: tegra: Fix refcount leak in tegra210_clock_init
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 56c78cb1f00a9dde8cd762131ce8f4c5eb046fbb ]
+
+of_find_matching_node() returns a node pointer with refcount
+incremented, we should use of_node_put() on it when not need anymore.
+Add missing of_node_put() to avoid refcount leak.
+
+Fixes: 6b301a059eb2 ("clk: tegra: Add support for Tegra210 clocks")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Link: https://lore.kernel.org/r/20220523142608.65074-1-linmq006@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/tegra/clk-tegra210.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
+index b9099012dc7b..499f999e91e1 100644
+--- a/drivers/clk/tegra/clk-tegra210.c
++++ b/drivers/clk/tegra/clk-tegra210.c
+@@ -3748,6 +3748,7 @@ static void __init tegra210_clock_init(struct device_node *np)
+ }
+
+ pmc_base = of_iomap(node, 0);
++ of_node_put(node);
+ if (!pmc_base) {
+ pr_err("Can't map pmc registers\n");
+ WARN_ON(1);
+--
+2.35.1
+
--- /dev/null
+From 6386de163081deaf08b6b84d158e9b863b031fa1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 19:28:11 +0400
+Subject: clk: tegra20: Fix refcount leak in tegra20_clock_init
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 4e343bafe03ff68a62f48f8235cf98f2c685468b ]
+
+of_find_matching_node() returns a node pointer with refcount
+incremented, we should use of_node_put() on it when not need anymore.
+Add missing of_node_put() to avoid refcount leak.
+
+Fixes: 37c26a906527 ("clk: tegra: add clock support for Tegra20")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Link: https://lore.kernel.org/r/20220523152811.19692-1-linmq006@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/tegra/clk-tegra20.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
+index 3664593a5ba4..d246a39a6b4f 100644
+--- a/drivers/clk/tegra/clk-tegra20.c
++++ b/drivers/clk/tegra/clk-tegra20.c
+@@ -1128,6 +1128,7 @@ static void __init tegra20_clock_init(struct device_node *np)
+ }
+
+ pmc_base = of_iomap(node, 0);
++ of_node_put(node);
+ if (!pmc_base) {
+ pr_err("Can't map pmc registers\n");
+ BUG();
+--
+2.35.1
+
--- /dev/null
+From fb4ab30dff20091d8068226b6fa10ed10630b643 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 2 Jun 2022 07:08:36 +0400
+Subject: clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 9c59a01caba26ec06fefd6ca1f22d5fd1de57d63 ]
+
+pm_runtime_get_sync() will increment pm usage counter.
+Forgetting to putting operation will result in reference leak.
+Add missing pm_runtime_put_sync in some error paths.
+
+Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.com
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/ti/clk-dra7-atl.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
+index 8d4c08b034bd..e2e59d78c173 100644
+--- a/drivers/clk/ti/clk-dra7-atl.c
++++ b/drivers/clk/ti/clk-dra7-atl.c
+@@ -251,14 +251,16 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
+ if (rc) {
+ pr_err("%s: failed to lookup atl clock %d\n", __func__,
+ i);
+- return -EINVAL;
++ ret = -EINVAL;
++ goto pm_put;
+ }
+
+ clk = of_clk_get_from_provider(&clkspec);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to get atl clock %d from provider\n",
+ __func__, i);
+- return PTR_ERR(clk);
++ ret = PTR_ERR(clk);
++ goto pm_put;
+ }
+
+ cdesc = to_atl_desc(__clk_get_hw(clk));
+@@ -291,8 +293,9 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
+ if (cdesc->enabled)
+ atl_clk_enable(__clk_get_hw(clk));
+ }
+- pm_runtime_put_sync(cinfo->dev);
+
++pm_put:
++ pm_runtime_put_sync(cinfo->dev);
+ return ret;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 98ed80f78654c8f699ca2105d7d94c3193c9ee46 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 01:53:55 +0300
+Subject: clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit c388cc804016cf0f65afdc2362b120aa594ff3e6 ]
+
+We have discovered random glitches during the system boot up procedure.
+The problem investigation led us to the weird outcomes: when none of the
+Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the
+glitches disappeared. It was a mystery since the SoC external clock
+domains were fed with different 5P49V6901 outputs. The driver code didn't
+seem like bogus either. We almost despaired to find out a root cause when
+the solution has been found for a more modern revision of the chip. It
+turned out the 5P49V6901 clock generator stopped its output for a short
+period of time during the VC5_OUT_DIV_CONTROL register writing. The same
+problem was found for the 5P49V6965 revision of the chip and was
+successfully fixed in commit fc336ae622df ("clk: vc5: fix output disabling
+when enabling a FOD") by enabling the "bypass_sync" flag hidden inside
+"Unused Factory Reserved Register". Even though the 5P49V6901 registers
+description and programming guide doesn't provide any intel regarding that
+flag, setting it up anyway in the officially unused register completely
+eliminated the denoted glitches. Thus let's activate the functionality
+submitted in commit fc336ae622df ("clk: vc5: fix output disabling when
+enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the
+ports implicit inter-dependency.
+
+Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901")
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
+Link: https://lore.kernel.org/r/20220929225402.9696-2-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/clk-versaclock5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
+index c6d3b1ab3d55..5f8bd49b0810 100644
+--- a/drivers/clk/clk-versaclock5.c
++++ b/drivers/clk/clk-versaclock5.c
+@@ -1204,7 +1204,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = {
+ .model = IDT_VC6_5P49V6901,
+ .clk_fod_cnt = 4,
+ .clk_out_cnt = 5,
+- .flags = VC5_HAS_PFD_FREQ_DBL,
++ .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
+ };
+
+ static const struct vc5_chip_info idt_5p49v6965_info = {
+--
+2.35.1
+
--- /dev/null
+From 609855a73cbd05aca59b01447294fa91a6555c8c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 May 2022 12:31:54 +0530
+Subject: clk: zynqmp: Fix stack-out-of-bounds in strncpy`
+
+From: Ian Nam <young.kwan.nam@xilinx.com>
+
+[ Upstream commit dd80fb2dbf1cd8751efbe4e53e54056f56a9b115 ]
+
+"BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68"
+
+Linux-ATF interface is using 16 bytes of SMC payload. In case clock name is
+longer than 15 bytes, string terminated NULL character will not be received
+by Linux. Add explicit NULL character at last byte to fix issues when clock
+name is longer.
+
+This fixes below bug reported by KASAN:
+
+ ==================================================================
+ BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68
+ Read of size 1 at addr ffff0008c89a7410 by task swapper/0/1
+
+ CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.4.0-00396-g81ef9e7-dirty #3
+ Hardware name: Xilinx Versal vck190 Eval board revA (QSPI) (DT)
+ Call trace:
+ dump_backtrace+0x0/0x1e8
+ show_stack+0x14/0x20
+ dump_stack+0xd4/0x108
+ print_address_description.isra.0+0xbc/0x37c
+ __kasan_report+0x144/0x198
+ kasan_report+0xc/0x18
+ __asan_load1+0x5c/0x68
+ strncpy+0x30/0x68
+ zynqmp_clock_probe+0x238/0x7b8
+ platform_drv_probe+0x6c/0xc8
+ really_probe+0x14c/0x418
+ driver_probe_device+0x74/0x130
+ __device_attach_driver+0xc4/0xe8
+ bus_for_each_drv+0xec/0x150
+ __device_attach+0x160/0x1d8
+ device_initial_probe+0x10/0x18
+ bus_probe_device+0xe0/0xf0
+ device_add+0x528/0x950
+ of_device_add+0x5c/0x80
+ of_platform_device_create_pdata+0x120/0x168
+ of_platform_bus_create+0x244/0x4e0
+ of_platform_populate+0x50/0xe8
+ zynqmp_firmware_probe+0x370/0x3a8
+ platform_drv_probe+0x6c/0xc8
+ really_probe+0x14c/0x418
+ driver_probe_device+0x74/0x130
+ device_driver_attach+0x94/0xa0
+ __driver_attach+0x70/0x108
+ bus_for_each_dev+0xe4/0x158
+ driver_attach+0x30/0x40
+ bus_add_driver+0x21c/0x2b8
+ driver_register+0xbc/0x1d0
+ __platform_driver_register+0x7c/0x88
+ zynqmp_firmware_driver_init+0x1c/0x24
+ do_one_initcall+0xa4/0x234
+ kernel_init_freeable+0x1b0/0x24c
+ kernel_init+0x10/0x110
+ ret_from_fork+0x10/0x18
+
+ The buggy address belongs to the page:
+ page:ffff0008f9be1c88 refcount:0 mapcount:0 mapping:0000000000000000 index:0x0
+ raw: 0008d00000000000 ffff0008f9be1c90 ffff0008f9be1c90 0000000000000000
+ raw: 0000000000000000 0000000000000000 00000000ffffffff
+ page dumped because: kasan: bad access detected
+
+ addr ffff0008c89a7410 is located in stack of task swapper/0/1 at offset 112 in frame:
+ zynqmp_clock_probe+0x0/0x7b8
+
+ this frame has 3 objects:
+ [32, 44) 'response'
+ [64, 80) 'ret_payload'
+ [96, 112) 'name'
+
+ Memory state around the buggy address:
+ ffff0008c89a7300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ ffff0008c89a7380: 00 00 00 00 f1 f1 f1 f1 00 04 f2 f2 00 00 f2 f2
+ >ffff0008c89a7400: 00 00 f3 f3 00 00 00 00 00 00 00 00 00 00 00 00
+ ^
+ ffff0008c89a7480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ ffff0008c89a7500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ ==================================================================
+
+Signed-off-by: Ian Nam <young.kwan.nam@xilinx.com>
+Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+Link: https://lore.kernel.org/r/20220510070154.29528-3-shubhrajyoti.datta@xilinx.com
+Acked-by: Michal Simek <michal.simek@amd.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/zynqmp/clkc.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
+index eb25303eefed..2c9da6623b84 100644
+--- a/drivers/clk/zynqmp/clkc.c
++++ b/drivers/clk/zynqmp/clkc.c
+@@ -710,6 +710,13 @@ static void zynqmp_get_clock_info(void)
+ FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
+
+ zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
++
++ /*
++ * Terminate with NULL character in case name provided by firmware
++ * is longer and truncated due to size limit.
++ */
++ name.name[sizeof(name.name) - 1] = '\0';
++
+ if (!strcmp(name.name, RESERVED_CLK_NAME))
+ continue;
+ strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
+--
+2.35.1
+
--- /dev/null
+From 9c71fd9173119adf86e54c747bb188af4e26ecd5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 22:20:30 +0800
+Subject: clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
+
+From: Quanyang Wang <quanyang.wang@windriver.com>
+
+[ Upstream commit 30eaf02149ecc3c5815e45d27187bf09e925071d ]
+
+The function zynqmp_pll_round_rate is used to find a most appropriate
+PLL frequency which the hardware can generate according to the desired
+frequency. For example, if the desired frequency is 297MHz, considering
+the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
+of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
+
+There are two problems with the current code of zynqmp_pll_round_rate:
+
+1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate
+when the parameter "rate" is an integer multiple of *prate, in other words,
+if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which
+is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz
+and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and
+just return 660MHz, and this will cause clk_calc_new_rates failure since
+zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
+
+2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk
+that zynqmp_pll_round_rate returns an invalid rate because the function
+DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
+clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz,
+this function will return 1499999985Hz by using the formula below:
+ value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
+This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
+because DIV_ROUND_CLOSEST makes some loss in the fractional part.
+
+Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
+Link: https://lore.kernel.org/r/20220826142030.213805-1-quanyang.wang@windriver.com
+Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/zynqmp/pll.c | 31 +++++++++++++++----------------
+ 1 file changed, 15 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
+index 036e4ff64a2f..bc066f300345 100644
+--- a/drivers/clk/zynqmp/pll.c
++++ b/drivers/clk/zynqmp/pll.c
+@@ -102,26 +102,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+ {
+ u32 fbdiv;
+- long rate_div, f;
++ u32 mult, div;
+
+- /* Enable the fractional mode if needed */
+- rate_div = (rate * FRAC_DIV) / *prate;
+- f = rate_div % FRAC_DIV;
+- if (f) {
+- if (rate > PS_PLL_VCO_MAX) {
+- fbdiv = rate / PS_PLL_VCO_MAX;
+- rate = rate / (fbdiv + 1);
+- }
+- if (rate < PS_PLL_VCO_MIN) {
+- fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
+- rate = rate * fbdiv;
+- }
+- return rate;
++ /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
++ if (rate > PS_PLL_VCO_MAX) {
++ div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
++ rate = rate / div;
++ }
++ if (rate < PS_PLL_VCO_MIN) {
++ mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
++ rate = rate * mult;
+ }
+
+ fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+- fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
+- return *prate * fbdiv;
++ if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
++ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
++ rate = *prate * fbdiv;
++ }
++
++ return rate;
+ }
+
+ /**
+--
+2.35.1
+
--- /dev/null
+From 76a985f835e3b535bf6574b9babb7ca37482cfe7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 13:28:57 -0700
+Subject: cpufreq: intel_pstate: Add Tigerlake support in no-HWP mode
+
+From: Doug Smythies <dsmythies@telus.net>
+
+[ Upstream commit 71bb5c82aaaea007167f3ba68d3a669c74d7d55d ]
+
+Users may disable HWP in firmware, in which case intel_pstate wouldn't load
+unless the CPU model is explicitly supported.
+
+Add TIGERLAKE to the list of CPUs that can register intel_pstate while not
+advertising the HWP capability. Without this change, an TIGERLAKE in no-HWP
+mode could only use the acpi_cpufreq frequency scaling driver.
+
+See also commits:
+d8de7a44e11f: cpufreq: intel_pstate: Add Skylake servers support
+fbdc21e9b038: cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode
+706c5328851d: cpufreq: intel_pstate: Add Cometlake support in no-HWP mode
+
+Reported by: M. Cargi Ari <cagriari@pm.me>
+Signed-off-by: Doug Smythies <dsmythies@telus.net>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/cpufreq/intel_pstate.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
+index 8a2c6b58b652..c57229c108a7 100644
+--- a/drivers/cpufreq/intel_pstate.c
++++ b/drivers/cpufreq/intel_pstate.c
+@@ -2257,6 +2257,7 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
+ X86_MATCH(SKYLAKE_X, core_funcs),
+ X86_MATCH(COMETLAKE, core_funcs),
+ X86_MATCH(ICELAKE_X, core_funcs),
++ X86_MATCH(TIGERLAKE, core_funcs),
+ {}
+ };
+ MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
+--
+2.35.1
+
--- /dev/null
+From 92f1623446f766874da499bb227e73aa39c8bf32 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 19:37:06 +0100
+Subject: crypto: akcipher - default implementation for setting a private key
+
+From: Ignat Korchagin <ignat@cloudflare.com>
+
+[ Upstream commit bc155c6c188c2f0c5749993b1405673d25a80389 ]
+
+Changes from v1:
+ * removed the default implementation from set_pub_key: it is assumed that
+ an implementation must always have this callback defined as there are
+ no use case for an algorithm, which doesn't need a public key
+
+Many akcipher implementations (like ECDSA) support only signature
+verifications, so they don't have all callbacks defined.
+
+Commit 78a0324f4a53 ("crypto: akcipher - default implementations for
+request callbacks") introduced default callbacks for sign/verify
+operations, which just return an error code.
+
+However, these are not enough, because before calling sign the caller would
+likely call set_priv_key first on the instantiated transform (as the
+in-kernel testmgr does). This function does not have a default stub, so the
+kernel crashes, when trying to set a private key on an akcipher, which
+doesn't support signature generation.
+
+I've noticed this, when trying to add a KAT vector for ECDSA signature to
+the testmgr.
+
+With this patch the testmgr returns an error in dmesg (as it should)
+instead of crashing the kernel NULL ptr dereference.
+
+Fixes: 78a0324f4a53 ("crypto: akcipher - default implementations for request callbacks")
+Signed-off-by: Ignat Korchagin <ignat@cloudflare.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ crypto/akcipher.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/crypto/akcipher.c b/crypto/akcipher.c
+index f866085c8a4a..ab975a420e1e 100644
+--- a/crypto/akcipher.c
++++ b/crypto/akcipher.c
+@@ -120,6 +120,12 @@ static int akcipher_default_op(struct akcipher_request *req)
+ return -ENOSYS;
+ }
+
++static int akcipher_default_set_key(struct crypto_akcipher *tfm,
++ const void *key, unsigned int keylen)
++{
++ return -ENOSYS;
++}
++
+ int crypto_register_akcipher(struct akcipher_alg *alg)
+ {
+ struct crypto_alg *base = &alg->base;
+@@ -132,6 +138,8 @@ int crypto_register_akcipher(struct akcipher_alg *alg)
+ alg->encrypt = akcipher_default_op;
+ if (!alg->decrypt)
+ alg->decrypt = akcipher_default_op;
++ if (!alg->set_priv_key)
++ alg->set_priv_key = akcipher_default_set_key;
+
+ akcipher_prepare_alg(alg);
+ return crypto_register_alg(base);
+--
+2.35.1
+
--- /dev/null
+From 56d958ca85e7e11617c457a89dbf7c91645f9f5e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 09:43:27 +0300
+Subject: crypto: cavium - prevent integer overflow loading firmware
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 2526d6bf27d15054bb0778b2f7bc6625fd934905 ]
+
+The "code_length" value comes from the firmware file. If your firmware
+is untrusted realistically there is probably very little you can do to
+protect yourself. Still we try to limit the damage as much as possible.
+Also Smatch marks any data read from the filesystem as untrusted and
+prints warnings if it not capped correctly.
+
+The "ntohl(ucode->code_length) * 2" multiplication can have an
+integer overflow.
+
+Fixes: 9e2c7d99941d ("crypto: cavium - Add Support for Octeon-tx CPT Engine")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/cavium/cpt/cptpf_main.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/crypto/cavium/cpt/cptpf_main.c b/drivers/crypto/cavium/cpt/cptpf_main.c
+index 8c32d0eb8fcf..6872ac344001 100644
+--- a/drivers/crypto/cavium/cpt/cptpf_main.c
++++ b/drivers/crypto/cavium/cpt/cptpf_main.c
+@@ -253,6 +253,7 @@ static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae)
+ const struct firmware *fw_entry;
+ struct device *dev = &cpt->pdev->dev;
+ struct ucode_header *ucode;
++ unsigned int code_length;
+ struct microcode *mcode;
+ int j, ret = 0;
+
+@@ -263,11 +264,12 @@ static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae)
+ ucode = (struct ucode_header *)fw_entry->data;
+ mcode = &cpt->mcode[cpt->next_mc_idx];
+ memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ);
+- mcode->code_size = ntohl(ucode->code_length) * 2;
+- if (!mcode->code_size) {
++ code_length = ntohl(ucode->code_length);
++ if (code_length == 0 || code_length >= INT_MAX / 2) {
+ ret = -EINVAL;
+ goto fw_release;
+ }
++ mcode->code_size = code_length * 2;
+
+ mcode->is_ae = is_ae;
+ mcode->core_mask = 0ULL;
+--
+2.35.1
+
--- /dev/null
+From 3e7c3dabae4ed0bf4f1dd9095f65ea3dfbe9e501 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 22:47:12 +0800
+Subject: crypto: ccp - Release dma channels before dmaengine unrgister
+
+From: Koba Ko <koba.ko@canonical.com>
+
+[ Upstream commit 68dbe80f5b510c66c800b9e8055235c5b07e37d1 ]
+
+A warning is shown during shutdown,
+
+__dma_async_device_channel_unregister called while 2 clients hold a reference
+WARNING: CPU: 15 PID: 1 at drivers/dma/dmaengine.c:1110 __dma_async_device_channel_unregister+0xb7/0xc0
+
+Call dma_release_channel for occupied channles before dma_async_device_unregister.
+
+Fixes: 54cce8ecb925 ("crypto: ccp - ccp_dmaengine_unregister release dma channels")
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Koba Ko <koba.ko@canonical.com>
+Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/ccp/ccp-dmaengine.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/crypto/ccp/ccp-dmaengine.c b/drivers/crypto/ccp/ccp-dmaengine.c
+index 7d4b4ad1db1f..9f753cb4f5f1 100644
+--- a/drivers/crypto/ccp/ccp-dmaengine.c
++++ b/drivers/crypto/ccp/ccp-dmaengine.c
+@@ -641,6 +641,10 @@ static void ccp_dma_release(struct ccp_device *ccp)
+ for (i = 0; i < ccp->cmd_q_count; i++) {
+ chan = ccp->ccp_dma_chan + i;
+ dma_chan = &chan->dma_chan;
++
++ if (dma_chan->client_count)
++ dma_release_channel(dma_chan);
++
+ tasklet_kill(&chan->cleanup_tasklet);
+ list_del_rcu(&dma_chan->device_node);
+ }
+@@ -766,8 +770,8 @@ void ccp_dmaengine_unregister(struct ccp_device *ccp)
+ if (!dmaengine)
+ return;
+
+- dma_async_device_unregister(dma_dev);
+ ccp_dma_release(ccp);
++ dma_async_device_unregister(dma_dev);
+
+ kmem_cache_destroy(ccp->dma_desc_cache);
+ kmem_cache_destroy(ccp->dma_cmd_cache);
+--
+2.35.1
+
--- /dev/null
+From 5567b9e57531693471c86e75e4dbbfc12e2752aa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 27 Aug 2022 18:27:37 +0800
+Subject: crypto: hisilicon/qm - fix missing put dfx access
+
+From: Weili Qian <qianweili@huawei.com>
+
+[ Upstream commit 5afc904f443de2afd31c4e0686ba178beede86fe ]
+
+In function qm_cmd_write(), if function returns from
+branch 'atomic_read(&qm->status.flags) == QM_STOP',
+the got dfx access is forgotten to put.
+
+Fixes: 607c191b371d ("crypto: hisilicon - support runtime PM for accelerator device")
+Signed-off-by: Weili Qian <qianweili@huawei.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/hisilicon/qm.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
+index b616d2d8e773..b8900a5dbf6e 100644
+--- a/drivers/crypto/hisilicon/qm.c
++++ b/drivers/crypto/hisilicon/qm.c
+@@ -1888,8 +1888,10 @@ static ssize_t qm_cmd_write(struct file *filp, const char __user *buffer,
+ return ret;
+
+ /* Judge if the instance is being reset. */
+- if (unlikely(atomic_read(&qm->status.flags) == QM_STOP))
+- return 0;
++ if (unlikely(atomic_read(&qm->status.flags) == QM_STOP)) {
++ ret = 0;
++ goto put_dfx_access;
++ }
+
+ if (count > QM_DBG_WRITE_LEN) {
+ ret = -ENOSPC;
+--
+2.35.1
+
--- /dev/null
+From b0f109ffc36442e21bd745f7c3d7a13e91d3e6d1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Jul 2022 10:07:58 +0800
+Subject: crypto: hisilicon/zip - fix mismatch in get/set sgl_sge_nr
+
+From: Ye Weihua <yeweihua4@huawei.com>
+
+[ Upstream commit d74f9340097a881869c4c22ca376654cc2516ecc ]
+
+KASAN reported this Bug:
+
+ [17619.659757] BUG: KASAN: global-out-of-bounds in param_get_int+0x34/0x60
+ [17619.673193] Read of size 4 at addr fffff01332d7ed00 by task read_all/1507958
+ ...
+ [17619.698934] The buggy address belongs to the variable:
+ [17619.708371] sgl_sge_nr+0x0/0xffffffffffffa300 [hisi_zip]
+
+There is a mismatch in hisi_zip when get/set the variable sgl_sge_nr.
+The type of sgl_sge_nr is u16, and get/set sgl_sge_nr by
+param_get/set_int.
+
+Replacing param_get/set_int to param_get/set_ushort can fix this bug.
+
+Fixes: f081fda293ffb ("crypto: hisilicon - add sgl_sge_nr module param for zip")
+Signed-off-by: Ye Weihua <yeweihua4@huawei.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/hisilicon/zip/zip_crypto.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/crypto/hisilicon/zip/zip_crypto.c b/drivers/crypto/hisilicon/zip/zip_crypto.c
+index 9520a4113c81..a91e6e0e9c69 100644
+--- a/drivers/crypto/hisilicon/zip/zip_crypto.c
++++ b/drivers/crypto/hisilicon/zip/zip_crypto.c
+@@ -122,12 +122,12 @@ static int sgl_sge_nr_set(const char *val, const struct kernel_param *kp)
+ if (ret || n == 0 || n > HISI_ACC_SGL_SGE_NR_MAX)
+ return -EINVAL;
+
+- return param_set_int(val, kp);
++ return param_set_ushort(val, kp);
+ }
+
+ static const struct kernel_param_ops sgl_sge_nr_ops = {
+ .set = sgl_sge_nr_set,
+- .get = param_get_int,
++ .get = param_get_ushort,
+ };
+
+ static u16 sgl_sge_nr = HZIP_SGL_SGE_NR;
+--
+2.35.1
+
--- /dev/null
+From 70d2fe8c9d425cf618e346b69bc9750c75f0a15c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 10:51:28 +0800
+Subject: crypto: inside-secure - Change swab to swab32
+
+From: Peter Harliman Liem <pliem@maxlinear.com>
+
+[ Upstream commit 664593407e936b6438fbfaaf98876910fd31cf9a ]
+
+The use of swab() is causing failures in 64-bit arch, as it
+translates to __swab64() instead of the intended __swab32().
+It eventually causes wrong results in xcbcmac & cmac algo.
+
+Fixes: 78cf1c8bfcb8 ("crypto: inside-secure - Move ipad/opad into safexcel_context")
+Signed-off-by: Peter Harliman Liem <pliem@maxlinear.com>
+Acked-by: Antoine Tenart <atenart@kernel.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/inside-secure/safexcel_hash.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/crypto/inside-secure/safexcel_hash.c b/drivers/crypto/inside-secure/safexcel_hash.c
+index bc60b5802256..2124416742f8 100644
+--- a/drivers/crypto/inside-secure/safexcel_hash.c
++++ b/drivers/crypto/inside-secure/safexcel_hash.c
+@@ -383,7 +383,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
+ u32 x;
+
+ x = ipad[i] ^ ipad[i + 4];
+- cache[i] ^= swab(x);
++ cache[i] ^= swab32(x);
+ }
+ }
+ cache_len = AES_BLOCK_SIZE;
+@@ -821,7 +821,7 @@ static int safexcel_ahash_final(struct ahash_request *areq)
+ u32 *result = (void *)areq->result;
+
+ /* K3 */
+- result[i] = swab(ctx->base.ipad.word[i + 4]);
++ result[i] = swab32(ctx->base.ipad.word[i + 4]);
+ }
+ areq->result[0] ^= 0x80; // 10- padding
+ crypto_cipher_encrypt_one(ctx->kaes, areq->result, areq->result);
+@@ -2106,7 +2106,7 @@ static int safexcel_xcbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
+ crypto_cipher_encrypt_one(ctx->kaes, (u8 *)key_tmp + AES_BLOCK_SIZE,
+ "\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3");
+ for (i = 0; i < 3 * AES_BLOCK_SIZE / sizeof(u32); i++)
+- ctx->base.ipad.word[i] = swab(key_tmp[i]);
++ ctx->base.ipad.word[i] = swab32(key_tmp[i]);
+
+ crypto_cipher_clear_flags(ctx->kaes, CRYPTO_TFM_REQ_MASK);
+ crypto_cipher_set_flags(ctx->kaes, crypto_ahash_get_flags(tfm) &
+@@ -2189,7 +2189,7 @@ static int safexcel_cmac_setkey(struct crypto_ahash *tfm, const u8 *key,
+ return ret;
+
+ for (i = 0; i < len / sizeof(u32); i++)
+- ctx->base.ipad.word[i + 8] = swab(aes.key_enc[i]);
++ ctx->base.ipad.word[i + 8] = swab32(aes.key_enc[i]);
+
+ /* precompute the CMAC key material */
+ crypto_cipher_clear_flags(ctx->kaes, CRYPTO_TFM_REQ_MASK);
+--
+2.35.1
+
--- /dev/null
+From 2019f4b07b7bffed3ec730cef0456213b49b74f2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 09:43:19 +0300
+Subject: crypto: marvell/octeontx - prevent integer overflows
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit caca37cf6c749ff0303f68418cfe7b757a4e0697 ]
+
+The "code_length" value comes from the firmware file. If your firmware
+is untrusted realistically there is probably very little you can do to
+protect yourself. Still we try to limit the damage as much as possible.
+Also Smatch marks any data read from the filesystem as untrusted and
+prints warnings if it not capped correctly.
+
+The "code_length * 2" can overflow. The round_up(ucode_size, 16) +
+sizeof() expression can overflow too. Prevent these overflows.
+
+Fixes: d9110b0b01ff ("crypto: marvell - add support for OCTEON TX CPT engine")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../crypto/marvell/octeontx/otx_cptpf_ucode.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c
+index 40b482198ebc..a765eefb18c2 100644
+--- a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c
++++ b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c
+@@ -286,6 +286,7 @@ static int process_tar_file(struct device *dev,
+ struct tar_ucode_info_t *tar_info;
+ struct otx_cpt_ucode_hdr *ucode_hdr;
+ int ucode_type, ucode_size;
++ unsigned int code_length;
+
+ /*
+ * If size is less than microcode header size then don't report
+@@ -303,7 +304,13 @@ static int process_tar_file(struct device *dev,
+ if (get_ucode_type(ucode_hdr, &ucode_type))
+ return 0;
+
+- ucode_size = ntohl(ucode_hdr->code_length) * 2;
++ code_length = ntohl(ucode_hdr->code_length);
++ if (code_length >= INT_MAX / 2) {
++ dev_err(dev, "Invalid code_length %u\n", code_length);
++ return -EINVAL;
++ }
++
++ ucode_size = code_length * 2;
+ if (!ucode_size || (size < round_up(ucode_size, 16) +
+ sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) {
+ dev_err(dev, "Ucode %s invalid size\n", filename);
+@@ -886,6 +893,7 @@ static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode,
+ {
+ struct otx_cpt_ucode_hdr *ucode_hdr;
+ const struct firmware *fw;
++ unsigned int code_length;
+ int ret;
+
+ set_ucode_filename(ucode, ucode_filename);
+@@ -896,7 +904,13 @@ static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode,
+ ucode_hdr = (struct otx_cpt_ucode_hdr *) fw->data;
+ memcpy(ucode->ver_str, ucode_hdr->ver_str, OTX_CPT_UCODE_VER_STR_SZ);
+ ucode->ver_num = ucode_hdr->ver_num;
+- ucode->size = ntohl(ucode_hdr->code_length) * 2;
++ code_length = ntohl(ucode_hdr->code_length);
++ if (code_length >= INT_MAX / 2) {
++ dev_err(dev, "Ucode invalid code_length %u\n", code_length);
++ ret = -EINVAL;
++ goto release_fw;
++ }
++ ucode->size = code_length * 2;
+ if (!ucode->size || (fw->size < round_up(ucode->size, 16)
+ + sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) {
+ dev_err(dev, "Ucode %s invalid size\n", ucode_filename);
+--
+2.35.1
+
--- /dev/null
+From ed3cc5e7552b5a5099a08e2e0c2a1dd8dc1d7f94 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 12:32:16 +0200
+Subject: crypto: qat - fix default value of WDT timer
+
+From: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com>
+
+[ Upstream commit cc40b04c08400d86d2d6ea0159e0617e717f729c ]
+
+The QAT HW supports an hardware mechanism to detect an accelerator hang.
+The reporting of a hang occurs after a watchdog timer (WDT) expires.
+
+The value of the WDT set previously was too small and was causing false
+positives.
+Change the default value of the WDT to 0x7000000ULL to avoid this.
+
+Fixes: 1c4d9d5bbb5a ("crypto: qat - enable detection of accelerators hang")
+Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
+Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/qat/qat_common/adf_gen4_hw_data.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
+index b8fca1ff7aab..0b7086cae00b 100644
+--- a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
++++ b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
+@@ -99,7 +99,7 @@ do { \
+ * Timeout is in cycles. Clock speed may vary across products but this
+ * value should be a few milli-seconds.
+ */
+-#define ADF_SSM_WDT_DEFAULT_VALUE 0x200000
++#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL
+ #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000
+ #define ADF_SSMWDTL_OFFSET 0x54
+ #define ADF_SSMWDTH_OFFSET 0x5C
+--
+2.35.1
+
--- /dev/null
+From a3614ccef9436e23eaf4f1bdfde0b46113769c08 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 11:49:12 +0100
+Subject: crypto: qat - fix DMA transfer direction
+
+From: Damian Muszynski <damian.muszynski@intel.com>
+
+[ Upstream commit cf5bb835b7c8a5fee7f26455099cca7feb57f5e9 ]
+
+When CONFIG_DMA_API_DEBUG is selected, while running the crypto self
+test on the QAT crypto algorithms, the function add_dma_entry() reports
+a warning similar to the one below, saying that overlapping mappings
+are not supported. This occurs in tests where the input and the output
+scatter list point to the same buffers (i.e. two different scatter lists
+which point to the same chunks of memory).
+
+The logic that implements the mapping uses the flag DMA_BIDIRECTIONAL
+for both the input and the output scatter lists which leads to
+overlapped write mappings. These are not supported by the DMA layer.
+
+Fix by specifying the correct DMA transfer directions when mapping
+buffers. For in-place operations where the input scatter list
+matches the output scatter list, buffers are mapped once with
+DMA_BIDIRECTIONAL, otherwise input buffers are mapped using the flag
+DMA_TO_DEVICE and output buffers are mapped with DMA_FROM_DEVICE.
+Overlapping a read mapping with a write mapping is a valid case in
+dma-coherent devices like QAT.
+The function that frees and unmaps the buffers, qat_alg_free_bufl()
+has been changed accordingly to the changes to the mapping function.
+
+ DMA-API: 4xxx 0000:06:00.0: cacheline tracking EEXIST, overlapping mappings aren't supported
+ WARNING: CPU: 53 PID: 4362 at kernel/dma/debug.c:570 add_dma_entry+0x1e9/0x270
+ ...
+ Call Trace:
+ dma_map_page_attrs+0x82/0x2d0
+ ? preempt_count_add+0x6a/0xa0
+ qat_alg_sgl_to_bufl+0x45b/0x990 [intel_qat]
+ qat_alg_aead_dec+0x71/0x250 [intel_qat]
+ crypto_aead_decrypt+0x3d/0x70
+ test_aead_vec_cfg+0x649/0x810
+ ? number+0x310/0x3a0
+ ? vsnprintf+0x2a3/0x550
+ ? scnprintf+0x42/0x70
+ ? valid_sg_divisions.constprop.0+0x86/0xa0
+ ? test_aead_vec+0xdf/0x120
+ test_aead_vec+0xdf/0x120
+ alg_test_aead+0x185/0x400
+ alg_test+0x3d8/0x500
+ ? crypto_acomp_scomp_free_ctx+0x30/0x30
+ ? __schedule+0x32a/0x12a0
+ ? ttwu_queue_wakelist+0xbf/0x110
+ ? _raw_spin_unlock_irqrestore+0x23/0x40
+ ? try_to_wake_up+0x83/0x570
+ ? _raw_spin_unlock_irqrestore+0x23/0x40
+ ? __set_cpus_allowed_ptr_locked+0xea/0x1b0
+ ? crypto_acomp_scomp_free_ctx+0x30/0x30
+ cryptomgr_test+0x27/0x50
+ kthread+0xe6/0x110
+ ? kthread_complete_and_exit+0x20/0x20
+ ret_from_fork+0x1f/0x30
+
+Fixes: d370cec ("crypto: qat - Intel(R) QAT crypto interface")
+Link: https://lore.kernel.org/linux-crypto/20220223080400.139367-1-gilad@benyossef.com/
+Signed-off-by: Damian Muszynski <damian.muszynski@intel.com>
+Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/qat/qat_common/qat_algs.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c
+index 873533dc43a7..9abdaf7cd2cf 100644
+--- a/drivers/crypto/qat/qat_common/qat_algs.c
++++ b/drivers/crypto/qat/qat_common/qat_algs.c
+@@ -673,11 +673,14 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst,
+ dma_addr_t blpout = qat_req->buf.bloutp;
+ size_t sz = qat_req->buf.sz;
+ size_t sz_out = qat_req->buf.sz_out;
++ int bl_dma_dir;
+ int i;
+
++ bl_dma_dir = blp != blpout ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
++
+ for (i = 0; i < bl->num_bufs; i++)
+ dma_unmap_single(dev, bl->bufers[i].addr,
+- bl->bufers[i].len, DMA_BIDIRECTIONAL);
++ bl->bufers[i].len, bl_dma_dir);
+
+ dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE);
+
+@@ -691,7 +694,7 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst,
+ for (i = bufless; i < blout->num_bufs; i++) {
+ dma_unmap_single(dev, blout->bufers[i].addr,
+ blout->bufers[i].len,
+- DMA_BIDIRECTIONAL);
++ DMA_FROM_DEVICE);
+ }
+ dma_unmap_single(dev, blpout, sz_out, DMA_TO_DEVICE);
+
+@@ -715,6 +718,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+ struct scatterlist *sg;
+ size_t sz_out, sz = struct_size(bufl, bufers, n);
+ int node = dev_to_node(&GET_DEV(inst->accel_dev));
++ int bufl_dma_dir;
+
+ if (unlikely(!n))
+ return -EINVAL;
+@@ -732,6 +736,8 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+ qat_req->buf.sgl_src_valid = true;
+ }
+
++ bufl_dma_dir = sgl != sglout ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
++
+ for_each_sg(sgl, sg, n, i)
+ bufl->bufers[i].addr = DMA_MAPPING_ERROR;
+
+@@ -743,7 +749,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+
+ bufl->bufers[y].addr = dma_map_single(dev, sg_virt(sg),
+ sg->length,
+- DMA_BIDIRECTIONAL);
++ bufl_dma_dir);
+ bufl->bufers[y].len = sg->length;
+ if (unlikely(dma_mapping_error(dev, bufl->bufers[y].addr)))
+ goto err_in;
+@@ -786,7 +792,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+
+ bufers[y].addr = dma_map_single(dev, sg_virt(sg),
+ sg->length,
+- DMA_BIDIRECTIONAL);
++ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(dev, bufers[y].addr)))
+ goto err_out;
+ bufers[y].len = sg->length;
+@@ -816,7 +822,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+ if (!dma_mapping_error(dev, buflout->bufers[i].addr))
+ dma_unmap_single(dev, buflout->bufers[i].addr,
+ buflout->bufers[i].len,
+- DMA_BIDIRECTIONAL);
++ DMA_FROM_DEVICE);
+
+ if (!qat_req->buf.sgl_dst_valid)
+ kfree(buflout);
+@@ -830,7 +836,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
+ if (!dma_mapping_error(dev, bufl->bufers[i].addr))
+ dma_unmap_single(dev, bufl->bufers[i].addr,
+ bufl->bufers[i].len,
+- DMA_BIDIRECTIONAL);
++ bufl_dma_dir);
+
+ if (!qat_req->buf.sgl_src_valid)
+ kfree(bufl);
+--
+2.35.1
+
--- /dev/null
+From 9eb1c1965515c7a52be0cd562863039d99f4322f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Jul 2022 12:09:28 +0800
+Subject: crypto: sahara - don't sleep when in softirq
+
+From: Zhengchao Shao <shaozhengchao@huawei.com>
+
+[ Upstream commit 108586eba094b318e6a831f977f4ddcc403a15da ]
+
+Function of sahara_aes_crypt maybe could be called by function
+of crypto_skcipher_encrypt during the rx softirq, so it is not
+allowed to use mutex lock.
+
+Fixes: c0c3c89ae347 ("crypto: sahara - replace tasklets with...")
+Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/crypto/sahara.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
+index 457084b344c1..b07ae4ba165e 100644
+--- a/drivers/crypto/sahara.c
++++ b/drivers/crypto/sahara.c
+@@ -26,10 +26,10 @@
+ #include <linux/kernel.h>
+ #include <linux/kthread.h>
+ #include <linux/module.h>
+-#include <linux/mutex.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
++#include <linux/spinlock.h>
+
+ #define SHA_BUFFER_LEN PAGE_SIZE
+ #define SAHARA_MAX_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
+@@ -196,7 +196,7 @@ struct sahara_dev {
+ void __iomem *regs_base;
+ struct clk *clk_ipg;
+ struct clk *clk_ahb;
+- struct mutex queue_mutex;
++ spinlock_t queue_spinlock;
+ struct task_struct *kthread;
+ struct completion dma_completion;
+
+@@ -642,9 +642,9 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode)
+
+ rctx->mode = mode;
+
+- mutex_lock(&dev->queue_mutex);
++ spin_lock_bh(&dev->queue_spinlock);
+ err = crypto_enqueue_request(&dev->queue, &req->base);
+- mutex_unlock(&dev->queue_mutex);
++ spin_unlock_bh(&dev->queue_spinlock);
+
+ wake_up_process(dev->kthread);
+
+@@ -1043,10 +1043,10 @@ static int sahara_queue_manage(void *data)
+ do {
+ __set_current_state(TASK_INTERRUPTIBLE);
+
+- mutex_lock(&dev->queue_mutex);
++ spin_lock_bh(&dev->queue_spinlock);
+ backlog = crypto_get_backlog(&dev->queue);
+ async_req = crypto_dequeue_request(&dev->queue);
+- mutex_unlock(&dev->queue_mutex);
++ spin_unlock_bh(&dev->queue_spinlock);
+
+ if (backlog)
+ backlog->complete(backlog, -EINPROGRESS);
+@@ -1092,9 +1092,9 @@ static int sahara_sha_enqueue(struct ahash_request *req, int last)
+ rctx->first = 1;
+ }
+
+- mutex_lock(&dev->queue_mutex);
++ spin_lock_bh(&dev->queue_spinlock);
+ ret = crypto_enqueue_request(&dev->queue, &req->base);
+- mutex_unlock(&dev->queue_mutex);
++ spin_unlock_bh(&dev->queue_spinlock);
+
+ wake_up_process(dev->kthread);
+
+@@ -1449,7 +1449,7 @@ static int sahara_probe(struct platform_device *pdev)
+
+ crypto_init_queue(&dev->queue, SAHARA_QUEUE_LENGTH);
+
+- mutex_init(&dev->queue_mutex);
++ spin_lock_init(&dev->queue_spinlock);
+
+ dev_ptr = dev;
+
+--
+2.35.1
+
--- /dev/null
+From 81455d6027348db266a4e5a21c9581896b008b3a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 14:22:47 +0800
+Subject: dmaengine: hisilicon: Add multi-thread support for a DMA channel
+
+From: Jie Hai <haijie1@huawei.com>
+
+[ Upstream commit 2cbb95883c990d0002a77e13d3278913ab26ad79 ]
+
+When we get a DMA channel and try to use it in multiple threads it
+will cause oops and hanging the system.
+
+% echo 100 > /sys/module/dmatest/parameters/threads_per_chan
+% echo 100 > /sys/module/dmatest/parameters/iterations
+% echo 1 > /sys/module/dmatest/parameters/run
+[383493.327077] Unable to handle kernel paging request at virtual
+ address dead000000000108
+[383493.335103] Mem abort info:
+[383493.335103] ESR = 0x96000044
+[383493.335105] EC = 0x25: DABT (current EL), IL = 32 bits
+[383493.335107] SET = 0, FnV = 0
+[383493.335108] EA = 0, S1PTW = 0
+[383493.335109] FSC = 0x04: level 0 translation fault
+[383493.335110] Data abort info:
+[383493.335111] ISV = 0, ISS = 0x00000044
+[383493.364739] CM = 0, WnR = 1
+[383493.367793] [dead000000000108] address between user and kernel
+ address ranges
+[383493.375021] Internal error: Oops: 96000044 [#1] PREEMPT SMP
+[383493.437574] CPU: 63 PID: 27895 Comm: dma0chan0-copy2 Kdump:
+ loaded Tainted: GO 5.17.0-rc4+ #2
+[383493.457851] pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT
+ -SSBS BTYPE=--)
+[383493.465331] pc : vchan_tx_submit+0x64/0xa0
+[383493.469957] lr : vchan_tx_submit+0x34/0xa0
+
+This occurs because the transmission timed out, and that's due
+to data race. Each thread rewrite channels's descriptor as soon as
+device_issue_pending is called. It leads to the situation that
+the driver thinks that it uses the right descriptor in interrupt
+handler while channels's descriptor has been changed by other
+thread. The descriptor which in fact reported interrupt will not
+be handled any more, as well as its tx->callback.
+That's why timeout reports.
+
+With current fixes channels' descriptor changes it's value only
+when it has been used. A new descriptor is acquired from
+vc->desc_issued queue that is already filled with descriptors
+that are ready to be sent. Threads have no direct access to DMA
+channel descriptor. In case of channel's descriptor is busy, try
+to submit to HW again when a descriptor is completed. In this case,
+vc->desc_issued may be empty when hisi_dma_start_transfer is called,
+so delete error reporting on this. Now it is just possible to queue
+a descriptor for further processing.
+
+Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support")
+Signed-off-by: Jie Hai <haijie1@huawei.com>
+Acked-by: Zhou Wang <wangzhou1@hisilicon.com>
+Link: https://lore.kernel.org/r/20220830062251.52993-4-haijie1@huawei.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/hisi_dma.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c
+index 9e6ce3731ca5..df6be7ca340c 100644
+--- a/drivers/dma/hisi_dma.c
++++ b/drivers/dma/hisi_dma.c
+@@ -271,7 +271,6 @@ static void hisi_dma_start_transfer(struct hisi_dma_chan *chan)
+
+ vd = vchan_next_desc(&chan->vc);
+ if (!vd) {
+- dev_err(&hdma_dev->pdev->dev, "no issued task!\n");
+ chan->desc = NULL;
+ return;
+ }
+@@ -303,7 +302,7 @@ static void hisi_dma_issue_pending(struct dma_chan *c)
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+- if (vchan_issue_pending(&chan->vc))
++ if (vchan_issue_pending(&chan->vc) && !chan->desc)
+ hisi_dma_start_transfer(chan);
+
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+@@ -441,11 +440,10 @@ static irqreturn_t hisi_dma_irq(int irq, void *data)
+ chan->qp_num, chan->cq_head);
+ if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
+ vchan_cookie_complete(&desc->vd);
++ hisi_dma_start_transfer(chan);
+ } else {
+ dev_err(&hdma_dev->pdev->dev, "task error!\n");
+ }
+-
+- chan->desc = NULL;
+ }
+
+ spin_unlock(&chan->vc.lock);
+--
+2.35.1
+
--- /dev/null
+From b3c2d8c8c8f159a45134309e3359f14cb16c9538 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 14:22:45 +0800
+Subject: dmaengine: hisilicon: Disable channels when unregister hisi_dma
+
+From: Jie Hai <haijie1@huawei.com>
+
+[ Upstream commit e3bdaa04ada31f46d0586df83a2789b8913053c5 ]
+
+When hisi_dma is unloaded or unbinded, all of channels should be
+disabled. This patch disables DMA channels when driver is unloaded
+or unbinded.
+
+Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support")
+Signed-off-by: Jie Hai <haijie1@huawei.com>
+Acked-by: Zhou Wang <wangzhou1@hisilicon.com>
+Link: https://lore.kernel.org/r/20220830062251.52993-2-haijie1@huawei.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/hisi_dma.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c
+index f680e9b40bf7..70a0d784a6a3 100644
+--- a/drivers/dma/hisi_dma.c
++++ b/drivers/dma/hisi_dma.c
+@@ -180,7 +180,8 @@ static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
+ hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
+ }
+
+-static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan)
++static void hisi_dma_reset_or_disable_hw_chan(struct hisi_dma_chan *chan,
++ bool disable)
+ {
+ struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
+ u32 index = chan->qp_num, tmp;
+@@ -201,8 +202,11 @@ static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan)
+ hisi_dma_do_reset(hdma_dev, index);
+ hisi_dma_reset_qp_point(hdma_dev, index);
+ hisi_dma_pause_dma(hdma_dev, index, false);
+- hisi_dma_enable_dma(hdma_dev, index, true);
+- hisi_dma_unmask_irq(hdma_dev, index);
++
++ if (!disable) {
++ hisi_dma_enable_dma(hdma_dev, index, true);
++ hisi_dma_unmask_irq(hdma_dev, index);
++ }
+
+ ret = readl_relaxed_poll_timeout(hdma_dev->base +
+ HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
+@@ -218,7 +222,7 @@ static void hisi_dma_free_chan_resources(struct dma_chan *c)
+ struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
+ struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
+
+- hisi_dma_reset_hw_chan(chan);
++ hisi_dma_reset_or_disable_hw_chan(chan, false);
+ vchan_free_chan_resources(&chan->vc);
+
+ memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
+@@ -394,7 +398,7 @@ static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
+
+ static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
+ {
+- hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]);
++ hisi_dma_reset_or_disable_hw_chan(&hdma_dev->chan[qp_index], true);
+ }
+
+ static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev)
+--
+2.35.1
+
--- /dev/null
+From b7a102b549ee34aff14a404f8ab1b7dbd3216954 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 14:22:46 +0800
+Subject: dmaengine: hisilicon: Fix CQ head update
+
+From: Jie Hai <haijie1@huawei.com>
+
+[ Upstream commit 94477a79cf80e8ab55b68f14bc579a12ddea1e0b ]
+
+After completion of data transfer of one or multiple descriptors,
+the completion status and the current head pointer to submission
+queue are written into the CQ and interrupt can be generated to
+inform the software. In interrupt process CQ is read and cq_head
+is updated.
+
+hisi_dma_irq updates cq_head only when the completion status is
+success. When an abnormal interrupt reports, cq_head will not update
+which will cause subsequent interrupt processes read the error CQ
+and never report the correct status.
+
+This patch updates cq_head whenever CQ is accessed.
+
+Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support")
+Signed-off-by: Jie Hai <haijie1@huawei.com>
+Acked-by: Zhou Wang <wangzhou1@hisilicon.com>
+Link: https://lore.kernel.org/r/20220830062251.52993-3-haijie1@huawei.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/hisi_dma.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c
+index 70a0d784a6a3..9e6ce3731ca5 100644
+--- a/drivers/dma/hisi_dma.c
++++ b/drivers/dma/hisi_dma.c
+@@ -436,12 +436,10 @@ static irqreturn_t hisi_dma_irq(int irq, void *data)
+ desc = chan->desc;
+ cqe = chan->cq + chan->cq_head;
+ if (desc) {
++ chan->cq_head = (chan->cq_head + 1) % hdma_dev->chan_depth;
++ hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR,
++ chan->qp_num, chan->cq_head);
+ if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
+- chan->cq_head = (chan->cq_head + 1) %
+- hdma_dev->chan_depth;
+- hisi_dma_chan_write(hdma_dev->base,
+- HISI_DMA_CQ_HEAD_PTR, chan->qp_num,
+- chan->cq_head);
+ vchan_cookie_complete(&desc->vd);
+ } else {
+ dev_err(&hdma_dev->pdev->dev, "task error!\n");
+--
+2.35.1
+
--- /dev/null
+From 6e5dbef048a1b4e682849fe47e6cf44eccea3166 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 09:58:42 -0700
+Subject: dmaengine: ioat: stop mod_timer from resurrecting deleted timer in
+ __cleanup()
+
+From: Dave Jiang <dave.jiang@intel.com>
+
+[ Upstream commit 898ec89dbb55b8294695ad71694a0684e62b2a73 ]
+
+User reports observing timer event report channel halted but no error
+observed in CHANERR register. The driver finished self-test and released
+channel resources. Debug shows that __cleanup() can call
+mod_timer() after the timer has been deleted and thus resurrect the
+timer. While harmless, it causes suprious error message to be emitted.
+Use mod_timer_pending() call to prevent deleted timer from being
+resurrected.
+
+Fixes: 3372de5813e4 ("dmaengine: ioatdma: removal of dma_v3.c and relevant ioat3 references")
+Signed-off-by: Dave Jiang <dave.jiang@intel.com>
+Link: https://lore.kernel.org/r/166360672197.3851724.17040290563764838369.stgit@djiang5-desk3.ch.intel.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/ioat/dma.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
+index 37ff4ec7db76..e2070df6cad2 100644
+--- a/drivers/dma/ioat/dma.c
++++ b/drivers/dma/ioat/dma.c
+@@ -656,7 +656,7 @@ static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete)
+ if (active - i == 0) {
+ dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n",
+ __func__);
+- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
+ }
+
+ /* microsecond delay by sysfs variable per pending descriptor */
+@@ -682,7 +682,7 @@ static void ioat_cleanup(struct ioatdma_chan *ioat_chan)
+
+ if (chanerr &
+ (IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) {
+- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
+ ioat_eh(ioat_chan);
+ }
+ }
+@@ -879,7 +879,7 @@ static void check_active(struct ioatdma_chan *ioat_chan)
+ }
+
+ if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state))
+- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
+ }
+
+ static void ioat_reboot_chan(struct ioatdma_chan *ioat_chan)
+--
+2.35.1
+
--- /dev/null
+From 87d54edf887a1b85c705ae239b2901983022bf7c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 Aug 2022 11:18:35 +0530
+Subject: dmaengine: ti: k3-udma: Reset UDMA_CHAN_RT byte counters to prevent
+ overflow
+
+From: Vaishnav Achath <vaishnav.a@ti.com>
+
+[ Upstream commit 7c94dcfa8fcff2dba53915f1dabfee49a3df8b88 ]
+
+UDMA_CHAN_RT_*BCNT_REG stores the real-time channel bytecount statistics.
+These registers are 32-bit hardware counters and the driver uses these
+counters to monitor the operational progress status for a channel, when
+transferring more than 4GB of data it was observed that these counters
+overflow and completion calculation of a operation gets affected and the
+transfer hangs indefinitely.
+
+This commit adds changes to decrease the byte count for every complete
+transaction so that these registers never overflow and the proper byte
+count statistics is maintained for ongoing transaction by the RT counters.
+
+Earlier uc->bcnt used to maintain a count of the completed bytes at driver
+side, since the RT counters maintain the statistics of current transaction
+now, the maintenance of uc->bcnt is not necessary.
+
+Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
+Link: https://lore.kernel.org/r/20220802054835.19482-1-vaishnav.a@ti.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/ti/k3-udma.c | 25 +++++++++++++++++--------
+ 1 file changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
+index 041d8e32d630..75f2a0006c73 100644
+--- a/drivers/dma/ti/k3-udma.c
++++ b/drivers/dma/ti/k3-udma.c
+@@ -300,8 +300,6 @@ struct udma_chan {
+
+ struct udma_tx_drain tx_drain;
+
+- u32 bcnt; /* number of bytes completed since the start of the channel */
+-
+ /* Channel configuration parameters */
+ struct udma_chan_config config;
+
+@@ -757,6 +755,20 @@ static void udma_reset_rings(struct udma_chan *uc)
+ }
+ }
+
++static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val)
++{
++ if (uc->desc->dir == DMA_DEV_TO_MEM) {
++ udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
++ udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
++ udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
++ } else {
++ udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
++ udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
++ if (!uc->bchan)
++ udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
++ }
++}
++
+ static void udma_reset_counters(struct udma_chan *uc)
+ {
+ u32 val;
+@@ -790,8 +802,6 @@ static void udma_reset_counters(struct udma_chan *uc)
+ val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
+ udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
+ }
+-
+- uc->bcnt = 0;
+ }
+
+ static int udma_reset_chan(struct udma_chan *uc, bool hard)
+@@ -1115,7 +1125,7 @@ static void udma_check_tx_completion(struct work_struct *work)
+ if (uc->desc) {
+ struct udma_desc *d = uc->desc;
+
+- uc->bcnt += d->residue;
++ udma_decrement_byte_counters(uc, d->residue);
+ udma_start(uc);
+ vchan_cookie_complete(&d->vd);
+ break;
+@@ -1168,7 +1178,7 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data)
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ if (udma_is_desc_really_done(uc, d)) {
+- uc->bcnt += d->residue;
++ udma_decrement_byte_counters(uc, d->residue);
+ udma_start(uc);
+ vchan_cookie_complete(&d->vd);
+ } else {
+@@ -1204,7 +1214,7 @@ static irqreturn_t udma_udma_irq_handler(int irq, void *data)
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ /* TODO: figure out the real amount of data */
+- uc->bcnt += d->residue;
++ udma_decrement_byte_counters(uc, d->residue);
+ udma_start(uc);
+ vchan_cookie_complete(&d->vd);
+ }
+@@ -3811,7 +3821,6 @@ static enum dma_status udma_tx_status(struct dma_chan *chan,
+ bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ }
+
+- bcnt -= uc->bcnt;
+ if (bcnt && !(bcnt % uc->desc->residue))
+ residue = 0;
+ else
+--
+2.35.1
+
--- /dev/null
+From c11be10dc501d3dab1d310c31eab54d99b34ba0f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 14:22:47 +0300
+Subject: drivers: serial: jsm: fix some leaks in probe
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 1d5859ef229e381f4db38dce8ed58e4bf862006b ]
+
+This error path needs to unwind instead of just returning directly.
+
+Fixes: 03a8482c17dd ("drivers: serial: jsm: Enable support for Digi Classic adapters")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Link: https://lore.kernel.org/r/YyxFh1+lOeZ9WfKO@kili
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/jsm/jsm_driver.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/jsm/jsm_driver.c b/drivers/tty/serial/jsm/jsm_driver.c
+index 0ea799bf8dbb..417a5b6bffc3 100644
+--- a/drivers/tty/serial/jsm/jsm_driver.c
++++ b/drivers/tty/serial/jsm/jsm_driver.c
+@@ -211,7 +211,8 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+
+ break;
+ default:
+- return -ENXIO;
++ rc = -ENXIO;
++ goto out_kfree_brd;
+ }
+
+ rc = request_irq(brd->irq, brd->bd_ops->intr, IRQF_SHARED, "JSM", brd);
+--
+2.35.1
+
--- /dev/null
+From 6d15b9c041d3eb54917da6b57815a2827730074c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 15:01:46 -0400
+Subject: drm/amd/display: fix array-bounds error in
+ dc_stream_remove_writeback()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Hamza Mahfooz <hamza.mahfooz@amd.com>
+
+[ Upstream commit 5d8c3e836fc224dfe633e41f7f2856753b39a905 ]
+
+Address the following error:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function ‘dc_stream_remove_writeback’:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55: error: array subscript [0, 0] is outside array bounds of ‘struct dc_writeback_info[1]’ [-Werror=array-bounds]
+ 527 | stream->writeback_info[j] = stream->writeback_info[i];
+ | ~~~~~~~~~~~~~~~~~~~~~~^~~
+In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc.h:1269,
+ from ./drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:29,
+ from ./drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.h:29,
+ from drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:27:
+./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_stream.h:241:34: note: while referencing ‘writeback_info’
+ 241 | struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+ |
+
+Currently, we aren't checking to see if j remains within
+writeback_info[]'s bounds. So, add a check to make sure that we aren't
+overflowing the buffer.
+
+Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index f0f54f4d3d9b..1f1f3d3c8884 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -519,7 +519,7 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ }
+
+ /* remove writeback info for disabled writeback pipes from stream */
+- for (i = 0, j = 0; i < stream->num_wb_info; i++) {
++ for (i = 0, j = 0; i < stream->num_wb_info && j < MAX_DWB_PIPES; i++) {
+ if (stream->writeback_info[i].wb_enabled) {
+ if (i != j)
+ /* trim the array */
+--
+2.35.1
+
--- /dev/null
+From 2be7549049ddb476a5bac95fc4a939f00969aae1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Aug 2022 17:43:26 -0300
+Subject: drm/amd/display: fix overflow on MIN_I64 definition
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: David Gow <davidgow@google.com>
+
+[ Upstream commit 6ae0632d17759852c07e2d1e0a31c728eb6ba246 ]
+
+The definition of MIN_I64 in bw_fixed.c can cause gcc to whinge about
+integer overflow, because it is treated as a positive value, which is
+then negated. The temporary positive value is not necessarily
+representable.
+
+This causes the following warning:
+../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.c:30:19:
+warning: integer overflow in expression ‘-9223372036854775808’ of type
+‘long long int’ results in ‘-9223372036854775808’ [-Woverflow]
+ 30 | (int64_t)(-(1LL << 63))
+ | ^
+
+Writing out (-MAX_I64 - 1) works instead.
+
+Signed-off-by: David Gow <davidgow@google.com>
+Signed-off-by: Tales Aparecida <tales.aparecida@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
+index 6ca288fb5fb9..2d46bc527b21 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c
+@@ -26,12 +26,12 @@
+ #include "bw_fixed.h"
+
+
+-#define MIN_I64 \
+- (int64_t)(-(1LL << 63))
+-
+ #define MAX_I64 \
+ (int64_t)((1ULL << 63) - 1)
+
++#define MIN_I64 \
++ (-MAX_I64 - 1)
++
+ #define FRACTIONAL_PART_MASK \
+ ((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1)
+
+--
+2.35.1
+
--- /dev/null
+From 2ccb277ab632b237a25645c18f1affb6fabd7c97 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 18:07:59 -0400
+Subject: drm/amd/display: Remove interface for periodic interrupt 1
+
+From: Aric Cyr <aric.cyr@amd.com>
+
+[ Upstream commit 97d8d6f075bd8f988589be02b91f6fa644d0b0b8 ]
+
+[why]
+Only a single VLINE interrupt is available so interface should not
+expose the second one which is used by DMU firmware.
+
+[how]
+Remove references to periodic_interrupt1 and VLINE1 from DC interfaces.
+
+Reviewed-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +++------
+ drivers/gpu/drm/amd/display/dc/dc_stream.h | 6 ++--
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 ++++++-------------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +-
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 +----
+ 5 files changed, 18 insertions(+), 50 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 1bde9d4e82d4..6c9378208127 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2462,11 +2462,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ if (update->abm_level)
+ stream->abm_level = *update->abm_level;
+
+- if (update->periodic_interrupt0)
+- stream->periodic_interrupt0 = *update->periodic_interrupt0;
+-
+- if (update->periodic_interrupt1)
+- stream->periodic_interrupt1 = *update->periodic_interrupt1;
++ if (update->periodic_interrupt)
++ stream->periodic_interrupt = *update->periodic_interrupt;
+
+ if (update->gamut_remap)
+ stream->gamut_remap_matrix = *update->gamut_remap;
+@@ -2550,13 +2547,8 @@ static void commit_planes_do_stream_update(struct dc *dc,
+
+ if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
+
+- if (stream_update->periodic_interrupt0 &&
+- dc->hwss.setup_periodic_interrupt)
+- dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
+-
+- if (stream_update->periodic_interrupt1 &&
+- dc->hwss.setup_periodic_interrupt)
+- dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
++ if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
++ dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
+
+ if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
+ stream_update->vrr_infopacket ||
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index b8ebc1f09538..7644f0e747d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -193,8 +193,7 @@ struct dc_stream_state {
+ /* DMCU info */
+ unsigned int abm_level;
+
+- struct periodic_interrupt_config periodic_interrupt0;
+- struct periodic_interrupt_config periodic_interrupt1;
++ struct periodic_interrupt_config periodic_interrupt;
+
+ /* from core_stream struct */
+ struct dc_context *ctx;
+@@ -260,8 +259,7 @@ struct dc_stream_update {
+ struct dc_info_packet *hdr_static_metadata;
+ unsigned int *abm_level;
+
+- struct periodic_interrupt_config *periodic_interrupt0;
+- struct periodic_interrupt_config *periodic_interrupt1;
++ struct periodic_interrupt_config *periodic_interrupt;
+
+ struct dc_info_packet *vrr_infopacket;
+ struct dc_info_packet *vsc_infopacket;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 93f31e4aeecb..91ab4dbbe1a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -3517,7 +3517,7 @@ void dcn10_calc_vupdate_position(
+ {
+ const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
+ int vline_int_offset_from_vupdate =
+- pipe_ctx->stream->periodic_interrupt0.lines_offset;
++ pipe_ctx->stream->periodic_interrupt.lines_offset;
+ int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ int start_position;
+
+@@ -3542,18 +3542,10 @@ void dcn10_calc_vupdate_position(
+ static void dcn10_cal_vline_position(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+- enum vline_select vline,
+ uint32_t *start_line,
+ uint32_t *end_line)
+ {
+- enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
+-
+- if (vline == VLINE0)
+- ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
+- else if (vline == VLINE1)
+- ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
+-
+- switch (ref_point) {
++ switch (pipe_ctx->stream->periodic_interrupt.ref_point) {
+ case START_V_UPDATE:
+ dcn10_calc_vupdate_position(
+ dc,
+@@ -3562,7 +3554,9 @@ static void dcn10_cal_vline_position(
+ end_line);
+ break;
+ case START_V_SYNC:
+- // Suppose to do nothing because vsync is 0;
++ // vsync is line 0 so start_line is just the requested line offset
++ *start_line = pipe_ctx->stream->periodic_interrupt.lines_offset;
++ *end_line = *start_line + 2;
+ break;
+ default:
+ ASSERT(0);
+@@ -3572,24 +3566,15 @@ static void dcn10_cal_vline_position(
+
+ void dcn10_setup_periodic_interrupt(
+ struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- enum vline_select vline)
++ struct pipe_ctx *pipe_ctx)
+ {
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
++ uint32_t start_line = 0;
++ uint32_t end_line = 0;
+
+- if (vline == VLINE0) {
+- uint32_t start_line = 0;
+- uint32_t end_line = 0;
++ dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);
+
+- dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
+-
+- tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
+-
+- } else if (vline == VLINE1) {
+- pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
+- tg,
+- pipe_ctx->stream->periodic_interrupt1.lines_offset);
+- }
++ tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
+ }
+
+ void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+index 9ae07c77fdc0..0ef7bf7ddb75 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+@@ -175,8 +175,7 @@ void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
+ void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
+ void dcn10_setup_periodic_interrupt(
+ struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- enum vline_select vline);
++ struct pipe_ctx *pipe_ctx);
+ enum dc_status dcn10_set_clock(struct dc *dc,
+ enum dc_clock_type clock_type,
+ uint32_t clk_khz,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index ad5f2adcc40d..c8427d738c87 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -32,11 +32,6 @@
+ #include "inc/hw/link_encoder.h"
+ #include "core_status.h"
+
+-enum vline_select {
+- VLINE0,
+- VLINE1
+-};
+-
+ struct pipe_ctx;
+ struct dc_state;
+ struct dc_stream_status;
+@@ -115,8 +110,7 @@ struct hw_sequencer_funcs {
+ int group_index, int group_size,
+ struct pipe_ctx *grouped_pipes[]);
+ void (*setup_periodic_interrupt)(struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- enum vline_select vline);
++ struct pipe_ctx *pipe_ctx);
+ void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+ struct dc_crtc_timing_adjust adjust);
+ void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
+--
+2.35.1
+
--- /dev/null
+From dbab66e2852eb810a1866fae01c5825e46a2d0a4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 16:57:54 +0800
+Subject: drm/amdgpu: add missing pci_disable_device() in
+ amdgpu_pmops_runtime_resume()
+
+From: Yang Yingliang <yangyingliang@huawei.com>
+
+[ Upstream commit 6b11af6d1c8f5d4135332bb932baaa06e511173d ]
+
+Add missing pci_disable_device() if amdgpu_device_resume() fails.
+
+Fixes: 8e4d5d43cc6c ("drm/amdgpu: Handling of amdgpu_device_resume return value for graceful teardown")
+Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index f65b4b233ffb..28dea2eb61c7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -2415,8 +2415,11 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ amdgpu_device_baco_exit(drm_dev);
+ }
+ ret = amdgpu_device_resume(drm_dev, false);
+- if (ret)
++ if (ret) {
++ if (amdgpu_device_supports_px(drm_dev))
++ pci_disable_device(pdev);
+ return ret;
++ }
+
+ if (amdgpu_device_supports_px(drm_dev))
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
+--
+2.35.1
+
--- /dev/null
+From 2bb9ec6d42c2fd64bb542442664506244e7534fd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 17:24:53 +0800
+Subject: drm/amdgpu: fix initial connector audio value
+
+From: hongao <hongao@uniontech.com>
+
+[ Upstream commit 4bb71fce58f30df3f251118291d6b0187ce531e6 ]
+
+This got lost somewhere along the way, This fixes
+audio not working until set_property was called.
+
+Signed-off-by: hongao <hongao@uniontech.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+index a09876bb7ec8..4b1d62ebf8dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -1671,10 +1671,12 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ adev->mode_info.dither_property,
+ AMDGPU_FMT_DITHER_DISABLE);
+
+- if (amdgpu_audio != 0)
++ if (amdgpu_audio != 0) {
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.audio_property,
+ AMDGPU_AUDIO_AUTO);
++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
++ }
+
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = true;
+@@ -1796,6 +1798,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.audio_property,
+ AMDGPU_AUDIO_AUTO);
++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
+ }
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.dither_property,
+@@ -1849,6 +1852,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.audio_property,
+ AMDGPU_AUDIO_AUTO);
++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
+ }
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.dither_property,
+@@ -1899,6 +1903,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.audio_property,
+ AMDGPU_AUDIO_AUTO);
++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
+ }
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.dither_property,
+--
+2.35.1
+
--- /dev/null
+From 3944dbec41a861c3b04b2046e181d9ead470d4af Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 19:34:32 -0300
+Subject: drm/amdgpu: Fix memory leak in hpd_rx_irq_create_workqueue()
+
+From: Rafael Mendonca <rafaelmendsr@gmail.com>
+
+[ Upstream commit 7136f956c73c4ba50bfeb61653dfd6a9669ea915 ]
+
+If construction of the array of work queues to handle hpd_rx_irq offload
+work fails, we need to unwind. Destroy all the created workqueues and
+the allocated memory for the hpd_rx_irq_offload_work_queue struct array.
+
+Fixes: 8e794421bc98 ("drm/amd/display: Fork thread to offload work of hpd_rx_irq")
+Signed-off-by: Rafael Mendonca <rafaelmendsr@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 9b815950b860..484c28919271 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1307,13 +1307,21 @@ static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct
+
+ if (hpd_rx_offload_wq[i].wq == NULL) {
+ DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
+- return NULL;
++ goto out_err;
+ }
+
+ spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
+ }
+
+ return hpd_rx_offload_wq;
++
++out_err:
++ for (i = 0; i < max_caps; i++) {
++ if (hpd_rx_offload_wq[i].wq)
++ destroy_workqueue(hpd_rx_offload_wq[i].wq);
++ }
++ kfree(hpd_rx_offload_wq);
++ return NULL;
+ }
+
+ struct amdgpu_stutter_quirk {
+--
+2.35.1
+
--- /dev/null
+From 11d1a7e4b256741cca9cb40c0cfbb4cde2bc1cc3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 16:29:57 +0200
+Subject: drm/bochs: fix blanking
+
+From: Gerd Hoffmann <kraxel@redhat.com>
+
+[ Upstream commit e740ceb53e4579a7a4063712cebecac3c343b189 ]
+
+VGA_IS1_RC is the color mode register (VGA_IS1_RM the one for monochrome
+mode, note C vs. M at the end). So when using VGA_IS1_RC make sure the
+vga device is actually in color mode and set the corresponding bit in the
+misc register.
+
+Reproducible when booting VMs in UEFI mode with some edk2 versions (edk2
+fix is on the way too). Doesn't happen in BIOS mode because in that
+case the vgabios already flips the bit.
+
+Fixes: 250e743915d4 ("drm/bochs: Add screen blanking support")
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+Link: http://patchwork.freedesktop.org/patch/msgid/20220906142957.2763577-1-kraxel@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/tiny/bochs.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/tiny/bochs.c b/drivers/gpu/drm/tiny/bochs.c
+index 73415fa9ae0f..eb8116ff0d90 100644
+--- a/drivers/gpu/drm/tiny/bochs.c
++++ b/drivers/gpu/drm/tiny/bochs.c
+@@ -305,6 +305,8 @@ static void bochs_hw_fini(struct drm_device *dev)
+ static void bochs_hw_blank(struct bochs_device *bochs, bool blank)
+ {
+ DRM_DEBUG_DRIVER("hw_blank %d\n", blank);
++ /* enable color bit (so VGA_IS1_RC access works) */
++ bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR);
+ /* discard ar_flip_flop */
+ (void)bochs_vga_readb(bochs, VGA_IS1_RC);
+ /* blank or unblank; we need only update index and set 0x20 */
+--
+2.35.1
+
--- /dev/null
+From 8e2d3f0fc3531d4d30fa925f4843ee5c5700b726 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 12 Jun 2022 16:48:53 +0200
+Subject: drm: bridge: adv7511: fix CEC power down control register offset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alvin Šipraga <alsi@bang-olufsen.dk>
+
+[ Upstream commit 1d22b6033ea113a4c3850dfa2c0770885c81aec8 ]
+
+The ADV7511_REG_CEC_CTRL = 0xE2 register is part of the main register
+map - not the CEC register map. As such, we shouldn't apply an offset to
+the register address. Doing so will cause us to address a bogus register
+for chips with a CEC register map offset (e.g. ADV7533).
+
+Fixes: 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support")
+Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
+Reviewed-by: Robert Foss <robert.foss@linaro.org>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220612144854.2223873-2-alvin@pqrs.dk
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511.h | 5 +----
+ drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 4 ++--
+ 2 files changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+index 1b00dfda6e0d..aeeb09a27202 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+@@ -387,10 +387,7 @@ void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
+ #else
+ static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
+ {
+- unsigned int offset = adv7511->type == ADV7533 ?
+- ADV7533_REG_CEC_OFFSET : 0;
+-
+- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
+ ADV7511_CEC_CTRL_POWER_DOWN);
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+index a20a45c0b353..ddd1305b82b2 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+@@ -316,7 +316,7 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
+ goto err_cec_alloc;
+ }
+
+- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, 0);
+ /* cec soft reset */
+ regmap_write(adv7511->regmap_cec,
+ ADV7511_REG_CEC_SOFT_RESET + offset, 0x01);
+@@ -343,7 +343,7 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
+ dev_info(dev, "Initializing CEC failed with error %d, disabling CEC\n",
+ ret);
+ err_cec_parse_dt:
+- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
+ ADV7511_CEC_CTRL_POWER_DOWN);
+ return ret == -EPROBE_DEFER ? ret : 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From c488921cfbbc76ea19500fa3f72550fda4fb028e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 12 Jun 2022 16:48:54 +0200
+Subject: drm: bridge: adv7511: unregister cec i2c device after cec adapter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alvin Šipraga <alsi@bang-olufsen.dk>
+
+[ Upstream commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f ]
+
+cec_unregister_adapter() assumes that the underlying adapter ops are
+callable. For example, if the CEC adapter currently has a valid physical
+address, then the unregistration procedure will invalidate the physical
+address by setting it to f.f.f.f. Whence the following kernel oops
+observed after removing the adv7511 module:
+
+ Unable to handle kernel execution of user memory at virtual address 0000000000000000
+ Internal error: Oops: 86000004 [#1] PREEMPT_RT SMP
+ Call trace:
+ 0x0
+ adv7511_cec_adap_log_addr+0x1ac/0x1c8 [adv7511]
+ cec_adap_unconfigure+0x44/0x90 [cec]
+ __cec_s_phys_addr.part.0+0x68/0x230 [cec]
+ __cec_s_phys_addr+0x40/0x50 [cec]
+ cec_unregister_adapter+0xb4/0x118 [cec]
+ adv7511_remove+0x60/0x90 [adv7511]
+ i2c_device_remove+0x34/0xe0
+ device_release_driver_internal+0x114/0x1f0
+ driver_detach+0x54/0xe0
+ bus_remove_driver+0x60/0xd8
+ driver_unregister+0x34/0x60
+ i2c_del_driver+0x2c/0x68
+ adv7511_exit+0x1c/0x67c [adv7511]
+ __arm64_sys_delete_module+0x154/0x288
+ invoke_syscall+0x48/0x100
+ el0_svc_common.constprop.0+0x48/0xe8
+ do_el0_svc+0x28/0x88
+ el0_svc+0x1c/0x50
+ el0t_64_sync_handler+0xa8/0xb0
+ el0t_64_sync+0x15c/0x160
+ Code: bad PC value
+ ---[ end trace 0000000000000000 ]---
+
+Protect against this scenario by unregistering i2c_cec after
+unregistering the CEC adapter. Duly disable the CEC clock afterwards
+too.
+
+Fixes: 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support")
+Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
+Reviewed-by: Robert Foss <robert.foss@linaro.org>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220612144854.2223873-3-alvin@pqrs.dk
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 7e3f6633f255..3dc551d223d6 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -1326,8 +1326,6 @@ static int adv7511_remove(struct i2c_client *i2c)
+
+ if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
+ adv7533_detach_dsi(adv7511);
+- i2c_unregister_device(adv7511->i2c_cec);
+- clk_disable_unprepare(adv7511->cec_clk);
+
+ adv7511_uninit_regulators(adv7511);
+
+@@ -1336,6 +1334,8 @@ static int adv7511_remove(struct i2c_client *i2c)
+ adv7511_audio_exit(adv7511);
+
+ cec_unregister_adapter(adv7511->cec_adap);
++ i2c_unregister_device(adv7511->i2c_cec);
++ clk_disable_unprepare(adv7511->cec_clk);
+
+ i2c_unregister_device(adv7511->i2c_packet);
+ i2c_unregister_device(adv7511->i2c_edid);
+--
+2.35.1
+
--- /dev/null
+From d49713b3b1fd127a5fcb6ed093e365d555e6f245 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Jul 2022 13:55:40 +0300
+Subject: drm/bridge: Avoid uninitialized variable warning
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 7d1202738efda60155d98b370b3c70d336be0eea ]
+
+This code works, but technically it uses "num_in_bus_fmts" before it
+has been initialized so it leads to static checker warnings and probably
+KMEMsan warnings at run time. Initialize the variable to zero to
+silence the warning.
+
+Fixes: f32df58acc68 ("drm/bridge: Add the necessary bits to support bus format negotiation")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+Link: https://patchwork.freedesktop.org/patch/msgid/YrrIs3hoGcPVmXc5@kili
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_bridge.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
+index 7ee29f073857..78bc315b0b73 100644
+--- a/drivers/gpu/drm/drm_bridge.c
++++ b/drivers/gpu/drm/drm_bridge.c
+@@ -762,8 +762,8 @@ static int select_bus_fmt_recursive(struct drm_bridge *first_bridge,
+ struct drm_connector_state *conn_state,
+ u32 out_bus_fmt)
+ {
++ unsigned int i, num_in_bus_fmts = 0;
+ struct drm_bridge_state *cur_state;
+- unsigned int num_in_bus_fmts, i;
+ struct drm_bridge *prev_bridge;
+ u32 *in_bus_fmts;
+ int ret;
+@@ -884,7 +884,7 @@ drm_atomic_bridge_chain_select_bus_fmts(struct drm_bridge *bridge,
+ struct drm_connector *conn = conn_state->connector;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_bridge_state *last_bridge_state;
+- unsigned int i, num_out_bus_fmts;
++ unsigned int i, num_out_bus_fmts = 0;
+ struct drm_bridge *last_bridge;
+ u32 *out_bus_fmts;
+ int ret = 0;
+--
+2.35.1
+
--- /dev/null
+From c31a6899a0265e5443a22a0a6b9373dd6206cd60 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 20:57:33 +0200
+Subject: drm: bridge: dw_hdmi: only trigger hotplug event on link change
+
+From: Lucas Stach <l.stach@pengutronix.de>
+
+[ Upstream commit da09daf881082266e4075657fac53c7966de8e4d ]
+
+There are two events that signal a real change of the link state: HPD going
+high means the sink is newly connected or wants the source to re-read the
+EDID, RX sense going low is a indication that the link has been disconnected.
+
+Ignore the other two events that also trigger interrupts, but don't need
+immediate attention: HPD going low does not necessarily mean the link has
+been lost and should not trigger a immediate read of the status. RX sense
+going high also does not require a detect cycle, as HPD going high is the
+right point in time to read the EDID.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> (v1)
+Reviewed-by: Robert Foss <robert.foss@linaro.org>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220826185733.3213248-1-l.stach@pengutronix.de
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 25d58dcfc87e..d3129a3e6ab7 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2970,6 +2970,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ {
+ struct dw_hdmi *hdmi = dev_id;
+ u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
++ enum drm_connector_status status = connector_status_unknown;
+
+ intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
+ phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
+@@ -3008,13 +3009,15 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
+ mutex_unlock(&hdmi->cec_notifier_mutex);
+ }
+- }
+
+- if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
+- enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD
+- ? connector_status_connected
+- : connector_status_disconnected;
++ if (phy_stat & HDMI_PHY_HPD)
++ status = connector_status_connected;
++
++ if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE)))
++ status = connector_status_disconnected;
++ }
+
++ if (status != connector_status_unknown) {
+ dev_dbg(hdmi->dev, "EVENT=%s\n",
+ status == connector_status_connected ?
+ "plugin" : "plugout");
+--
+2.35.1
+
--- /dev/null
+From 5a87f43b8ecc9b651117623fb1ba2306b28c47bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 15:34:50 +0800
+Subject: drm/bridge: megachips: Fix a null pointer dereference bug
+
+From: Zheyu Ma <zheyuma97@gmail.com>
+
+[ Upstream commit 1ff673333d46d2c1b053ebd0c1c7c7c79e36943e ]
+
+When removing the module we will get the following warning:
+
+[ 31.911505] i2c-core: driver [stdp2690-ge-b850v3-fw] unregistered
+[ 31.912484] general protection fault, probably for non-canonical address 0xdffffc0000000001: 0000 [#1] PREEMPT SMP KASAN PTI
+[ 31.913338] KASAN: null-ptr-deref in range [0x0000000000000008-0x000000000000000f]
+[ 31.915280] RIP: 0010:drm_bridge_remove+0x97/0x130
+[ 31.921825] Call Trace:
+[ 31.922533] stdp4028_ge_b850v3_fw_remove+0x34/0x60 [megachips_stdpxxxx_ge_b850v3_fw]
+[ 31.923139] i2c_device_remove+0x181/0x1f0
+
+The two bridges (stdp2690, stdp4028) do not probe at the same time, so
+the driver does not call ge_b850v3_resgiter() when probing, causing the
+driver to try to remove the object that has not been initialized.
+
+Fix this by checking whether both the bridges are probed.
+
+Fixes: 11632d4aa2b3 ("drm/bridge: megachips: Ensure both bridges are probed before registration")
+Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220830073450.1897020-1-zheyuma97@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
+index cce98bf2a4e7..72248a565579 100644
+--- a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
++++ b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
+@@ -296,7 +296,9 @@ static void ge_b850v3_lvds_remove(void)
+ * This check is to avoid both the drivers
+ * removing the bridge in their remove() function
+ */
+- if (!ge_b850v3_lvds_ptr)
++ if (!ge_b850v3_lvds_ptr ||
++ !ge_b850v3_lvds_ptr->stdp2690_i2c ||
++ !ge_b850v3_lvds_ptr->stdp4028_i2c)
+ goto out;
+
+ drm_bridge_remove(&ge_b850v3_lvds_ptr->bridge);
+--
+2.35.1
+
--- /dev/null
+From 2d9eb1483129ca84e2f02222ef920c57bf86b378 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Sep 2021 11:06:17 -0700
+Subject: drm/bridge: parade-ps8640: Add support for AUX channel
+
+From: Philip Chen <philipchen@chromium.org>
+
+[ Upstream commit 13afcdd7277eff9ab5c92dc0d8d21335d132ab2f ]
+
+Implement the first version of AUX support, which will be useful as
+we expand the driver to support varied use cases.
+
+Signed-off-by: Philip Chen <philipchen@chromium.org>
+Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+[dianders: whitespace fixes reported by dim apply-branch]
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20210921110556.v6.2.I1d6ea362dc76efa77cca2b46253d31b7651eaf17@changeid
+Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/parade-ps8640.c | 180 ++++++++++++++++++++++++-
+ 1 file changed, 179 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
+index 88c9f3404ac1..43afa848a36a 100644
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -13,11 +13,36 @@
+ #include <linux/regulator/consumer.h>
+
+ #include <drm/drm_bridge.h>
++#include <drm/drm_dp_helper.h>
+ #include <drm/drm_mipi_dsi.h>
+ #include <drm/drm_of.h>
+ #include <drm/drm_panel.h>
+ #include <drm/drm_print.h>
+
++#define PAGE0_AUXCH_CFG3 0x76
++#define AUXCH_CFG3_RESET 0xff
++#define PAGE0_SWAUX_ADDR_7_0 0x7d
++#define PAGE0_SWAUX_ADDR_15_8 0x7e
++#define PAGE0_SWAUX_ADDR_23_16 0x7f
++#define SWAUX_ADDR_MASK GENMASK(19, 0)
++#define PAGE0_SWAUX_LENGTH 0x80
++#define SWAUX_LENGTH_MASK GENMASK(3, 0)
++#define SWAUX_NO_PAYLOAD BIT(7)
++#define PAGE0_SWAUX_WDATA 0x81
++#define PAGE0_SWAUX_RDATA 0x82
++#define PAGE0_SWAUX_CTRL 0x83
++#define SWAUX_SEND BIT(0)
++#define PAGE0_SWAUX_STATUS 0x84
++#define SWAUX_M_MASK GENMASK(4, 0)
++#define SWAUX_STATUS_MASK GENMASK(7, 5)
++#define SWAUX_STATUS_NACK (0x1 << 5)
++#define SWAUX_STATUS_DEFER (0x2 << 5)
++#define SWAUX_STATUS_ACKM (0x3 << 5)
++#define SWAUX_STATUS_INVALID (0x4 << 5)
++#define SWAUX_STATUS_I2C_NACK (0x5 << 5)
++#define SWAUX_STATUS_I2C_DEFER (0x6 << 5)
++#define SWAUX_STATUS_TIMEOUT (0x7 << 5)
++
+ #define PAGE2_GPIO_H 0xa7
+ #define PS_GPIO9 BIT(1)
+ #define PAGE2_I2C_BYPASS 0xea
+@@ -66,6 +91,7 @@ enum ps8640_vdo_control {
+ struct ps8640 {
+ struct drm_bridge bridge;
+ struct drm_bridge *panel_bridge;
++ struct drm_dp_aux aux;
+ struct mipi_dsi_device *dsi;
+ struct i2c_client *page[MAX_DEVS];
+ struct regmap *regmap[MAX_DEVS];
+@@ -115,6 +141,137 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+ return container_of(e, struct ps8640, bridge);
+ }
+
++static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
++{
++ return container_of(aux, struct ps8640, aux);
++}
++
++static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
++ struct drm_dp_aux_msg *msg)
++{
++ struct ps8640 *ps_bridge = aux_to_ps8640(aux);
++ struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
++ unsigned int len = msg->size;
++ unsigned int data;
++ unsigned int base;
++ int ret;
++ u8 request = msg->request &
++ ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
++ u8 *buf = msg->buffer;
++ u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
++ u8 i;
++ bool is_native_aux = false;
++
++ if (len > DP_AUX_MAX_PAYLOAD_BYTES)
++ return -EINVAL;
++
++ if (msg->address & ~SWAUX_ADDR_MASK)
++ return -EINVAL;
++
++ switch (request) {
++ case DP_AUX_NATIVE_WRITE:
++ case DP_AUX_NATIVE_READ:
++ is_native_aux = true;
++ fallthrough;
++ case DP_AUX_I2C_WRITE:
++ case DP_AUX_I2C_READ:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
++ if (ret) {
++ DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
++ ret);
++ return ret;
++ }
++
++ /* Assume it's good */
++ msg->reply = 0;
++
++ base = PAGE0_SWAUX_ADDR_7_0;
++ addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
++ addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
++ addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
++ (msg->request << 4);
++ addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
++ ((len - 1) & SWAUX_LENGTH_MASK);
++
++ regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
++ ARRAY_SIZE(addr_len));
++
++ if (len && (request == DP_AUX_NATIVE_WRITE ||
++ request == DP_AUX_I2C_WRITE)) {
++ /* Write to the internal FIFO buffer */
++ for (i = 0; i < len; i++) {
++ ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
++ if (ret) {
++ DRM_DEV_ERROR(dev,
++ "failed to write WDATA: %d\n",
++ ret);
++ return ret;
++ }
++ }
++ }
++
++ regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
++
++ /* Zero delay loop because i2c transactions are slow already */
++ regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
++ !(data & SWAUX_SEND), 0, 50 * 1000);
++
++ regmap_read(map, PAGE0_SWAUX_STATUS, &data);
++ if (ret) {
++ DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
++ ret);
++ return ret;
++ }
++
++ switch (data & SWAUX_STATUS_MASK) {
++ /* Ignore the DEFER cases as they are already handled in hardware */
++ case SWAUX_STATUS_NACK:
++ case SWAUX_STATUS_I2C_NACK:
++ /*
++ * The programming guide is not clear about whether a I2C NACK
++ * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
++ * we handle both cases together.
++ */
++ if (is_native_aux)
++ msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
++ else
++ msg->reply |= DP_AUX_I2C_REPLY_NACK;
++
++ fallthrough;
++ case SWAUX_STATUS_ACKM:
++ len = data & SWAUX_M_MASK;
++ break;
++ case SWAUX_STATUS_INVALID:
++ return -EOPNOTSUPP;
++ case SWAUX_STATUS_TIMEOUT:
++ return -ETIMEDOUT;
++ }
++
++ if (len && (request == DP_AUX_NATIVE_READ ||
++ request == DP_AUX_I2C_READ)) {
++ /* Read from the internal FIFO buffer */
++ for (i = 0; i < len; i++) {
++ ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
++ if (ret) {
++ DRM_DEV_ERROR(dev,
++ "failed to read RDATA: %d\n",
++ ret);
++ return ret;
++ }
++
++ buf[i] = data;
++ }
++ }
++
++ return len;
++}
++
+ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
+ const enum ps8640_vdo_control ctrl)
+ {
+@@ -284,18 +441,33 @@ static int ps8640_bridge_attach(struct drm_bridge *bridge,
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = DP_NUM_LANES;
+ ret = mipi_dsi_attach(dsi);
+- if (ret)
++ if (ret) {
++ dev_err(dev, "failed to attach dsi device: %d\n", ret);
+ goto err_dsi_attach;
++ }
++
++ ret = drm_dp_aux_register(&ps_bridge->aux);
++ if (ret) {
++ dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
++ goto err_aux_register;
++ }
+
+ /* Attach the panel-bridge to the dsi bridge */
+ return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
+ &ps_bridge->bridge, flags);
+
++err_aux_register:
++ mipi_dsi_detach(dsi);
+ err_dsi_attach:
+ mipi_dsi_device_unregister(dsi);
+ return ret;
+ }
+
++static void ps8640_bridge_detach(struct drm_bridge *bridge)
++{
++ drm_dp_aux_unregister(&bridge_to_ps8640(bridge)->aux);
++}
++
+ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+ {
+@@ -332,6 +504,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
+
+ static const struct drm_bridge_funcs ps8640_bridge_funcs = {
+ .attach = ps8640_bridge_attach,
++ .detach = ps8640_bridge_detach,
+ .get_edid = ps8640_bridge_get_edid,
+ .post_disable = ps8640_post_disable,
+ .pre_enable = ps8640_pre_enable,
+@@ -407,6 +580,11 @@ static int ps8640_probe(struct i2c_client *client)
+
+ i2c_set_clientdata(client, ps_bridge);
+
++ ps_bridge->aux.name = "parade-ps8640-aux";
++ ps_bridge->aux.dev = dev;
++ ps_bridge->aux.transfer = ps8640_aux_transfer;
++ drm_dp_aux_init(&ps_bridge->aux);
++
+ drm_bridge_add(&ps_bridge->bridge);
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From f911e7903705123552b722cc5f997dc674f91bfe Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Oct 2021 10:58:10 -0700
+Subject: drm/bridge: parade-ps8640: Enable runtime power management
+
+From: Philip Chen <philipchen@chromium.org>
+
+[ Upstream commit 826cff3f7ebba460d3db61f135798ce76b0d26ed ]
+
+Fit ps8640 driver into runtime power management framework:
+
+First, break _poweron() to 3 parts: (1) turn on power and wait for
+ps8640's internal MCU to finish init (2) check panel HPD (which is
+proxied by GPIO9) (3) the other configs. As runtime_resume() can be
+called before panel is powered, we only add (1) to _resume() and leave
+(2)(3) to _pre_enable(). We also add (2) to _aux_transfer() as we want
+to ensure panel HPD is asserted before we start AUX CH transactions.
+
+Second, the original driver has a mysterious delay of 50 ms between (2)
+and (3). Since Parade's support can't explain what the delay is for,
+and we don't see removing the delay break any boards at hand, remove
+the delay to fit into this driver change.
+
+In addition, rename "powered" to "pre_enabled" and don't check for it
+in the pm_runtime calls. The pm_runtime calls are already refcounted
+so there's no reason to check there. The other user of "powered",
+_get_edid(), only cares if pre_enable() has already been called.
+
+Lastly, change some existing DRM_...() logging to dev_...() along the
+way, since DRM_...() seem to be deprecated in [1].
+
+[1] https://patchwork.freedesktop.org/patch/454760/
+
+Signed-off-by: Philip Chen <philipchen@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+[dianders: fixed whitespace warning reported by dim tool]
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20211028105754.v5.1.I828f5db745535fb7e36e8ffdd62d546f6d08b6d1@changeid
+Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/parade-ps8640.c | 190 ++++++++++++++++---------
+ 1 file changed, 119 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
+index 43afa848a36a..52f2ea6fcb26 100644
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -9,6 +9,7 @@
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+ #include <linux/of_graph.h>
++#include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+
+@@ -98,7 +99,7 @@ struct ps8640 {
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_powerdown;
+- bool powered;
++ bool pre_enabled;
+ };
+
+ static const struct regmap_config ps8640_regmap_config[] = {
+@@ -146,8 +147,29 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
+ return container_of(aux, struct ps8640, aux);
+ }
+
+-static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
+- struct drm_dp_aux_msg *msg)
++static int ps8640_ensure_hpd(struct ps8640 *ps_bridge)
++{
++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
++ struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev;
++ int status;
++ int ret;
++
++ /*
++ * Apparently something about the firmware in the chip signals that
++ * HPD goes high by reporting GPIO9 as high (even though HPD isn't
++ * actually connected to GPIO9).
++ */
++ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
++ status & PS_GPIO9, 20 * 1000, 200 * 1000);
++
++ if (ret < 0)
++ dev_warn(dev, "HPD didn't go high: %d\n", ret);
++
++ return ret;
++}
++
++static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
++ struct drm_dp_aux_msg *msg)
+ {
+ struct ps8640 *ps_bridge = aux_to_ps8640(aux);
+ struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
+@@ -272,38 +294,49 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
+ return len;
+ }
+
+-static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
+- const enum ps8640_vdo_control ctrl)
++static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
++ struct drm_dp_aux_msg *msg)
++{
++ struct ps8640 *ps_bridge = aux_to_ps8640(aux);
++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
++ int ret;
++
++ pm_runtime_get_sync(dev);
++ ret = ps8640_ensure_hpd(ps_bridge);
++ if (!ret)
++ ret = ps8640_aux_transfer_msg(aux, msg);
++ pm_runtime_mark_last_busy(dev);
++ pm_runtime_put_autosuspend(dev);
++
++ return ret;
++}
++
++static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
++ const enum ps8640_vdo_control ctrl)
+ {
+ struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
++ struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
+ u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
+ int ret;
+
+ ret = regmap_bulk_write(map, PAGE3_SET_ADD,
+ vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+
+- if (ret < 0) {
+- DRM_ERROR("failed to %sable VDO: %d\n",
+- ctrl == ENABLE ? "en" : "dis", ret);
+- return ret;
+- }
+-
+- return 0;
++ if (ret < 0)
++ dev_err(dev, "failed to %sable VDO: %d\n",
++ ctrl == ENABLE ? "en" : "dis", ret);
+ }
+
+-static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
++static int __maybe_unused ps8640_resume(struct device *dev)
+ {
+- struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
+- int ret, status;
+-
+- if (ps_bridge->powered)
+- return;
++ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
++ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret < 0) {
+- DRM_ERROR("cannot enable regulators %d\n", ret);
+- return;
++ dev_err(dev, "cannot enable regulators %d\n", ret);
++ return ret;
+ }
+
+ gpiod_set_value(ps_bridge->gpio_powerdown, 0);
+@@ -312,86 +345,78 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+
+ /*
+- * Wait for the ps8640 embedded MCU to be ready
+- * First wait 200ms and then check the MCU ready flag every 20ms
++ * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
++ * this is truly necessary since the MCU will already signal that
++ * things are "good to go" by signaling HPD on "gpio 9". See
++ * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in
++ * case.
+ */
+ msleep(200);
+
+- ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
+- status & PS_GPIO9, 20 * 1000, 200 * 1000);
+-
+- if (ret < 0) {
+- DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret);
+- goto err_regulators_disable;
+- }
+-
+- msleep(50);
+-
+- /*
+- * The Manufacturer Command Set (MCS) is a device dependent interface
+- * intended for factory programming of the display module default
+- * parameters. Once the display module is configured, the MCS shall be
+- * disabled by the manufacturer. Once disabled, all MCS commands are
+- * ignored by the display interface.
+- */
+-
+- ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
+- if (ret < 0) {
+- DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret);
+- goto err_regulators_disable;
+- }
+-
+- /* Switch access edp panel's edid through i2c */
+- ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+- if (ret < 0) {
+- DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret);
+- goto err_regulators_disable;
+- }
+-
+- ps_bridge->powered = true;
+-
+- return;
+-
+-err_regulators_disable:
+- regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+- ps_bridge->supplies);
++ return 0;
+ }
+
+-static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge)
++static int __maybe_unused ps8640_suspend(struct device *dev)
+ {
++ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ int ret;
+
+- if (!ps_bridge->powered)
+- return;
+-
+ gpiod_set_value(ps_bridge->gpio_reset, 1);
+ gpiod_set_value(ps_bridge->gpio_powerdown, 1);
+ ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret < 0)
+- DRM_ERROR("cannot disable regulators %d\n", ret);
++ dev_err(dev, "cannot disable regulators %d\n", ret);
+
+- ps_bridge->powered = false;
++ return ret;
+ }
+
++static const struct dev_pm_ops ps8640_pm_ops = {
++ SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++ pm_runtime_force_resume)
++};
++
+ static void ps8640_pre_enable(struct drm_bridge *bridge)
+ {
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
+ int ret;
+
+- ps8640_bridge_poweron(ps_bridge);
++ pm_runtime_get_sync(dev);
++ ps8640_ensure_hpd(ps_bridge);
+
+- ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE);
++ /*
++ * The Manufacturer Command Set (MCS) is a device dependent interface
++ * intended for factory programming of the display module default
++ * parameters. Once the display module is configured, the MCS shall be
++ * disabled by the manufacturer. Once disabled, all MCS commands are
++ * ignored by the display interface.
++ */
++
++ ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
++ if (ret < 0)
++ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
++
++ /* Switch access edp panel's edid through i2c */
++ ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+ if (ret < 0)
+- ps8640_bridge_poweroff(ps_bridge);
++ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
++
++ ps8640_bridge_vdo_control(ps_bridge, ENABLE);
++
++ ps_bridge->pre_enabled = true;
+ }
+
+ static void ps8640_post_disable(struct drm_bridge *bridge)
+ {
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+
++ ps_bridge->pre_enabled = false;
++
+ ps8640_bridge_vdo_control(ps_bridge, DISABLE);
+- ps8640_bridge_poweroff(ps_bridge);
++ pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
+ }
+
+ static int ps8640_bridge_attach(struct drm_bridge *bridge,
+@@ -472,7 +497,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+ {
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+- bool poweroff = !ps_bridge->powered;
++ bool poweroff = !ps_bridge->pre_enabled;
+ struct edid *edid;
+
+ /*
+@@ -502,6 +527,12 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
+ return edid;
+ }
+
++static void ps8640_runtime_disable(void *data)
++{
++ pm_runtime_dont_use_autosuspend(data);
++ pm_runtime_disable(data);
++}
++
+ static const struct drm_bridge_funcs ps8640_bridge_funcs = {
+ .attach = ps8640_bridge_attach,
+ .detach = ps8640_bridge_detach,
+@@ -585,6 +616,22 @@ static int ps8640_probe(struct i2c_client *client)
+ ps_bridge->aux.transfer = ps8640_aux_transfer;
+ drm_dp_aux_init(&ps_bridge->aux);
+
++ pm_runtime_enable(dev);
++ /*
++ * Powering on ps8640 takes ~300ms. To avoid wasting time on power
++ * cycling ps8640 too often, set autosuspend_delay to 500ms to ensure
++ * the bridge wouldn't suspend in between each _aux_transfer_msg() call
++ * during EDID read (~20ms in my experiment) and in between the last
++ * _aux_transfer_msg() call during EDID read and the _pre_enable() call
++ * (~100ms in my experiment).
++ */
++ pm_runtime_set_autosuspend_delay(dev, 500);
++ pm_runtime_use_autosuspend(dev);
++ pm_suspend_ignore_children(dev, true);
++ ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
++ if (ret)
++ return ret;
++
+ drm_bridge_add(&ps_bridge->bridge);
+
+ return 0;
+@@ -611,6 +658,7 @@ static struct i2c_driver ps8640_driver = {
+ .driver = {
+ .name = "ps8640",
+ .of_match_table = ps8640_match,
++ .pm = &ps8640_pm_ops,
+ },
+ };
+ module_i2c_driver(ps8640_driver);
+--
+2.35.1
+
--- /dev/null
+From d97cea27d322fcdbbf4a20bec79762e436a0eef7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Jul 2022 17:22:58 +0800
+Subject: drm/bridge: parade-ps8640: Fix regulator supply order
+
+From: Chen-Yu Tsai <wenst@chromium.org>
+
+[ Upstream commit fc94224c2e0ae8d83ac511a3ef4962178505469d ]
+
+The datasheet says that VDD12 must be enabled and at full voltage before
+VDD33 is enabled.
+
+Reorder the bulk regulator supply names so that VDD12 is enabled before
+VDD33. Any enable ramp delays should be handled by setting proper
+constraints on the regulators.
+
+Fixes: bc1aee7fc8f0 ("drm/bridge: Add I2C based driver for ps8640 bridge")
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220721092258.3397461-1-wenst@chromium.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/parade-ps8640.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
+index 3de796cf9328..f0ab75a5ea41 100644
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -572,8 +572,8 @@ static int ps8640_probe(struct i2c_client *client)
+ if (!ps_bridge)
+ return -ENOMEM;
+
+- ps_bridge->supplies[0].supply = "vdd33";
+- ps_bridge->supplies[1].supply = "vdd12";
++ ps_bridge->supplies[0].supply = "vdd12";
++ ps_bridge->supplies[1].supply = "vdd33";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret)
+--
+2.35.1
+
--- /dev/null
+From 7c5fbace745bb2f2268545c25c495e0bea111cbb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Oct 2021 10:58:11 -0700
+Subject: drm/bridge: parade-ps8640: Populate devices on aux-bus
+
+From: Philip Chen <philipchen@chromium.org>
+
+[ Upstream commit e9d9f9582c3d90bced286a63d1f718d4aae60a03 ]
+
+Conventionally, panel is listed under the root of the device tree.
+When userland asks for display mode, ps8640 bridge is responsible
+for returning EDID when ps8640_bridge_get_edid() is called.
+
+Now enable a new option of listing panel under "aux-bus" of ps8640
+bridge node in the device tree. In this case, panel driver can retrieve
+EDID by triggering AUX transactions, without ps8640_bridge_get_edid()
+calls at all.
+
+To prevent the "old" and "new" options from interfering with each
+other's logic flow, disable DRM_BRIDGE_OP_EDID when the new option
+is taken.
+
+Signed-off-by: Philip Chen <philipchen@chromium.org>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20211028105754.v5.2.I09899dea340f11feab97d719cb4b62bef3179e4b@changeid
+Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/Kconfig | 1 +
+ drivers/gpu/drm/bridge/parade-ps8640.c | 51 ++++++++++++++++++++------
+ 2 files changed, 40 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
+index 68ec45abc1fb..44ad70939663 100644
+--- a/drivers/gpu/drm/bridge/Kconfig
++++ b/drivers/gpu/drm/bridge/Kconfig
+@@ -182,6 +182,7 @@ config DRM_PARADE_PS8622
+ config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on OF
++ select DRM_DP_AUX_BUS
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
+index 52f2ea6fcb26..3de796cf9328 100644
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -14,6 +14,7 @@
+ #include <linux/regulator/consumer.h>
+
+ #include <drm/drm_bridge.h>
++#include <drm/drm_dp_aux_bus.h>
+ #include <drm/drm_dp_helper.h>
+ #include <drm/drm_mipi_dsi.h>
+ #include <drm/drm_of.h>
+@@ -147,6 +148,23 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
+ return container_of(aux, struct ps8640, aux);
+ }
+
++static bool ps8640_of_panel_on_aux_bus(struct device *dev)
++{
++ struct device_node *bus, *panel;
++
++ bus = of_get_child_by_name(dev->of_node, "aux-bus");
++ if (!bus)
++ return false;
++
++ panel = of_get_child_by_name(bus, "panel");
++ of_node_put(bus);
++ if (!panel)
++ return false;
++ of_node_put(panel);
++
++ return true;
++}
++
+ static int ps8640_ensure_hpd(struct ps8640 *ps_bridge)
+ {
+ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
+@@ -554,17 +572,6 @@ static int ps8640_probe(struct i2c_client *client)
+ if (!ps_bridge)
+ return -ENOMEM;
+
+- /* port@1 is ps8640 output port */
+- ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
+- if (ret < 0)
+- return ret;
+- if (!panel)
+- return -ENODEV;
+-
+- ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
+- if (IS_ERR(ps_bridge->panel_bridge))
+- return PTR_ERR(ps_bridge->panel_bridge);
+-
+ ps_bridge->supplies[0].supply = "vdd33";
+ ps_bridge->supplies[1].supply = "vdd12";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
+@@ -587,9 +594,16 @@ static int ps8640_probe(struct i2c_client *client)
+
+ ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
+ ps_bridge->bridge.of_node = dev->of_node;
+- ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
+ ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
+
++ /*
++ * In the device tree, if panel is listed under aux-bus of the bridge
++ * node, panel driver should be able to retrieve EDID by itself using
++ * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here.
++ */
++ if (!ps8640_of_panel_on_aux_bus(&client->dev))
++ ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
++
+ ps_bridge->page[PAGE0_DP_CNTL] = client;
+
+ ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
+@@ -632,6 +646,19 @@ static int ps8640_probe(struct i2c_client *client)
+ if (ret)
+ return ret;
+
++ devm_of_dp_aux_populate_ep_devices(&ps_bridge->aux);
++
++ /* port@1 is ps8640 output port */
++ ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
++ if (ret < 0)
++ return ret;
++ if (!panel)
++ return -ENODEV;
++
++ ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
++ if (IS_ERR(ps_bridge->panel_bridge))
++ return PTR_ERR(ps_bridge->panel_bridge);
++
+ drm_bridge_add(&ps_bridge->bridge);
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From 85a877c02788c394efcf8308482dabfa98117eb0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Sep 2021 11:06:16 -0700
+Subject: drm/bridge: parade-ps8640: Use regmap APIs
+
+From: Philip Chen <philipchen@chromium.org>
+
+[ Upstream commit 692d8db0a5ca123017d7d4847856343512f87af9 ]
+
+Replace the direct i2c access (i2c_smbus_* functions) with regmap APIs,
+which will simplify the future update on ps8640 driver.
+
+Signed-off-by: Philip Chen <philipchen@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Acked-by: Sam Ravnborg <sam@ravnborg.org>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+[dianders: whitespace fixes reported by dim apply-branch]
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20210921110556.v6.1.I2351df94f18d5d8debc22d4d100f36fac560409a@changeid
+Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/parade-ps8640.c | 94 ++++++++++++++++++--------
+ 1 file changed, 64 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
+index 7bd0affa057a..88c9f3404ac1 100644
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -9,6 +9,7 @@
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+ #include <linux/of_graph.h>
++#include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+
+ #include <drm/drm_bridge.h>
+@@ -29,6 +30,11 @@
+ #define VDO_EN 0x1c
+ #define DP_NUM_LANES 4
+
++#define COMMON_PS8640_REGMAP_CONFIG \
++ .reg_bits = 8, \
++ .val_bits = 8, \
++ .cache_type = REGCACHE_NONE
++
+ /*
+ * PS8640 uses multiple addresses:
+ * page[0]: for DP control
+@@ -62,12 +68,48 @@ struct ps8640 {
+ struct drm_bridge *panel_bridge;
+ struct mipi_dsi_device *dsi;
+ struct i2c_client *page[MAX_DEVS];
++ struct regmap *regmap[MAX_DEVS];
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_powerdown;
+ bool powered;
+ };
+
++static const struct regmap_config ps8640_regmap_config[] = {
++ [PAGE0_DP_CNTL] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xbf,
++ },
++ [PAGE1_VDO_BDG] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++ [PAGE2_TOP_CNTL] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++ [PAGE3_DSI_CNTL1] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++ [PAGE4_MIPI_PHY] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++ [PAGE5_VPLL] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0x7f,
++ },
++ [PAGE6_DSI_CNTL2] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++ [PAGE7_SPI_CNTL] = {
++ COMMON_PS8640_REGMAP_CONFIG,
++ .max_register = 0xff,
++ },
++};
++
+ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+ {
+ return container_of(e, struct ps8640, bridge);
+@@ -76,13 +118,13 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
+ const enum ps8640_vdo_control ctrl)
+ {
+- struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
++ struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
+ int ret;
+
+- ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD,
+- sizeof(vdo_ctrl_buf),
+- vdo_ctrl_buf);
++ ret = regmap_bulk_write(map, PAGE3_SET_ADD,
++ vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
++
+ if (ret < 0) {
+ DRM_ERROR("failed to %sable VDO: %d\n",
+ ctrl == ENABLE ? "en" : "dis", ret);
+@@ -94,8 +136,7 @@ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
+
+ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
+ {
+- struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+- unsigned long timeout;
++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
+ int ret, status;
+
+ if (ps_bridge->powered)
+@@ -119,18 +160,12 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
+ */
+ msleep(200);
+
+- timeout = jiffies + msecs_to_jiffies(200) + 1;
+-
+- while (time_is_after_jiffies(timeout)) {
+- status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H);
+- if (status < 0) {
+- DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status);
+- goto err_regulators_disable;
+- }
+- if ((status & PS_GPIO9) == PS_GPIO9)
+- break;
++ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
++ status & PS_GPIO9, 20 * 1000, 200 * 1000);
+
+- msleep(20);
++ if (ret < 0) {
++ DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret);
++ goto err_regulators_disable;
+ }
+
+ msleep(50);
+@@ -142,22 +177,15 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
+ * disabled by the manufacturer. Once disabled, all MCS commands are
+ * ignored by the display interface.
+ */
+- status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN);
+- if (status < 0) {
+- DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status);
+- goto err_regulators_disable;
+- }
+
+- ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN,
+- status & ~MCS_EN);
++ ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
+ if (ret < 0) {
+ DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret);
+ goto err_regulators_disable;
+ }
+
+ /* Switch access edp panel's edid through i2c */
+- ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS,
+- I2C_BYPASS_EN);
++ ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+ if (ret < 0) {
+ DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret);
+ goto err_regulators_disable;
+@@ -360,15 +388,21 @@ static int ps8640_probe(struct i2c_client *client)
+
+ ps_bridge->page[PAGE0_DP_CNTL] = client;
+
++ ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
++ if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
++ return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
++
+ for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
+ ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
+ client->adapter,
+ client->addr + i);
+- if (IS_ERR(ps_bridge->page[i])) {
+- dev_err(dev, "failed i2c dummy device, address %02x\n",
+- client->addr + i);
++ if (IS_ERR(ps_bridge->page[i]))
+ return PTR_ERR(ps_bridge->page[i]);
+- }
++
++ ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
++ ps8640_regmap_config + i);
++ if (IS_ERR(ps_bridge->regmap[i]))
++ return PTR_ERR(ps_bridge->regmap[i]);
+ }
+
+ i2c_set_clientdata(client, ps_bridge);
+--
+2.35.1
+
--- /dev/null
+From 0153adef33ffe635cf974510fa4bbacd2334c879 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 15 Sep 2022 22:49:00 -0700
+Subject: drm/dp: Don't rewrite link config when setting phy test pattern
+
+From: Khaled Almahallawy <khaled.almahallawy@intel.com>
+
+[ Upstream commit 7b4d8db657192066bc6f1f6635d348413dac1e18 ]
+
+The sequence for Source DP PHY CTS automation is [2][1]:
+1- Emulate successful Link Training(LT)
+2- Short HPD and change link rates and number of lanes by LT.
+(This is same flow for Link Layer CTS)
+3- Short HPD and change PHY test pattern and swing/pre-emphasis
+levels (This step should not trigger LT)
+
+The problem is with DP PHY compliance setup as follow:
+
+ [DPTX + on board LTTPR]------Main Link--->[Scope]
+ ^ |
+ | |
+ | |
+ ----------Aux Ch------>[Aux Emulator]
+
+At step 3, before writing TRAINING_LANEx_SET/LINK_QUAL_PATTERN_SET
+to declare the pattern/swing requested by scope, we write link
+config in LINK_BW_SET/LANE_COUNT_SET on a port that has LTTPR.
+As LTTPR snoops aux transaction, LINK_BW_SET/LANE_COUNT_SET writes
+indicate a LT will start [Check DP 2.0 E11 -Sec 3.6.8.2 & 3.6.8.6.3],
+and LTTPR will reset the link and stop sending DP signals to
+DPTX/Scope causing the measurements to fail. Note that step 3 will
+not trigger LT and DP link will never recovered by the
+Aux Emulator/Scope.
+
+The reset of link can be tested with a monitor connected to LTTPR
+port simply by writing to LINK_BW_SET or LANE_COUNT_SET as follow
+
+ igt/tools/dpcd_reg write --offset=0x100 --value 0x14 --device=2
+
+OR
+
+ printf '\x14' | sudo dd of=/dev/drm_dp_aux2 bs=1 count=1 conv=notrunc
+ seek=$((0x100))
+
+This single aux write causes the screen to blank, sending short HPD to
+DPTX, setting LINK_STATUS_UPDATE = 1 in DPCD 0x204, and triggering LT.
+
+As stated in [1]:
+"Before any TX electrical testing can be performed, the link between a
+DPTX and DPRX (in this case, a piece of test equipment), including all
+LTTPRs within the path, shall be trained as defined in this Standard."
+
+In addition, changing Phy pattern/Swing/Pre-emphasis (Step 3) uses the
+same link rate and lane count applied on step 2, so no need to redo LT.
+
+The fix is to not rewrite link config in step 3, and just writes
+TRAINING_LANEx_SET and LINK_QUAL_PATTERN_SET
+
+[1]: DP 2.0 E11 - 3.6.11.1 LTTPR DPTX_PHY Electrical Compliance
+
+[2]: Configuring UnigrafDPTC Controller - Automation Test Sequence
+https://www.keysight.com/us/en/assets/9922-01244/help-files/
+D9040DPPC-DisplayPort-Test-Software-Online-Help-latest.chm
+
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Or Cochvi <or.cochvi@intel.com>
+Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220916054900.415804-1-khaled.almahallawy@intel.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_dp_helper.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
+index 7bb24523a749..b8815e7f5832 100644
+--- a/drivers/gpu/drm/drm_dp_helper.c
++++ b/drivers/gpu/drm/drm_dp_helper.c
+@@ -2376,17 +2376,8 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev)
+ {
+ int err, i;
+- u8 link_config[2];
+ u8 test_pattern;
+
+- link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+- link_config[1] = data->num_lanes;
+- if (data->enhanced_frame_cap)
+- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+- err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+- if (err < 0)
+- return err;
+-
+ test_pattern = data->phy_pattern;
+ if (dp_rev < 0x12) {
+ test_pattern = (test_pattern << 2) &
+--
+2.35.1
+
--- /dev/null
+From bf3b50a1eaed401336807e9f97eb24a2817d7505 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 10 Feb 2022 15:40:25 +0000
+Subject: drm/dp_mst: fix drm_dp_dpcd_read return value checks
+
+From: Simon Ser <contact@emersion.fr>
+
+[ Upstream commit 2ac6cdd581f48c8f68747156fde5868486a44985 ]
+
+drm_dp_dpcd_read returns the number of bytes read. The previous code
+would print garbage on DPCD error, and would exit with on error on
+success.
+
+Signed-off-by: Simon Ser <contact@emersion.fr>
+Fixes: cb897542c6d2 ("drm/dp_mst: Fix W=1 warnings")
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/473500/
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
+index 2a586e6489da..9bf9430209b0 100644
+--- a/drivers/gpu/drm/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/drm_dp_mst_topology.c
+@@ -4899,14 +4899,14 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
+ seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf);
+
+ ret = drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2);
+- if (ret) {
++ if (ret != 2) {
+ seq_printf(m, "faux/mst read failed\n");
+ goto out;
+ }
+ seq_printf(m, "faux/mst: %*ph\n", 2, buf);
+
+ ret = drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1);
+- if (ret) {
++ if (ret != 1) {
+ seq_printf(m, "mst ctrl read failed\n");
+ goto out;
+ }
+@@ -4914,7 +4914,7 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
+
+ /* dump the standard OUI branch header */
+ ret = drm_dp_dpcd_read(mgr->aux, DP_BRANCH_OUI, buf, DP_BRANCH_OUI_HEADER_SIZE);
+- if (ret) {
++ if (ret != DP_BRANCH_OUI_HEADER_SIZE) {
+ seq_printf(m, "branch oui read failed\n");
+ goto out;
+ }
+--
+2.35.1
+
--- /dev/null
+From bed7cbab0bd9ffeee46378ea15746cba495d4a0d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 09:31:00 +0900
+Subject: drm/exynos: Fix return type for mixer_mode_valid and hdmi_mode_valid
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 1261255531088208daeca818e2b486030b5339e5 ]
+
+The field mode_valid in exynos_drm_crtc_ops is expected to be of type enum
+drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
+ const struct drm_display_mode *mode);
+
+Likewise for mode_valid in drm_connector_helper_funcs.
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of mixer_mode_valid and hdmi_mode_valid should be changed
+from int to enum drm_mode_status.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://protect2.fireeye.com/v1/url?k=3e644738-5fef521d-3e65cc77-
+74fe485cbff6-36ad29bf912d3c9f&q=1&e=5cc06174-77dd-4abd-ab50-
+155da5711aa3&u=https%3A%2F%2Fgithub.com%2FClangBuiltLinux%2Flinux%2Fissues%2F
+1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Signed-off-by: Inki Dae <inki.dae@samsung.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/exynos/exynos_hdmi.c | 4 ++--
+ drivers/gpu/drm/exynos/exynos_mixer.c | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
+index 7655142a4651..912a7df9f8c4 100644
+--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
++++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
+@@ -922,8 +922,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
+ return -EINVAL;
+ }
+
+-static int hdmi_mode_valid(struct drm_connector *connector,
+- struct drm_display_mode *mode)
++static enum drm_mode_status hdmi_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode)
+ {
+ struct hdmi_context *hdata = connector_to_hdmi(connector);
+ int ret;
+diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
+index 41c54f1f60bc..8d01e1068245 100644
+--- a/drivers/gpu/drm/exynos/exynos_mixer.c
++++ b/drivers/gpu/drm/exynos/exynos_mixer.c
+@@ -1044,7 +1044,7 @@ static void mixer_atomic_disable(struct exynos_drm_crtc *crtc)
+ clear_bit(MXR_BIT_POWERED, &ctx->flags);
+ }
+
+-static int mixer_mode_valid(struct exynos_drm_crtc *crtc,
++static enum drm_mode_status mixer_mode_valid(struct exynos_drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+ {
+ struct mixer_context *ctx = crtc->ctx;
+--
+2.35.1
+
--- /dev/null
+From c9de26dccfb3e519ba4f3fbffd2f6669b9c8e218 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 Jul 2022 16:39:21 +0100
+Subject: drm/komeda: Fix handling of atomic commits in the atomic_commit_tail
+ hook
+
+From: Liviu Dudau <liviu.dudau@arm.com>
+
+[ Upstream commit eaa225b6b52233d45457fd33730e1528c604d92d ]
+
+Komeda driver relies on the generic DRM atomic helper functions to handle
+commits. It only implements an atomic_commit_tail hook for the
+mode_config_helper_funcs and even that one is pretty close to the generic
+implementation with the exception of additional dma_fence signalling.
+
+What the generic helper framework doesn't do is waiting for the actual
+hardware to signal that the commit parameters have been written into the
+appropriate registers. As we signal CRTC events only on the irq handlers,
+we need to flush the configuration and wait for the hardware to respond.
+
+Add the Komeda specific implementation for atomic_commit_hw_done() that
+flushes and waits for flip done before calling drm_atomic_helper_commit_hw_done().
+
+The fix was prompted by a patch from Carsten Haitzler where he was trying to
+solve the same issue but in a different way that I think can lead to wrong
+event signaling to userspace.
+
+Reported-by: Carsten Haitzler <carsten.haitzler@arm.com>
+Tested-by: Carsten Haitzler <carsten.haitzler@arm.com>
+Reviewed-by: Carsten Haitzler <carsten.haitzler@arm.com>
+Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220722122139.288486-1-liviu.dudau@arm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 4 ++--
+ .../gpu/drm/arm/display/komeda/komeda_kms.c | 21 ++++++++++++++++++-
+ .../gpu/drm/arm/display/komeda/komeda_kms.h | 2 ++
+ 3 files changed, 24 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+index 59172acb9738..292f533d8cf0 100644
+--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
++++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+@@ -235,7 +235,7 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
+ crtc->state->event = NULL;
+ drm_crtc_send_vblank_event(crtc, event);
+ } else {
+- DRM_WARN("CRTC[%d]: FLIP happen but no pending commit.\n",
++ DRM_WARN("CRTC[%d]: FLIP happened but no pending commit.\n",
+ drm_crtc_index(&kcrtc->base));
+ }
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+@@ -286,7 +286,7 @@ komeda_crtc_atomic_enable(struct drm_crtc *crtc,
+ komeda_crtc_do_flush(crtc, old);
+ }
+
+-static void
++void
+ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc,
+ struct completion *input_flip_done)
+ {
+diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
+index 93b7f09b96ca..327051bba5b6 100644
+--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
++++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
+@@ -69,6 +69,25 @@ static const struct drm_driver komeda_kms_driver = {
+ .minor = 1,
+ };
+
++static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_state *state)
++{
++ struct drm_device *dev = state->dev;
++ struct komeda_kms_dev *kms = to_kdev(dev);
++ int i;
++
++ for (i = 0; i < kms->n_crtcs; i++) {
++ struct komeda_crtc *kcrtc = &kms->crtcs[i];
++
++ if (kcrtc->base.state->active) {
++ struct completion *flip_done = NULL;
++ if (kcrtc->base.state->event)
++ flip_done = kcrtc->base.state->event->base.completion;
++ komeda_crtc_flush_and_wait_for_flip_done(kcrtc, flip_done);
++ }
++ }
++ drm_atomic_helper_commit_hw_done(state);
++}
++
+ static void komeda_kms_commit_tail(struct drm_atomic_state *old_state)
+ {
+ struct drm_device *dev = old_state->dev;
+@@ -81,7 +100,7 @@ static void komeda_kms_commit_tail(struct drm_atomic_state *old_state)
+
+ drm_atomic_helper_commit_modeset_enables(dev, old_state);
+
+- drm_atomic_helper_commit_hw_done(old_state);
++ komeda_kms_atomic_commit_hw_done(old_state);
+
+ drm_atomic_helper_wait_for_flip_done(dev, old_state);
+
+diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+index 456f3c435719..bf6e8fba5061 100644
+--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
++++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+@@ -182,6 +182,8 @@ void komeda_kms_cleanup_private_objs(struct komeda_kms_dev *kms);
+
+ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
+ struct komeda_events *evts);
++void komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc,
++ struct completion *input_flip_done);
+
+ struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);
+ void komeda_kms_detach(struct komeda_kms_dev *kms);
+--
+2.35.1
+
--- /dev/null
+From c025ae50ff6b6409c5999a9540e111fe7ad11cbd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 02:09:39 +0100
+Subject: drm/meson: explicitly remove aggregate driver at module unload time
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Adrián Larumbe <adrian.larumbe@collabora.com>
+
+[ Upstream commit 8616f2a0589a80e08434212324250eb22f6a66ce ]
+
+Because component_master_del wasn't being called when unloading the
+meson_drm module, the aggregate device would linger forever in the global
+aggregate_devices list. That means when unloading and reloading the
+meson_dw_hdmi module, component_add would call into
+try_to_bring_up_aggregate_device and find the unbound meson_drm aggregate
+device.
+
+This would in turn dereference some of the aggregate_device's struct
+entries which point to memory automatically freed by the devres API when
+unbinding the aggregate device from meson_drv_unbind, and trigger an
+use-after-free bug:
+
+[ +0.000014] =============================================================
+[ +0.000007] BUG: KASAN: use-after-free in find_components+0x468/0x500
+[ +0.000017] Read of size 8 at addr ffff000006731688 by task modprobe/2536
+[ +0.000018] CPU: 4 PID: 2536 Comm: modprobe Tainted: G C O 5.19.0-rc6-lrmbkasan+ #1
+[ +0.000010] Hardware name: Hardkernel ODROID-N2Plus (DT)
+[ +0.000008] Call trace:
+[ +0.000005] dump_backtrace+0x1ec/0x280
+[ +0.000011] show_stack+0x24/0x80
+[ +0.000007] dump_stack_lvl+0x98/0xd4
+[ +0.000010] print_address_description.constprop.0+0x80/0x520
+[ +0.000011] print_report+0x128/0x260
+[ +0.000007] kasan_report+0xb8/0xfc
+[ +0.000007] __asan_report_load8_noabort+0x3c/0x50
+[ +0.000009] find_components+0x468/0x500
+[ +0.000008] try_to_bring_up_aggregate_device+0x64/0x390
+[ +0.000009] __component_add+0x1dc/0x49c
+[ +0.000009] component_add+0x20/0x30
+[ +0.000008] meson_dw_hdmi_probe+0x28/0x34 [meson_dw_hdmi]
+[ +0.000013] platform_probe+0xd0/0x220
+[ +0.000008] really_probe+0x3ac/0xa80
+[ +0.000008] __driver_probe_device+0x1f8/0x400
+[ +0.000008] driver_probe_device+0x68/0x1b0
+[ +0.000008] __driver_attach+0x20c/0x480
+[ +0.000009] bus_for_each_dev+0x114/0x1b0
+[ +0.000007] driver_attach+0x48/0x64
+[ +0.000009] bus_add_driver+0x390/0x564
+[ +0.000007] driver_register+0x1a8/0x3e4
+[ +0.000009] __platform_driver_register+0x6c/0x94
+[ +0.000007] meson_dw_hdmi_platform_driver_init+0x30/0x1000 [meson_dw_hdmi]
+[ +0.000014] do_one_initcall+0xc4/0x2b0
+[ +0.000008] do_init_module+0x154/0x570
+[ +0.000010] load_module+0x1a78/0x1ea4
+[ +0.000008] __do_sys_init_module+0x184/0x1cc
+[ +0.000008] __arm64_sys_init_module+0x78/0xb0
+[ +0.000008] invoke_syscall+0x74/0x260
+[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260
+[ +0.000009] do_el0_svc+0x50/0x70
+[ +0.000008] el0_svc+0x68/0x1a0
+[ +0.000009] el0t_64_sync_handler+0x11c/0x150
+[ +0.000009] el0t_64_sync+0x18c/0x190
+
+[ +0.000014] Allocated by task 902:
+[ +0.000007] kasan_save_stack+0x2c/0x5c
+[ +0.000009] __kasan_kmalloc+0x90/0xd0
+[ +0.000007] __kmalloc_node+0x240/0x580
+[ +0.000010] memcg_alloc_slab_cgroups+0xa4/0x1ac
+[ +0.000010] memcg_slab_post_alloc_hook+0xbc/0x4c0
+[ +0.000008] kmem_cache_alloc_node+0x1d0/0x490
+[ +0.000009] __alloc_skb+0x1d4/0x310
+[ +0.000010] alloc_skb_with_frags+0x8c/0x620
+[ +0.000008] sock_alloc_send_pskb+0x5ac/0x6d0
+[ +0.000010] unix_dgram_sendmsg+0x2e0/0x12f0
+[ +0.000010] sock_sendmsg+0xcc/0x110
+[ +0.000007] sock_write_iter+0x1d0/0x304
+[ +0.000008] new_sync_write+0x364/0x460
+[ +0.000007] vfs_write+0x420/0x5ac
+[ +0.000008] ksys_write+0x19c/0x1f0
+[ +0.000008] __arm64_sys_write+0x78/0xb0
+[ +0.000007] invoke_syscall+0x74/0x260
+[ +0.000008] el0_svc_common.constprop.0+0x1a8/0x260
+[ +0.000009] do_el0_svc+0x50/0x70
+[ +0.000007] el0_svc+0x68/0x1a0
+[ +0.000008] el0t_64_sync_handler+0x11c/0x150
+[ +0.000008] el0t_64_sync+0x18c/0x190
+
+[ +0.000013] Freed by task 2509:
+[ +0.000008] kasan_save_stack+0x2c/0x5c
+[ +0.000007] kasan_set_track+0x2c/0x40
+[ +0.000008] kasan_set_free_info+0x28/0x50
+[ +0.000008] ____kasan_slab_free+0x128/0x1d4
+[ +0.000008] __kasan_slab_free+0x18/0x24
+[ +0.000007] slab_free_freelist_hook+0x108/0x230
+[ +0.000010] kfree+0x110/0x35c
+[ +0.000008] release_nodes+0xf0/0x16c
+[ +0.000008] devres_release_all+0xfc/0x180
+[ +0.000008] device_unbind_cleanup+0x24/0x164
+[ +0.000008] device_release_driver_internal+0x3e8/0x5b0
+[ +0.000010] driver_detach+0xac/0x1b0
+[ +0.000008] bus_remove_driver+0x158/0x29c
+[ +0.000008] driver_unregister+0x70/0xb0
+[ +0.000009] platform_driver_unregister+0x20/0x2c
+[ +0.000007] 0xffff800003722d98
+[ +0.000012] __do_sys_delete_module+0x288/0x400
+[ +0.000009] __arm64_sys_delete_module+0x5c/0x80
+[ +0.000008] invoke_syscall+0x74/0x260
+[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260
+[ +0.000008] do_el0_svc+0x50/0x70
+[ +0.000007] el0_svc+0x68/0x1a0
+[ +0.000008] el0t_64_sync_handler+0x11c/0x150
+[ +0.000009] el0t_64_sync+0x18c/0x190
+
+[ +0.000013] Last potentially related work creation:
+[ +0.000007] kasan_save_stack+0x2c/0x5c
+[ +0.000007] __kasan_record_aux_stack+0xb8/0xf0
+[ +0.000009] kasan_record_aux_stack_noalloc+0x14/0x20
+[ +0.000008] insert_work+0x54/0x290
+[ +0.000009] __queue_work+0x48c/0xd24
+[ +0.000008] queue_work_on+0x90/0x11c
+[ +0.000008] call_usermodehelper_exec+0x188/0x404
+[ +0.000010] kobject_uevent_env+0x5a8/0x794
+[ +0.000010] kobject_uevent+0x14/0x20
+[ +0.000008] driver_register+0x230/0x3e4
+[ +0.000009] __platform_driver_register+0x6c/0x94
+[ +0.000007] gxbb_driver_init+0x28/0x34
+[ +0.000010] do_one_initcall+0xc4/0x2b0
+[ +0.000008] do_initcalls+0x20c/0x24c
+[ +0.000010] kernel_init_freeable+0x22c/0x278
+[ +0.000009] kernel_init+0x3c/0x170
+[ +0.000008] ret_from_fork+0x10/0x20
+
+[ +0.000013] The buggy address belongs to the object at ffff000006731600
+ which belongs to the cache kmalloc-256 of size 256
+[ +0.000009] The buggy address is located 136 bytes inside of
+ 256-byte region [ffff000006731600, ffff000006731700)
+
+[ +0.000015] The buggy address belongs to the physical page:
+[ +0.000008] page:fffffc000019cc00 refcount:1 mapcount:0 mapping:0000000000000000 index:0xffff000006730a00 pfn:0x6730
+[ +0.000011] head:fffffc000019cc00 order:2 compound_mapcount:0 compound_pincount:0
+[ +0.000008] flags: 0xffff00000010200(slab|head|node=0|zone=0|lastcpupid=0xffff)
+[ +0.000016] raw: 0ffff00000010200 fffffc00000c3d08 fffffc0000ef2b08 ffff000000002680
+[ +0.000009] raw: ffff000006730a00 0000000000150014 00000001ffffffff 0000000000000000
+[ +0.000006] page dumped because: kasan: bad access detected
+
+[ +0.000011] Memory state around the buggy address:
+[ +0.000007] ffff000006731580: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ +0.000007] ffff000006731600: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] >ffff000006731680: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] ^
+[ +0.000006] ffff000006731700: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ +0.000007] ffff000006731780: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ +0.000006] ==================================================================
+
+Fix by adding 'remove' driver callback for meson-drm, and explicitly deleting the
+aggregate device.
+
+Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220919010940.419893-3-adrian.larumbe@collabora.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 56c7daeb116a..6e37de4fcb46 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -520,6 +520,13 @@ static int meson_drv_probe(struct platform_device *pdev)
+ return 0;
+ };
+
++static int meson_drv_remove(struct platform_device *pdev)
++{
++ component_master_del(&pdev->dev, &meson_drv_master_ops);
++
++ return 0;
++}
++
+ static struct meson_drm_match_data meson_drm_gxbb_data = {
+ .compat = VPU_COMPATIBLE_GXBB,
+ };
+@@ -557,6 +564,7 @@ static const struct dev_pm_ops meson_drv_pm_ops = {
+
+ static struct platform_driver meson_drm_platform_driver = {
+ .probe = meson_drv_probe,
++ .remove = meson_drv_remove,
+ .shutdown = meson_drv_shutdown,
+ .driver = {
+ .name = "meson-drm",
+--
+2.35.1
+
--- /dev/null
+From 68a04919437f4523c483027f3bd6e69c916323f1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 02:09:38 +0100
+Subject: drm/meson: reorder driver deinit sequence to fix use-after-free bug
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Adrián Larumbe <adrian.larumbe@collabora.com>
+
+[ Upstream commit 31c519981eb141c7ec39bfd5be25d35f02edb868 ]
+
+Unloading the driver triggers the following KASAN warning:
+
+[ +0.006275] =============================================================
+[ +0.000029] BUG: KASAN: use-after-free in __list_del_entry_valid+0xe0/0x1a0
+[ +0.000026] Read of size 8 at addr ffff000020c395e0 by task rmmod/2695
+
+[ +0.000019] CPU: 5 PID: 2695 Comm: rmmod Tainted: G C O 5.19.0-rc6-lrmbkasan+ #1
+[ +0.000013] Hardware name: Hardkernel ODROID-N2Plus (DT)
+[ +0.000008] Call trace:
+[ +0.000007] dump_backtrace+0x1ec/0x280
+[ +0.000013] show_stack+0x24/0x80
+[ +0.000008] dump_stack_lvl+0x98/0xd4
+[ +0.000011] print_address_description.constprop.0+0x80/0x520
+[ +0.000011] print_report+0x128/0x260
+[ +0.000007] kasan_report+0xb8/0xfc
+[ +0.000008] __asan_report_load8_noabort+0x3c/0x50
+[ +0.000010] __list_del_entry_valid+0xe0/0x1a0
+[ +0.000009] drm_atomic_private_obj_fini+0x30/0x200 [drm]
+[ +0.000172] drm_bridge_detach+0x94/0x260 [drm]
+[ +0.000145] drm_encoder_cleanup+0xa4/0x290 [drm]
+[ +0.000144] drm_mode_config_cleanup+0x118/0x740 [drm]
+[ +0.000143] drm_mode_config_init_release+0x1c/0x2c [drm]
+[ +0.000144] drm_managed_release+0x170/0x414 [drm]
+[ +0.000142] drm_dev_put.part.0+0xc0/0x124 [drm]
+[ +0.000143] drm_dev_put+0x20/0x30 [drm]
+[ +0.000142] meson_drv_unbind+0x1d8/0x2ac [meson_drm]
+[ +0.000028] take_down_aggregate_device+0xb0/0x160
+[ +0.000016] component_del+0x18c/0x360
+[ +0.000009] meson_dw_hdmi_remove+0x28/0x40 [meson_dw_hdmi]
+[ +0.000015] platform_remove+0x64/0xb0
+[ +0.000009] device_remove+0xb8/0x154
+[ +0.000009] device_release_driver_internal+0x398/0x5b0
+[ +0.000009] driver_detach+0xac/0x1b0
+[ +0.000009] bus_remove_driver+0x158/0x29c
+[ +0.000009] driver_unregister+0x70/0xb0
+[ +0.000008] platform_driver_unregister+0x20/0x2c
+[ +0.000008] meson_dw_hdmi_platform_driver_exit+0x1c/0x30 [meson_dw_hdmi]
+[ +0.000012] __do_sys_delete_module+0x288/0x400
+[ +0.000011] __arm64_sys_delete_module+0x5c/0x80
+[ +0.000009] invoke_syscall+0x74/0x260
+[ +0.000009] el0_svc_common.constprop.0+0xcc/0x260
+[ +0.000009] do_el0_svc+0x50/0x70
+[ +0.000007] el0_svc+0x68/0x1a0
+[ +0.000012] el0t_64_sync_handler+0x11c/0x150
+[ +0.000008] el0t_64_sync+0x18c/0x190
+
+[ +0.000018] Allocated by task 0:
+[ +0.000007] (stack is not available)
+
+[ +0.000011] Freed by task 2695:
+[ +0.000008] kasan_save_stack+0x2c/0x5c
+[ +0.000011] kasan_set_track+0x2c/0x40
+[ +0.000008] kasan_set_free_info+0x28/0x50
+[ +0.000009] ____kasan_slab_free+0x128/0x1d4
+[ +0.000008] __kasan_slab_free+0x18/0x24
+[ +0.000007] slab_free_freelist_hook+0x108/0x230
+[ +0.000011] kfree+0x110/0x35c
+[ +0.000008] release_nodes+0xf0/0x16c
+[ +0.000009] devres_release_group+0x180/0x270
+[ +0.000008] component_unbind+0x128/0x1e0
+[ +0.000010] component_unbind_all+0x1b8/0x264
+[ +0.000009] meson_drv_unbind+0x1a0/0x2ac [meson_drm]
+[ +0.000025] take_down_aggregate_device+0xb0/0x160
+[ +0.000009] component_del+0x18c/0x360
+[ +0.000009] meson_dw_hdmi_remove+0x28/0x40 [meson_dw_hdmi]
+[ +0.000012] platform_remove+0x64/0xb0
+[ +0.000008] device_remove+0xb8/0x154
+[ +0.000009] device_release_driver_internal+0x398/0x5b0
+[ +0.000009] driver_detach+0xac/0x1b0
+[ +0.000009] bus_remove_driver+0x158/0x29c
+[ +0.000008] driver_unregister+0x70/0xb0
+[ +0.000008] platform_driver_unregister+0x20/0x2c
+[ +0.000008] meson_dw_hdmi_platform_driver_exit+0x1c/0x30 [meson_dw_hdmi]
+[ +0.000011] __do_sys_delete_module+0x288/0x400
+[ +0.000010] __arm64_sys_delete_module+0x5c/0x80
+[ +0.000008] invoke_syscall+0x74/0x260
+[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260
+[ +0.000008] do_el0_svc+0x50/0x70
+[ +0.000007] el0_svc+0x68/0x1a0
+[ +0.000009] el0t_64_sync_handler+0x11c/0x150
+[ +0.000009] el0t_64_sync+0x18c/0x190
+
+[ +0.000014] The buggy address belongs to the object at ffff000020c39000
+ which belongs to the cache kmalloc-4k of size 4096
+[ +0.000008] The buggy address is located 1504 bytes inside of
+ 4096-byte region [ffff000020c39000, ffff000020c3a000)
+
+[ +0.000016] The buggy address belongs to the physical page:
+[ +0.000009] page:fffffc0000830e00 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x20c38
+[ +0.000013] head:fffffc0000830e00 order:3 compound_mapcount:0 compound_pincount:0
+[ +0.000008] flags: 0xffff00000010200(slab|head|node=0|zone=0|lastcpupid=0xffff)
+[ +0.000019] raw: 0ffff00000010200 fffffc0000fd4808 fffffc0000126208 ffff000000002e80
+[ +0.000009] raw: 0000000000000000 0000000000020002 00000001ffffffff 0000000000000000
+[ +0.000008] page dumped because: kasan: bad access detected
+
+[ +0.000011] Memory state around the buggy address:
+[ +0.000008] ffff000020c39480: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] ffff000020c39500: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] >ffff000020c39580: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] ^
+[ +0.000007] ffff000020c39600: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000007] ffff000020c39680: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ +0.000006] ==================================================================
+
+The reason this is happening is unloading meson-dw-hdmi will cause the
+component API to take down the aggregate device, which in turn will cause
+all devres-managed memory to be freed, including the struct dw_hdmi
+allocated in dw_hdmi_probe. This struct embeds a struct drm_bridge that is
+added at the end of the function, and which is later on picked up in
+meson_encoder_hdmi_init.
+
+However, when attaching the bridge to the encoder created in
+meson_encoder_hdmi_init, it's linked to the encoder's bridge chain, from
+where it never leaves, even after devres_release_group is called when the
+driver's components are unbound and the embedding structure freed.
+
+Then, when calling drm_dev_put in the aggregate driver's unbind function,
+drm_bridge_detach is called for every single bridge linked to the encoder,
+including the one whose memory had already been deallocated.
+
+Fix by calling component_unbind_all after drm_dev_put.
+
+Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220919010940.419893-2-adrian.larumbe@collabora.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/meson/meson_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index a56607501d36..56c7daeb116a 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -387,9 +387,9 @@ static void meson_drv_unbind(struct device *dev)
+ drm_dev_unregister(drm);
+ drm_kms_helper_poll_fini(drm);
+ drm_atomic_helper_shutdown(drm);
+- component_unbind_all(dev, drm);
+ free_irq(priv->vsync_irq, drm);
+ drm_dev_put(drm);
++ component_unbind_all(dev, drm);
+
+ if (priv->afbcd.ops)
+ priv->afbcd.ops->exit(priv);
+--
+2.35.1
+
--- /dev/null
+From 02009adcf5d2f91171094fbc161c453a5b12ada6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 11 Jul 2022 19:38:31 +0200
+Subject: drm/mipi-dsi: Detach devices when removing the host
+
+From: Maxime Ripard <maxime@cerno.tech>
+
+[ Upstream commit 668a8f17b5290d04ef7343636a5588a0692731a1 ]
+
+Whenever the MIPI-DSI host is unregistered, the code of
+mipi_dsi_host_unregister() loops over every device currently found on that
+bus and will unregister it.
+
+However, it doesn't detach it from the bus first, which leads to all kind
+of resource leaks if the host wants to perform some clean up whenever a
+device is detached.
+
+Fixes: 068a00233969 ("drm: Add MIPI DSI bus support")
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+Link: https://lore.kernel.org/r/20220711173939.1132294-2-maxime@cerno.tech
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_mipi_dsi.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
+index 5dd475e82995..2c43d54766f3 100644
+--- a/drivers/gpu/drm/drm_mipi_dsi.c
++++ b/drivers/gpu/drm/drm_mipi_dsi.c
+@@ -300,6 +300,7 @@ static int mipi_dsi_remove_device_fn(struct device *dev, void *priv)
+ {
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+
++ mipi_dsi_detach(dsi);
+ mipi_dsi_device_unregister(dsi);
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From 9d923339b067857677061b9d0bcf58b325082917 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 13:15:50 -0700
+Subject: drm/msm/dp: correct 1.62G link rate at dp_catalog_ctrl_config_msa()
+
+From: Kuogee Hsieh <quic_khsieh@quicinc.com>
+
+[ Upstream commit aa0bff10af1c4b92e6b56e3e1b7f81c660d3ba78 ]
+
+At current implementation there is an extra 0 at 1.62G link rate which
+cause no correct pixel_div selected for 1.62G link rate to calculate
+mvid and nvid. This patch delete the extra 0 to have mvid and nvid be
+calculated correctly.
+
+Changes in v2:
+-- fix Fixes tag's text
+
+Changes in v3:
+-- fix misspelling of "Reviewed-by"
+
+Fixes: 937f941ca06f ("drm/msm/dp: Use qmp phy for DP PLL and PHY")
+Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
+Reviewed-by: Stephen Boyd <swboyd@chromium.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/499328/
+Link: https://lore.kernel.org/r/1661372150-3764-1-git-send-email-quic_khsieh@quicinc.com
+[DB: rewrapped commit message]
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
+index cc2bb8295329..9ef24ced6586 100644
+--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
++++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
+@@ -437,7 +437,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
+
+ if (rate == link_rate_hbr3)
+ pixel_div = 6;
+- else if (rate == 1620000 || rate == 270000)
++ else if (rate == 162000 || rate == 270000)
+ pixel_div = 2;
+ else if (rate == link_rate_hbr2)
+ pixel_div = 4;
+--
+2.35.1
+
--- /dev/null
+From 907017d0473e695ed530c28b22d6308fe22357af Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 15 Jun 2022 15:57:01 +0300
+Subject: drm/msm/dpu: index dpu_kms->hw_vbif using vbif_idx
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 7538f80ae0d98bf51eb89eee5344aec219902d42 ]
+
+Remove loops over hw_vbif. Instead always VBIF's idx as an index in the
+array. This fixes an error in dpu_kms_hw_init(), where we fill
+dpu_kms->hw_vbif[i], but check for an error pointer at
+dpu_kms->hw_vbif[vbif_idx].
+
+Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/489569/
+Link: https://lore.kernel.org/r/20220615125703.24647-1-dmitry.baryshkov@linaro.org
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++------
+ drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 29 +++++++++++-------------
+ 2 files changed, 18 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+index 8b7693883e7c..6d36622977af 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+@@ -725,12 +725,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
+ _dpu_kms_mmu_destroy(dpu_kms);
+
+ if (dpu_kms->catalog) {
+- for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
+- u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
+-
+- if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) {
+- dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]);
+- dpu_kms->hw_vbif[vbif_idx] = NULL;
++ for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
++ if (dpu_kms->hw_vbif[i]) {
++ dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]);
++ dpu_kms->hw_vbif[i] = NULL;
+ }
+ }
+ }
+@@ -1049,7 +1047,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
+ for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
+ u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
+
+- dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx,
++ dpu_kms->hw_vbif[vbif_idx] = dpu_hw_vbif_init(vbif_idx,
+ dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
+ if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) {
+ rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+index 21d20373eb8b..a18fb649301c 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+@@ -11,6 +11,14 @@
+ #include "dpu_hw_vbif.h"
+ #include "dpu_trace.h"
+
++static struct dpu_hw_vbif *dpu_get_vbif(struct dpu_kms *dpu_kms, enum dpu_vbif vbif_idx)
++{
++ if (vbif_idx < ARRAY_SIZE(dpu_kms->hw_vbif))
++ return dpu_kms->hw_vbif[vbif_idx];
++
++ return NULL;
++}
++
+ /**
+ * _dpu_vbif_wait_for_xin_halt - wait for the xin to halt
+ * @vbif: Pointer to hardware vbif driver
+@@ -148,20 +156,15 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif,
+ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
+ struct dpu_vbif_set_ot_params *params)
+ {
+- struct dpu_hw_vbif *vbif = NULL;
++ struct dpu_hw_vbif *vbif;
+ struct dpu_hw_mdp *mdp;
+ bool forced_on = false;
+ u32 ot_lim;
+- int ret, i;
++ int ret;
+
+ mdp = dpu_kms->hw_mdp;
+
+- for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
+- if (dpu_kms->hw_vbif[i] &&
+- dpu_kms->hw_vbif[i]->idx == params->vbif_idx)
+- vbif = dpu_kms->hw_vbif[i];
+- }
+-
++ vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);
+ if (!vbif || !mdp) {
+ DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n",
+ vbif != NULL, mdp != NULL);
+@@ -204,7 +207,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
+ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
+ struct dpu_vbif_set_qos_params *params)
+ {
+- struct dpu_hw_vbif *vbif = NULL;
++ struct dpu_hw_vbif *vbif;
+ struct dpu_hw_mdp *mdp;
+ bool forced_on = false;
+ const struct dpu_vbif_qos_tbl *qos_tbl;
+@@ -216,13 +219,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
+ }
+ mdp = dpu_kms->hw_mdp;
+
+- for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
+- if (dpu_kms->hw_vbif[i] &&
+- dpu_kms->hw_vbif[i]->idx == params->vbif_idx) {
+- vbif = dpu_kms->hw_vbif[i];
+- break;
+- }
+- }
++ vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);
+
+ if (!vbif || !vbif->cap) {
+ DPU_ERROR("invalid vbif %d\n", params->vbif_idx);
+--
+2.35.1
+
--- /dev/null
+From 13371be0fcd1a289c1bec4cafdc154dc1270dbc8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 15:46:12 +0200
+Subject: drm/msm: Make .remove and .shutdown HW shutdown consistent
+
+From: Javier Martinez Canillas <javierm@redhat.com>
+
+[ Upstream commit 0a58d2ae572adaec8d046f8d35b40c2c32ac7468 ]
+
+Drivers' .remove and .shutdown callbacks are executed on different code
+paths. The former is called when a device is removed from the bus, while
+the latter is called at system shutdown time to quiesce the device.
+
+This means that some overlap exists between the two, because both have to
+take care of properly shutting down the hardware. But currently the logic
+used in these two callbacks isn't consistent in msm drivers, which could
+lead to kernel panic.
+
+For example, on .remove the component is deleted and its .unbind callback
+leads to the hardware being shutdown but only if the DRM device has been
+marked as registered.
+
+That check doesn't exist in the .shutdown logic and this can lead to the
+driver calling drm_atomic_helper_shutdown() for a DRM device that hasn't
+been properly initialized.
+
+A situation like this can happen if drivers for expected sub-devices fail
+to probe, since the .bind callback will never be executed. If that is the
+case, drm_atomic_helper_shutdown() will attempt to take mutexes that are
+only initialized if drm_mode_config_init() is called during a device bind.
+
+This bug was attempted to be fixed in commit 623f279c7781 ("drm/msm: fix
+shutdown hook in case GPU components failed to bind"), but unfortunately
+it still happens in some cases as the one mentioned above, i.e:
+
+ systemd-shutdown[1]: Powering off.
+ kvm: exiting hardware virtualization
+ platform wifi-firmware.0: Removing from iommu group 12
+ platform video-firmware.0: Removing from iommu group 10
+ ------------[ cut here ]------------
+ WARNING: CPU: 6 PID: 1 at drivers/gpu/drm/drm_modeset_lock.c:317 drm_modeset_lock_all_ctx+0x3c4/0x3d0
+ ...
+ Hardware name: Google CoachZ (rev3+) (DT)
+ pstate: a0400009 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+ pc : drm_modeset_lock_all_ctx+0x3c4/0x3d0
+ lr : drm_modeset_lock_all_ctx+0x48/0x3d0
+ sp : ffff80000805bb80
+ x29: ffff80000805bb80 x28: ffff327c00128000 x27: 0000000000000000
+ x26: 0000000000000000 x25: 0000000000000001 x24: ffffc95d820ec030
+ x23: ffff327c00bbd090 x22: ffffc95d8215eca0 x21: ffff327c039c5800
+ x20: ffff327c039c5988 x19: ffff80000805bbe8 x18: 0000000000000034
+ x17: 000000040044ffff x16: ffffc95d80cac920 x15: 0000000000000000
+ x14: 0000000000000315 x13: 0000000000000315 x12: 0000000000000000
+ x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000
+ x8 : ffff80000805bc28 x7 : 0000000000000000 x6 : 0000000000000000
+ x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
+ x2 : ffff327c00128000 x1 : 0000000000000000 x0 : ffff327c039c59b0
+ Call trace:
+ drm_modeset_lock_all_ctx+0x3c4/0x3d0
+ drm_atomic_helper_shutdown+0x70/0x134
+ msm_drv_shutdown+0x30/0x40
+ platform_shutdown+0x28/0x40
+ device_shutdown+0x148/0x350
+ kernel_power_off+0x38/0x80
+ __do_sys_reboot+0x288/0x2c0
+ __arm64_sys_reboot+0x28/0x34
+ invoke_syscall+0x48/0x114
+ el0_svc_common.constprop.0+0x44/0xec
+ do_el0_svc+0x2c/0xc0
+ el0_svc+0x2c/0x84
+ el0t_64_sync_handler+0x11c/0x150
+ el0t_64_sync+0x18c/0x190
+ ---[ end trace 0000000000000000 ]---
+ Unable to handle kernel NULL pointer dereference at virtual address 0000000000000018
+ Mem abort info:
+ ESR = 0x0000000096000004
+ EC = 0x25: DABT (current EL), IL = 32 bits
+ SET = 0, FnV = 0
+ EA = 0, S1PTW = 0
+ FSC = 0x04: level 0 translation fault
+ Data abort info:
+ ISV = 0, ISS = 0x00000004
+ CM = 0, WnR = 0
+ user pgtable: 4k pages, 48-bit VAs, pgdp=000000010eab1000
+ [0000000000000018] pgd=0000000000000000, p4d=0000000000000000
+ Internal error: Oops: 96000004 [#1] PREEMPT SMP
+ ...
+ Hardware name: Google CoachZ (rev3+) (DT)
+ pstate: a0400009 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+ pc : ww_mutex_lock+0x28/0x32c
+ lr : drm_modeset_lock_all_ctx+0x1b0/0x3d0
+ sp : ffff80000805bb50
+ x29: ffff80000805bb50 x28: ffff327c00128000 x27: 0000000000000000
+ x26: 0000000000000000 x25: 0000000000000001 x24: 0000000000000018
+ x23: ffff80000805bc10 x22: ffff327c039c5ad8 x21: ffff327c039c5800
+ x20: ffff80000805bbe8 x19: 0000000000000018 x18: 0000000000000034
+ x17: 000000040044ffff x16: ffffc95d80cac920 x15: 0000000000000000
+ x14: 0000000000000315 x13: 0000000000000315 x12: 0000000000000000
+ x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000
+ x8 : ffff80000805bc28 x7 : 0000000000000000 x6 : 0000000000000000
+ x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
+ x2 : ffff327c00128000 x1 : 0000000000000000 x0 : 0000000000000018
+ Call trace:
+ ww_mutex_lock+0x28/0x32c
+ drm_modeset_lock_all_ctx+0x1b0/0x3d0
+ drm_atomic_helper_shutdown+0x70/0x134
+ msm_drv_shutdown+0x30/0x40
+ platform_shutdown+0x28/0x40
+ device_shutdown+0x148/0x350
+ kernel_power_off+0x38/0x80
+ __do_sys_reboot+0x288/0x2c0
+ __arm64_sys_reboot+0x28/0x34
+ invoke_syscall+0x48/0x114
+ el0_svc_common.constprop.0+0x44/0xec
+ do_el0_svc+0x2c/0xc0
+ el0_svc+0x2c/0x84
+ el0t_64_sync_handler+0x11c/0x150
+ el0t_64_sync+0x18c/0x190
+ Code: aa0103f4 d503201f d2800001 aa0103e3 (c8e37c02)
+ ---[ end trace 0000000000000000 ]---
+ Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
+ Kernel Offset: 0x495d77c00000 from 0xffff800008000000
+ PHYS_OFFSET: 0xffffcd8500000000
+ CPU features: 0x800,00c2a015,19801c82
+ Memory Limit: none
+ ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---
+
+Fixes: 9d5cbf5fe46e ("drm/msm: add shutdown support for display platform_driver")
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220816134612.916527-1-javierm@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/msm_drv.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
+index 916361c30d77..65df12fb9f95 100644
+--- a/drivers/gpu/drm/msm/msm_drv.c
++++ b/drivers/gpu/drm/msm/msm_drv.c
+@@ -1417,10 +1417,15 @@ static void msm_pdev_shutdown(struct platform_device *pdev)
+ struct drm_device *drm = platform_get_drvdata(pdev);
+ struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
+
+- if (!priv || !priv->kms)
+- return;
+-
+- drm_atomic_helper_shutdown(drm);
++ /*
++ * Shutdown the hw if we're far enough along where things might be on.
++ * If we run this too early, we'll end up panicking in any variety of
++ * places. Since we don't register the drm device until late in
++ * msm_drm_init, drm_dev->registered is used as an indicator that the
++ * shutdown will be successful.
++ */
++ if (drm && drm->registered)
++ drm_atomic_helper_shutdown(drm);
+ }
+
+ static const struct of_device_id dt_match[] = {
+--
+2.35.1
+
--- /dev/null
+From d9e8618369397c7e89876152775c27e811a06385 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 17:43:06 +0800
+Subject: drm/nouveau/nouveau_bo: fix potential memory leak in
+ nouveau_bo_alloc()
+
+From: Jianglei Nie <niejianglei2021@163.com>
+
+[ Upstream commit 6dc548745d5b5102e3c53dc5097296ac270b6c69 ]
+
+nouveau_bo_alloc() allocates a memory chunk for "nvbo" with kzalloc().
+When some error occurs, "nvbo" should be released. But when
+WARN_ON(pi < 0)) equals true, the function return ERR_PTR without
+releasing the "nvbo", which will lead to a memory leak.
+
+We should release the "nvbo" with kfree() if WARN_ON(pi < 0)) equals true.
+
+Signed-off-by: Jianglei Nie <niejianglei2021@163.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Reviewed-by: Lyude Paul <lyude@redhat.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220705094306.2244103-1-niejianglei2021@163.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/nouveau/nouveau_bo.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
+index 511fb8dfb4c4..da58230bcb1f 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
+@@ -281,8 +281,10 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
+ break;
+ }
+
+- if (WARN_ON(pi < 0))
++ if (WARN_ON(pi < 0)) {
++ kfree(nvbo);
+ return ERR_PTR(-EINVAL);
++ }
+
+ /* Disable compression if suitable settings couldn't be found. */
+ if (nvbo->comp && !vmm->page[pi].comp) {
+--
+2.35.1
+
--- /dev/null
+From 875b729a99d6686deb2383c3978ae0fc0ee3ee94 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 22 Jul 2022 22:43:48 +0800
+Subject: drm/omap: dss: Fix refcount leak bugs
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 8b42057e62120813ebe9274f508fa785b7cab33a ]
+
+In dss_init_ports() and __dss_uninit_ports(), we should call
+of_node_put() for the reference returned by of_graph_get_port_by_id()
+in fail path or when it is not used anymore.
+
+Fixes: 09bffa6e5192 ("drm: omap: use common OF graph helpers")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220722144348.1306569-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/omapdrm/dss/dss.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
+index d6a5862b4dbf..7567e2265aa3 100644
+--- a/drivers/gpu/drm/omapdrm/dss/dss.c
++++ b/drivers/gpu/drm/omapdrm/dss/dss.c
+@@ -1176,6 +1176,7 @@ static void __dss_uninit_ports(struct dss_device *dss, unsigned int num_ports)
+ default:
+ break;
+ }
++ of_node_put(port);
+ }
+ }
+
+@@ -1208,11 +1209,13 @@ static int dss_init_ports(struct dss_device *dss)
+ default:
+ break;
+ }
++ of_node_put(port);
+ }
+
+ return 0;
+
+ error:
++ of_node_put(port);
+ __dss_uninit_ports(dss, i);
+ return r;
+ }
+--
+2.35.1
+
--- /dev/null
+From 931e91ebe4448e887408dcc5716c1d826ce70a28 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 20:24:03 +0200
+Subject: drm: panel-orientation-quirks: Add quirk for Anbernic Win600
+
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+
+[ Upstream commit 770e19076065e079a32f33eb11be2057c87f1cde ]
+
+This device is another x86 gaming handheld, and as (hopefully) there is
+only one set of DMI IDs it's using DMI_EXACT_MATCH
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220803182402.1217293-1-maccraft123mc@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c
+index f5ab891731d0..083273736c83 100644
+--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
++++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
+@@ -128,6 +128,12 @@ static const struct dmi_system_id orientation_data[] = {
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "One S1003"),
+ },
+ .driver_data = (void *)&lcd800x1280_rightside_up,
++ }, { /* Anbernic Win600 */
++ .matches = {
++ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Anbernic"),
++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Win600"),
++ },
++ .driver_data = (void *)&lcd720x1280_rightside_up,
+ }, { /* Asus T100HA */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+--
+2.35.1
+
--- /dev/null
+From 40a9d2423617a82c7405d1d3a9bb74b5adc532f3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 11 Jul 2022 21:15:50 +0800
+Subject: drm:pl111: Add of_node_put() when breaking out of
+ for_each_available_child_of_node()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit e0686dc6f2252e009c455fe99e2ce9d62a60eb47 ]
+
+The reference 'child' in the iteration of for_each_available_child_of_node()
+is only escaped out into a local variable which is only used to check
+its value. So we still need to the of_node_put() when breaking of the
+for_each_available_child_of_node() which will automatically increase
+and decrease the refcount.
+
+Fixes: ca454bd42dc2 ("drm/pl111: Support the Versatile Express")
+Signed-off-by: Liang He <windhl@126.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220711131550.361350-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/pl111/pl111_versatile.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c
+index bdd883f4f0da..963a5d5e6987 100644
+--- a/drivers/gpu/drm/pl111/pl111_versatile.c
++++ b/drivers/gpu/drm/pl111/pl111_versatile.c
+@@ -402,6 +402,7 @@ static int pl111_vexpress_clcd_init(struct device *dev, struct device_node *np,
+ if (of_device_is_compatible(child, "arm,pl111")) {
+ has_coretile_clcd = true;
+ ct_clcd = child;
++ of_node_put(child);
+ break;
+ }
+ if (of_device_is_compatible(child, "arm,hdlcd")) {
+--
+2.35.1
+
--- /dev/null
+From 007513b5e9c725d64be1eceaf457538c6a109257 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 12:02:14 +0200
+Subject: drm: Prevent drm_copy_field() to attempt copying a NULL pointer
+
+From: Javier Martinez Canillas <javierm@redhat.com>
+
+[ Upstream commit f6ee30407e883042482ad4ad30da5eaba47872ee ]
+
+There are some struct drm_driver fields that are required by drivers since
+drm_copy_field() attempts to copy them to user-space via DRM_IOCTL_VERSION.
+
+But it can be possible that a driver has a bug and did not set some of the
+fields, which leads to drm_copy_field() attempting to copy a NULL pointer:
+
+[ +10.395966] Unable to handle kernel access to user memory outside uaccess routines at virtual address 0000000000000000
+[ +0.010955] Mem abort info:
+[ +0.002835] ESR = 0x0000000096000004
+[ +0.003872] EC = 0x25: DABT (current EL), IL = 32 bits
+[ +0.005395] SET = 0, FnV = 0
+[ +0.003113] EA = 0, S1PTW = 0
+[ +0.003182] FSC = 0x04: level 0 translation fault
+[ +0.004964] Data abort info:
+[ +0.002919] ISV = 0, ISS = 0x00000004
+[ +0.003886] CM = 0, WnR = 0
+[ +0.003040] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000115dad000
+[ +0.006536] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000
+[ +0.006925] Internal error: Oops: 96000004 [#1] SMP
+...
+[ +0.011113] pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[ +0.007061] pc : __pi_strlen+0x14/0x150
+[ +0.003895] lr : drm_copy_field+0x30/0x1a4
+[ +0.004156] sp : ffff8000094b3a50
+[ +0.003355] x29: ffff8000094b3a50 x28: ffff8000094b3b70 x27: 0000000000000040
+[ +0.007242] x26: ffff443743c2ba00 x25: 0000000000000000 x24: 0000000000000040
+[ +0.007243] x23: ffff443743c2ba00 x22: ffff8000094b3b70 x21: 0000000000000000
+[ +0.007241] x20: 0000000000000000 x19: ffff8000094b3b90 x18: 0000000000000000
+[ +0.007241] x17: 0000000000000000 x16: 0000000000000000 x15: 0000aaab14b9af40
+[ +0.007241] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000
+[ +0.007239] x11: 0000000000000000 x10: 0000000000000000 x9 : ffffa524ad67d4d8
+[ +0.007242] x8 : 0101010101010101 x7 : 7f7f7f7f7f7f7f7f x6 : 6c6e6263606e7141
+[ +0.007239] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
+[ +0.007241] x2 : 0000000000000000 x1 : ffff8000094b3b90 x0 : 0000000000000000
+[ +0.007240] Call trace:
+[ +0.002475] __pi_strlen+0x14/0x150
+[ +0.003537] drm_version+0x84/0xac
+[ +0.003448] drm_ioctl_kernel+0xa8/0x16c
+[ +0.003975] drm_ioctl+0x270/0x580
+[ +0.003448] __arm64_sys_ioctl+0xb8/0xfc
+[ +0.003978] invoke_syscall+0x78/0x100
+[ +0.003799] el0_svc_common.constprop.0+0x4c/0xf4
+[ +0.004767] do_el0_svc+0x38/0x4c
+[ +0.003357] el0_svc+0x34/0x100
+[ +0.003185] el0t_64_sync_handler+0x11c/0x150
+[ +0.004418] el0t_64_sync+0x190/0x194
+[ +0.003716] Code: 92402c04 b200c3e8 f13fc09f 5400088c (a9400c02)
+[ +0.006180] ---[ end trace 0000000000000000 ]---
+
+Reported-by: Peter Robinson <pbrobinson@gmail.com>
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220705100215.572498-3-javierm@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_ioctl.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
+index 5669c6cf7135..fb5e6f86dea2 100644
+--- a/drivers/gpu/drm/drm_ioctl.c
++++ b/drivers/gpu/drm/drm_ioctl.c
+@@ -474,6 +474,12 @@ static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value)
+ {
+ size_t len;
+
++ /* don't attempt to copy a NULL pointer */
++ if (WARN_ONCE(!value, "BUG: the value to copy was not set!")) {
++ *buf_len = 0;
++ return 0;
++ }
++
+ /* don't overflow userbuf */
+ len = strlen(value);
+ if (len > *buf_len)
+--
+2.35.1
+
--- /dev/null
+From a3435dc9e39d1f0c7bd80acd5f3e3eae8d98c03b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 12:02:13 +0200
+Subject: drm: Use size_t type for len variable in drm_copy_field()
+
+From: Javier Martinez Canillas <javierm@redhat.com>
+
+[ Upstream commit 94dc3471d1b2b58b3728558d0e3f264e9ce6ff59 ]
+
+The strlen() function returns a size_t which is an unsigned int on 32-bit
+arches and an unsigned long on 64-bit arches. But in the drm_copy_field()
+function, the strlen() return value is assigned to an 'int len' variable.
+
+Later, the len variable is passed as copy_from_user() third argument that
+is an unsigned long parameter as well.
+
+In theory, this can lead to an integer overflow via type conversion. Since
+the assignment happens to a signed int lvalue instead of a size_t lvalue.
+
+In practice though, that's unlikely since the values copied are set by DRM
+drivers and not controlled by userspace. But using a size_t for len is the
+correct thing to do anyways.
+
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Tested-by: Peter Robinson <pbrobinson@gmail.com>
+Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220705100215.572498-2-javierm@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_ioctl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
+index be4a52dc4d6f..5669c6cf7135 100644
+--- a/drivers/gpu/drm/drm_ioctl.c
++++ b/drivers/gpu/drm/drm_ioctl.c
+@@ -472,7 +472,7 @@ EXPORT_SYMBOL(drm_invalid_op);
+ */
+ static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value)
+ {
+- int len;
++ size_t len;
+
+ /* don't overflow userbuf */
+ len = strlen(value);
+--
+2.35.1
+
--- /dev/null
+From b2f42f8ce53abc75f7d10ea49e0e18f869194443 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 11 Jul 2022 19:39:23 +0200
+Subject: drm/vc4: txp: Protect device resources
+
+From: Maxime Ripard <maxime@cerno.tech>
+
+[ Upstream commit b7345c9799da578c150fde3072446e4049c39c41 ]
+
+Our current code now mixes some resources whose lifetime are tied to the
+device (clocks, IO mappings, etc.) and some that are tied to the DRM device
+(encoder, bridge).
+
+The device one will be freed at unbind time, but the DRM one will only be
+freed when the last user of the DRM device closes its file handle.
+
+So we end up with a time window during which we can call the encoder hooks,
+but we don't have access to the underlying resources and device.
+
+Let's protect all those sections with drm_dev_enter() and drm_dev_exit() so
+that we bail out if we are during that window.
+
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+Link: https://lore.kernel.org/r/20220711173939.1132294-54-maxime@cerno.tech
+Stable-dep-of: 84dfc46594b0 ("drm/panel: use 'select' for Ili9341 panel driver helpers")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/vc4/vc4_txp.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
+index 82beb8c159f2..e2b6eb437e98 100644
+--- a/drivers/gpu/drm/vc4/vc4_txp.c
++++ b/drivers/gpu/drm/vc4/vc4_txp.c
+@@ -15,6 +15,7 @@
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_drv.h>
+ #include <drm/drm_edid.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_fourcc.h>
+@@ -275,6 +276,7 @@ static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
+ static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
+ struct drm_atomic_state *state)
+ {
++ struct drm_device *drm = conn->dev;
+ struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state,
+ conn);
+ struct vc4_txp *txp = connector_to_vc4_txp(conn);
+@@ -282,6 +284,7 @@ static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
+ struct drm_display_mode *mode;
+ struct drm_framebuffer *fb;
+ u32 ctrl;
++ int idx;
+ int i;
+
+ if (WARN_ON(!conn_state->writeback_job))
+@@ -311,6 +314,9 @@ static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
+ */
+ ctrl |= TXP_ALPHA_INVERT;
+
++ if (!drm_dev_enter(drm, &idx))
++ return;
++
+ gem = drm_fb_cma_get_gem_obj(fb, 0);
+ TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
+ TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
+@@ -321,6 +327,8 @@ static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
+ TXP_WRITE(TXP_DST_CTRL, ctrl);
+
+ drm_writeback_queue_job(&txp->connector, conn_state);
++
++ drm_dev_exit(idx);
+ }
+
+ static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
+@@ -353,7 +361,12 @@ static const struct drm_connector_funcs vc4_txp_connector_funcs = {
+
+ static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
+ {
++ struct drm_device *drm = encoder->dev;
+ struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
++ int idx;
++
++ if (!drm_dev_enter(drm, &idx))
++ return;
+
+ if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+@@ -368,6 +381,8 @@ static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
+ }
+
+ TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
++
++ drm_dev_exit(idx);
+ }
+
+ static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
+@@ -452,6 +467,16 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data)
+ struct vc4_txp *txp = data;
+ struct vc4_crtc *vc4_crtc = &txp->base;
+
++ /*
++ * We don't need to protect the register access using
++ * drm_dev_enter() there because the interrupt handler lifetime
++ * is tied to the device itself, and not to the DRM device.
++ *
++ * So when the device will be gone, one of the first thing we
++ * will be doing will be to unregister the interrupt handler,
++ * and then unregister the DRM device. drm_dev_enter() would
++ * thus always succeed if we are here.
++ */
+ TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
+ vc4_crtc_handle_vblank(vc4_crtc);
+ drm_writeback_signal_completion(&txp->connector, 0);
+--
+2.35.1
+
--- /dev/null
+From e066d44026725690f4e98a3e5b3510ac3afa500b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 15:11:42 +0200
+Subject: drm/vc4: vec: Fix timings for VEC modes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
+
+[ Upstream commit 30d7565be96b3946c18a1ce3fd538f7946839092 ]
+
+This commit fixes vertical timings of the VEC (composite output) modes
+to accurately represent the 525-line ("NTSC") and 625-line ("PAL") ITU-R
+standards.
+
+Previous timings were actually defined as 502 and 601 lines, resulting
+in non-standard 62.69 Hz and 52 Hz signals being generated,
+respectively.
+
+Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
+Acked-by: Noralf Trønnes <noralf@tronnes.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220728-rpi-analog-tv-properties-v2-28-459522d653a7@cerno.tech
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/vc4/vc4_vec.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
+index 11fc3d6f66b1..4e2250b8fa23 100644
+--- a/drivers/gpu/drm/vc4/vc4_vec.c
++++ b/drivers/gpu/drm/vc4/vc4_vec.c
+@@ -256,7 +256,7 @@ static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
+ static const struct drm_display_mode ntsc_mode = {
+ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
+ 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
+- 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
++ 480, 480 + 7, 480 + 7 + 6, 525, 0,
+ DRM_MODE_FLAG_INTERLACE)
+ };
+
+@@ -278,7 +278,7 @@ static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
+ static const struct drm_display_mode pal_mode = {
+ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
+ 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
+- 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
++ 576, 576 + 4, 576 + 4 + 6, 625, 0,
+ DRM_MODE_FLAG_INTERLACE)
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 82419930a80087b17694b832cd70c9d37f33100e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 30 Jun 2022 23:07:18 +0300
+Subject: drm/virtio: Correct drm_gem_shmem_get_sg_table() error handling
+
+From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+
+[ Upstream commit 64b88afbd92fbf434759d1896a7cf705e1c00e79 ]
+
+Previous commit fixed checking of the ERR_PTR value returned by
+drm_gem_shmem_get_sg_table(), but it missed to zero out the shmem->pages,
+which will crash virtio_gpu_cleanup_object(). Add the missing zeroing of
+the shmem->pages.
+
+Fixes: c24968734abf ("drm/virtio: Fix NULL vs IS_ERR checking in virtio_gpu_object_shmem_init")
+Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/20220630200726.1884320-2-dmitry.osipenko@collabora.com
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/virtio/virtgpu_object.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c
+index 248ecd3006c3..7e75fb0fc7bd 100644
+--- a/drivers/gpu/drm/virtio/virtgpu_object.c
++++ b/drivers/gpu/drm/virtio/virtgpu_object.c
+@@ -169,6 +169,7 @@ static int virtio_gpu_object_shmem_init(struct virtio_gpu_device *vgdev,
+ shmem->pages = drm_gem_shmem_get_sg_table(&bo->base);
+ if (IS_ERR(shmem->pages)) {
+ drm_gem_shmem_unpin(&bo->base);
++ shmem->pages = NULL;
+ return PTR_ERR(shmem->pages);
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 7c050e0197cad8114b3bebabfaa8f0bf72e927dd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 17:47:51 -0300
+Subject: drm/vmwgfx: Fix memory leak in vmw_mksstat_add_ioctl()
+
+From: Rafael Mendonca <rafaelmendsr@gmail.com>
+
+[ Upstream commit a40c7f61d12fbd1e785e59140b9efd57127c0c33 ]
+
+If the copy of the description string from userspace fails, then the page
+for the instance descriptor doesn't get freed before returning -EFAULT,
+which leads to a memleak.
+
+Fixes: 7a7a933edd6c ("drm/vmwgfx: Introduce VMware mks-guest-stats")
+Signed-off-by: Rafael Mendonca <rafaelmendsr@gmail.com>
+Reviewed-by: Martin Krastev <krastevm@vmware.com>
+Signed-off-by: Zack Rusin <zackr@vmware.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220916204751.720716-1-rafaelmendsr@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/vmwgfx/vmwgfx_msg.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+index e50fb82a3030..47eb3a50dd08 100644
+--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+@@ -1076,6 +1076,7 @@ int vmw_mksstat_add_ioctl(struct drm_device *dev, void *data,
+
+ if (desc_len < 0) {
+ atomic_set(&dev_priv->mksstat_user_pids[slot], 0);
++ __free_page(page);
+ return -EFAULT;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 9b4f42c440d66c0a87a5af3855f0bc6c599fc8cd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 15:40:46 -0600
+Subject: dyndbg: drop EXPORTed dynamic_debug_exec_queries
+
+From: Jim Cromie <jim.cromie@gmail.com>
+
+[ Upstream commit e26ef3af964acfea311403126acee8c56c89e26b ]
+
+This exported fn is unused, and will not be needed. Lets dump it.
+
+The export was added to let drm control pr_debugs, as part of using
+them to avoid drm_debug_enabled overheads. But its better to just
+implement the drm.debug bitmap interface, then its available for
+everyone.
+
+Fixes: a2d375eda771 ("dyndbg: refine export, rename to dynamic_debug_exec_queries()")
+Fixes: 4c0d77828d4f ("dyndbg: export ddebug_exec_queries")
+Acked-by: Jason Baron <jbaron@akamai.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jim Cromie <jim.cromie@gmail.com>
+Link: https://lore.kernel.org/r/20220904214134.408619-10-jim.cromie@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/dynamic_debug.h | 9 ---------
+ lib/dynamic_debug.c | 29 -----------------------------
+ 2 files changed, 38 deletions(-)
+
+diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
+index f30b01aa9fa4..8d9eec5f6d8b 100644
+--- a/include/linux/dynamic_debug.h
++++ b/include/linux/dynamic_debug.h
+@@ -55,9 +55,6 @@ struct _ddebug {
+
+ #if defined(CONFIG_DYNAMIC_DEBUG_CORE)
+
+-/* exported for module authors to exercise >control */
+-int dynamic_debug_exec_queries(const char *query, const char *modname);
+-
+ int ddebug_add_module(struct _ddebug *tab, unsigned int n,
+ const char *modname);
+ extern int ddebug_remove_module(const char *mod_name);
+@@ -221,12 +218,6 @@ static inline int ddebug_dyndbg_module_param_cb(char *param, char *val,
+ rowsize, groupsize, buf, len, ascii); \
+ } while (0)
+
+-static inline int dynamic_debug_exec_queries(const char *query, const char *modname)
+-{
+- pr_warn("kernel not built with CONFIG_DYNAMIC_DEBUG_CORE\n");
+- return 0;
+-}
+-
+ #endif /* !CONFIG_DYNAMIC_DEBUG_CORE */
+
+ #endif
+diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
+index 60d453974155..2ca56c22a169 100644
+--- a/lib/dynamic_debug.c
++++ b/lib/dynamic_debug.c
+@@ -552,35 +552,6 @@ static int ddebug_exec_queries(char *query, const char *modname)
+ return nfound;
+ }
+
+-/**
+- * dynamic_debug_exec_queries - select and change dynamic-debug prints
+- * @query: query-string described in admin-guide/dynamic-debug-howto
+- * @modname: string containing module name, usually &module.mod_name
+- *
+- * This uses the >/proc/dynamic_debug/control reader, allowing module
+- * authors to modify their dynamic-debug callsites. The modname is
+- * canonically struct module.mod_name, but can also be null or a
+- * module-wildcard, for example: "drm*".
+- */
+-int dynamic_debug_exec_queries(const char *query, const char *modname)
+-{
+- int rc;
+- char *qry; /* writable copy of query */
+-
+- if (!query) {
+- pr_err("non-null query/command string expected\n");
+- return -EINVAL;
+- }
+- qry = kstrndup(query, PAGE_SIZE, GFP_KERNEL);
+- if (!qry)
+- return -ENOMEM;
+-
+- rc = ddebug_exec_queries(qry, modname);
+- kfree(qry);
+- return rc;
+-}
+-EXPORT_SYMBOL_GPL(dynamic_debug_exec_queries);
+-
+ #define PREFIX_SIZE 64
+
+ static int remaining(int wrote)
+--
+2.35.1
+
--- /dev/null
+From 6bf2cf85b515bed8e5645a862399b950d0e0e93d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 15:40:39 -0600
+Subject: dyndbg: fix module.dyndbg handling
+
+From: Jim Cromie <jim.cromie@gmail.com>
+
+[ Upstream commit 85d6b66d31c35158364058ee98fb69ab5bb6a6b1 ]
+
+For CONFIG_DYNAMIC_DEBUG=N, the ddebug_dyndbg_module_param_cb()
+stub-fn is too permissive:
+
+bash-5.1# modprobe drm JUNKdyndbg
+bash-5.1# modprobe drm dyndbgJUNK
+[ 42.933220] dyndbg param is supported only in CONFIG_DYNAMIC_DEBUG builds
+[ 42.937484] ACPI: bus type drm_connector registered
+
+This caused no ill effects, because unknown parameters are either
+ignored by default with an "unknown parameter" warning, or ignored
+because dyndbg allows its no-effect use on non-dyndbg builds.
+
+But since the code has an explicit feedback message, it should be
+issued accurately. Fix with strcmp for exact param-name match.
+
+Fixes: b48420c1d301 dynamic_debug: make dynamic-debug work for module initialization
+Reported-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
+Acked-by: Jason Baron <jbaron@akamai.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jim Cromie <jim.cromie@gmail.com>
+Link: https://lore.kernel.org/r/20220904214134.408619-3-jim.cromie@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/dynamic_debug.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
+index dce631e678dd..f30b01aa9fa4 100644
+--- a/include/linux/dynamic_debug.h
++++ b/include/linux/dynamic_debug.h
+@@ -201,7 +201,7 @@ static inline int ddebug_remove_module(const char *mod)
+ static inline int ddebug_dyndbg_module_param_cb(char *param, char *val,
+ const char *modname)
+ {
+- if (strstr(param, "dyndbg")) {
++ if (!strcmp(param, "dyndbg")) {
+ /* avoid pr_warn(), which wants pr_fmt() fully defined */
+ printk(KERN_WARNING "dyndbg param is supported only in "
+ "CONFIG_DYNAMIC_DEBUG builds\n");
+--
+2.35.1
+
--- /dev/null
+From 098b2ea3fdc77d8c2fe455eea437839340aa3f78 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 15:40:38 -0600
+Subject: dyndbg: fix static_branch manipulation
+
+From: Jim Cromie <jim.cromie@gmail.com>
+
+[ Upstream commit ee879be38bc87f8cedc79ae2742958db6533ca59 ]
+
+In https://lore.kernel.org/lkml/20211209150910.GA23668@axis.com/
+
+Vincent's patch commented on, and worked around, a bug toggling
+static_branch's, when a 2nd PRINTK-ish flag was added. The bug
+results in a premature static_branch_disable when the 1st of 2 flags
+was disabled.
+
+The cited commit computed newflags, but then in the JUMP_LABEL block,
+failed to use that result, instead using just one of the terms in it.
+Using newflags instead made the code work properly.
+
+This is Vincents test-case, reduced. It needs the 2nd flag to
+demonstrate the bug, but it's explanatory here.
+
+pt_test() {
+ echo 5 > /sys/module/dynamic_debug/verbose
+
+ site="module tcp" # just one callsite
+ echo " $site =_ " > /proc/dynamic_debug/control # clear it
+
+ # A B ~A ~B
+ for flg in +T +p "-T #broke here" -p; do
+ echo " $site $flg " > /proc/dynamic_debug/control
+ done;
+
+ # A B ~B ~A
+ for flg in +T +p "-p #broke here" -T; do
+ echo " $site $flg " > /proc/dynamic_debug/control
+ done
+}
+pt_test
+
+Fixes: 84da83a6ffc0 dyndbg: combine flags & mask into a struct, simplify with it
+CC: vincent.whitchurch@axis.com
+Acked-by: Jason Baron <jbaron@akamai.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jim Cromie <jim.cromie@gmail.com>
+Link: https://lore.kernel.org/r/20220904214134.408619-2-jim.cromie@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ lib/dynamic_debug.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
+index 84c16309cc63..00e6507972d8 100644
+--- a/lib/dynamic_debug.c
++++ b/lib/dynamic_debug.c
+@@ -207,10 +207,11 @@ static int ddebug_change(const struct ddebug_query *query,
+ continue;
+ #ifdef CONFIG_JUMP_LABEL
+ if (dp->flags & _DPRINTK_FLAGS_PRINT) {
+- if (!(modifiers->flags & _DPRINTK_FLAGS_PRINT))
++ if (!(newflags & _DPRINTK_FLAGS_PRINT))
+ static_branch_disable(&dp->key.dd_key_true);
+- } else if (modifiers->flags & _DPRINTK_FLAGS_PRINT)
++ } else if (newflags & _DPRINTK_FLAGS_PRINT) {
+ static_branch_enable(&dp->key.dd_key_true);
++ }
+ #endif
+ dp->flags = newflags;
+ v2pr_info("changed %s:%d [%s]%s =%s\n",
+--
+2.35.1
+
--- /dev/null
+From f62f95640b73c3b66c6b6c17652412bc2ba5b5c5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 15:40:44 -0600
+Subject: dyndbg: let query-modname override actual module name
+
+From: Jim Cromie <jim.cromie@gmail.com>
+
+[ Upstream commit e75ef56f74965f426dd819a41336b640ffdd8fbc ]
+
+dyndbg's control-parser: ddebug_parse_query(), requires that search
+terms: module, func, file, lineno, are used only once in a query; a
+thing cannot be named both foo and bar.
+
+The cited commit added an overriding module modname, taken from the
+module loader, which is authoritative. So it set query.module 1st,
+which disallowed its use in the query-string.
+
+But now, its useful to allow a module-load to enable classes across a
+whole (or part of) a subsystem at once.
+
+ # enable (dynamic-debug in) drm only
+ modprobe drm dyndbg="class DRM_UT_CORE +p"
+
+ # get drm_helper too
+ modprobe drm dyndbg="class DRM_UT_CORE module drm* +p"
+
+ # get everything that knows DRM_UT_CORE
+ modprobe drm dyndbg="class DRM_UT_CORE module * +p"
+
+ # also for boot-args:
+ drm.dyndbg="class DRM_UT_CORE module * +p"
+
+So convert the override into a default, by filling it only when/after
+the query-string omitted the module.
+
+NB: the query class FOO handling is forthcoming.
+
+Fixes: 8e59b5cfb9a6 dynamic_debug: add modname arg to exec_query callchain
+Acked-by: Jason Baron <jbaron@akamai.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jim Cromie <jim.cromie@gmail.com>
+Link: https://lore.kernel.org/r/20220904214134.408619-8-jim.cromie@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ lib/dynamic_debug.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
+index 00e6507972d8..60d453974155 100644
+--- a/lib/dynamic_debug.c
++++ b/lib/dynamic_debug.c
+@@ -380,10 +380,6 @@ static int ddebug_parse_query(char *words[], int nwords,
+ return -EINVAL;
+ }
+
+- if (modname)
+- /* support $modname.dyndbg=<multiple queries> */
+- query->module = modname;
+-
+ for (i = 0; i < nwords; i += 2) {
+ char *keyword = words[i];
+ char *arg = words[i+1];
+@@ -424,6 +420,13 @@ static int ddebug_parse_query(char *words[], int nwords,
+ if (rc)
+ return rc;
+ }
++ if (!query->module && modname)
++ /*
++ * support $modname.dyndbg=<multiple queries>, when
++ * not given in the query itself
++ */
++ query->module = modname;
++
+ vpr_info_dq(query, "parsed");
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From ecaaea6b76fe67db78057166a895c5065d9675dd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 11:12:36 -0700
+Subject: eth: alx: take rtnl_lock on resume
+
+From: Jakub Kicinski <kuba@kernel.org>
+
+[ Upstream commit 6ad1c94e1e7e374d88f0cfd77936dddb8339aaba ]
+
+Zbynek reports that alx trips an rtnl assertion on resume:
+
+ RTNL: assertion failed at net/core/dev.c (2891)
+ RIP: 0010:netif_set_real_num_tx_queues+0x1ac/0x1c0
+ Call Trace:
+ <TASK>
+ __alx_open+0x230/0x570 [alx]
+ alx_resume+0x54/0x80 [alx]
+ ? pci_legacy_resume+0x80/0x80
+ dpm_run_callback+0x4a/0x150
+ device_resume+0x8b/0x190
+ async_resume+0x19/0x30
+ async_run_entry_fn+0x30/0x130
+ process_one_work+0x1e5/0x3b0
+
+indeed the driver does not hold rtnl_lock during its internal close
+and re-open functions during suspend/resume. Note that this is not
+a huge bug as the driver implements its own locking, and does not
+implement changing the number of queues, but we need to silence
+the splat.
+
+Fixes: 4a5fe57e7751 ("alx: use fine-grained locking instead of RTNL")
+Reported-and-tested-by: Zbynek Michl <zbynek.michl@gmail.com>
+Reviewed-by: Niels Dossche <dossche.niels@gmail.com>
+Link: https://lore.kernel.org/r/20220928181236.1053043-1-kuba@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/atheros/alx/main.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/net/ethernet/atheros/alx/main.c b/drivers/net/ethernet/atheros/alx/main.c
+index 98a8698a3201..2ac5253ff89a 100644
+--- a/drivers/net/ethernet/atheros/alx/main.c
++++ b/drivers/net/ethernet/atheros/alx/main.c
+@@ -1912,11 +1912,14 @@ static int alx_suspend(struct device *dev)
+
+ if (!netif_running(alx->dev))
+ return 0;
++
++ rtnl_lock();
+ netif_device_detach(alx->dev);
+
+ mutex_lock(&alx->mtx);
+ __alx_stop(alx);
+ mutex_unlock(&alx->mtx);
++ rtnl_unlock();
+
+ return 0;
+ }
+@@ -1927,6 +1930,7 @@ static int alx_resume(struct device *dev)
+ struct alx_hw *hw = &alx->hw;
+ int err;
+
++ rtnl_lock();
+ mutex_lock(&alx->mtx);
+ alx_reset_phy(hw);
+
+@@ -1943,6 +1947,7 @@ static int alx_resume(struct device *dev)
+
+ unlock:
+ mutex_unlock(&alx->mtx);
++ rtnl_unlock();
+ return err;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 5ae7cd74fddb4324f5dbde9ad57df3ded72e69aa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 06:59:59 -0700
+Subject: eventfd: guard wake_up in eventfd fs calls as well
+
+From: Dylan Yudaken <dylany@fb.com>
+
+[ Upstream commit 9f0deaa12d832f488500a5afe9b912e9b3cfc432 ]
+
+Guard wakeups that the user can trigger, and that may end up triggering a
+call back into eventfd_signal. This is in addition to the current approach
+that only guards in eventfd_signal.
+
+Rename in_eventfd_signal -> in_eventfd at the same time to reflect this.
+
+Without this there would be a deadlock in the following code using libaio:
+
+int main()
+{
+ struct io_context *ctx = NULL;
+ struct iocb iocb;
+ struct iocb *iocbs[] = { &iocb };
+ int evfd;
+ uint64_t val = 1;
+
+ evfd = eventfd(0, EFD_CLOEXEC);
+ assert(!io_setup(2, &ctx));
+ io_prep_poll(&iocb, evfd, POLLIN);
+ io_set_eventfd(&iocb, evfd);
+ assert(1 == io_submit(ctx, 1, iocbs));
+ write(evfd, &val, 8);
+}
+
+Signed-off-by: Dylan Yudaken <dylany@fb.com>
+Reviewed-by: Jens Axboe <axboe@kernel.dk>
+Link: https://lore.kernel.org/r/20220816135959.1490641-1-dylany@fb.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/eventfd.c | 10 +++++++---
+ include/linux/eventfd.h | 2 +-
+ include/linux/sched.h | 2 +-
+ 3 files changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/fs/eventfd.c b/fs/eventfd.c
+index 3627dd7d25db..c0ffee99ad23 100644
+--- a/fs/eventfd.c
++++ b/fs/eventfd.c
+@@ -69,17 +69,17 @@ __u64 eventfd_signal(struct eventfd_ctx *ctx, __u64 n)
+ * it returns false, the eventfd_signal() call should be deferred to a
+ * safe context.
+ */
+- if (WARN_ON_ONCE(current->in_eventfd_signal))
++ if (WARN_ON_ONCE(current->in_eventfd))
+ return 0;
+
+ spin_lock_irqsave(&ctx->wqh.lock, flags);
+- current->in_eventfd_signal = 1;
++ current->in_eventfd = 1;
+ if (ULLONG_MAX - ctx->count < n)
+ n = ULLONG_MAX - ctx->count;
+ ctx->count += n;
+ if (waitqueue_active(&ctx->wqh))
+ wake_up_locked_poll(&ctx->wqh, EPOLLIN);
+- current->in_eventfd_signal = 0;
++ current->in_eventfd = 0;
+ spin_unlock_irqrestore(&ctx->wqh.lock, flags);
+
+ return n;
+@@ -253,8 +253,10 @@ static ssize_t eventfd_read(struct kiocb *iocb, struct iov_iter *to)
+ __set_current_state(TASK_RUNNING);
+ }
+ eventfd_ctx_do_read(ctx, &ucnt);
++ current->in_eventfd = 1;
+ if (waitqueue_active(&ctx->wqh))
+ wake_up_locked_poll(&ctx->wqh, EPOLLOUT);
++ current->in_eventfd = 0;
+ spin_unlock_irq(&ctx->wqh.lock);
+ if (unlikely(copy_to_iter(&ucnt, sizeof(ucnt), to) != sizeof(ucnt)))
+ return -EFAULT;
+@@ -301,8 +303,10 @@ static ssize_t eventfd_write(struct file *file, const char __user *buf, size_t c
+ }
+ if (likely(res > 0)) {
+ ctx->count += ucnt;
++ current->in_eventfd = 1;
+ if (waitqueue_active(&ctx->wqh))
+ wake_up_locked_poll(&ctx->wqh, EPOLLIN);
++ current->in_eventfd = 0;
+ }
+ spin_unlock_irq(&ctx->wqh.lock);
+
+diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h
+index 305d5f19093b..30eb30d6909b 100644
+--- a/include/linux/eventfd.h
++++ b/include/linux/eventfd.h
+@@ -46,7 +46,7 @@ void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt);
+
+ static inline bool eventfd_signal_allowed(void)
+ {
+- return !current->in_eventfd_signal;
++ return !current->in_eventfd;
+ }
+
+ #else /* CONFIG_EVENTFD */
+diff --git a/include/linux/sched.h b/include/linux/sched.h
+index dcba347cbffa..e418935f8db6 100644
+--- a/include/linux/sched.h
++++ b/include/linux/sched.h
+@@ -933,7 +933,7 @@ struct task_struct {
+ #endif
+ #ifdef CONFIG_EVENTFD
+ /* Recursion prevention for eventfd_signal() */
+- unsigned in_eventfd_signal:1;
++ unsigned in_eventfd:1;
+ #endif
+
+ unsigned long atomic_flags; /* Flags requiring atomic access. */
+--
+2.35.1
+
--- /dev/null
+From b7f079a9dddec99d297c48e9524239a1d4a0b737 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 17:29:33 +0200
+Subject: ext2: Use kvmalloc() for group descriptor array
+
+From: Jan Kara <jack@suse.cz>
+
+[ Upstream commit e7c7fbb9a8574ebd89cc05db49d806c7476863ad ]
+
+Array of group descriptor block buffers can get rather large. In theory
+in can reach 1MB for perfectly valid filesystem and even more for
+maliciously crafted ones. Use kvmalloc() to allocate the array to avoid
+straining memory allocator with large order allocations unnecessarily.
+
+Reported-by: syzbot+0f2f7e65a3007d39539f@syzkaller.appspotmail.com
+Signed-off-by: Jan Kara <jack@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ext2/super.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/fs/ext2/super.c b/fs/ext2/super.c
+index fd855574ef09..02d82f8fe85d 100644
+--- a/fs/ext2/super.c
++++ b/fs/ext2/super.c
+@@ -163,7 +163,7 @@ static void ext2_put_super (struct super_block * sb)
+ db_count = sbi->s_gdb_count;
+ for (i = 0; i < db_count; i++)
+ brelse(sbi->s_group_desc[i]);
+- kfree(sbi->s_group_desc);
++ kvfree(sbi->s_group_desc);
+ kfree(sbi->s_debts);
+ percpu_counter_destroy(&sbi->s_freeblocks_counter);
+ percpu_counter_destroy(&sbi->s_freeinodes_counter);
+@@ -1080,7 +1080,7 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent)
+ }
+ db_count = (sbi->s_groups_count + EXT2_DESC_PER_BLOCK(sb) - 1) /
+ EXT2_DESC_PER_BLOCK(sb);
+- sbi->s_group_desc = kmalloc_array(db_count,
++ sbi->s_group_desc = kvmalloc_array(db_count,
+ sizeof(struct buffer_head *),
+ GFP_KERNEL);
+ if (sbi->s_group_desc == NULL) {
+@@ -1206,7 +1206,7 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent)
+ for (i = 0; i < db_count; i++)
+ brelse(sbi->s_group_desc[i]);
+ failed_mount_group_desc:
+- kfree(sbi->s_group_desc);
++ kvfree(sbi->s_group_desc);
+ kfree(sbi->s_debts);
+ failed_mount:
+ brelse(bh);
+--
+2.35.1
+
--- /dev/null
+From ebff1dc71ffdc2112dbb9adef79b8f18b027da42 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 31 Jul 2022 20:24:53 -0700
+Subject: ext4: don't run ext4lazyinit for read-only filesystems
+
+From: Josh Triplett <josh@joshtriplett.org>
+
+[ Upstream commit 426d15ad11419066f7042ffa8fbf1b5c21a1ecbe ]
+
+On a read-only filesystem, we won't invoke the block allocator, so we
+don't need to prefetch the block bitmaps.
+
+This avoids starting and running the ext4lazyinit thread at all on a
+system with no read-write ext4 filesystems (for instance, a container VM
+with read-only filesystems underneath an overlayfs).
+
+Fixes: 21175ca434c5 ("ext4: make prefetch_block_bitmaps default")
+Signed-off-by: Josh Triplett <josh@joshtriplett.org>
+Reviewed-by: Lukas Czerner <lczerner@redhat.com>
+Link: https://lore.kernel.org/r/48b41da1498fcac3287e2e06b660680646c1c050.1659323972.git.josh@joshtriplett.org
+Signed-off-by: Theodore Ts'o <tytso@mit.edu>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ext4/super.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/fs/ext4/super.c b/fs/ext4/super.c
+index eec41990fa65..985d79fb6128 100644
+--- a/fs/ext4/super.c
++++ b/fs/ext4/super.c
+@@ -3587,9 +3587,9 @@ int ext4_register_li_request(struct super_block *sb,
+ goto out;
+ }
+
+- if (test_opt(sb, NO_PREFETCH_BLOCK_BITMAPS) &&
+- (first_not_zeroed == ngroups || sb_rdonly(sb) ||
+- !test_opt(sb, INIT_INODE_TABLE)))
++ if (sb_rdonly(sb) ||
++ (test_opt(sb, NO_PREFETCH_BLOCK_BITMAPS) &&
++ (first_not_zeroed == ngroups || !test_opt(sb, INIT_INODE_TABLE))))
+ goto out;
+
+ elr = ext4_li_request_new(sb, first_not_zeroed);
+--
+2.35.1
+
--- /dev/null
+From b3dbe3fe1f2586230740247f99f7eb6b21578ee8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 12:59:17 +0800
+Subject: f2fs: fix race condition on setting FI_NO_EXTENT flag
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit 07725adc55c0a414c10acb5c8c86cea34b95ddef ]
+
+The following scenarios exist.
+process A: process B:
+->f2fs_drop_extent_tree ->f2fs_update_extent_cache_range
+ ->f2fs_update_extent_tree_range
+ ->write_lock
+ ->set_inode_flag
+ ->is_inode_flag_set
+ ->__free_extent_tree // Shouldn't
+ // have been
+ // cleaned up
+ // here
+ ->write_lock
+
+In this case, the "FI_NO_EXTENT" flag is set between
+f2fs_update_extent_tree_range and is_inode_flag_set
+by other process. it leads to clearing the whole exten
+tree which should not have happened. And we fix it by
+move the setting it to the range of write_lock.
+
+Fixes:5f281fab9b9a3 ("f2fs: disable extent_cache for fcollapse/finsert inodes")
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Reviewed-by: Chao Yu <chao@kernel.org>
+Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/f2fs/extent_cache.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
+index 866e72b29bd5..761fd42c93f2 100644
+--- a/fs/f2fs/extent_cache.c
++++ b/fs/f2fs/extent_cache.c
+@@ -804,9 +804,8 @@ void f2fs_drop_extent_tree(struct inode *inode)
+ if (!f2fs_may_extent_tree(inode))
+ return;
+
+- set_inode_flag(inode, FI_NO_EXTENT);
+-
+ write_lock(&et->lock);
++ set_inode_flag(inode, FI_NO_EXTENT);
+ __free_extent_tree(sbi, et);
+ if (et->largest.len) {
+ et->largest.len = 0;
+--
+2.35.1
+
--- /dev/null
+From 553b0a923c6f9ace715df87e622f7151175047f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 21:28:46 +0800
+Subject: f2fs: fix to account FS_CP_DATA_IO correctly
+
+From: Chao Yu <chao@kernel.org>
+
+[ Upstream commit d80afefb17e01aa0c46a8eebc01882e0ebd8b0f6 ]
+
+f2fs_inode_info.cp_task was introduced for FS_CP_DATA_IO accounting
+since commit b0af6d491a6b ("f2fs: add app/fs io stat").
+
+However, cp_task usage coverage has been increased due to below
+commits:
+commit 040d2bb318d1 ("f2fs: fix to avoid deadloop if data_flush is on")
+commit 186857c5a14a ("f2fs: fix potential recursive call when enabling data_flush")
+
+So that, if data_flush mountoption is on, when data flush was
+triggered from background, the IO from data flush will be accounted
+as checkpoint IO type incorrectly.
+
+In order to fix this issue, this patch splits cp_task into two:
+a) cp_task: used for IO accounting
+b) wb_task: used to avoid deadlock
+
+Fixes: 040d2bb318d1 ("f2fs: fix to avoid deadloop if data_flush is on")
+Fixes: 186857c5a14a ("f2fs: fix potential recursive call when enabling data_flush")
+Signed-off-by: Chao Yu <chao@kernel.org>
+Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/f2fs/checkpoint.c | 13 +++++++++----
+ fs/f2fs/data.c | 4 ++--
+ fs/f2fs/f2fs.h | 4 +++-
+ fs/f2fs/segment.c | 2 +-
+ 4 files changed, 15 insertions(+), 8 deletions(-)
+
+diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c
+index 2917299d45c0..02840dadde5d 100644
+--- a/fs/f2fs/checkpoint.c
++++ b/fs/f2fs/checkpoint.c
+@@ -1062,7 +1062,8 @@ void f2fs_remove_dirty_inode(struct inode *inode)
+ spin_unlock(&sbi->inode_lock[type]);
+ }
+
+-int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type)
++int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type,
++ bool from_cp)
+ {
+ struct list_head *head;
+ struct inode *inode;
+@@ -1097,11 +1098,15 @@ int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type)
+ if (inode) {
+ unsigned long cur_ino = inode->i_ino;
+
+- F2FS_I(inode)->cp_task = current;
++ if (from_cp)
++ F2FS_I(inode)->cp_task = current;
++ F2FS_I(inode)->wb_task = current;
+
+ filemap_fdatawrite(inode->i_mapping);
+
+- F2FS_I(inode)->cp_task = NULL;
++ F2FS_I(inode)->wb_task = NULL;
++ if (from_cp)
++ F2FS_I(inode)->cp_task = NULL;
+
+ iput(inode);
+ /* We need to give cpu to another writers. */
+@@ -1230,7 +1235,7 @@ static int block_operations(struct f2fs_sb_info *sbi)
+ /* write all the dirty dentry pages */
+ if (get_pages(sbi, F2FS_DIRTY_DENTS)) {
+ f2fs_unlock_all(sbi);
+- err = f2fs_sync_dirty_inodes(sbi, DIR_INODE);
++ err = f2fs_sync_dirty_inodes(sbi, DIR_INODE, true);
+ if (err)
+ return err;
+ cond_resched();
+diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c
+index 4cf522120cb1..cfa6e1322e46 100644
+--- a/fs/f2fs/data.c
++++ b/fs/f2fs/data.c
+@@ -2862,7 +2862,7 @@ int f2fs_write_single_data_page(struct page *page, int *submitted,
+ }
+ unlock_page(page);
+ if (!S_ISDIR(inode->i_mode) && !IS_NOQUOTA(inode) &&
+- !F2FS_I(inode)->cp_task && allow_balance)
++ !F2FS_I(inode)->wb_task && allow_balance)
+ f2fs_balance_fs(sbi, need_balance_fs);
+
+ if (unlikely(f2fs_cp_error(sbi))) {
+@@ -3160,7 +3160,7 @@ static inline bool __should_serialize_io(struct inode *inode,
+ struct writeback_control *wbc)
+ {
+ /* to avoid deadlock in path of data flush */
+- if (F2FS_I(inode)->cp_task)
++ if (F2FS_I(inode)->wb_task)
+ return false;
+
+ if (!S_ISREG(inode->i_mode))
+diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h
+index 4caac78e2034..a144471c5316 100644
+--- a/fs/f2fs/f2fs.h
++++ b/fs/f2fs/f2fs.h
+@@ -749,6 +749,7 @@ struct f2fs_inode_info {
+ unsigned int clevel; /* maximum level of given file name */
+ struct task_struct *task; /* lookup and create consistency */
+ struct task_struct *cp_task; /* separate cp/wb IO stats*/
++ struct task_struct *wb_task; /* indicate inode is in context of writeback */
+ nid_t i_xattr_nid; /* node id that contains xattrs */
+ loff_t last_disk_size; /* lastly written file size */
+ spinlock_t i_size_lock; /* protect last_disk_size */
+@@ -3573,7 +3574,8 @@ int f2fs_recover_orphan_inodes(struct f2fs_sb_info *sbi);
+ int f2fs_get_valid_checkpoint(struct f2fs_sb_info *sbi);
+ void f2fs_update_dirty_page(struct inode *inode, struct page *page);
+ void f2fs_remove_dirty_inode(struct inode *inode);
+-int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type);
++int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type,
++ bool from_cp);
+ void f2fs_wait_on_all_pages(struct f2fs_sb_info *sbi, int type);
+ u64 f2fs_get_sectors_written(struct f2fs_sb_info *sbi);
+ int f2fs_write_checkpoint(struct f2fs_sb_info *sbi, struct cp_control *cpc);
+diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
+index e98c90bd8ef6..af810b2d5d90 100644
+--- a/fs/f2fs/segment.c
++++ b/fs/f2fs/segment.c
+@@ -575,7 +575,7 @@ void f2fs_balance_fs_bg(struct f2fs_sb_info *sbi, bool from_bg)
+ mutex_lock(&sbi->flush_lock);
+
+ blk_start_plug(&plug);
+- f2fs_sync_dirty_inodes(sbi, FILE_INODE);
++ f2fs_sync_dirty_inodes(sbi, FILE_INODE, false);
+ blk_finish_plug(&plug);
+
+ mutex_unlock(&sbi->flush_lock);
+--
+2.35.1
+
--- /dev/null
+From 2a9db409835a627e99012792e4c4f281d993c217 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 17:07:55 -0300
+Subject: firmware: google: Test spinlock on panic path to avoid lockups
+
+From: Guilherme G. Piccoli <gpiccoli@igalia.com>
+
+[ Upstream commit 3e081438b8e639cc76ef1a5ce0c1bd8a154082c7 ]
+
+Currently the gsmi driver registers a panic notifier as well as
+reboot and die notifiers. The callbacks registered are called in
+atomic and very limited context - for instance, panic disables
+preemption and local IRQs, also all secondary CPUs (not executing
+the panic path) are shutdown.
+
+With that said, taking a spinlock in this scenario is a dangerous
+invitation for lockup scenarios. So, fix that by checking if the
+spinlock is free to acquire in the panic notifier callback - if not,
+bail-out and avoid a potential hang.
+
+Fixes: 74c5b31c6618 ("driver: Google EFI SMI")
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: Ard Biesheuvel <ardb@kernel.org>
+Cc: David Gow <davidgow@google.com>
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: Julius Werner <jwerner@chromium.org>
+Cc: Petr Mladek <pmladek@suse.com>
+Reviewed-by: Evan Green <evgreen@chromium.org>
+Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
+Link: https://lore.kernel.org/r/20220909200755.189679-1-gpiccoli@igalia.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/firmware/google/gsmi.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/firmware/google/gsmi.c b/drivers/firmware/google/gsmi.c
+index adaa492c3d2d..4e2575dfeb90 100644
+--- a/drivers/firmware/google/gsmi.c
++++ b/drivers/firmware/google/gsmi.c
+@@ -681,6 +681,15 @@ static struct notifier_block gsmi_die_notifier = {
+ static int gsmi_panic_callback(struct notifier_block *nb,
+ unsigned long reason, void *arg)
+ {
++
++ /*
++ * Panic callbacks are executed with all other CPUs stopped,
++ * so we must not attempt to spin waiting for gsmi_dev.lock
++ * to be released.
++ */
++ if (spin_is_locked(&gsmi_dev.lock))
++ return NOTIFY_DONE;
++
+ gsmi_shutdown_reason(GSMI_SHUTDOWN_PANIC);
+ return NOTIFY_DONE;
+ }
+--
+2.35.1
+
--- /dev/null
+From cf6580fdd6bae2affcd55ef1381f35dd05945858 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 08:18:45 +0300
+Subject: fpga: prevent integer overflow in dfl_feature_ioctl_set_irq()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 939bc5453b8cbdde9f1e5110ce8309aedb1b501a ]
+
+The "hdr.count * sizeof(s32)" multiplication can overflow on 32 bit
+systems leading to memory corruption. Use array_size() to fix that.
+
+Fixes: 322b598be4d9 ("fpga: dfl: introduce interrupt trigger setting API")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Xu Yilun <yilun.xu@intel.com>
+Link: https://lore.kernel.org/r/YxBAtYCM38dM7yzI@kili
+Signed-off-by: Xu Yilun <yilun.xu@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/fpga/dfl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index f86666cf2c6a..c38143ef23c6 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -1864,7 +1864,7 @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
+ return -EINVAL;
+
+ fds = memdup_user((void __user *)(arg + sizeof(hdr)),
+- hdr.count * sizeof(s32));
++ array_size(hdr.count, sizeof(s32)));
+ if (IS_ERR(fds))
+ return PTR_ERR(fds);
+
+--
+2.35.1
+
--- /dev/null
+From 4ef6d4b203fd8d40436a03b773744af1c8acd509 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 15:43:13 -0400
+Subject: fs: dlm: fix race in lowcomms
+
+From: Alexander Aring <aahringo@redhat.com>
+
+[ Upstream commit 30ea3257e8766027c4d8d609dcbd256ff9a76073 ]
+
+This patch fixes a race between queue_work() in
+_dlm_lowcomms_commit_msg() and srcu_read_unlock(). The queue_work() can
+take the final reference of a dlm_msg and so msg->idx can contain
+garbage which is signaled by the following warning:
+
+[ 676.237050] ------------[ cut here ]------------
+[ 676.237052] WARNING: CPU: 0 PID: 1060 at include/linux/srcu.h:189 dlm_lowcomms_commit_msg+0x41/0x50
+[ 676.238945] Modules linked in: dlm_locktorture torture rpcsec_gss_krb5 intel_rapl_msr intel_rapl_common iTCO_wdt iTCO_vendor_support qxl kvm_intel drm_ttm_helper vmw_vsock_virtio_transport kvm vmw_vsock_virtio_transport_common ttm irqbypass crc32_pclmul joydev crc32c_intel serio_raw drm_kms_helper vsock virtio_scsi virtio_console virtio_balloon snd_pcm drm syscopyarea sysfillrect sysimgblt snd_timer fb_sys_fops i2c_i801 lpc_ich snd i2c_smbus soundcore pcspkr
+[ 676.244227] CPU: 0 PID: 1060 Comm: lock_torture_wr Not tainted 5.19.0-rc3+ #1546
+[ 676.245216] Hardware name: Red Hat KVM/RHEL-AV, BIOS 1.16.0-2.module+el8.7.0+15506+033991b0 04/01/2014
+[ 676.246460] RIP: 0010:dlm_lowcomms_commit_msg+0x41/0x50
+[ 676.247132] Code: fe ff ff ff 75 24 48 c7 c6 bd 0f 49 bb 48 c7 c7 38 7c 01 bd e8 00 e7 ca ff 89 de 48 c7 c7 60 78 01 bd e8 42 3d cd ff 5b 5d c3 <0f> 0b eb d8 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48
+[ 676.249253] RSP: 0018:ffffa401c18ffc68 EFLAGS: 00010282
+[ 676.249855] RAX: 0000000000000001 RBX: 00000000ffff8b76 RCX: 0000000000000006
+[ 676.250713] RDX: 0000000000000000 RSI: ffffffffbccf3a10 RDI: ffffffffbcc7b62e
+[ 676.251610] RBP: ffffa401c18ffc70 R08: 0000000000000001 R09: 0000000000000001
+[ 676.252481] R10: 0000000000000001 R11: 0000000000000001 R12: 0000000000000005
+[ 676.253421] R13: ffff8b76786ec370 R14: ffff8b76786ec370 R15: ffff8b76786ec480
+[ 676.254257] FS: 0000000000000000(0000) GS:ffff8b7777800000(0000) knlGS:0000000000000000
+[ 676.255239] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[ 676.255897] CR2: 00005590205d88b8 CR3: 000000017656c003 CR4: 0000000000770ee0
+[ 676.256734] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+[ 676.257567] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+[ 676.258397] PKRU: 55555554
+[ 676.258729] Call Trace:
+[ 676.259063] <TASK>
+[ 676.259354] dlm_midcomms_commit_mhandle+0xcc/0x110
+[ 676.259964] queue_bast+0x8b/0xb0
+[ 676.260423] grant_pending_locks+0x166/0x1b0
+[ 676.261007] _unlock_lock+0x75/0x90
+[ 676.261469] unlock_lock.isra.57+0x62/0xa0
+[ 676.262009] dlm_unlock+0x21e/0x330
+[ 676.262457] ? lock_torture_stats+0x80/0x80 [dlm_locktorture]
+[ 676.263183] torture_unlock+0x5a/0x90 [dlm_locktorture]
+[ 676.263815] ? preempt_count_sub+0xba/0x100
+[ 676.264361] ? complete+0x1d/0x60
+[ 676.264777] lock_torture_writer+0xb8/0x150 [dlm_locktorture]
+[ 676.265555] kthread+0x10a/0x130
+[ 676.266007] ? kthread_complete_and_exit+0x20/0x20
+[ 676.266616] ret_from_fork+0x22/0x30
+[ 676.267097] </TASK>
+[ 676.267381] irq event stamp: 9579855
+[ 676.267824] hardirqs last enabled at (9579863): [<ffffffffbb14e6f8>] __up_console_sem+0x58/0x60
+[ 676.268896] hardirqs last disabled at (9579872): [<ffffffffbb14e6dd>] __up_console_sem+0x3d/0x60
+[ 676.270008] softirqs last enabled at (9579798): [<ffffffffbc200349>] __do_softirq+0x349/0x4c7
+[ 676.271438] softirqs last disabled at (9579897): [<ffffffffbb0d54c0>] irq_exit_rcu+0xb0/0xf0
+[ 676.272796] ---[ end trace 0000000000000000 ]---
+
+I reproduced this warning with dlm_locktorture test which is currently
+not upstream. However this patch fix the issue by make a additional
+refcount between dlm_lowcomms_new_msg() and dlm_lowcomms_commit_msg().
+In case of the race the kref_put() in dlm_lowcomms_commit_msg() will be
+the final put.
+
+Signed-off-by: Alexander Aring <aahringo@redhat.com>
+Signed-off-by: David Teigland <teigland@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/dlm/lowcomms.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/fs/dlm/lowcomms.c b/fs/dlm/lowcomms.c
+index b11f695261f5..9d7078a1dc8b 100644
+--- a/fs/dlm/lowcomms.c
++++ b/fs/dlm/lowcomms.c
+@@ -1319,6 +1319,8 @@ struct dlm_msg *dlm_lowcomms_new_msg(int nodeid, int len, gfp_t allocation,
+ return NULL;
+ }
+
++ /* for dlm_lowcomms_commit_msg() */
++ kref_get(&msg->ref);
+ /* we assume if successful commit must called */
+ msg->idx = idx;
+ return msg;
+@@ -1353,6 +1355,8 @@ void dlm_lowcomms_commit_msg(struct dlm_msg *msg)
+ {
+ _dlm_lowcomms_commit_msg(msg);
+ srcu_read_unlock(&connections_srcu, msg->idx);
++ /* because dlm_lowcomms_new_msg() */
++ kref_put(&msg->ref, dlm_msg_release);
+ }
+
+ void dlm_lowcomms_put_msg(struct dlm_msg *msg)
+--
+2.35.1
+
--- /dev/null
+From 3fed658e73d0c7e04b5f0380cf88b31fbdbd9ce0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 12:32:06 -0700
+Subject: fscrypt: stop using keyrings subsystem for fscrypt_master_key
+
+From: Eric Biggers <ebiggers@google.com>
+
+[ Upstream commit d7e7b9af104c7b389a0c21eb26532511bce4b510 ]
+
+The approach of fs/crypto/ internally managing the fscrypt_master_key
+structs as the payloads of "struct key" objects contained in a
+"struct key" keyring has outlived its usefulness. The original idea was
+to simplify the code by reusing code from the keyrings subsystem.
+However, several issues have arisen that can't easily be resolved:
+
+- When a master key struct is destroyed, blk_crypto_evict_key() must be
+ called on any per-mode keys embedded in it. (This started being the
+ case when inline encryption support was added.) Yet, the keyrings
+ subsystem can arbitrarily delay the destruction of keys, even past the
+ time the filesystem was unmounted. Therefore, currently there is no
+ easy way to call blk_crypto_evict_key() when a master key is
+ destroyed. Currently, this is worked around by holding an extra
+ reference to the filesystem's request_queue(s). But it was overlooked
+ that the request_queue reference is *not* guaranteed to pin the
+ corresponding blk_crypto_profile too; for device-mapper devices that
+ support inline crypto, it doesn't. This can cause a use-after-free.
+
+- When the last inode that was using an incompletely-removed master key
+ is evicted, the master key removal is completed by removing the key
+ struct from the keyring. Currently this is done via key_invalidate().
+ Yet, key_invalidate() takes the key semaphore. This can deadlock when
+ called from the shrinker, since in fscrypt_ioctl_add_key(), memory is
+ allocated with GFP_KERNEL under the same semaphore.
+
+- More generally, the fact that the keyrings subsystem can arbitrarily
+ delay the destruction of keys (via garbage collection delay, or via
+ random processes getting temporary key references) is undesirable, as
+ it means we can't strictly guarantee that all secrets are ever wiped.
+
+- Doing the master key lookups via the keyrings subsystem results in the
+ key_permission LSM hook being called. fscrypt doesn't want this, as
+ all access control for encrypted files is designed to happen via the
+ files themselves, like any other files. The workaround which SELinux
+ users are using is to change their SELinux policy to grant key search
+ access to all domains. This works, but it is an odd extra step that
+ shouldn't really have to be done.
+
+The fix for all these issues is to change the implementation to what I
+should have done originally: don't use the keyrings subsystem to keep
+track of the filesystem's fscrypt_master_key structs. Instead, just
+store them in a regular kernel data structure, and rework the reference
+counting, locking, and lifetime accordingly. Retain support for
+RCU-mode key lookups by using a hash table. Replace fscrypt_sb_free()
+with fscrypt_sb_delete(), which releases the keys synchronously and runs
+a bit earlier during unmount, so that block devices are still available.
+
+A side effect of this patch is that neither the master keys themselves
+nor the filesystem keyrings will be listed in /proc/keys anymore.
+("Master key users" and the master key users keyrings will still be
+listed.) However, this was mostly an implementation detail, and it was
+intended just for debugging purposes. I don't know of anyone using it.
+
+This patch does *not* change how "master key users" (->mk_users) works;
+that still uses the keyrings subsystem. That is still needed for key
+quotas, and changing that isn't necessary to solve the issues listed
+above. If we decide to change that too, it would be a separate patch.
+
+I've marked this as fixing the original commit that added the fscrypt
+keyring, but as noted above the most important issue that this patch
+fixes wasn't introduced until the addition of inline encryption support.
+
+Fixes: 22d94f493bfb ("fscrypt: add FS_IOC_ADD_ENCRYPTION_KEY ioctl")
+Signed-off-by: Eric Biggers <ebiggers@google.com>
+Link: https://lore.kernel.org/r/20220901193208.138056-2-ebiggers@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/crypto/fscrypt_private.h | 71 ++++--
+ fs/crypto/hooks.c | 10 +-
+ fs/crypto/keyring.c | 486 +++++++++++++++++++-----------------
+ fs/crypto/keysetup.c | 81 +++---
+ fs/crypto/policy.c | 8 +-
+ fs/super.c | 2 +-
+ include/linux/fs.h | 2 +-
+ include/linux/fscrypt.h | 4 +-
+ 8 files changed, 353 insertions(+), 311 deletions(-)
+
+diff --git a/fs/crypto/fscrypt_private.h b/fs/crypto/fscrypt_private.h
+index cb25ef0cdf1f..373c434b375c 100644
+--- a/fs/crypto/fscrypt_private.h
++++ b/fs/crypto/fscrypt_private.h
+@@ -220,7 +220,7 @@ struct fscrypt_info {
+ * will be NULL if the master key was found in a process-subscribed
+ * keyring rather than in the filesystem-level keyring.
+ */
+- struct key *ci_master_key;
++ struct fscrypt_master_key *ci_master_key;
+
+ /*
+ * Link in list of inodes that were unlocked with the master key.
+@@ -430,6 +430,40 @@ struct fscrypt_master_key_secret {
+ */
+ struct fscrypt_master_key {
+
++ /*
++ * Back-pointer to the super_block of the filesystem to which this
++ * master key has been added. Only valid if ->mk_active_refs > 0.
++ */
++ struct super_block *mk_sb;
++
++ /*
++ * Link in ->mk_sb->s_master_keys->key_hashtable.
++ * Only valid if ->mk_active_refs > 0.
++ */
++ struct hlist_node mk_node;
++
++ /* Semaphore that protects ->mk_secret and ->mk_users */
++ struct rw_semaphore mk_sem;
++
++ /*
++ * Active and structural reference counts. An active ref guarantees
++ * that the struct continues to exist, continues to be in the keyring
++ * ->mk_sb->s_master_keys, and that any embedded subkeys (e.g.
++ * ->mk_direct_keys) that have been prepared continue to exist.
++ * A structural ref only guarantees that the struct continues to exist.
++ *
++ * There is one active ref associated with ->mk_secret being present,
++ * and one active ref for each inode in ->mk_decrypted_inodes.
++ *
++ * There is one structural ref associated with the active refcount being
++ * nonzero. Finding a key in the keyring also takes a structural ref,
++ * which is then held temporarily while the key is operated on.
++ */
++ refcount_t mk_active_refs;
++ refcount_t mk_struct_refs;
++
++ struct rcu_head mk_rcu_head;
++
+ /*
+ * The secret key material. After FS_IOC_REMOVE_ENCRYPTION_KEY is
+ * executed, this is wiped and no new inodes can be unlocked with this
+@@ -438,7 +472,10 @@ struct fscrypt_master_key {
+ * FS_IOC_REMOVE_ENCRYPTION_KEY can be retried, or
+ * FS_IOC_ADD_ENCRYPTION_KEY can add the secret again.
+ *
+- * Locking: protected by this master key's key->sem.
++ * While ->mk_secret is present, one ref in ->mk_active_refs is held.
++ *
++ * Locking: protected by ->mk_sem. The manipulation of ->mk_active_refs
++ * associated with this field is protected by ->mk_sem as well.
+ */
+ struct fscrypt_master_key_secret mk_secret;
+
+@@ -459,22 +496,12 @@ struct fscrypt_master_key {
+ *
+ * This is NULL for v1 policy keys; those can only be added by root.
+ *
+- * Locking: in addition to this keyring's own semaphore, this is
+- * protected by this master key's key->sem, so we can do atomic
+- * search+insert. It can also be searched without taking any locks, but
+- * in that case the returned key may have already been removed.
++ * Locking: protected by ->mk_sem. (We don't just rely on the keyrings
++ * subsystem semaphore ->mk_users->sem, as we need support for atomic
++ * search+insert along with proper synchronization with ->mk_secret.)
+ */
+ struct key *mk_users;
+
+- /*
+- * Length of ->mk_decrypted_inodes, plus one if mk_secret is present.
+- * Once this goes to 0, the master key is removed from ->s_master_keys.
+- * The 'struct fscrypt_master_key' will continue to live as long as the
+- * 'struct key' whose payload it is, but we won't let this reference
+- * count rise again.
+- */
+- refcount_t mk_refcount;
+-
+ /*
+ * List of inodes that were unlocked using this key. This allows the
+ * inodes to be evicted efficiently if the key is removed.
+@@ -500,10 +527,10 @@ static inline bool
+ is_master_key_secret_present(const struct fscrypt_master_key_secret *secret)
+ {
+ /*
+- * The READ_ONCE() is only necessary for fscrypt_drop_inode() and
+- * fscrypt_key_describe(). These run in atomic context, so they can't
+- * take the key semaphore and thus 'secret' can change concurrently
+- * which would be a data race. But they only need to know whether the
++ * The READ_ONCE() is only necessary for fscrypt_drop_inode().
++ * fscrypt_drop_inode() runs in atomic context, so it can't take the key
++ * semaphore and thus 'secret' can change concurrently which would be a
++ * data race. But fscrypt_drop_inode() only need to know whether the
+ * secret *was* present at the time of check, so READ_ONCE() suffices.
+ */
+ return READ_ONCE(secret->size) != 0;
+@@ -532,7 +559,11 @@ static inline int master_key_spec_len(const struct fscrypt_key_specifier *spec)
+ return 0;
+ }
+
+-struct key *
++void fscrypt_put_master_key(struct fscrypt_master_key *mk);
++
++void fscrypt_put_master_key_activeref(struct fscrypt_master_key *mk);
++
++struct fscrypt_master_key *
+ fscrypt_find_master_key(struct super_block *sb,
+ const struct fscrypt_key_specifier *mk_spec);
+
+diff --git a/fs/crypto/hooks.c b/fs/crypto/hooks.c
+index af74599ae1cf..be5c650e4957 100644
+--- a/fs/crypto/hooks.c
++++ b/fs/crypto/hooks.c
+@@ -5,8 +5,6 @@
+ * Encryption hooks for higher-level filesystem operations.
+ */
+
+-#include <linux/key.h>
+-
+ #include "fscrypt_private.h"
+
+ /**
+@@ -142,7 +140,6 @@ int fscrypt_prepare_setflags(struct inode *inode,
+ unsigned int oldflags, unsigned int flags)
+ {
+ struct fscrypt_info *ci;
+- struct key *key;
+ struct fscrypt_master_key *mk;
+ int err;
+
+@@ -158,14 +155,13 @@ int fscrypt_prepare_setflags(struct inode *inode,
+ ci = inode->i_crypt_info;
+ if (ci->ci_policy.version != FSCRYPT_POLICY_V2)
+ return -EINVAL;
+- key = ci->ci_master_key;
+- mk = key->payload.data[0];
+- down_read(&key->sem);
++ mk = ci->ci_master_key;
++ down_read(&mk->mk_sem);
+ if (is_master_key_secret_present(&mk->mk_secret))
+ err = fscrypt_derive_dirhash_key(ci, mk);
+ else
+ err = -ENOKEY;
+- up_read(&key->sem);
++ up_read(&mk->mk_sem);
+ return err;
+ }
+ return 0;
+diff --git a/fs/crypto/keyring.c b/fs/crypto/keyring.c
+index 0b3ffbb4faf4..175b071beaf8 100644
+--- a/fs/crypto/keyring.c
++++ b/fs/crypto/keyring.c
+@@ -18,6 +18,7 @@
+ * information about these ioctls.
+ */
+
++#include <asm/unaligned.h>
+ #include <crypto/skcipher.h>
+ #include <linux/key-type.h>
+ #include <linux/random.h>
+@@ -25,6 +26,18 @@
+
+ #include "fscrypt_private.h"
+
++/* The master encryption keys for a filesystem (->s_master_keys) */
++struct fscrypt_keyring {
++ /*
++ * Lock that protects ->key_hashtable. It does *not* protect the
++ * fscrypt_master_key structs themselves.
++ */
++ spinlock_t lock;
++
++ /* Hash table that maps fscrypt_key_specifier to fscrypt_master_key */
++ struct hlist_head key_hashtable[128];
++};
++
+ static void wipe_master_key_secret(struct fscrypt_master_key_secret *secret)
+ {
+ fscrypt_destroy_hkdf(&secret->hkdf);
+@@ -38,20 +51,70 @@ static void move_master_key_secret(struct fscrypt_master_key_secret *dst,
+ memzero_explicit(src, sizeof(*src));
+ }
+
+-static void free_master_key(struct fscrypt_master_key *mk)
++static void fscrypt_free_master_key(struct rcu_head *head)
++{
++ struct fscrypt_master_key *mk =
++ container_of(head, struct fscrypt_master_key, mk_rcu_head);
++ /*
++ * The master key secret and any embedded subkeys should have already
++ * been wiped when the last active reference to the fscrypt_master_key
++ * struct was dropped; doing it here would be unnecessarily late.
++ * Nevertheless, use kfree_sensitive() in case anything was missed.
++ */
++ kfree_sensitive(mk);
++}
++
++void fscrypt_put_master_key(struct fscrypt_master_key *mk)
++{
++ if (!refcount_dec_and_test(&mk->mk_struct_refs))
++ return;
++ /*
++ * No structural references left, so free ->mk_users, and also free the
++ * fscrypt_master_key struct itself after an RCU grace period ensures
++ * that concurrent keyring lookups can no longer find it.
++ */
++ WARN_ON(refcount_read(&mk->mk_active_refs) != 0);
++ key_put(mk->mk_users);
++ mk->mk_users = NULL;
++ call_rcu(&mk->mk_rcu_head, fscrypt_free_master_key);
++}
++
++void fscrypt_put_master_key_activeref(struct fscrypt_master_key *mk)
+ {
++ struct super_block *sb = mk->mk_sb;
++ struct fscrypt_keyring *keyring = sb->s_master_keys;
+ size_t i;
+
+- wipe_master_key_secret(&mk->mk_secret);
++ if (!refcount_dec_and_test(&mk->mk_active_refs))
++ return;
++ /*
++ * No active references left, so complete the full removal of this
++ * fscrypt_master_key struct by removing it from the keyring and
++ * destroying any subkeys embedded in it.
++ */
++
++ spin_lock(&keyring->lock);
++ hlist_del_rcu(&mk->mk_node);
++ spin_unlock(&keyring->lock);
++
++ /*
++ * ->mk_active_refs == 0 implies that ->mk_secret is not present and
++ * that ->mk_decrypted_inodes is empty.
++ */
++ WARN_ON(is_master_key_secret_present(&mk->mk_secret));
++ WARN_ON(!list_empty(&mk->mk_decrypted_inodes));
+
+ for (i = 0; i <= FSCRYPT_MODE_MAX; i++) {
+ fscrypt_destroy_prepared_key(&mk->mk_direct_keys[i]);
+ fscrypt_destroy_prepared_key(&mk->mk_iv_ino_lblk_64_keys[i]);
+ fscrypt_destroy_prepared_key(&mk->mk_iv_ino_lblk_32_keys[i]);
+ }
++ memzero_explicit(&mk->mk_ino_hash_key,
++ sizeof(mk->mk_ino_hash_key));
++ mk->mk_ino_hash_key_initialized = false;
+
+- key_put(mk->mk_users);
+- kfree_sensitive(mk);
++ /* Drop the structural ref associated with the active refs. */
++ fscrypt_put_master_key(mk);
+ }
+
+ static inline bool valid_key_spec(const struct fscrypt_key_specifier *spec)
+@@ -61,44 +124,6 @@ static inline bool valid_key_spec(const struct fscrypt_key_specifier *spec)
+ return master_key_spec_len(spec) != 0;
+ }
+
+-static int fscrypt_key_instantiate(struct key *key,
+- struct key_preparsed_payload *prep)
+-{
+- key->payload.data[0] = (struct fscrypt_master_key *)prep->data;
+- return 0;
+-}
+-
+-static void fscrypt_key_destroy(struct key *key)
+-{
+- free_master_key(key->payload.data[0]);
+-}
+-
+-static void fscrypt_key_describe(const struct key *key, struct seq_file *m)
+-{
+- seq_puts(m, key->description);
+-
+- if (key_is_positive(key)) {
+- const struct fscrypt_master_key *mk = key->payload.data[0];
+-
+- if (!is_master_key_secret_present(&mk->mk_secret))
+- seq_puts(m, ": secret removed");
+- }
+-}
+-
+-/*
+- * Type of key in ->s_master_keys. Each key of this type represents a master
+- * key which has been added to the filesystem. Its payload is a
+- * 'struct fscrypt_master_key'. The "." prefix in the key type name prevents
+- * users from adding keys of this type via the keyrings syscalls rather than via
+- * the intended method of FS_IOC_ADD_ENCRYPTION_KEY.
+- */
+-static struct key_type key_type_fscrypt = {
+- .name = "._fscrypt",
+- .instantiate = fscrypt_key_instantiate,
+- .destroy = fscrypt_key_destroy,
+- .describe = fscrypt_key_describe,
+-};
+-
+ static int fscrypt_user_key_instantiate(struct key *key,
+ struct key_preparsed_payload *prep)
+ {
+@@ -131,32 +156,6 @@ static struct key_type key_type_fscrypt_user = {
+ .describe = fscrypt_user_key_describe,
+ };
+
+-/* Search ->s_master_keys or ->mk_users */
+-static struct key *search_fscrypt_keyring(struct key *keyring,
+- struct key_type *type,
+- const char *description)
+-{
+- /*
+- * We need to mark the keyring reference as "possessed" so that we
+- * acquire permission to search it, via the KEY_POS_SEARCH permission.
+- */
+- key_ref_t keyref = make_key_ref(keyring, true /* possessed */);
+-
+- keyref = keyring_search(keyref, type, description, false);
+- if (IS_ERR(keyref)) {
+- if (PTR_ERR(keyref) == -EAGAIN || /* not found */
+- PTR_ERR(keyref) == -EKEYREVOKED) /* recently invalidated */
+- keyref = ERR_PTR(-ENOKEY);
+- return ERR_CAST(keyref);
+- }
+- return key_ref_to_ptr(keyref);
+-}
+-
+-#define FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE \
+- (CONST_STRLEN("fscrypt-") + sizeof_field(struct super_block, s_id))
+-
+-#define FSCRYPT_MK_DESCRIPTION_SIZE (2 * FSCRYPT_KEY_IDENTIFIER_SIZE + 1)
+-
+ #define FSCRYPT_MK_USERS_DESCRIPTION_SIZE \
+ (CONST_STRLEN("fscrypt-") + 2 * FSCRYPT_KEY_IDENTIFIER_SIZE + \
+ CONST_STRLEN("-users") + 1)
+@@ -164,21 +163,6 @@ static struct key *search_fscrypt_keyring(struct key *keyring,
+ #define FSCRYPT_MK_USER_DESCRIPTION_SIZE \
+ (2 * FSCRYPT_KEY_IDENTIFIER_SIZE + CONST_STRLEN(".uid.") + 10 + 1)
+
+-static void format_fs_keyring_description(
+- char description[FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE],
+- const struct super_block *sb)
+-{
+- sprintf(description, "fscrypt-%s", sb->s_id);
+-}
+-
+-static void format_mk_description(
+- char description[FSCRYPT_MK_DESCRIPTION_SIZE],
+- const struct fscrypt_key_specifier *mk_spec)
+-{
+- sprintf(description, "%*phN",
+- master_key_spec_len(mk_spec), (u8 *)&mk_spec->u);
+-}
+-
+ static void format_mk_users_keyring_description(
+ char description[FSCRYPT_MK_USERS_DESCRIPTION_SIZE],
+ const u8 mk_identifier[FSCRYPT_KEY_IDENTIFIER_SIZE])
+@@ -199,20 +183,15 @@ static void format_mk_user_description(
+ /* Create ->s_master_keys if needed. Synchronized by fscrypt_add_key_mutex. */
+ static int allocate_filesystem_keyring(struct super_block *sb)
+ {
+- char description[FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE];
+- struct key *keyring;
++ struct fscrypt_keyring *keyring;
+
+ if (sb->s_master_keys)
+ return 0;
+
+- format_fs_keyring_description(description, sb);
+- keyring = keyring_alloc(description, GLOBAL_ROOT_UID, GLOBAL_ROOT_GID,
+- current_cred(), KEY_POS_SEARCH |
+- KEY_USR_SEARCH | KEY_USR_READ | KEY_USR_VIEW,
+- KEY_ALLOC_NOT_IN_QUOTA, NULL, NULL);
+- if (IS_ERR(keyring))
+- return PTR_ERR(keyring);
+-
++ keyring = kzalloc(sizeof(*keyring), GFP_KERNEL);
++ if (!keyring)
++ return -ENOMEM;
++ spin_lock_init(&keyring->lock);
+ /*
+ * Pairs with the smp_load_acquire() in fscrypt_find_master_key().
+ * I.e., here we publish ->s_master_keys with a RELEASE barrier so that
+@@ -222,21 +201,75 @@ static int allocate_filesystem_keyring(struct super_block *sb)
+ return 0;
+ }
+
+-void fscrypt_sb_free(struct super_block *sb)
++/*
++ * This is called at unmount time to release all encryption keys that have been
++ * added to the filesystem, along with the keyring that contains them.
++ *
++ * Note that besides clearing and freeing memory, this might need to evict keys
++ * from the keyslots of an inline crypto engine. Therefore, this must be called
++ * while the filesystem's underlying block device(s) are still available.
++ */
++void fscrypt_sb_delete(struct super_block *sb)
+ {
+- key_put(sb->s_master_keys);
++ struct fscrypt_keyring *keyring = sb->s_master_keys;
++ size_t i;
++
++ if (!keyring)
++ return;
++
++ for (i = 0; i < ARRAY_SIZE(keyring->key_hashtable); i++) {
++ struct hlist_head *bucket = &keyring->key_hashtable[i];
++ struct fscrypt_master_key *mk;
++ struct hlist_node *tmp;
++
++ hlist_for_each_entry_safe(mk, tmp, bucket, mk_node) {
++ /*
++ * Since all inodes were already evicted, every key
++ * remaining in the keyring should have an empty inode
++ * list, and should only still be in the keyring due to
++ * the single active ref associated with ->mk_secret.
++ * There should be no structural refs beyond the one
++ * associated with the active ref.
++ */
++ WARN_ON(refcount_read(&mk->mk_active_refs) != 1);
++ WARN_ON(refcount_read(&mk->mk_struct_refs) != 1);
++ WARN_ON(!is_master_key_secret_present(&mk->mk_secret));
++ wipe_master_key_secret(&mk->mk_secret);
++ fscrypt_put_master_key_activeref(mk);
++ }
++ }
++ kfree_sensitive(keyring);
+ sb->s_master_keys = NULL;
+ }
+
++static struct hlist_head *
++fscrypt_mk_hash_bucket(struct fscrypt_keyring *keyring,
++ const struct fscrypt_key_specifier *mk_spec)
++{
++ /*
++ * Since key specifiers should be "random" values, it is sufficient to
++ * use a trivial hash function that just takes the first several bits of
++ * the key specifier.
++ */
++ unsigned long i = get_unaligned((unsigned long *)&mk_spec->u);
++
++ return &keyring->key_hashtable[i % ARRAY_SIZE(keyring->key_hashtable)];
++}
++
+ /*
+- * Find the specified master key in ->s_master_keys.
+- * Returns ERR_PTR(-ENOKEY) if not found.
++ * Find the specified master key struct in ->s_master_keys and take a structural
++ * ref to it. The structural ref guarantees that the key struct continues to
++ * exist, but it does *not* guarantee that ->s_master_keys continues to contain
++ * the key struct. The structural ref needs to be dropped by
++ * fscrypt_put_master_key(). Returns NULL if the key struct is not found.
+ */
+-struct key *fscrypt_find_master_key(struct super_block *sb,
+- const struct fscrypt_key_specifier *mk_spec)
++struct fscrypt_master_key *
++fscrypt_find_master_key(struct super_block *sb,
++ const struct fscrypt_key_specifier *mk_spec)
+ {
+- struct key *keyring;
+- char description[FSCRYPT_MK_DESCRIPTION_SIZE];
++ struct fscrypt_keyring *keyring;
++ struct hlist_head *bucket;
++ struct fscrypt_master_key *mk;
+
+ /*
+ * Pairs with the smp_store_release() in allocate_filesystem_keyring().
+@@ -246,10 +279,38 @@ struct key *fscrypt_find_master_key(struct super_block *sb,
+ */
+ keyring = smp_load_acquire(&sb->s_master_keys);
+ if (keyring == NULL)
+- return ERR_PTR(-ENOKEY); /* No keyring yet, so no keys yet. */
+-
+- format_mk_description(description, mk_spec);
+- return search_fscrypt_keyring(keyring, &key_type_fscrypt, description);
++ return NULL; /* No keyring yet, so no keys yet. */
++
++ bucket = fscrypt_mk_hash_bucket(keyring, mk_spec);
++ rcu_read_lock();
++ switch (mk_spec->type) {
++ case FSCRYPT_KEY_SPEC_TYPE_DESCRIPTOR:
++ hlist_for_each_entry_rcu(mk, bucket, mk_node) {
++ if (mk->mk_spec.type ==
++ FSCRYPT_KEY_SPEC_TYPE_DESCRIPTOR &&
++ memcmp(mk->mk_spec.u.descriptor,
++ mk_spec->u.descriptor,
++ FSCRYPT_KEY_DESCRIPTOR_SIZE) == 0 &&
++ refcount_inc_not_zero(&mk->mk_struct_refs))
++ goto out;
++ }
++ break;
++ case FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER:
++ hlist_for_each_entry_rcu(mk, bucket, mk_node) {
++ if (mk->mk_spec.type ==
++ FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER &&
++ memcmp(mk->mk_spec.u.identifier,
++ mk_spec->u.identifier,
++ FSCRYPT_KEY_IDENTIFIER_SIZE) == 0 &&
++ refcount_inc_not_zero(&mk->mk_struct_refs))
++ goto out;
++ }
++ break;
++ }
++ mk = NULL;
++out:
++ rcu_read_unlock();
++ return mk;
+ }
+
+ static int allocate_master_key_users_keyring(struct fscrypt_master_key *mk)
+@@ -277,17 +338,30 @@ static int allocate_master_key_users_keyring(struct fscrypt_master_key *mk)
+ static struct key *find_master_key_user(struct fscrypt_master_key *mk)
+ {
+ char description[FSCRYPT_MK_USER_DESCRIPTION_SIZE];
++ key_ref_t keyref;
+
+ format_mk_user_description(description, mk->mk_spec.u.identifier);
+- return search_fscrypt_keyring(mk->mk_users, &key_type_fscrypt_user,
+- description);
++
++ /*
++ * We need to mark the keyring reference as "possessed" so that we
++ * acquire permission to search it, via the KEY_POS_SEARCH permission.
++ */
++ keyref = keyring_search(make_key_ref(mk->mk_users, true /*possessed*/),
++ &key_type_fscrypt_user, description, false);
++ if (IS_ERR(keyref)) {
++ if (PTR_ERR(keyref) == -EAGAIN || /* not found */
++ PTR_ERR(keyref) == -EKEYREVOKED) /* recently invalidated */
++ keyref = ERR_PTR(-ENOKEY);
++ return ERR_CAST(keyref);
++ }
++ return key_ref_to_ptr(keyref);
+ }
+
+ /*
+ * Give the current user a "key" in ->mk_users. This charges the user's quota
+ * and marks the master key as added by the current user, so that it cannot be
+- * removed by another user with the key. Either the master key's key->sem must
+- * be held for write, or the master key must be still undergoing initialization.
++ * removed by another user with the key. Either ->mk_sem must be held for
++ * write, or the master key must be still undergoing initialization.
+ */
+ static int add_master_key_user(struct fscrypt_master_key *mk)
+ {
+@@ -309,7 +383,7 @@ static int add_master_key_user(struct fscrypt_master_key *mk)
+
+ /*
+ * Remove the current user's "key" from ->mk_users.
+- * The master key's key->sem must be held for write.
++ * ->mk_sem must be held for write.
+ *
+ * Returns 0 if removed, -ENOKEY if not found, or another -errno code.
+ */
+@@ -327,63 +401,49 @@ static int remove_master_key_user(struct fscrypt_master_key *mk)
+ }
+
+ /*
+- * Allocate a new fscrypt_master_key which contains the given secret, set it as
+- * the payload of a new 'struct key' of type fscrypt, and link the 'struct key'
+- * into the given keyring. Synchronized by fscrypt_add_key_mutex.
++ * Allocate a new fscrypt_master_key, transfer the given secret over to it, and
++ * insert it into sb->s_master_keys.
+ */
+-static int add_new_master_key(struct fscrypt_master_key_secret *secret,
+- const struct fscrypt_key_specifier *mk_spec,
+- struct key *keyring)
++static int add_new_master_key(struct super_block *sb,
++ struct fscrypt_master_key_secret *secret,
++ const struct fscrypt_key_specifier *mk_spec)
+ {
++ struct fscrypt_keyring *keyring = sb->s_master_keys;
+ struct fscrypt_master_key *mk;
+- char description[FSCRYPT_MK_DESCRIPTION_SIZE];
+- struct key *key;
+ int err;
+
+ mk = kzalloc(sizeof(*mk), GFP_KERNEL);
+ if (!mk)
+ return -ENOMEM;
+
++ mk->mk_sb = sb;
++ init_rwsem(&mk->mk_sem);
++ refcount_set(&mk->mk_struct_refs, 1);
+ mk->mk_spec = *mk_spec;
+
+- move_master_key_secret(&mk->mk_secret, secret);
+-
+- refcount_set(&mk->mk_refcount, 1); /* secret is present */
+ INIT_LIST_HEAD(&mk->mk_decrypted_inodes);
+ spin_lock_init(&mk->mk_decrypted_inodes_lock);
+
+ if (mk_spec->type == FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER) {
+ err = allocate_master_key_users_keyring(mk);
+ if (err)
+- goto out_free_mk;
++ goto out_put;
+ err = add_master_key_user(mk);
+ if (err)
+- goto out_free_mk;
++ goto out_put;
+ }
+
+- /*
+- * Note that we don't charge this key to anyone's quota, since when
+- * ->mk_users is in use those keys are charged instead, and otherwise
+- * (when ->mk_users isn't in use) only root can add these keys.
+- */
+- format_mk_description(description, mk_spec);
+- key = key_alloc(&key_type_fscrypt, description,
+- GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, current_cred(),
+- KEY_POS_SEARCH | KEY_USR_SEARCH | KEY_USR_VIEW,
+- KEY_ALLOC_NOT_IN_QUOTA, NULL);
+- if (IS_ERR(key)) {
+- err = PTR_ERR(key);
+- goto out_free_mk;
+- }
+- err = key_instantiate_and_link(key, mk, sizeof(*mk), keyring, NULL);
+- key_put(key);
+- if (err)
+- goto out_free_mk;
++ move_master_key_secret(&mk->mk_secret, secret);
++ refcount_set(&mk->mk_active_refs, 1); /* ->mk_secret is present */
+
++ spin_lock(&keyring->lock);
++ hlist_add_head_rcu(&mk->mk_node,
++ fscrypt_mk_hash_bucket(keyring, mk_spec));
++ spin_unlock(&keyring->lock);
+ return 0;
+
+-out_free_mk:
+- free_master_key(mk);
++out_put:
++ fscrypt_put_master_key(mk);
+ return err;
+ }
+
+@@ -392,42 +452,34 @@ static int add_new_master_key(struct fscrypt_master_key_secret *secret,
+ static int add_existing_master_key(struct fscrypt_master_key *mk,
+ struct fscrypt_master_key_secret *secret)
+ {
+- struct key *mk_user;
+- bool rekey;
+ int err;
+
+ /*
+ * If the current user is already in ->mk_users, then there's nothing to
+- * do. (Not applicable for v1 policy keys, which have NULL ->mk_users.)
++ * do. Otherwise, we need to add the user to ->mk_users. (Neither is
++ * applicable for v1 policy keys, which have NULL ->mk_users.)
+ */
+ if (mk->mk_users) {
+- mk_user = find_master_key_user(mk);
++ struct key *mk_user = find_master_key_user(mk);
++
+ if (mk_user != ERR_PTR(-ENOKEY)) {
+ if (IS_ERR(mk_user))
+ return PTR_ERR(mk_user);
+ key_put(mk_user);
+ return 0;
+ }
+- }
+-
+- /* If we'll be re-adding ->mk_secret, try to take the reference. */
+- rekey = !is_master_key_secret_present(&mk->mk_secret);
+- if (rekey && !refcount_inc_not_zero(&mk->mk_refcount))
+- return KEY_DEAD;
+-
+- /* Add the current user to ->mk_users, if applicable. */
+- if (mk->mk_users) {
+ err = add_master_key_user(mk);
+- if (err) {
+- if (rekey && refcount_dec_and_test(&mk->mk_refcount))
+- return KEY_DEAD;
++ if (err)
+ return err;
+- }
+ }
+
+ /* Re-add the secret if needed. */
+- if (rekey)
++ if (!is_master_key_secret_present(&mk->mk_secret)) {
++ if (!refcount_inc_not_zero(&mk->mk_active_refs))
++ return KEY_DEAD;
+ move_master_key_secret(&mk->mk_secret, secret);
++ }
++
+ return 0;
+ }
+
+@@ -436,38 +488,36 @@ static int do_add_master_key(struct super_block *sb,
+ const struct fscrypt_key_specifier *mk_spec)
+ {
+ static DEFINE_MUTEX(fscrypt_add_key_mutex);
+- struct key *key;
++ struct fscrypt_master_key *mk;
+ int err;
+
+ mutex_lock(&fscrypt_add_key_mutex); /* serialize find + link */
+-retry:
+- key = fscrypt_find_master_key(sb, mk_spec);
+- if (IS_ERR(key)) {
+- err = PTR_ERR(key);
+- if (err != -ENOKEY)
+- goto out_unlock;
++
++ mk = fscrypt_find_master_key(sb, mk_spec);
++ if (!mk) {
+ /* Didn't find the key in ->s_master_keys. Add it. */
+ err = allocate_filesystem_keyring(sb);
+- if (err)
+- goto out_unlock;
+- err = add_new_master_key(secret, mk_spec, sb->s_master_keys);
++ if (!err)
++ err = add_new_master_key(sb, secret, mk_spec);
+ } else {
+ /*
+ * Found the key in ->s_master_keys. Re-add the secret if
+ * needed, and add the user to ->mk_users if needed.
+ */
+- down_write(&key->sem);
+- err = add_existing_master_key(key->payload.data[0], secret);
+- up_write(&key->sem);
++ down_write(&mk->mk_sem);
++ err = add_existing_master_key(mk, secret);
++ up_write(&mk->mk_sem);
+ if (err == KEY_DEAD) {
+- /* Key being removed or needs to be removed */
+- key_invalidate(key);
+- key_put(key);
+- goto retry;
++ /*
++ * We found a key struct, but it's already been fully
++ * removed. Ignore the old struct and add a new one.
++ * fscrypt_add_key_mutex means we don't need to worry
++ * about concurrent adds.
++ */
++ err = add_new_master_key(sb, secret, mk_spec);
+ }
+- key_put(key);
++ fscrypt_put_master_key(mk);
+ }
+-out_unlock:
+ mutex_unlock(&fscrypt_add_key_mutex);
+ return err;
+ }
+@@ -731,19 +781,19 @@ int fscrypt_verify_key_added(struct super_block *sb,
+ const u8 identifier[FSCRYPT_KEY_IDENTIFIER_SIZE])
+ {
+ struct fscrypt_key_specifier mk_spec;
+- struct key *key, *mk_user;
+ struct fscrypt_master_key *mk;
++ struct key *mk_user;
+ int err;
+
+ mk_spec.type = FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER;
+ memcpy(mk_spec.u.identifier, identifier, FSCRYPT_KEY_IDENTIFIER_SIZE);
+
+- key = fscrypt_find_master_key(sb, &mk_spec);
+- if (IS_ERR(key)) {
+- err = PTR_ERR(key);
++ mk = fscrypt_find_master_key(sb, &mk_spec);
++ if (!mk) {
++ err = -ENOKEY;
+ goto out;
+ }
+- mk = key->payload.data[0];
++ down_read(&mk->mk_sem);
+ mk_user = find_master_key_user(mk);
+ if (IS_ERR(mk_user)) {
+ err = PTR_ERR(mk_user);
+@@ -751,7 +801,8 @@ int fscrypt_verify_key_added(struct super_block *sb,
+ key_put(mk_user);
+ err = 0;
+ }
+- key_put(key);
++ up_read(&mk->mk_sem);
++ fscrypt_put_master_key(mk);
+ out:
+ if (err == -ENOKEY && capable(CAP_FOWNER))
+ err = 0;
+@@ -913,11 +964,10 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users)
+ struct super_block *sb = file_inode(filp)->i_sb;
+ struct fscrypt_remove_key_arg __user *uarg = _uarg;
+ struct fscrypt_remove_key_arg arg;
+- struct key *key;
+ struct fscrypt_master_key *mk;
+ u32 status_flags = 0;
+ int err;
+- bool dead;
++ bool inodes_remain;
+
+ if (copy_from_user(&arg, uarg, sizeof(arg)))
+ return -EFAULT;
+@@ -937,12 +987,10 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users)
+ return -EACCES;
+
+ /* Find the key being removed. */
+- key = fscrypt_find_master_key(sb, &arg.key_spec);
+- if (IS_ERR(key))
+- return PTR_ERR(key);
+- mk = key->payload.data[0];
+-
+- down_write(&key->sem);
++ mk = fscrypt_find_master_key(sb, &arg.key_spec);
++ if (!mk)
++ return -ENOKEY;
++ down_write(&mk->mk_sem);
+
+ /* If relevant, remove current user's (or all users) claim to the key */
+ if (mk->mk_users && mk->mk_users->keys.nr_leaves_on_tree != 0) {
+@@ -951,7 +999,7 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users)
+ else
+ err = remove_master_key_user(mk);
+ if (err) {
+- up_write(&key->sem);
++ up_write(&mk->mk_sem);
+ goto out_put_key;
+ }
+ if (mk->mk_users->keys.nr_leaves_on_tree != 0) {
+@@ -963,26 +1011,22 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users)
+ status_flags |=
+ FSCRYPT_KEY_REMOVAL_STATUS_FLAG_OTHER_USERS;
+ err = 0;
+- up_write(&key->sem);
++ up_write(&mk->mk_sem);
+ goto out_put_key;
+ }
+ }
+
+ /* No user claims remaining. Go ahead and wipe the secret. */
+- dead = false;
++ err = -ENOKEY;
+ if (is_master_key_secret_present(&mk->mk_secret)) {
+ wipe_master_key_secret(&mk->mk_secret);
+- dead = refcount_dec_and_test(&mk->mk_refcount);
+- }
+- up_write(&key->sem);
+- if (dead) {
+- /*
+- * No inodes reference the key, and we wiped the secret, so the
+- * key object is free to be removed from the keyring.
+- */
+- key_invalidate(key);
++ fscrypt_put_master_key_activeref(mk);
+ err = 0;
+- } else {
++ }
++ inodes_remain = refcount_read(&mk->mk_active_refs) > 0;
++ up_write(&mk->mk_sem);
++
++ if (inodes_remain) {
+ /* Some inodes still reference this key; try to evict them. */
+ err = try_to_lock_encrypted_files(sb, mk);
+ if (err == -EBUSY) {
+@@ -998,7 +1042,7 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users)
+ * has been fully removed including all files locked.
+ */
+ out_put_key:
+- key_put(key);
++ fscrypt_put_master_key(mk);
+ if (err == 0)
+ err = put_user(status_flags, &uarg->removal_status_flags);
+ return err;
+@@ -1045,7 +1089,6 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg)
+ {
+ struct super_block *sb = file_inode(filp)->i_sb;
+ struct fscrypt_get_key_status_arg arg;
+- struct key *key;
+ struct fscrypt_master_key *mk;
+ int err;
+
+@@ -1062,19 +1105,18 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg)
+ arg.user_count = 0;
+ memset(arg.__out_reserved, 0, sizeof(arg.__out_reserved));
+
+- key = fscrypt_find_master_key(sb, &arg.key_spec);
+- if (IS_ERR(key)) {
+- if (key != ERR_PTR(-ENOKEY))
+- return PTR_ERR(key);
++ mk = fscrypt_find_master_key(sb, &arg.key_spec);
++ if (!mk) {
+ arg.status = FSCRYPT_KEY_STATUS_ABSENT;
+ err = 0;
+ goto out;
+ }
+- mk = key->payload.data[0];
+- down_read(&key->sem);
++ down_read(&mk->mk_sem);
+
+ if (!is_master_key_secret_present(&mk->mk_secret)) {
+- arg.status = FSCRYPT_KEY_STATUS_INCOMPLETELY_REMOVED;
++ arg.status = refcount_read(&mk->mk_active_refs) > 0 ?
++ FSCRYPT_KEY_STATUS_INCOMPLETELY_REMOVED :
++ FSCRYPT_KEY_STATUS_ABSENT /* raced with full removal */;
+ err = 0;
+ goto out_release_key;
+ }
+@@ -1096,8 +1138,8 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg)
+ }
+ err = 0;
+ out_release_key:
+- up_read(&key->sem);
+- key_put(key);
++ up_read(&mk->mk_sem);
++ fscrypt_put_master_key(mk);
+ out:
+ if (!err && copy_to_user(uarg, &arg, sizeof(arg)))
+ err = -EFAULT;
+@@ -1109,13 +1151,9 @@ int __init fscrypt_init_keyring(void)
+ {
+ int err;
+
+- err = register_key_type(&key_type_fscrypt);
+- if (err)
+- return err;
+-
+ err = register_key_type(&key_type_fscrypt_user);
+ if (err)
+- goto err_unregister_fscrypt;
++ return err;
+
+ err = register_key_type(&key_type_fscrypt_provisioning);
+ if (err)
+@@ -1125,7 +1163,5 @@ int __init fscrypt_init_keyring(void)
+
+ err_unregister_fscrypt_user:
+ unregister_key_type(&key_type_fscrypt_user);
+-err_unregister_fscrypt:
+- unregister_key_type(&key_type_fscrypt);
+ return err;
+ }
+diff --git a/fs/crypto/keysetup.c b/fs/crypto/keysetup.c
+index 89cd533a88bf..c3fbd594cc79 100644
+--- a/fs/crypto/keysetup.c
++++ b/fs/crypto/keysetup.c
+@@ -9,7 +9,6 @@
+ */
+
+ #include <crypto/skcipher.h>
+-#include <linux/key.h>
+ #include <linux/random.h>
+
+ #include "fscrypt_private.h"
+@@ -151,6 +150,7 @@ void fscrypt_destroy_prepared_key(struct fscrypt_prepared_key *prep_key)
+ {
+ crypto_free_skcipher(prep_key->tfm);
+ fscrypt_destroy_inline_crypt_key(prep_key);
++ memzero_explicit(prep_key, sizeof(*prep_key));
+ }
+
+ /* Given a per-file encryption key, set up the file's crypto transform object */
+@@ -404,20 +404,18 @@ static bool fscrypt_valid_master_key_size(const struct fscrypt_master_key *mk,
+ /*
+ * Find the master key, then set up the inode's actual encryption key.
+ *
+- * If the master key is found in the filesystem-level keyring, then the
+- * corresponding 'struct key' is returned in *master_key_ret with its semaphore
+- * read-locked. This is needed to ensure that only one task links the
+- * fscrypt_info into ->mk_decrypted_inodes (as multiple tasks may race to create
+- * an fscrypt_info for the same inode), and to synchronize the master key being
+- * removed with a new inode starting to use it.
++ * If the master key is found in the filesystem-level keyring, then it is
++ * returned in *mk_ret with its semaphore read-locked. This is needed to ensure
++ * that only one task links the fscrypt_info into ->mk_decrypted_inodes (as
++ * multiple tasks may race to create an fscrypt_info for the same inode), and to
++ * synchronize the master key being removed with a new inode starting to use it.
+ */
+ static int setup_file_encryption_key(struct fscrypt_info *ci,
+ bool need_dirhash_key,
+- struct key **master_key_ret)
++ struct fscrypt_master_key **mk_ret)
+ {
+- struct key *key;
+- struct fscrypt_master_key *mk = NULL;
+ struct fscrypt_key_specifier mk_spec;
++ struct fscrypt_master_key *mk;
+ int err;
+
+ err = fscrypt_select_encryption_impl(ci);
+@@ -442,11 +440,10 @@ static int setup_file_encryption_key(struct fscrypt_info *ci,
+ return -EINVAL;
+ }
+
+- key = fscrypt_find_master_key(ci->ci_inode->i_sb, &mk_spec);
+- if (IS_ERR(key)) {
+- if (key != ERR_PTR(-ENOKEY) ||
+- ci->ci_policy.version != FSCRYPT_POLICY_V1)
+- return PTR_ERR(key);
++ mk = fscrypt_find_master_key(ci->ci_inode->i_sb, &mk_spec);
++ if (!mk) {
++ if (ci->ci_policy.version != FSCRYPT_POLICY_V1)
++ return -ENOKEY;
+
+ /*
+ * As a legacy fallback for v1 policies, search for the key in
+@@ -456,9 +453,7 @@ static int setup_file_encryption_key(struct fscrypt_info *ci,
+ */
+ return fscrypt_setup_v1_file_key_via_subscribed_keyrings(ci);
+ }
+-
+- mk = key->payload.data[0];
+- down_read(&key->sem);
++ down_read(&mk->mk_sem);
+
+ /* Has the secret been removed (via FS_IOC_REMOVE_ENCRYPTION_KEY)? */
+ if (!is_master_key_secret_present(&mk->mk_secret)) {
+@@ -486,18 +481,18 @@ static int setup_file_encryption_key(struct fscrypt_info *ci,
+ if (err)
+ goto out_release_key;
+
+- *master_key_ret = key;
++ *mk_ret = mk;
+ return 0;
+
+ out_release_key:
+- up_read(&key->sem);
+- key_put(key);
++ up_read(&mk->mk_sem);
++ fscrypt_put_master_key(mk);
+ return err;
+ }
+
+ static void put_crypt_info(struct fscrypt_info *ci)
+ {
+- struct key *key;
++ struct fscrypt_master_key *mk;
+
+ if (!ci)
+ return;
+@@ -507,24 +502,18 @@ static void put_crypt_info(struct fscrypt_info *ci)
+ else if (ci->ci_owns_key)
+ fscrypt_destroy_prepared_key(&ci->ci_enc_key);
+
+- key = ci->ci_master_key;
+- if (key) {
+- struct fscrypt_master_key *mk = key->payload.data[0];
+-
++ mk = ci->ci_master_key;
++ if (mk) {
+ /*
+ * Remove this inode from the list of inodes that were unlocked
+- * with the master key.
+- *
+- * In addition, if we're removing the last inode from a key that
+- * already had its secret removed, invalidate the key so that it
+- * gets removed from ->s_master_keys.
++ * with the master key. In addition, if we're removing the last
++ * inode from a master key struct that already had its secret
++ * removed, then complete the full removal of the struct.
+ */
+ spin_lock(&mk->mk_decrypted_inodes_lock);
+ list_del(&ci->ci_master_key_link);
+ spin_unlock(&mk->mk_decrypted_inodes_lock);
+- if (refcount_dec_and_test(&mk->mk_refcount))
+- key_invalidate(key);
+- key_put(key);
++ fscrypt_put_master_key_activeref(mk);
+ }
+ memzero_explicit(ci, sizeof(*ci));
+ kmem_cache_free(fscrypt_info_cachep, ci);
+@@ -538,7 +527,7 @@ fscrypt_setup_encryption_info(struct inode *inode,
+ {
+ struct fscrypt_info *crypt_info;
+ struct fscrypt_mode *mode;
+- struct key *master_key = NULL;
++ struct fscrypt_master_key *mk = NULL;
+ int res;
+
+ res = fscrypt_initialize(inode->i_sb->s_cop->flags);
+@@ -561,8 +550,7 @@ fscrypt_setup_encryption_info(struct inode *inode,
+ WARN_ON(mode->ivsize > FSCRYPT_MAX_IV_SIZE);
+ crypt_info->ci_mode = mode;
+
+- res = setup_file_encryption_key(crypt_info, need_dirhash_key,
+- &master_key);
++ res = setup_file_encryption_key(crypt_info, need_dirhash_key, &mk);
+ if (res)
+ goto out;
+
+@@ -577,12 +565,9 @@ fscrypt_setup_encryption_info(struct inode *inode,
+ * We won the race and set ->i_crypt_info to our crypt_info.
+ * Now link it into the master key's inode list.
+ */
+- if (master_key) {
+- struct fscrypt_master_key *mk =
+- master_key->payload.data[0];
+-
+- refcount_inc(&mk->mk_refcount);
+- crypt_info->ci_master_key = key_get(master_key);
++ if (mk) {
++ crypt_info->ci_master_key = mk;
++ refcount_inc(&mk->mk_active_refs);
+ spin_lock(&mk->mk_decrypted_inodes_lock);
+ list_add(&crypt_info->ci_master_key_link,
+ &mk->mk_decrypted_inodes);
+@@ -592,9 +577,9 @@ fscrypt_setup_encryption_info(struct inode *inode,
+ }
+ res = 0;
+ out:
+- if (master_key) {
+- up_read(&master_key->sem);
+- key_put(master_key);
++ if (mk) {
++ up_read(&mk->mk_sem);
++ fscrypt_put_master_key(mk);
+ }
+ put_crypt_info(crypt_info);
+ return res;
+@@ -759,7 +744,6 @@ EXPORT_SYMBOL(fscrypt_free_inode);
+ int fscrypt_drop_inode(struct inode *inode)
+ {
+ const struct fscrypt_info *ci = fscrypt_get_info(inode);
+- const struct fscrypt_master_key *mk;
+
+ /*
+ * If ci is NULL, then the inode doesn't have an encryption key set up
+@@ -769,7 +753,6 @@ int fscrypt_drop_inode(struct inode *inode)
+ */
+ if (!ci || !ci->ci_master_key)
+ return 0;
+- mk = ci->ci_master_key->payload.data[0];
+
+ /*
+ * With proper, non-racy use of FS_IOC_REMOVE_ENCRYPTION_KEY, all inodes
+@@ -788,6 +771,6 @@ int fscrypt_drop_inode(struct inode *inode)
+ * then the thread removing the key will either evict the inode itself
+ * or will correctly detect that it wasn't evicted due to the race.
+ */
+- return !is_master_key_secret_present(&mk->mk_secret);
++ return !is_master_key_secret_present(&ci->ci_master_key->mk_secret);
+ }
+ EXPORT_SYMBOL_GPL(fscrypt_drop_inode);
+diff --git a/fs/crypto/policy.c b/fs/crypto/policy.c
+index ed3d623724cd..cad34dbe8e29 100644
+--- a/fs/crypto/policy.c
++++ b/fs/crypto/policy.c
+@@ -692,12 +692,8 @@ int fscrypt_set_context(struct inode *inode, void *fs_data)
+ * delayed key setup that requires the inode number.
+ */
+ if (ci->ci_policy.version == FSCRYPT_POLICY_V2 &&
+- (ci->ci_policy.v2.flags & FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32)) {
+- const struct fscrypt_master_key *mk =
+- ci->ci_master_key->payload.data[0];
+-
+- fscrypt_hash_inode_number(ci, mk);
+- }
++ (ci->ci_policy.v2.flags & FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32))
++ fscrypt_hash_inode_number(ci, ci->ci_master_key);
+
+ return inode->i_sb->s_cop->set_context(inode, &ctx, ctxsize, fs_data);
+ }
+diff --git a/fs/super.c b/fs/super.c
+index 87379bb1f7a3..479c6bfc5033 100644
+--- a/fs/super.c
++++ b/fs/super.c
+@@ -293,7 +293,6 @@ static void __put_super(struct super_block *s)
+ WARN_ON(s->s_inode_lru.node);
+ WARN_ON(!list_empty(&s->s_mounts));
+ security_sb_free(s);
+- fscrypt_sb_free(s);
+ put_user_ns(s->s_user_ns);
+ kfree(s->s_subtype);
+ call_rcu(&s->rcu, destroy_super_rcu);
+@@ -454,6 +453,7 @@ void generic_shutdown_super(struct super_block *sb)
+ evict_inodes(sb);
+ /* only nonzero refcount inodes can have marks */
+ fsnotify_sb_delete(sb);
++ fscrypt_sb_delete(sb);
+ security_sb_delete(sb);
+
+ if (sb->s_dio_done_wq) {
+diff --git a/include/linux/fs.h b/include/linux/fs.h
+index fd4c450dc612..806ac72c7220 100644
+--- a/include/linux/fs.h
++++ b/include/linux/fs.h
+@@ -1487,7 +1487,7 @@ struct super_block {
+ const struct xattr_handler **s_xattr;
+ #ifdef CONFIG_FS_ENCRYPTION
+ const struct fscrypt_operations *s_cop;
+- struct key *s_master_keys; /* master crypto keys in use */
++ struct fscrypt_keyring *s_master_keys; /* master crypto keys in use */
+ #endif
+ #ifdef CONFIG_FS_VERITY
+ const struct fsverity_operations *s_vop;
+diff --git a/include/linux/fscrypt.h b/include/linux/fscrypt.h
+index e912ed9141d9..3867e25d5a95 100644
+--- a/include/linux/fscrypt.h
++++ b/include/linux/fscrypt.h
+@@ -294,7 +294,7 @@ fscrypt_free_dummy_policy(struct fscrypt_dummy_policy *dummy_policy)
+ }
+
+ /* keyring.c */
+-void fscrypt_sb_free(struct super_block *sb);
++void fscrypt_sb_delete(struct super_block *sb);
+ int fscrypt_ioctl_add_key(struct file *filp, void __user *arg);
+ int fscrypt_ioctl_remove_key(struct file *filp, void __user *arg);
+ int fscrypt_ioctl_remove_key_all_users(struct file *filp, void __user *arg);
+@@ -482,7 +482,7 @@ fscrypt_free_dummy_policy(struct fscrypt_dummy_policy *dummy_policy)
+ }
+
+ /* keyring.c */
+-static inline void fscrypt_sb_free(struct super_block *sb)
++static inline void fscrypt_sb_delete(struct super_block *sb)
+ {
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 56f31b0a27df79cf62ebe5602566d08dfc29227a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Jan 2022 15:34:11 +0800
+Subject: fsi: core: Check error number after calling ida_simple_get
+
+From: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+
+[ Upstream commit 35af9fb49bc5c6d61ef70b501c3a56fe161cce3e ]
+
+If allocation fails, the ida_simple_get() will return error number.
+So master->idx could be error number and be used in dev_set_name().
+Therefore, it should be better to check it and return error if fails,
+like the ida_simple_get() in __fsi_get_new_minor().
+
+Fixes: 09aecfab93b8 ("drivers/fsi: Add fsi master definition")
+Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+Reviewed-by: Eddie James <eajames@linux.ibm.com>
+Link: https://lore.kernel.org/r/20220111073411.614138-1-jiasheng@iscas.ac.cn
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/fsi/fsi-core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c
+index 59ddc9fd5bca..92e6eebd1851 100644
+--- a/drivers/fsi/fsi-core.c
++++ b/drivers/fsi/fsi-core.c
+@@ -1309,6 +1309,9 @@ int fsi_master_register(struct fsi_master *master)
+
+ mutex_init(&master->scan_lock);
+ master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL);
++ if (master->idx < 0)
++ return master->idx;
++
+ dev_set_name(&master->dev, "fsi%d", master->idx);
+ master->dev.class = &fsi_master_class;
+
+--
+2.35.1
+
--- /dev/null
+From d9f6437c0a9dedc760f98edc714e4ed490262a40 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Apr 2022 08:59:11 +0000
+Subject: fsi: master-ast-cf: Fix missing of_node_put in fsi_master_acf_probe
+
+From: Lv Ruyi <lv.ruyi@zte.com.cn>
+
+[ Upstream commit 182d98e00e4745fe253cb0c24c63bbac253464a2 ]
+
+of_parse_phandle returns node pointer with refcount incremented, use
+of_node_put() on it when done.
+
+Reported-by: Zeal Robot <zealci@zte.com.cn>
+Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn>
+Link: https://lore.kernel.org/r/20220407085911.2491719-1-lv.ruyi@zte.com.cn
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/fsi/fsi-master-ast-cf.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c
+index 24292acdbaf8..5f608ef8b53c 100644
+--- a/drivers/fsi/fsi-master-ast-cf.c
++++ b/drivers/fsi/fsi-master-ast-cf.c
+@@ -1324,12 +1324,14 @@ static int fsi_master_acf_probe(struct platform_device *pdev)
+ }
+ master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);
+ if (IS_ERR(master->cvic)) {
++ of_node_put(np);
+ rc = PTR_ERR(master->cvic);
+ dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc);
+ goto err_free;
+ }
+ rc = of_property_read_u32(np, "copro-sw-interrupts",
+ &master->cvic_sw_irq);
++ of_node_put(np);
+ if (rc) {
+ dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n");
+ goto err_free;
+--
+2.35.1
+
--- /dev/null
+From 15530c236059ca932df86e1799a469325c9ae3b1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 10:19:40 +0200
+Subject: genetlink: hold read cb_lock during iteration of genl_fam_idr in
+ genl_bind()
+
+From: Jiri Pirko <jiri@nvidia.com>
+
+[ Upstream commit 8f1948bdcf2fb50e9092c0950c3c9ac591382101 ]
+
+In genl_bind(), currently genl_lock and write cb_lock are taken
+for iteration of genl_fam_idr and processing of static values
+stored in struct genl_family. Take just read cb_lock for this task
+as it is sufficient to guard the idr and the struct against
+concurrent genl_register/unregister_family() calls.
+
+This will allow to run genl command processing in genl_rcv() and
+mnl_socket_setsockopt(.., NETLINK_ADD_MEMBERSHIP, ..) in parallel.
+
+Reported-by: Vikas Gupta <vikas.gupta@broadcom.com>
+Signed-off-by: Jiri Pirko <jiri@nvidia.com>
+Link: https://lore.kernel.org/r/20220825081940.1283335-1-jiri@resnulli.us
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/netlink/genetlink.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/net/netlink/genetlink.c b/net/netlink/genetlink.c
+index 57010927e20a..76aed0571e3a 100644
+--- a/net/netlink/genetlink.c
++++ b/net/netlink/genetlink.c
+@@ -1362,7 +1362,7 @@ static int genl_bind(struct net *net, int group)
+ unsigned int id;
+ int ret = 0;
+
+- genl_lock_all();
++ down_read(&cb_lock);
+
+ idr_for_each_entry(&genl_fam_idr, family, id) {
+ const struct genl_multicast_group *grp;
+@@ -1383,7 +1383,7 @@ static int genl_bind(struct net *net, int group)
+ break;
+ }
+
+- genl_unlock_all();
++ up_read(&cb_lock);
+ return ret;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 28075bdf17ab8e4d3a55007f8fe33eea5c62f989 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 15:31:19 +0800
+Subject: gpu: lontium-lt9611: Fix NULL pointer dereference in
+ lt9611_connector_init()
+
+From: Zeng Jingxiang <linuszeng@tencent.com>
+
+[ Upstream commit ef8886f321c5dab8124b9153d25afa2a71d05323 ]
+
+A NULL check for bridge->encoder shows that it may be NULL, but it
+already been dereferenced on all paths leading to the check.
+812 if (!bridge->encoder) {
+
+Dereference the pointer bridge->encoder.
+810 drm_connector_attach_encoder(<9611->connector, bridge->encoder);
+
+Signed-off-by: Zeng Jingxiang <linuszeng@tencent.com>
+Signed-off-by: Robert Foss <robert.foss@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220727073119.1578972-1-zengjx95@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/bridge/lontium-lt9611.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c
+index 29b1ce2140ab..1dcc28a4d853 100644
+--- a/drivers/gpu/drm/bridge/lontium-lt9611.c
++++ b/drivers/gpu/drm/bridge/lontium-lt9611.c
+@@ -816,13 +816,14 @@ static int lt9611_connector_init(struct drm_bridge *bridge, struct lt9611 *lt961
+
+ drm_connector_helper_add(<9611->connector,
+ <9611_bridge_connector_helper_funcs);
+- drm_connector_attach_encoder(<9611->connector, bridge->encoder);
+
+ if (!bridge->encoder) {
+ DRM_ERROR("Parent encoder object not found");
+ return -ENODEV;
+ }
+
++ drm_connector_attach_encoder(<9611->connector, bridge->encoder);
++
+ return 0;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 57e52a3c274d176e140b1245bbe055cfe2f6cff6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 13:01:03 +0300
+Subject: habanalabs: remove some f/w descriptor validations
+
+From: farah kassabri <fkassabri@habana.ai>
+
+[ Upstream commit 6b9b9e244fdd0d6c5ee21b7b9d74282d9e43733a ]
+
+To be forward-backward compatible with the firmware in the initial
+communication during preboot, we need to remove the validation of the
+header size. This will allow us to add more fields to the
+lkd_fw_comms_desc structure.
+
+Instead of the validation of the header size, we just print warning
+when some mismatch in descriptor has been revealed, and we calculate
+the CRC base on descriptor size reported by the firmware instead of
+calculating it ourselves.
+
+Signed-off-by: farah kassabri <fkassabri@habana.ai>
+Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
+Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/misc/habanalabs/common/firmware_if.c | 43 +++++++-------------
+ 1 file changed, 14 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c
+index a8e683964ab0..5d08c1f660fd 100644
+--- a/drivers/misc/habanalabs/common/firmware_if.c
++++ b/drivers/misc/habanalabs/common/firmware_if.c
+@@ -1638,50 +1638,36 @@ static int hl_fw_dynamic_validate_descriptor(struct hl_device *hdev,
+ u64 addr;
+ int rc;
+
+- if (le32_to_cpu(fw_desc->header.magic) != HL_COMMS_DESC_MAGIC) {
+- dev_err(hdev->dev, "Invalid magic for dynamic FW descriptor (%x)\n",
++ if (le32_to_cpu(fw_desc->header.magic) != HL_COMMS_DESC_MAGIC)
++ dev_warn(hdev->dev, "Invalid magic for dynamic FW descriptor (%x)\n",
+ fw_desc->header.magic);
+- return -EIO;
+- }
+
+- if (fw_desc->header.version != HL_COMMS_DESC_VER) {
+- dev_err(hdev->dev, "Invalid version for dynamic FW descriptor (%x)\n",
++ if (fw_desc->header.version != HL_COMMS_DESC_VER)
++ dev_warn(hdev->dev, "Invalid version for dynamic FW descriptor (%x)\n",
+ fw_desc->header.version);
+- return -EIO;
+- }
+
+ /*
+- * calc CRC32 of data without header.
++ * Calc CRC32 of data without header. use the size of the descriptor
++ * reported by firmware, without calculating it ourself, to allow adding
++ * more fields to the lkd_fw_comms_desc structure.
+ * note that no alignment/stride address issues here as all structures
+- * are 64 bit padded
++ * are 64 bit padded.
+ */
+- data_size = sizeof(struct lkd_fw_comms_desc) -
+- sizeof(struct comms_desc_header);
+ data_ptr = (u8 *)fw_desc + sizeof(struct comms_desc_header);
+-
+- if (le16_to_cpu(fw_desc->header.size) != data_size) {
+- dev_err(hdev->dev,
+- "Invalid descriptor size 0x%x, expected size 0x%zx\n",
+- le16_to_cpu(fw_desc->header.size), data_size);
+- return -EIO;
+- }
++ data_size = le16_to_cpu(fw_desc->header.size);
+
+ data_crc32 = hl_fw_compat_crc32(data_ptr, data_size);
+-
+ if (data_crc32 != le32_to_cpu(fw_desc->header.crc32)) {
+- dev_err(hdev->dev,
+- "CRC32 mismatch for dynamic FW descriptor (%x:%x)\n",
+- data_crc32, fw_desc->header.crc32);
++ dev_err(hdev->dev, "CRC32 mismatch for dynamic FW descriptor (%x:%x)\n",
++ data_crc32, fw_desc->header.crc32);
+ return -EIO;
+ }
+
+ /* find memory region to which to copy the image */
+ addr = le64_to_cpu(fw_desc->img_addr);
+ region_id = hl_get_pci_memory_region(hdev, addr);
+- if ((region_id != PCI_REGION_SRAM) &&
+- ((region_id != PCI_REGION_DRAM))) {
+- dev_err(hdev->dev,
+- "Invalid region to copy FW image address=%llx\n", addr);
++ if ((region_id != PCI_REGION_SRAM) && ((region_id != PCI_REGION_DRAM))) {
++ dev_err(hdev->dev, "Invalid region to copy FW image address=%llx\n", addr);
+ return -EIO;
+ }
+
+@@ -1698,8 +1684,7 @@ static int hl_fw_dynamic_validate_descriptor(struct hl_device *hdev,
+ fw_loader->dynamic_loader.fw_image_size,
+ region);
+ if (rc) {
+- dev_err(hdev->dev,
+- "invalid mem transfer request for FW image\n");
++ dev_err(hdev->dev, "invalid mem transfer request for FW image\n");
+ return rc;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From b5ca218e4f68548e646be69dafa1f89eda4c5d13 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 4 Sep 2022 12:31:15 -0700
+Subject: HID: roccat: Fix use-after-free in roccat_read()
+
+From: Hyunwoo Kim <imv4bel@gmail.com>
+
+[ Upstream commit cacdb14b1c8d3804a3a7d31773bc7569837b71a4 ]
+
+roccat_report_event() is responsible for registering
+roccat-related reports in struct roccat_device.
+
+int roccat_report_event(int minor, u8 const *data)
+{
+ struct roccat_device *device;
+ struct roccat_reader *reader;
+ struct roccat_report *report;
+ uint8_t *new_value;
+
+ device = devices[minor];
+
+ new_value = kmemdup(data, device->report_size, GFP_ATOMIC);
+ if (!new_value)
+ return -ENOMEM;
+
+ report = &device->cbuf[device->cbuf_end];
+
+ /* passing NULL is safe */
+ kfree(report->value);
+ ...
+
+The registered report is stored in the struct roccat_device member
+"struct roccat_report cbuf[ROCCAT_CBUF_SIZE];".
+If more reports are received than the "ROCCAT_CBUF_SIZE" value,
+kfree() the saved report from cbuf[0] and allocates a new reprot.
+Since there is no lock when this kfree() is performed,
+kfree() can be performed even while reading the saved report.
+
+static ssize_t roccat_read(struct file *file, char __user *buffer,
+ size_t count, loff_t *ppos)
+{
+ struct roccat_reader *reader = file->private_data;
+ struct roccat_device *device = reader->device;
+ struct roccat_report *report;
+ ssize_t retval = 0, len;
+ DECLARE_WAITQUEUE(wait, current);
+
+ mutex_lock(&device->cbuf_lock);
+
+ ...
+
+ report = &device->cbuf[reader->cbuf_start];
+ /*
+ * If report is larger than requested amount of data, rest of report
+ * is lost!
+ */
+ len = device->report_size > count ? count : device->report_size;
+
+ if (copy_to_user(buffer, report->value, len)) {
+ retval = -EFAULT;
+ goto exit_unlock;
+ }
+ ...
+
+The roccat_read() function receives the device->cbuf report and
+delivers it to the user through copy_to_user().
+If the N+ROCCAT_CBUF_SIZE th report is received while copying of
+the Nth report->value is in progress, the pointer that copy_to_user()
+is working on is kfree()ed and UAF read may occur. (race condition)
+
+Since the device node of this driver does not set separate permissions,
+this is not a security vulnerability, but because it is used for
+requesting screen display of profile or dpi settings,
+a user using the roccat device can apply udev to this device node or
+There is a possibility to use it by giving.
+
+Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-roccat.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/hid/hid-roccat.c b/drivers/hid/hid-roccat.c
+index 26373b82fe81..6da80e442fdd 100644
+--- a/drivers/hid/hid-roccat.c
++++ b/drivers/hid/hid-roccat.c
+@@ -257,6 +257,8 @@ int roccat_report_event(int minor, u8 const *data)
+ if (!new_value)
+ return -ENOMEM;
+
++ mutex_lock(&device->cbuf_lock);
++
+ report = &device->cbuf[device->cbuf_end];
+
+ /* passing NULL is safe */
+@@ -276,6 +278,8 @@ int roccat_report_event(int minor, u8 const *data)
+ reader->cbuf_start = (reader->cbuf_start + 1) % ROCCAT_CBUF_SIZE;
+ }
+
++ mutex_unlock(&device->cbuf_lock);
++
+ wake_up_interruptible(&device->wait);
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From 0f32a4a8c436945c05f7051e889f273267bbc942 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 10 Sep 2022 20:36:13 -0400
+Subject: hid: topre: Add driver fixing report descriptor
+
+From: Harry Stern <harry@harrystern.net>
+
+[ Upstream commit a109d5c45b3d6728b9430716b915afbe16eef27c ]
+
+The Topre REALFORCE R2 firmware incorrectly reports that interface
+descriptor number 1, input report descriptor 2's events are array events
+rather than variable events. That particular report descriptor is used
+to report keypresses when there are more than 6 keys held at a time.
+This bug prevents events from this interface from being registered
+properly, so only 6 keypresses (from a different interface) can be
+registered at once, rather than full n-key rollover.
+
+This commit fixes the bug by setting the correct value in a report_fixup
+function.
+
+The original bug report can be found here:
+Link: https://gitlab.freedesktop.org/libinput/libinput/-/issues/804
+
+Thanks to Benjamin Tissoires for diagnosing the issue with the report
+descriptor.
+
+Signed-off-by: Harry Stern <harry@harrystern.net>
+Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
+Link: https://lore.kernel.org/r/20220911003614.297613-1-harry@harrystern.net
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/Kconfig | 6 +++++
+ drivers/hid/Makefile | 1 +
+ drivers/hid/hid-ids.h | 3 +++
+ drivers/hid/hid-topre.c | 49 +++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 59 insertions(+)
+ create mode 100644 drivers/hid/hid-topre.c
+
+diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig
+index 9235ab7161e3..58fcc21bf146 100644
+--- a/drivers/hid/Kconfig
++++ b/drivers/hid/Kconfig
+@@ -1057,6 +1057,12 @@ config HID_TOPSEED
+ Say Y if you have a TopSeed Cyberlink or BTC Emprex or Conceptronic
+ CLLRCMCE remote control.
+
++config HID_TOPRE
++ tristate "Topre REALFORCE keyboards"
++ depends on HID
++ help
++ Say Y for N-key rollover support on Topre REALFORCE R2 108 key keyboards.
++
+ config HID_THINGM
+ tristate "ThingM blink(1) USB RGB LED"
+ depends on HID
+diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile
+index e29efcb1c040..1026ac9e8206 100644
+--- a/drivers/hid/Makefile
++++ b/drivers/hid/Makefile
+@@ -117,6 +117,7 @@ obj-$(CONFIG_HID_GREENASIA) += hid-gaff.o
+ obj-$(CONFIG_HID_THRUSTMASTER) += hid-tmff.o hid-thrustmaster.o
+ obj-$(CONFIG_HID_TIVO) += hid-tivo.o
+ obj-$(CONFIG_HID_TOPSEED) += hid-topseed.o
++obj-$(CONFIG_HID_TOPRE) += hid-topre.o
+ obj-$(CONFIG_HID_TWINHAN) += hid-twinhan.o
+ obj-$(CONFIG_HID_U2FZERO) += hid-u2fzero.o
+ hid-uclogic-objs := hid-uclogic-core.o \
+diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
+index cb2b48d6915e..335b13251c0f 100644
+--- a/drivers/hid/hid-ids.h
++++ b/drivers/hid/hid-ids.h
+@@ -1198,6 +1198,9 @@
+ #define USB_DEVICE_ID_TIVO_SLIDE 0x1201
+ #define USB_DEVICE_ID_TIVO_SLIDE_PRO 0x1203
+
++#define USB_VENDOR_ID_TOPRE 0x0853
++#define USB_DEVICE_ID_TOPRE_REALFORCE_R2_108 0x0148
++
+ #define USB_VENDOR_ID_TOPSEED 0x0766
+ #define USB_DEVICE_ID_TOPSEED_CYBERLINK 0x0204
+
+diff --git a/drivers/hid/hid-topre.c b/drivers/hid/hid-topre.c
+new file mode 100644
+index 000000000000..88a91cdad5f8
+--- /dev/null
++++ b/drivers/hid/hid-topre.c
+@@ -0,0 +1,49 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * HID driver for Topre REALFORCE Keyboards
++ *
++ * Copyright (c) 2022 Harry Stern <harry@harrystern.net>
++ *
++ * Based on the hid-macally driver
++ */
++
++#include <linux/hid.h>
++#include <linux/module.h>
++
++#include "hid-ids.h"
++
++MODULE_AUTHOR("Harry Stern <harry@harrystern.net>");
++MODULE_DESCRIPTION("REALFORCE R2 Keyboard driver");
++MODULE_LICENSE("GPL");
++
++/*
++ * Fix the REALFORCE R2's non-boot interface's report descriptor to match the
++ * events it's actually sending. It claims to send array events but is instead
++ * sending variable events.
++ */
++static __u8 *topre_report_fixup(struct hid_device *hdev, __u8 *rdesc,
++ unsigned int *rsize)
++{
++ if (*rsize >= 119 && rdesc[69] == 0x29 && rdesc[70] == 0xe7 &&
++ rdesc[71] == 0x81 && rdesc[72] == 0x00) {
++ hid_info(hdev,
++ "fixing up Topre REALFORCE keyboard report descriptor\n");
++ rdesc[72] = 0x02;
++ }
++ return rdesc;
++}
++
++static const struct hid_device_id topre_id_table[] = {
++ { HID_USB_DEVICE(USB_VENDOR_ID_TOPRE,
++ USB_DEVICE_ID_TOPRE_REALFORCE_R2_108) },
++ { }
++};
++MODULE_DEVICE_TABLE(hid, topre_id_table);
++
++static struct hid_driver topre_driver = {
++ .name = "topre",
++ .id_table = topre_id_table,
++ .report_fixup = topre_report_fixup,
++};
++
++module_hid_driver(topre_driver);
+--
+2.35.1
+
--- /dev/null
+From b624ef90477250b97b157e8b9d77dd94bbdc9406 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 16:27:06 +0200
+Subject: HID: uclogic: Fix warning in uclogic_rdesc_template_apply
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: José Expósito <jose.exposito89@gmail.com>
+
+[ Upstream commit 609174edeb758d1e2d713e7ab4e09ea8d45aa4f7 ]
+
+Building with Sparse enabled prints this warning:
+
+ warning: incorrect type in assignment (different base types)
+ expected signed int x
+ got restricted __le32 [usertype]
+
+Cast the return value of cpu_to_le32() to fix the warning.
+
+Fixes: 08177f4 ("HID: uclogic: merge hid-huion driver in hid-uclogic")
+Signed-off-by: José Expósito <jose.exposito89@gmail.com>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-uclogic-rdesc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/hid/hid-uclogic-rdesc.c b/drivers/hid/hid-uclogic-rdesc.c
+index eb25e397a822..ef50116a1839 100644
+--- a/drivers/hid/hid-uclogic-rdesc.c
++++ b/drivers/hid/hid-uclogic-rdesc.c
+@@ -851,7 +851,7 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr,
+ if (memcmp(p, pen_head, sizeof(pen_head)) == 0 &&
+ p[sizeof(pen_head)] < param_num) {
+ v = param_list[p[sizeof(pen_head)]];
+- put_unaligned(cpu_to_le32(v), (s32 *)p);
++ put_unaligned((__force u32)cpu_to_le32(v), (s32 *)p);
+ p += sizeof(pen_head) + 1;
+ } else {
+ p++;
+--
+2.35.1
+
--- /dev/null
+From bb797030978882a83483843db2a0bdaa9f688ed4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 11 Jun 2022 13:39:11 +0200
+Subject: HID: uclogic: Make template placeholder IDs generic
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: José Expósito <jose.exposito89@gmail.com>
+
+[ Upstream commit 76e645be7ebecbf39ab2edd949ea7f1757f58900 ]
+
+Up until now, the report descriptor template parameter IDs were only
+used with pen report descriptors and they were named accordingly.
+
+Rename the enum and the total number of IDs to make them interface
+agnostic.
+
+Refactor, no functional changes.
+
+Signed-off-by: José Expósito <jose.exposito89@gmail.com>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Stable-dep-of: 609174edeb75 ("HID: uclogic: Fix warning in uclogic_rdesc_template_apply")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-uclogic-params.c | 4 ++--
+ drivers/hid/hid-uclogic-rdesc.c | 14 +++++++-------
+ drivers/hid/hid-uclogic-rdesc.h | 10 +++++-----
+ 3 files changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/hid/hid-uclogic-params.c b/drivers/hid/hid-uclogic-params.c
+index 3e70f969fb84..1b056ca154ac 100644
+--- a/drivers/hid/hid-uclogic-params.c
++++ b/drivers/hid/hid-uclogic-params.c
+@@ -149,7 +149,7 @@ static int uclogic_params_pen_init_v1(struct uclogic_params_pen *pen,
+ const int len = 12;
+ s32 resolution;
+ /* Pen report descriptor template parameters */
+- s32 desc_params[UCLOGIC_RDESC_PEN_PH_ID_NUM];
++ s32 desc_params[UCLOGIC_RDESC_PH_ID_NUM];
+ __u8 *desc_ptr = NULL;
+
+ /* Check arguments */
+@@ -277,7 +277,7 @@ static int uclogic_params_pen_init_v2(struct uclogic_params_pen *pen,
+ const int len = 18;
+ s32 resolution;
+ /* Pen report descriptor template parameters */
+- s32 desc_params[UCLOGIC_RDESC_PEN_PH_ID_NUM];
++ s32 desc_params[UCLOGIC_RDESC_PH_ID_NUM];
+ __u8 *desc_ptr = NULL;
+
+ /* Check arguments */
+diff --git a/drivers/hid/hid-uclogic-rdesc.c b/drivers/hid/hid-uclogic-rdesc.c
+index 6dd6dcd09c8b..eb25e397a822 100644
+--- a/drivers/hid/hid-uclogic-rdesc.c
++++ b/drivers/hid/hid-uclogic-rdesc.c
+@@ -821,7 +821,7 @@ const size_t uclogic_rdesc_xppen_deco01_frame_size =
+ * uclogic_rdesc_template_apply() - apply report descriptor parameters to a
+ * report descriptor template, creating a report descriptor. Copies the
+ * template over to the new report descriptor and replaces every occurrence of
+- * UCLOGIC_RDESC_PH_HEAD, followed by an index byte, with the value from the
++ * UCLOGIC_RDESC_PEN_PH_HEAD, followed by an index byte, with the value from the
+ * parameter list at that index.
+ *
+ * @template_ptr: Pointer to the template buffer.
+@@ -838,7 +838,7 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr,
+ const s32 *param_list,
+ size_t param_num)
+ {
+- static const __u8 head[] = {UCLOGIC_RDESC_PH_HEAD};
++ static const __u8 pen_head[] = {UCLOGIC_RDESC_PEN_PH_HEAD};
+ __u8 *rdesc_ptr;
+ __u8 *p;
+ s32 v;
+@@ -847,12 +847,12 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr,
+ if (rdesc_ptr == NULL)
+ return NULL;
+
+- for (p = rdesc_ptr; p + sizeof(head) < rdesc_ptr + template_size;) {
+- if (memcmp(p, head, sizeof(head)) == 0 &&
+- p[sizeof(head)] < param_num) {
+- v = param_list[p[sizeof(head)]];
++ for (p = rdesc_ptr; p + sizeof(pen_head) < rdesc_ptr + template_size;) {
++ if (memcmp(p, pen_head, sizeof(pen_head)) == 0 &&
++ p[sizeof(pen_head)] < param_num) {
++ v = param_list[p[sizeof(pen_head)]];
+ put_unaligned(cpu_to_le32(v), (s32 *)p);
+- p += sizeof(head) + 1;
++ p += sizeof(pen_head) + 1;
+ } else {
+ p++;
+ }
+diff --git a/drivers/hid/hid-uclogic-rdesc.h b/drivers/hid/hid-uclogic-rdesc.h
+index c5da51055af3..1bb9c1220ea7 100644
+--- a/drivers/hid/hid-uclogic-rdesc.h
++++ b/drivers/hid/hid-uclogic-rdesc.h
+@@ -81,7 +81,7 @@ extern __u8 uclogic_rdesc_twha60_fixed1_arr[];
+ extern const size_t uclogic_rdesc_twha60_fixed1_size;
+
+ /* Report descriptor template placeholder head */
+-#define UCLOGIC_RDESC_PH_HEAD 0xFE, 0xED, 0x1D
++#define UCLOGIC_RDESC_PEN_PH_HEAD 0xFE, 0xED, 0x1D
+
+ /* Apply report descriptor parameters to a report descriptor template */
+ extern __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr,
+@@ -89,19 +89,19 @@ extern __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr,
+ const s32 *param_list,
+ size_t param_num);
+
+-/* Pen report descriptor template placeholder IDs */
+-enum uclogic_rdesc_pen_ph_id {
++/* Report descriptor template placeholder IDs */
++enum uclogic_rdesc_ph_id {
+ UCLOGIC_RDESC_PEN_PH_ID_X_LM,
+ UCLOGIC_RDESC_PEN_PH_ID_X_PM,
+ UCLOGIC_RDESC_PEN_PH_ID_Y_LM,
+ UCLOGIC_RDESC_PEN_PH_ID_Y_PM,
+ UCLOGIC_RDESC_PEN_PH_ID_PRESSURE_LM,
+- UCLOGIC_RDESC_PEN_PH_ID_NUM
++ UCLOGIC_RDESC_PH_ID_NUM
+ };
+
+ /* Report descriptor pen template placeholder */
+ #define UCLOGIC_RDESC_PEN_PH(_ID) \
+- UCLOGIC_RDESC_PH_HEAD, UCLOGIC_RDESC_PEN_PH_ID_##_ID
++ UCLOGIC_RDESC_PEN_PH_HEAD, UCLOGIC_RDESC_PEN_PH_ID_##_ID
+
+ /* Report ID for v1 pen reports */
+ #define UCLOGIC_RDESC_PEN_V1_ID 0x07
+--
+2.35.1
+
--- /dev/null
+From f8bf0cd7ab964bc1cace7c25d00207deaa2b8c83 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Apr 2022 08:52:32 +0000
+Subject: HSI: omap_ssi: Fix refcount leak in ssi_probe
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 9a2ea132df860177b33c9fd421b26c4e9a0a9396 ]
+
+When returning or breaking early from a
+for_each_available_child_of_node() loop, we need to explicitly call
+of_node_put() on the child node to possibly release the node.
+
+Fixes: b209e047bc74 ("HSI: Introduce OMAP SSI driver")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hsi/controllers/omap_ssi_core.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/hsi/controllers/omap_ssi_core.c b/drivers/hsi/controllers/omap_ssi_core.c
+index 44a3f5660c10..eb9820158318 100644
+--- a/drivers/hsi/controllers/omap_ssi_core.c
++++ b/drivers/hsi/controllers/omap_ssi_core.c
+@@ -524,6 +524,7 @@ static int ssi_probe(struct platform_device *pd)
+ if (!childpdev) {
+ err = -ENODEV;
+ dev_err(&pd->dev, "failed to create ssi controller port\n");
++ of_node_put(child);
+ goto out3;
+ }
+ }
+--
+2.35.1
+
--- /dev/null
+From 8a1bbfcf08d23f5154122f8d4502ef1d4e3e123c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 12:12:27 +0200
+Subject: HSI: omap_ssi_port: Fix dma_map_sg error check
+
+From: Jack Wang <jinpu.wang@ionos.com>
+
+[ Upstream commit 551e325bbd3fb8b5a686ac1e6cf76e5641461cf2 ]
+
+dma_map_sg return 0 on error, in case of error return -EIO
+to caller.
+
+Cc: Sebastian Reichel <sre@kernel.org>
+Cc: linux-kernel@vger.kernel.org (open list)
+Fixes: b209e047bc74 ("HSI: Introduce OMAP SSI driver")
+Signed-off-by: Jack Wang <jinpu.wang@ionos.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hsi/controllers/omap_ssi_port.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/hsi/controllers/omap_ssi_port.c b/drivers/hsi/controllers/omap_ssi_port.c
+index a0cb5be246e1..b9495b720f1b 100644
+--- a/drivers/hsi/controllers/omap_ssi_port.c
++++ b/drivers/hsi/controllers/omap_ssi_port.c
+@@ -230,10 +230,10 @@ static int ssi_start_dma(struct hsi_msg *msg, int lch)
+ if (msg->ttype == HSI_MSG_READ) {
+ err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents,
+ DMA_FROM_DEVICE);
+- if (err < 0) {
++ if (!err) {
+ dev_dbg(&ssi->device, "DMA map SG failed !\n");
+ pm_runtime_put_autosuspend(omap_port->pdev);
+- return err;
++ return -EIO;
+ }
+ csdp = SSI_DST_BURST_4x32_BIT | SSI_DST_MEMORY_PORT |
+ SSI_SRC_SINGLE_ACCESS0 | SSI_SRC_PERIPHERAL_PORT |
+@@ -247,10 +247,10 @@ static int ssi_start_dma(struct hsi_msg *msg, int lch)
+ } else {
+ err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents,
+ DMA_TO_DEVICE);
+- if (err < 0) {
++ if (!err) {
+ dev_dbg(&ssi->device, "DMA map SG failed !\n");
+ pm_runtime_put_autosuspend(omap_port->pdev);
+- return err;
++ return -EIO;
+ }
+ csdp = SSI_SRC_BURST_4x32_BIT | SSI_SRC_MEMORY_PORT |
+ SSI_DST_SINGLE_ACCESS0 | SSI_DST_PERIPHERAL_PORT |
+--
+2.35.1
+
--- /dev/null
+From 521247f5e382920cc0b1ddb76fb92d0ec87be09b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 15:48:01 +0800
+Subject: HSI: ssi_protocol: fix potential resource leak in ssip_pn_open()
+
+From: Jianglei Nie <niejianglei2021@163.com>
+
+[ Upstream commit b28dbcb379e6a7f80262c2732a57681b1ee548ca ]
+
+ssip_pn_open() claims the HSI client's port with hsi_claim_port(). When
+hsi_register_port_event() gets some error and returns a negetive value,
+the HSI client's port should be released with hsi_release_port().
+
+Fix it by calling hsi_release_port() when hsi_register_port_event() fails.
+
+Signed-off-by: Jianglei Nie <niejianglei2021@163.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hsi/clients/ssi_protocol.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/hsi/clients/ssi_protocol.c b/drivers/hsi/clients/ssi_protocol.c
+index 96d0eccca3aa..f202751484aa 100644
+--- a/drivers/hsi/clients/ssi_protocol.c
++++ b/drivers/hsi/clients/ssi_protocol.c
+@@ -931,6 +931,7 @@ static int ssip_pn_open(struct net_device *dev)
+ if (err < 0) {
+ dev_err(&cl->device, "Register HSI port event failed (%d)\n",
+ err);
++ hsi_release_port(cl);
+ return err;
+ }
+ dev_dbg(&cl->device, "Configuring SSI port\n");
+--
+2.35.1
+
--- /dev/null
+From a22eb508a9731bfe9d33bb1bb6cf33a01cbd3a1f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 15:16:42 +0300
+Subject: hwmon: (pmbus/mp2888) Fix sensors readouts for MPS Multi-phase mp2888
+ controller
+
+From: Oleksandr Shamray <oleksandrs@nvidia.com>
+
+[ Upstream commit 525dd5aed67a2f4f7278116fb92a24e6a53e2622 ]
+
+Fix scale factors for reading MPS Multi-phase mp2888 controller.
+Fixed sensors:
+ - PIN/POUT: based on vendor documentation, set bscale factor 0.5W/LSB
+ - IOUT: based on vendor documentation, set scale factor 0.25 A/LSB
+
+Fixes: e4db7719d037 ("hwmon: (pmbus) Add support for MPS Multi-phase mp2888 controller")
+Signed-off-by: Oleksandr Shamray <oleksandrs@nvidia.com>
+Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
+Link: https://lore.kernel.org/r/20220929121642.63051-1-oleksandrs@nvidia.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hwmon/pmbus/mp2888.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/hwmon/pmbus/mp2888.c b/drivers/hwmon/pmbus/mp2888.c
+index 8ecd4adfef40..24e5194706cf 100644
+--- a/drivers/hwmon/pmbus/mp2888.c
++++ b/drivers/hwmon/pmbus/mp2888.c
+@@ -34,7 +34,7 @@ struct mp2888_data {
+ int curr_sense_gain;
+ };
+
+-#define to_mp2888_data(x) container_of(x, struct mp2888_data, info)
++#define to_mp2888_data(x) container_of(x, struct mp2888_data, info)
+
+ static int mp2888_read_byte_data(struct i2c_client *client, int page, int reg)
+ {
+@@ -109,7 +109,7 @@ mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page,
+ * - Kcs is the DrMOS current sense gain of power stage, which is obtained from the
+ * register MP2888_MFR_VR_CONFIG1, bits 13-12 with the following selection of DrMOS
+ * (data->curr_sense_gain):
+- * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A.
++ * 00b - 8.5µA/A, 01b - 9.7µA/A, 1b - 10µA/A, 11b - 5µA/A.
+ * - Rcs is the internal phase current sense resistor. This parameter depends on hardware
+ * assembly. By default it is set to 1kΩ. In case of different assembly, user should
+ * scale this parameter by dividing it by Rcs.
+@@ -118,10 +118,9 @@ mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page,
+ * because sampling of current occurrence of bit weight has a big deviation, especially for
+ * light load.
+ */
+- ret = DIV_ROUND_CLOSEST(ret * 100 - 9800, data->curr_sense_gain);
+- ret = (data->phase_curr_resolution) ? ret * 2 : ret;
++ ret = DIV_ROUND_CLOSEST(ret * 200 - 19600, data->curr_sense_gain);
+ /* Scale according to total current resolution. */
+- ret = (data->total_curr_resolution) ? ret * 8 : ret * 4;
++ ret = (data->total_curr_resolution) ? ret * 2 : ret;
+ return ret;
+ }
+
+@@ -212,7 +211,7 @@ static int mp2888_read_word_data(struct i2c_client *client, int page, int phase,
+ ret = pmbus_read_word_data(client, page, phase, reg);
+ if (ret < 0)
+ return ret;
+- ret = data->total_curr_resolution ? ret * 2 : ret;
++ ret = data->total_curr_resolution ? ret : DIV_ROUND_CLOSEST(ret, 2);
+ break;
+ case PMBUS_POUT_OP_WARN_LIMIT:
+ ret = pmbus_read_word_data(client, page, phase, reg);
+@@ -223,7 +222,7 @@ static int mp2888_read_word_data(struct i2c_client *client, int page, int phase,
+ * set 1. Actual power is reported with 0.5W or 1W respectively resolution. Scaling
+ * is needed to match both.
+ */
+- ret = data->total_curr_resolution ? ret * 4 : ret * 2;
++ ret = data->total_curr_resolution ? ret * 2 : ret;
+ break;
+ /*
+ * The below registers are not implemented by device or implemented not according to the
+--
+2.35.1
+
--- /dev/null
+From 510098379246ee119e30046cfe335a810d1cc3a1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 12:11:51 +0200
+Subject: hwmon: (sht4x) do not overflow clamping operation on 32-bit platforms
+
+From: Jason A. Donenfeld <Jason@zx2c4.com>
+
+[ Upstream commit f9c0cf8f26de367c58e48b02b1cdb9c377626e6f ]
+
+On 32-bit platforms, long is 32 bits, so (long)UINT_MAX is less than
+(long)SHT4X_MIN_POLL_INTERVAL, which means the clamping operation is
+bogus. Fix this by clamping at INT_MAX, so that the upperbound is the
+same on all platforms.
+
+Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
+Link: https://lore.kernel.org/r/20220924101151.4168414-1-Jason@zx2c4.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hwmon/sht4x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/hwmon/sht4x.c b/drivers/hwmon/sht4x.c
+index 09c2a0b06444..9aeb3dbf6c20 100644
+--- a/drivers/hwmon/sht4x.c
++++ b/drivers/hwmon/sht4x.c
+@@ -129,7 +129,7 @@ static int sht4x_read_values(struct sht4x_data *data)
+
+ static ssize_t sht4x_interval_write(struct sht4x_data *data, long val)
+ {
+- data->update_interval = clamp_val(val, SHT4X_MIN_POLL_INTERVAL, UINT_MAX);
++ data->update_interval = clamp_val(val, SHT4X_MIN_POLL_INTERVAL, INT_MAX);
+
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From 2d6be98014d8b8f4a642a4da03282e46bf3e47be Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Aug 2022 20:04:18 +0000
+Subject: hwrng: arm-smccc-trng - fix NO_ENTROPY handling
+
+From: James Cowgill <james.cowgill@blaize.com>
+
+[ Upstream commit 042b4b169c6fb9d4df268d66282d7302dd73d37b ]
+
+The SMCCC_RET_TRNG_NO_ENTROPY switch arm is never used because the
+NO_ENTROPY return value is negative and negative values are handled
+above the switch by immediately returning.
+
+Fix by handling errors using a default arm in the switch.
+
+Fixes: 0888d04b47a1 ("hwrng: Add Arm SMCCC TRNG based driver")
+Signed-off-by: James Cowgill <james.cowgill@blaize.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/char/hw_random/arm_smccc_trng.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/char/hw_random/arm_smccc_trng.c b/drivers/char/hw_random/arm_smccc_trng.c
+index b24ac39a903b..e34c3ea692b6 100644
+--- a/drivers/char/hw_random/arm_smccc_trng.c
++++ b/drivers/char/hw_random/arm_smccc_trng.c
+@@ -71,8 +71,6 @@ static int smccc_trng_read(struct hwrng *rng, void *data, size_t max, bool wait)
+ MAX_BITS_PER_CALL);
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND, bits, &res);
+- if ((int)res.a0 < 0)
+- return (int)res.a0;
+
+ switch ((int)res.a0) {
+ case SMCCC_RET_SUCCESS:
+@@ -88,6 +86,8 @@ static int smccc_trng_read(struct hwrng *rng, void *data, size_t max, bool wait)
+ return copied;
+ cond_resched();
+ break;
++ default:
++ return -EIO;
+ }
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 3324a30eba930652090561a7b03197e943d09fb8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 22 Aug 2022 13:19:03 +0200
+Subject: hwrng: imx-rngc - Moving IRQ handler registering after
+ imx_rngc_irq_mask_clear()
+
+From: Kshitiz Varshney <kshitiz.varshney@nxp.com>
+
+[ Upstream commit 10a2199caf437e893d9027d97700b3c6010048b7 ]
+
+Issue:
+While servicing interrupt, if the IRQ happens to be because of a SEED_DONE
+due to a previous boot stage, you end up completing the completion
+prematurely, hence causing kernel to crash while booting.
+
+Fix:
+Moving IRQ handler registering after imx_rngc_irq_mask_clear()
+
+Fixes: 1d5449445bd0 (hwrng: mx-rngc - add a driver for Freescale RNGC)
+Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/char/hw_random/imx-rngc.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c
+index e32c52c10d4d..1d7ce7443586 100644
+--- a/drivers/char/hw_random/imx-rngc.c
++++ b/drivers/char/hw_random/imx-rngc.c
+@@ -264,13 +264,6 @@ static int imx_rngc_probe(struct platform_device *pdev)
+ if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB)
+ return -ENODEV;
+
+- ret = devm_request_irq(&pdev->dev,
+- irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
+- if (ret) {
+- dev_err(rngc->dev, "Can't get interrupt working.\n");
+- return ret;
+- }
+-
+ init_completion(&rngc->rng_op_done);
+
+ rngc->rng.name = pdev->name;
+@@ -284,6 +277,13 @@ static int imx_rngc_probe(struct platform_device *pdev)
+
+ imx_rngc_irq_mask_clear(rngc);
+
++ ret = devm_request_irq(&pdev->dev,
++ irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
++ if (ret) {
++ dev_err(rngc->dev, "Can't get interrupt working.\n");
++ return ret;
++ }
++
+ if (self_test) {
+ ret = imx_rngc_self_test(rngc);
+ if (ret) {
+--
+2.35.1
+
--- /dev/null
+From 76048f815f7b87bfbaac9ce3e29853810a202a96 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 21:37:42 +0200
+Subject: hwrng: imx-rngc - use devm_clk_get_enabled
+
+From: Martin Kaiser <martin@kaiser.cx>
+
+[ Upstream commit 6a2bc448423cea44e7dba0f72d7c82ae04ab201e ]
+
+Use the new devm_clk_get_enabled function to get our clock.
+
+We don't have to disable and unprepare the clock ourselves any more in
+error paths and in the remove function.
+
+Signed-off-by: Martin Kaiser <martin@kaiser.cx>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/char/hw_random/imx-rngc.c | 25 ++++++-------------------
+ 1 file changed, 6 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c
+index b05d676ca814..e32c52c10d4d 100644
+--- a/drivers/char/hw_random/imx-rngc.c
++++ b/drivers/char/hw_random/imx-rngc.c
+@@ -245,7 +245,7 @@ static int imx_rngc_probe(struct platform_device *pdev)
+ if (IS_ERR(rngc->base))
+ return PTR_ERR(rngc->base);
+
+- rngc->clk = devm_clk_get(&pdev->dev, NULL);
++ rngc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(rngc->clk)) {
+ dev_err(&pdev->dev, "Can not get rng_clk\n");
+ return PTR_ERR(rngc->clk);
+@@ -255,26 +255,20 @@ static int imx_rngc_probe(struct platform_device *pdev)
+ if (irq < 0)
+ return irq;
+
+- ret = clk_prepare_enable(rngc->clk);
+- if (ret)
+- return ret;
+-
+ ver_id = readl(rngc->base + RNGC_VER_ID);
+ rng_type = ver_id >> RNGC_TYPE_SHIFT;
+ /*
+ * This driver supports only RNGC and RNGB. (There's a different
+ * driver for RNGA.)
+ */
+- if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
+- ret = -ENODEV;
+- goto err;
+- }
++ if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB)
++ return -ENODEV;
+
+ ret = devm_request_irq(&pdev->dev,
+ irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
+ if (ret) {
+ dev_err(rngc->dev, "Can't get interrupt working.\n");
+- goto err;
++ return ret;
+ }
+
+ init_completion(&rngc->rng_op_done);
+@@ -294,14 +288,14 @@ static int imx_rngc_probe(struct platform_device *pdev)
+ ret = imx_rngc_self_test(rngc);
+ if (ret) {
+ dev_err(rngc->dev, "self test failed\n");
+- goto err;
++ return ret;
+ }
+ }
+
+ ret = hwrng_register(&rngc->rng);
+ if (ret) {
+ dev_err(&pdev->dev, "hwrng registration failed\n");
+- goto err;
++ return ret;
+ }
+
+ dev_info(&pdev->dev,
+@@ -309,11 +303,6 @@ static int imx_rngc_probe(struct platform_device *pdev)
+ rng_type == RNGC_TYPE_RNGB ? 'B' : 'C',
+ (ver_id >> RNGC_VER_MAJ_SHIFT) & 0xff, ver_id & 0xff);
+ return 0;
+-
+-err:
+- clk_disable_unprepare(rngc->clk);
+-
+- return ret;
+ }
+
+ static int __exit imx_rngc_remove(struct platform_device *pdev)
+@@ -322,8 +311,6 @@ static int __exit imx_rngc_remove(struct platform_device *pdev)
+
+ hwrng_unregister(&rngc->rng);
+
+- clk_disable_unprepare(rngc->clk);
+-
+ return 0;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From b76e72d4551af9d9aabf011880c02dae50648d3f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 15:45:04 -0400
+Subject: i2c: mlxbf: support lock mechanism
+
+From: Asmaa Mnebhi <asmaa@nvidia.com>
+
+[ Upstream commit 86067ccfa1424a26491542d6f6d7546d40b61a10 ]
+
+Linux is not the only entity using the BlueField I2C busses so
+support a lock mechanism provided by hardware to avoid issues
+when multiple entities are trying to access the same bus.
+
+The lock is acquired whenever written explicitely or the lock
+register is read. So make sure it is always released at the end
+of a successful or failed transaction.
+
+Fixes: b5b5b32081cd206b (i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC)
+Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
+Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/i2c/busses/i2c-mlxbf.c | 44 ++++++++++++++++++++++++++++++----
+ 1 file changed, 39 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
+index ad5efd7497d1..0e840eba4fd6 100644
+--- a/drivers/i2c/busses/i2c-mlxbf.c
++++ b/drivers/i2c/busses/i2c-mlxbf.c
+@@ -306,6 +306,7 @@ static u64 mlxbf_i2c_corepll_frequency;
+ * exact.
+ */
+ #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */
++#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */
+
+ /* Encapsulates timing parameters. */
+ struct mlxbf_i2c_timings {
+@@ -514,6 +515,25 @@ static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)
+ return false;
+ }
+
++/*
++ * wait for the lock to be released before acquiring it.
++ */
++static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv)
++{
++ if (mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW,
++ MLXBF_I2C_MASTER_LOCK_BIT, true,
++ MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT))
++ return true;
++
++ return false;
++}
++
++static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv)
++{
++ /* Clear the gw to clear the lock */
++ writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
++}
++
+ static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,
+ u32 cause_status)
+ {
+@@ -705,10 +725,19 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
+ slave = request->slave & GENMASK(6, 0);
+ addr = slave << 1;
+
+- /* First of all, check whether the HW is idle. */
+- if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv)))
++ /*
++ * Try to acquire the smbus gw lock before any reads of the GW register since
++ * a read sets the lock.
++ */
++ if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv)))
+ return -EBUSY;
+
++ /* Check whether the HW is idle */
++ if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) {
++ ret = -EBUSY;
++ goto out_unlock;
++ }
++
+ /* Set first byte. */
+ data_desc[data_idx++] = addr;
+
+@@ -732,8 +761,10 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
+ write_en = 1;
+ write_len += operation->length;
+ if (data_idx + operation->length >
+- MLXBF_I2C_MASTER_DATA_DESC_SIZE)
+- return -ENOBUFS;
++ MLXBF_I2C_MASTER_DATA_DESC_SIZE) {
++ ret = -ENOBUFS;
++ goto out_unlock;
++ }
+ memcpy(data_desc + data_idx,
+ operation->buffer, operation->length);
+ data_idx += operation->length;
+@@ -765,7 +796,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
+ ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
+ pec_en, 0);
+ if (ret)
+- return ret;
++ goto out_unlock;
+ }
+
+ if (read_en) {
+@@ -792,6 +823,9 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
+ priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
+ }
+
++out_unlock:
++ mlxbf_i2c_smbus_master_unlock(priv);
++
+ return ret;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From a271fd1eaf82758ec79cc7c46bcf9ea2364d60ed Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 10 Sep 2022 18:26:16 -0700
+Subject: ia64: export memory_add_physaddr_to_nid to fix cxl build error
+
+From: Randy Dunlap <rdunlap@infradead.org>
+
+[ Upstream commit 97c318bfbe84efded246e80428054f300042f110 ]
+
+cxl_pmem.ko uses memory_add_physaddr_to_nid() but ia64 does not export it,
+so this causes a build error:
+
+ERROR: modpost: "memory_add_physaddr_to_nid" [drivers/cxl/cxl_pmem.ko] undefined!
+
+Fix this by exporting that function.
+
+Fixes: 8c2676a5870a ("hot-add-mem x86_64: memory_add_physaddr_to_nid node fixup")
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: Dan Williams <dan.j.williams@intel.com>
+Cc: Ben Widawsky <bwidawsk@kernel.org>
+Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Cc: linux-ia64@vger.kernel.org
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Keith Mannthey <kmannth@us.ibm.com>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/ia64/mm/numa.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/ia64/mm/numa.c b/arch/ia64/mm/numa.c
+index d6579ec3ea32..4c7b1f50e3b7 100644
+--- a/arch/ia64/mm/numa.c
++++ b/arch/ia64/mm/numa.c
+@@ -75,5 +75,6 @@ int memory_add_physaddr_to_nid(u64 addr)
+ return 0;
+ return nid;
+ }
++EXPORT_SYMBOL(memory_add_physaddr_to_nid);
+ #endif
+ #endif
+--
+2.35.1
+
--- /dev/null
+From fc46b0f0739239d4617900b88822a9f0a87b972f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 18 Aug 2022 13:32:33 +0200
+Subject: iavf: Fix race between iavf_close and iavf_reset_task
+
+From: Michal Jaron <michalx.jaron@intel.com>
+
+[ Upstream commit 11c12adcbc1598d91e73ab6ddfa41d25a01478ed ]
+
+During stress tests with adding VF to namespace and changing vf's
+trust there was a race between iavf_reset_task and iavf_close.
+Sometimes when IAVF_FLAG_AQ_DISABLE_QUEUES from iavf_close was sent
+to PF after reset and before IAVF_AQ_GET_CONFIG was sent then PF
+returns error IAVF_NOT_SUPPORTED to disable queues request and
+following requests. There is need to get_config before other
+aq_required will be send but iavf_close clears all flags, if
+get_config was not sent before iavf_close, then it will not be send
+at all.
+
+In case when IAVF_FLAG_AQ_GET_OFFLOAD_VLAN_V2_CAPS was sent before
+IAVF_FLAG_AQ_DISABLE_QUEUES then there was rtnl_lock deadlock
+between iavf_close and iavf_adminq_task until iavf_close timeouts
+and disable queues was sent after iavf_close ends.
+
+There was also a problem with sending delete/add filters.
+Sometimes when filters was not yet added to PF and in
+iavf_close all filters was set to remove there might be a try
+to remove nonexistent filters on PF.
+
+Add aq_required_tmp to save aq_required flags and send them after
+disable_queues will be handled. Clear flags given to iavf_down
+different than IAVF_FLAG_AQ_GET_CONFIG as this flag is necessary
+to sent other aq_required. Remove some flags that we don't
+want to send as we are in iavf_close and we want to disable
+interface. Remove filters which was not yet sent and send del
+filters flags only when there are filters to remove.
+
+Signed-off-by: Michal Jaron <michalx.jaron@intel.com>
+Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com>
+Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/iavf/iavf_main.c | 177 ++++++++++++++++----
+ 1 file changed, 141 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c
+index 00b2ef01f4ea..629ebdfa48b8 100644
+--- a/drivers/net/ethernet/intel/iavf/iavf_main.c
++++ b/drivers/net/ethernet/intel/iavf/iavf_main.c
+@@ -1012,66 +1012,138 @@ static void iavf_up_complete(struct iavf_adapter *adapter)
+ }
+
+ /**
+- * iavf_down - Shutdown the connection processing
++ * iavf_clear_mac_vlan_filters - Remove mac and vlan filters not sent to PF
++ * yet and mark other to be removed.
+ * @adapter: board private structure
+- *
+- * Expects to be called while holding the __IAVF_IN_CRITICAL_TASK bit lock.
+ **/
+-void iavf_down(struct iavf_adapter *adapter)
++static void iavf_clear_mac_vlan_filters(struct iavf_adapter *adapter)
+ {
+- struct net_device *netdev = adapter->netdev;
+- struct iavf_vlan_filter *vlf;
+- struct iavf_cloud_filter *cf;
+- struct iavf_fdir_fltr *fdir;
+- struct iavf_mac_filter *f;
+- struct iavf_adv_rss *rss;
+-
+- if (adapter->state <= __IAVF_DOWN_PENDING)
+- return;
+-
+- netif_carrier_off(netdev);
+- netif_tx_disable(netdev);
+- adapter->link_up = false;
+- iavf_napi_disable_all(adapter);
+- iavf_irq_disable(adapter);
++ struct iavf_vlan_filter *vlf, *vlftmp;
++ struct iavf_mac_filter *f, *ftmp;
+
+ spin_lock_bh(&adapter->mac_vlan_list_lock);
+-
+ /* clear the sync flag on all filters */
+ __dev_uc_unsync(adapter->netdev, NULL);
+ __dev_mc_unsync(adapter->netdev, NULL);
+
+ /* remove all MAC filters */
+- list_for_each_entry(f, &adapter->mac_filter_list, list) {
+- f->remove = true;
++ list_for_each_entry_safe(f, ftmp, &adapter->mac_filter_list,
++ list) {
++ if (f->add) {
++ list_del(&f->list);
++ kfree(f);
++ } else {
++ f->remove = true;
++ }
+ }
+
+ /* remove all VLAN filters */
+- list_for_each_entry(vlf, &adapter->vlan_filter_list, list) {
+- vlf->remove = true;
++ list_for_each_entry_safe(vlf, vlftmp, &adapter->vlan_filter_list,
++ list) {
++ if (vlf->add) {
++ list_del(&vlf->list);
++ kfree(vlf);
++ } else {
++ vlf->remove = true;
++ }
+ }
+-
+ spin_unlock_bh(&adapter->mac_vlan_list_lock);
++}
++
++/**
++ * iavf_clear_cloud_filters - Remove cloud filters not sent to PF yet and
++ * mark other to be removed.
++ * @adapter: board private structure
++ **/
++static void iavf_clear_cloud_filters(struct iavf_adapter *adapter)
++{
++ struct iavf_cloud_filter *cf, *cftmp;
+
+ /* remove all cloud filters */
+ spin_lock_bh(&adapter->cloud_filter_list_lock);
+- list_for_each_entry(cf, &adapter->cloud_filter_list, list) {
+- cf->del = true;
++ list_for_each_entry_safe(cf, cftmp, &adapter->cloud_filter_list,
++ list) {
++ if (cf->add) {
++ list_del(&cf->list);
++ kfree(cf);
++ adapter->num_cloud_filters--;
++ } else {
++ cf->del = true;
++ }
+ }
+ spin_unlock_bh(&adapter->cloud_filter_list_lock);
++}
++
++/**
++ * iavf_clear_fdir_filters - Remove fdir filters not sent to PF yet and mark
++ * other to be removed.
++ * @adapter: board private structure
++ **/
++static void iavf_clear_fdir_filters(struct iavf_adapter *adapter)
++{
++ struct iavf_fdir_fltr *fdir, *fdirtmp;
+
+ /* remove all Flow Director filters */
+ spin_lock_bh(&adapter->fdir_fltr_lock);
+- list_for_each_entry(fdir, &adapter->fdir_list_head, list) {
+- fdir->state = IAVF_FDIR_FLTR_DEL_REQUEST;
++ list_for_each_entry_safe(fdir, fdirtmp, &adapter->fdir_list_head,
++ list) {
++ if (fdir->state == IAVF_FDIR_FLTR_ADD_REQUEST) {
++ list_del(&fdir->list);
++ kfree(fdir);
++ adapter->fdir_active_fltr--;
++ } else {
++ fdir->state = IAVF_FDIR_FLTR_DEL_REQUEST;
++ }
+ }
+ spin_unlock_bh(&adapter->fdir_fltr_lock);
++}
++
++/**
++ * iavf_clear_adv_rss_conf - Remove adv rss conf not sent to PF yet and mark
++ * other to be removed.
++ * @adapter: board private structure
++ **/
++static void iavf_clear_adv_rss_conf(struct iavf_adapter *adapter)
++{
++ struct iavf_adv_rss *rss, *rsstmp;
+
+ /* remove all advance RSS configuration */
+ spin_lock_bh(&adapter->adv_rss_lock);
+- list_for_each_entry(rss, &adapter->adv_rss_list_head, list)
+- rss->state = IAVF_ADV_RSS_DEL_REQUEST;
++ list_for_each_entry_safe(rss, rsstmp, &adapter->adv_rss_list_head,
++ list) {
++ if (rss->state == IAVF_ADV_RSS_ADD_REQUEST) {
++ list_del(&rss->list);
++ kfree(rss);
++ } else {
++ rss->state = IAVF_ADV_RSS_DEL_REQUEST;
++ }
++ }
+ spin_unlock_bh(&adapter->adv_rss_lock);
++}
++
++/**
++ * iavf_down - Shutdown the connection processing
++ * @adapter: board private structure
++ *
++ * Expects to be called while holding the __IAVF_IN_CRITICAL_TASK bit lock.
++ **/
++void iavf_down(struct iavf_adapter *adapter)
++{
++ struct net_device *netdev = adapter->netdev;
++
++ if (adapter->state <= __IAVF_DOWN_PENDING)
++ return;
++
++ netif_carrier_off(netdev);
++ netif_tx_disable(netdev);
++ adapter->link_up = false;
++ iavf_napi_disable_all(adapter);
++ iavf_irq_disable(adapter);
++
++ iavf_clear_mac_vlan_filters(adapter);
++ iavf_clear_cloud_filters(adapter);
++ iavf_clear_fdir_filters(adapter);
++ iavf_clear_adv_rss_conf(adapter);
+
+ if (!(adapter->flags & IAVF_FLAG_PF_COMMS_FAILED)) {
+ /* cancel any current operation */
+@@ -1080,11 +1152,16 @@ void iavf_down(struct iavf_adapter *adapter)
+ * here for this to complete. The watchdog is still running
+ * and it will take care of this.
+ */
+- adapter->aq_required = IAVF_FLAG_AQ_DEL_MAC_FILTER;
+- adapter->aq_required |= IAVF_FLAG_AQ_DEL_VLAN_FILTER;
+- adapter->aq_required |= IAVF_FLAG_AQ_DEL_CLOUD_FILTER;
+- adapter->aq_required |= IAVF_FLAG_AQ_DEL_FDIR_FILTER;
+- adapter->aq_required |= IAVF_FLAG_AQ_DEL_ADV_RSS_CFG;
++ if (!list_empty(&adapter->mac_filter_list))
++ adapter->aq_required |= IAVF_FLAG_AQ_DEL_MAC_FILTER;
++ if (!list_empty(&adapter->vlan_filter_list))
++ adapter->aq_required |= IAVF_FLAG_AQ_DEL_VLAN_FILTER;
++ if (!list_empty(&adapter->cloud_filter_list))
++ adapter->aq_required |= IAVF_FLAG_AQ_DEL_CLOUD_FILTER;
++ if (!list_empty(&adapter->fdir_list_head))
++ adapter->aq_required |= IAVF_FLAG_AQ_DEL_FDIR_FILTER;
++ if (!list_empty(&adapter->adv_rss_list_head))
++ adapter->aq_required |= IAVF_FLAG_AQ_DEL_ADV_RSS_CFG;
+ adapter->aq_required |= IAVF_FLAG_AQ_DISABLE_QUEUES;
+ }
+
+@@ -3483,6 +3560,7 @@ static int iavf_open(struct net_device *netdev)
+ static int iavf_close(struct net_device *netdev)
+ {
+ struct iavf_adapter *adapter = netdev_priv(netdev);
++ u64 aq_to_restore;
+ int status;
+
+ mutex_lock(&adapter->crit_lock);
+@@ -3495,6 +3573,29 @@ static int iavf_close(struct net_device *netdev)
+ set_bit(__IAVF_VSI_DOWN, adapter->vsi.state);
+ if (CLIENT_ENABLED(adapter))
+ adapter->flags |= IAVF_FLAG_CLIENT_NEEDS_CLOSE;
++ /* We cannot send IAVF_FLAG_AQ_GET_OFFLOAD_VLAN_V2_CAPS before
++ * IAVF_FLAG_AQ_DISABLE_QUEUES because in such case there is rtnl
++ * deadlock with adminq_task() until iavf_close timeouts. We must send
++ * IAVF_FLAG_AQ_GET_CONFIG before IAVF_FLAG_AQ_DISABLE_QUEUES to make
++ * disable queues possible for vf. Give only necessary flags to
++ * iavf_down and save other to set them right before iavf_close()
++ * returns, when IAVF_FLAG_AQ_DISABLE_QUEUES will be already sent and
++ * iavf will be in DOWN state.
++ */
++ aq_to_restore = adapter->aq_required;
++ adapter->aq_required &= IAVF_FLAG_AQ_GET_CONFIG;
++
++ /* Remove flags which we do not want to send after close or we want to
++ * send before disable queues.
++ */
++ aq_to_restore &= ~(IAVF_FLAG_AQ_GET_CONFIG |
++ IAVF_FLAG_AQ_ENABLE_QUEUES |
++ IAVF_FLAG_AQ_CONFIGURE_QUEUES |
++ IAVF_FLAG_AQ_ADD_VLAN_FILTER |
++ IAVF_FLAG_AQ_ADD_MAC_FILTER |
++ IAVF_FLAG_AQ_ADD_CLOUD_FILTER |
++ IAVF_FLAG_AQ_ADD_FDIR_FILTER |
++ IAVF_FLAG_AQ_ADD_ADV_RSS_CFG);
+
+ iavf_down(adapter);
+ iavf_change_state(adapter, __IAVF_DOWN_PENDING);
+@@ -3518,6 +3619,10 @@ static int iavf_close(struct net_device *netdev)
+ msecs_to_jiffies(500));
+ if (!status)
+ netdev_warn(netdev, "Device resources not yet released\n");
++
++ mutex_lock(&adapter->crit_lock);
++ adapter->aq_required |= aq_to_restore;
++ mutex_unlock(&adapter->crit_lock);
+ return 0;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 55d6a7a2d1eda054b07ffe7793166794cedbabe0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 17:14:57 +0800
+Subject: IB/rdmavt: Add __init/__exit annotations to module init/exit funcs
+
+From: Xiu Jianfeng <xiujianfeng@huawei.com>
+
+[ Upstream commit 78657a445ca7603024348781c921f8ecaee10a49 ]
+
+Add missing __init/__exit annotations to module init/exit funcs.
+
+Fixes: 0194621b2253 ("IB/rdmavt: Create module framework and handle driver registration")
+Link: https://lore.kernel.org/r/20220924091457.52446-1-xiujianfeng@huawei.com
+Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/rdmavt/vt.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/infiniband/sw/rdmavt/vt.c b/drivers/infiniband/sw/rdmavt/vt.c
+index 59481ae39505..d61f8de7f21c 100644
+--- a/drivers/infiniband/sw/rdmavt/vt.c
++++ b/drivers/infiniband/sw/rdmavt/vt.c
+@@ -15,7 +15,7 @@
+ MODULE_LICENSE("Dual BSD/GPL");
+ MODULE_DESCRIPTION("RDMA Verbs Transport Library");
+
+-static int rvt_init(void)
++static int __init rvt_init(void)
+ {
+ int ret = rvt_driver_cq_init();
+
+@@ -26,7 +26,7 @@ static int rvt_init(void)
+ }
+ module_init(rvt_init);
+
+-static void rvt_cleanup(void)
++static void __exit rvt_cleanup(void)
+ {
+ rvt_cq_exit();
+ }
+--
+2.35.1
+
--- /dev/null
+From 1817762f5dccfb4b3dec7b61b79446b341ac8ed4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 17:08:43 +0900
+Subject: IB: Set IOVA/LENGTH on IB_MR in core/uverbs layers
+
+From: Daisuke Matsuda <matsuda-daisuke@fujitsu.com>
+
+[ Upstream commit 241f9a27e0fc0eaf23e3d52c8450f10648cd11f1 ]
+
+Set 'iova' and 'length' on ib_mr in ib_uverbs and ib_core layers to let all
+drivers have the members filled. Also, this commit removes redundancy in
+the respective drivers.
+
+Previously, commit 04c0a5fcfcf65 ("IB/uverbs: Set IOVA on IB MR in uverbs
+layer") changed to set 'iova', but seems to have missed 'length' and the
+ib_core layer at that time.
+
+Fixes: 04c0a5fcfcf65 ("IB/uverbs: Set IOVA on IB MR in uverbs layer")
+Signed-off-by: Daisuke Matsuda <matsuda-daisuke@fujitsu.com>
+Link: https://lore.kernel.org/r/20220921080844.1616883-1-matsuda-daisuke@fujitsu.com
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/core/uverbs_cmd.c | 5 ++++-
+ drivers/infiniband/core/verbs.c | 2 ++
+ drivers/infiniband/hw/hns/hns_roce_mr.c | 1 -
+ drivers/infiniband/hw/mlx4/mr.c | 1 -
+ 4 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c
+index d1345d76d9b1..9f0e0402fbc0 100644
+--- a/drivers/infiniband/core/uverbs_cmd.c
++++ b/drivers/infiniband/core/uverbs_cmd.c
+@@ -739,6 +739,7 @@ static int ib_uverbs_reg_mr(struct uverbs_attr_bundle *attrs)
+ mr->uobject = uobj;
+ atomic_inc(&pd->usecnt);
+ mr->iova = cmd.hca_va;
++ mr->length = cmd.length;
+
+ rdma_restrack_new(&mr->res, RDMA_RESTRACK_MR);
+ rdma_restrack_set_name(&mr->res, NULL);
+@@ -861,8 +862,10 @@ static int ib_uverbs_rereg_mr(struct uverbs_attr_bundle *attrs)
+ mr->pd = new_pd;
+ atomic_inc(&new_pd->usecnt);
+ }
+- if (cmd.flags & IB_MR_REREG_TRANS)
++ if (cmd.flags & IB_MR_REREG_TRANS) {
+ mr->iova = cmd.hca_va;
++ mr->length = cmd.length;
++ }
+ }
+
+ memset(&resp, 0, sizeof(resp));
+diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
+index 59e20936b800..b721085bb597 100644
+--- a/drivers/infiniband/core/verbs.c
++++ b/drivers/infiniband/core/verbs.c
+@@ -2157,6 +2157,8 @@ struct ib_mr *ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
+ mr->pd = pd;
+ mr->dm = NULL;
+ atomic_inc(&pd->usecnt);
++ mr->iova = virt_addr;
++ mr->length = length;
+
+ rdma_restrack_new(&mr->res, RDMA_RESTRACK_MR);
+ rdma_restrack_parent_name(&mr->res, &pd->res);
+diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c
+index 7089ac780291..20360df25771 100644
+--- a/drivers/infiniband/hw/hns/hns_roce_mr.c
++++ b/drivers/infiniband/hw/hns/hns_roce_mr.c
+@@ -272,7 +272,6 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
+ goto err_alloc_pbl;
+
+ mr->ibmr.rkey = mr->ibmr.lkey = mr->key;
+- mr->ibmr.length = length;
+
+ return &mr->ibmr;
+
+diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c
+index 04a67b481608..a40bf58bcdd3 100644
+--- a/drivers/infiniband/hw/mlx4/mr.c
++++ b/drivers/infiniband/hw/mlx4/mr.c
+@@ -439,7 +439,6 @@ struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
+ goto err_mr;
+
+ mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
+- mr->ibmr.length = length;
+ mr->ibmr.page_size = 1U << shift;
+
+ return &mr->ibmr;
+--
+2.35.1
+
--- /dev/null
+From a7b13568cf2cb8a8a8595ee9ded240857e83df9e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 16:15:57 -0700
+Subject: ice: set tx_tstamps when creating new Tx rings via ethtool
+
+From: Jacob Keller <jacob.e.keller@intel.com>
+
+[ Upstream commit b3b173745c8cab1e24d6821488b60abed3acb24d ]
+
+When the user changes the number of queues via ethtool, the driver
+allocates new rings. This allocation did not initialize tx_tstamps. This
+results in the tx_tstamps field being zero (due to kcalloc allocation), and
+would result in a NULL pointer dereference when attempting a transmit
+timestamp on the new ring.
+
+Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
+Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/ice/ice_ethtool.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c
+index 9b9c2b885486..f10d9c377c74 100644
+--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c
++++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c
+@@ -2788,6 +2788,7 @@ ice_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
+ tx_rings[i].count = new_tx_cnt;
+ tx_rings[i].desc = NULL;
+ tx_rings[i].tx_buf = NULL;
++ tx_rings[i].tx_tstamps = &pf->ptp.port.tx;
+ err = ice_setup_tx_ring(&tx_rings[i]);
+ if (err) {
+ while (i--)
+--
+2.35.1
+
--- /dev/null
+From 5c45428304965605a62a9ad8b530f7063d6bdf72 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 26 Jun 2022 13:29:23 +0100
+Subject: iio: ABI: Fix wrong format of differential capacitance channel ABI.
+
+From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+
+[ Upstream commit 1efc41035f1841acf0af2bab153158e27ce94f10 ]
+
+in_ only occurs once in these attributes.
+
+Fixes: 0baf29d658c7 ("staging:iio:documentation Add abi docs for capacitance adcs.")
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20220626122938.582107-3-jic23@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ Documentation/ABI/testing/sysfs-bus-iio | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
+index 6ad47a67521c..f41e767e702b 100644
+--- a/Documentation/ABI/testing/sysfs-bus-iio
++++ b/Documentation/ABI/testing/sysfs-bus-iio
+@@ -188,7 +188,7 @@ Description:
+ Raw capacitance measurement from channel Y. Units after
+ application of scale and offset are nanofarads.
+
+-What: /sys/.../iio:deviceX/in_capacitanceY-in_capacitanceZ_raw
++What: /sys/.../iio:deviceX/in_capacitanceY-capacitanceZ_raw
+ KernelVersion: 3.2
+ Contact: linux-iio@vger.kernel.org
+ Description:
+--
+2.35.1
+
--- /dev/null
+From 93ab1900d0fbda1c5b60ccac4e446d917e9c6262 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 13:28:38 +0300
+Subject: iio: adc: at91-sama5d2_adc: check return status for pressure and
+ touch
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit d84ace944a3b24529798dbae1340dea098473155 ]
+
+Check return status of at91_adc_read_position() and
+at91_adc_read_pressure() in at91_adc_read_info_raw().
+
+Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220803102855.2191070-3-claudiu.beznea@microchip.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/at91-sama5d2_adc.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
+index 92e2e7420aa9..6eb72ba6b4d2 100644
+--- a/drivers/iio/adc/at91-sama5d2_adc.c
++++ b/drivers/iio/adc/at91-sama5d2_adc.c
+@@ -1331,8 +1331,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
+ *val = tmp_val;
+ mutex_unlock(&st->lock);
+ iio_device_release_direct_mode(indio_dev);
++ if (ret > 0)
++ ret = at91_adc_adjust_val_osr(st, val);
+
+- return at91_adc_adjust_val_osr(st, val);
++ return ret;
+ }
+ if (chan->type == IIO_PRESSURE) {
+ ret = iio_device_claim_direct_mode(indio_dev);
+@@ -1345,8 +1347,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
+ *val = tmp_val;
+ mutex_unlock(&st->lock);
+ iio_device_release_direct_mode(indio_dev);
++ if (ret > 0)
++ ret = at91_adc_adjust_val_osr(st, val);
+
+- return at91_adc_adjust_val_osr(st, val);
++ return ret;
+ }
+
+ /* in this case we have a voltage channel */
+--
+2.35.1
+
--- /dev/null
+From 190000bcc4a226a701a1c2081421aab0aac71670 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 13:28:40 +0300
+Subject: iio: adc: at91-sama5d2_adc: disable/prepare buffer on suspend/resume
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit 808175e21d9b7f866eda742e8970f27b78afe5db ]
+
+In case triggered buffers are enabled while system is suspended they will
+not work anymore after resume. For this call at91_adc_buffer_postdisable()
+on suspend and at91_adc_buffer_prepare() on resume. On tests it has been
+seen that at91_adc_buffer_postdisable() call is not necessary but it has
+been kept because it also does the book keeping for DMA. On resume path
+there is no need to call at91_adc_configure_touch() as it is embedded in
+at91_adc_buffer_prepare().
+
+Fixes: 073c662017f2f ("iio: adc: at91-sama5d2_adc: add support for DMA")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220803102855.2191070-5-claudiu.beznea@microchip.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/at91-sama5d2_adc.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
+index 9cd6a779a217..403a29e4dc3e 100644
+--- a/drivers/iio/adc/at91-sama5d2_adc.c
++++ b/drivers/iio/adc/at91-sama5d2_adc.c
+@@ -1903,6 +1903,9 @@ static __maybe_unused int at91_adc_suspend(struct device *dev)
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct at91_adc_state *st = iio_priv(indio_dev);
+
++ if (iio_buffer_enabled(indio_dev))
++ at91_adc_buffer_postdisable(indio_dev);
++
+ /*
+ * Do a sofware reset of the ADC before we go to suspend.
+ * this will ensure that all pins are free from being muxed by the ADC
+@@ -1946,14 +1949,11 @@ static __maybe_unused int at91_adc_resume(struct device *dev)
+ if (!iio_buffer_enabled(indio_dev))
+ return 0;
+
+- /* check if we are enabling triggered buffer or the touchscreen */
+- if (at91_adc_current_chan_is_touch(indio_dev))
+- return at91_adc_configure_touch(st, true);
+- else
+- return at91_adc_configure_trigger(st->trig, true);
++ ret = at91_adc_buffer_prepare(indio_dev);
++ if (ret)
++ goto vref_disable_resume;
+
+- /* not needed but more explicit */
+- return 0;
++ return at91_adc_configure_trigger(st->trig, true);
+
+ vref_disable_resume:
+ regulator_disable(st->vref);
+--
+2.35.1
+
--- /dev/null
+From 241d13430b9f131df78798b8fb2995e8c09c98b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 13:28:37 +0300
+Subject: iio: adc: at91-sama5d2_adc: fix AT91_SAMA5D2_MR_TRACKTIM_MAX
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit bb73d5d9164c57c4bb916739a98e5cd8e0a5ed8c ]
+
+All ADC HW versions handled by this driver (SAMA5D2, SAM9X60, SAMA7G5)
+have MR.TRACKTIM on 4 bits. Fix AT91_SAMA5D2_MR_TRACKTIM_MAX to reflect
+this.
+
+Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220803102855.2191070-2-claudiu.beznea@microchip.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/at91-sama5d2_adc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
+index c4de706012e5..92e2e7420aa9 100644
+--- a/drivers/iio/adc/at91-sama5d2_adc.c
++++ b/drivers/iio/adc/at91-sama5d2_adc.c
+@@ -74,7 +74,7 @@
+ #define AT91_SAMA5D2_MR_ANACH BIT(23)
+ /* Tracking Time */
+ #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
+-#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
++#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf
+ /* Transfer Time */
+ #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
+ #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
+--
+2.35.1
+
--- /dev/null
+From 575068fb8ba083a6f7a1cdf0e3a262cc91b90d68 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 13:28:39 +0300
+Subject: iio: adc: at91-sama5d2_adc: lock around oversampling and sample freq
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit 9780a23ed5a0a0a63683e078f576719a98d4fb70 ]
+
+.read_raw()/.write_raw() could be called asynchronously from user space
+or other in kernel drivers. Without locking on st->lock these could be
+called asynchronously while there is a conversion in progress. Read will
+be harmless but changing registers while conversion is in progress may
+lead to inconsistent results. Thus, to avoid this lock st->lock.
+
+Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver")
+Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220803102855.2191070-4-claudiu.beznea@microchip.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/at91-sama5d2_adc.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
+index 6eb72ba6b4d2..9cd6a779a217 100644
+--- a/drivers/iio/adc/at91-sama5d2_adc.c
++++ b/drivers/iio/adc/at91-sama5d2_adc.c
+@@ -1329,10 +1329,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
+ ret = at91_adc_read_position(st, chan->channel,
+ &tmp_val);
+ *val = tmp_val;
+- mutex_unlock(&st->lock);
+- iio_device_release_direct_mode(indio_dev);
+ if (ret > 0)
+ ret = at91_adc_adjust_val_osr(st, val);
++ mutex_unlock(&st->lock);
++ iio_device_release_direct_mode(indio_dev);
+
+ return ret;
+ }
+@@ -1345,10 +1345,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
+ ret = at91_adc_read_pressure(st, chan->channel,
+ &tmp_val);
+ *val = tmp_val;
+- mutex_unlock(&st->lock);
+- iio_device_release_direct_mode(indio_dev);
+ if (ret > 0)
+ ret = at91_adc_adjust_val_osr(st, val);
++ mutex_unlock(&st->lock);
++ iio_device_release_direct_mode(indio_dev);
+
+ return ret;
+ }
+@@ -1441,16 +1441,20 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev,
+ /* if no change, optimize out */
+ if (val == st->oversampling_ratio)
+ return 0;
++ mutex_lock(&st->lock);
+ st->oversampling_ratio = val;
+ /* update ratio */
+ at91_adc_config_emr(st);
++ mutex_unlock(&st->lock);
+ return 0;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ if (val < st->soc_info.min_sample_rate ||
+ val > st->soc_info.max_sample_rate)
+ return -EINVAL;
+
++ mutex_lock(&st->lock);
+ at91_adc_setup_samp_freq(indio_dev, val);
++ mutex_unlock(&st->lock);
+ return 0;
+ default:
+ return -EINVAL;
+--
+2.35.1
+
--- /dev/null
+From 587aa29f8ec332c76741c41c409ea8c714a99a6c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 27 May 2022 09:17:39 +0000
+Subject: iio: Directly use ida_alloc()/free()
+
+From: keliu <liuke94@huawei.com>
+
+[ Upstream commit 319dbcd84fd2676afb2bcfee575fbc1fce474ec3 ]
+
+Use ida_alloc()/ida_free() instead of deprecated
+ida_simple_get()/ida_simple_remove() .
+
+Signed-off-by: keliu <liuke94@huawei.com>
+Link: https://lore.kernel.org/r/20220527091739.2949426-1-liuke94@huawei.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 2bc9cd66eb25 ("iio: Use per-device lockdep class for mlock")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/industrialio-core.c | 6 +++---
+ drivers/iio/industrialio-trigger.c | 6 +++---
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
+index a7f5d432c95d..0c81c7630fb9 100644
+--- a/drivers/iio/industrialio-core.c
++++ b/drivers/iio/industrialio-core.c
+@@ -1631,7 +1631,7 @@ static void iio_dev_release(struct device *device)
+
+ iio_device_detach_buffers(indio_dev);
+
+- ida_simple_remove(&iio_ida, iio_dev_opaque->id);
++ ida_free(&iio_ida, iio_dev_opaque->id);
+ kfree(iio_dev_opaque);
+ }
+
+@@ -1674,7 +1674,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv)
+ mutex_init(&iio_dev_opaque->info_exist_lock);
+ INIT_LIST_HEAD(&iio_dev_opaque->channel_attr_list);
+
+- iio_dev_opaque->id = ida_simple_get(&iio_ida, 0, 0, GFP_KERNEL);
++ iio_dev_opaque->id = ida_alloc(&iio_ida, GFP_KERNEL);
+ if (iio_dev_opaque->id < 0) {
+ /* cannot use a dev_err as the name isn't available */
+ pr_err("failed to get device id\n");
+@@ -1683,7 +1683,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv)
+ }
+
+ if (dev_set_name(&indio_dev->dev, "iio:device%d", iio_dev_opaque->id)) {
+- ida_simple_remove(&iio_ida, iio_dev_opaque->id);
++ ida_free(&iio_ida, iio_dev_opaque->id);
+ kfree(iio_dev_opaque);
+ return NULL;
+ }
+diff --git a/drivers/iio/industrialio-trigger.c b/drivers/iio/industrialio-trigger.c
+index f504ed351b3e..6eb9b721676e 100644
+--- a/drivers/iio/industrialio-trigger.c
++++ b/drivers/iio/industrialio-trigger.c
+@@ -71,7 +71,7 @@ int __iio_trigger_register(struct iio_trigger *trig_info,
+
+ trig_info->owner = this_mod;
+
+- trig_info->id = ida_simple_get(&iio_trigger_ida, 0, 0, GFP_KERNEL);
++ trig_info->id = ida_alloc(&iio_trigger_ida, GFP_KERNEL);
+ if (trig_info->id < 0)
+ return trig_info->id;
+
+@@ -98,7 +98,7 @@ int __iio_trigger_register(struct iio_trigger *trig_info,
+ mutex_unlock(&iio_trigger_list_lock);
+ device_del(&trig_info->dev);
+ error_unregister_id:
+- ida_simple_remove(&iio_trigger_ida, trig_info->id);
++ ida_free(&iio_trigger_ida, trig_info->id);
+ return ret;
+ }
+ EXPORT_SYMBOL(__iio_trigger_register);
+@@ -109,7 +109,7 @@ void iio_trigger_unregister(struct iio_trigger *trig_info)
+ list_del(&trig_info->list);
+ mutex_unlock(&iio_trigger_list_lock);
+
+- ida_simple_remove(&iio_trigger_ida, trig_info->id);
++ ida_free(&iio_trigger_ida, trig_info->id);
+ /* Possible issue in here */
+ device_del(&trig_info->dev);
+ }
+--
+2.35.1
+
--- /dev/null
+From ceddde54b5eb9f4013584b0f97f6b8dc3fa6020b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 15 Jul 2022 14:28:50 +0200
+Subject: iio: inkern: fix return value in devm_of_iio_channel_get_by_name()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Nuno Sá <nuno.sa@analog.com>
+
+[ Upstream commit 9e878dbc0e8322f8b2f5ab0093c1e89926362dbe ]
+
+of_iio_channel_get_by_name() can either return NULL or an error pointer
+so that only doing IS_ERR() is not enough. Fix it by checking the NULL
+pointer case and return -ENODEV in that case. Note this is done like this
+so that users of the function (which only check for error pointers) do
+not need to be changed. This is not ideal since we are losing error codes
+and as such, in a follow up change, things will be unified so that
+of_iio_channel_get_by_name() only returns error codes.
+
+Fixes: 6e39b145cef7 ("iio: provide of_iio_channel_get_by_name() and devm_ version it")
+Signed-off-by: Nuno Sá <nuno.sa@analog.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20220715122903.332535-3-nuno.sa@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/inkern.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c
+index 30a8ecb692f8..bf9ce01c854b 100644
+--- a/drivers/iio/inkern.c
++++ b/drivers/iio/inkern.c
+@@ -395,6 +395,8 @@ struct iio_channel *devm_of_iio_channel_get_by_name(struct device *dev,
+ channel = of_iio_channel_get_by_name(np, channel_name);
+ if (IS_ERR(channel))
+ return channel;
++ if (!channel)
++ return ERR_PTR(-ENODEV);
+
+ ret = devm_add_action_or_reset(dev, devm_iio_channel_free, channel);
+ if (ret)
+--
+2.35.1
+
--- /dev/null
+From e35762549db53aebf6c83ef47965005558a828c9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 15 Jul 2022 14:28:49 +0200
+Subject: iio: inkern: only release the device node when done with it
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Nuno Sá <nuno.sa@analog.com>
+
+[ Upstream commit 79c3e84874c7d14f04ad58313b64955a0d2e9437 ]
+
+'of_node_put()' can potentially release the memory pointed to by
+'iiospec.np' which would leave us with an invalid pointer (and we would
+still pass it in 'of_xlate()'). Note that it is not guaranteed for the
+of_node lifespan to be attached to the device (to which is attached)
+lifespan so that there is (even though very unlikely) the possibility
+for the node to be freed while the device is still around. Thus, as there
+are indeed some of_xlate users which do access the node, a race is indeed
+possible.
+
+As such, we can only release the node after we are done with it.
+
+Fixes: 17d82b47a215d ("iio: Add OF support")
+Signed-off-by: Nuno Sá <nuno.sa@analog.com>
+Link: https://lore.kernel.org/r/20220715122903.332535-2-nuno.sa@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/inkern.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c
+index b5966365d769..30a8ecb692f8 100644
+--- a/drivers/iio/inkern.c
++++ b/drivers/iio/inkern.c
+@@ -148,9 +148,10 @@ static int __of_iio_channel_get(struct iio_channel *channel,
+
+ idev = bus_find_device(&iio_bus_type, NULL, iiospec.np,
+ iio_dev_node_match);
+- of_node_put(iiospec.np);
+- if (idev == NULL)
++ if (idev == NULL) {
++ of_node_put(iiospec.np);
+ return -EPROBE_DEFER;
++ }
+
+ indio_dev = dev_to_iio_dev(idev);
+ channel->indio_dev = indio_dev;
+@@ -158,6 +159,7 @@ static int __of_iio_channel_get(struct iio_channel *channel,
+ index = indio_dev->info->of_xlate(indio_dev, &iiospec);
+ else
+ index = __of_iio_simple_xlate(indio_dev, &iiospec);
++ of_node_put(iiospec.np);
+ if (index < 0)
+ goto err_put;
+ channel->channel = &indio_dev->channels[index];
+--
+2.35.1
+
--- /dev/null
+From 11296fb8c2d4af8fec221062748b26c782d38402 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 Aug 2022 23:54:06 +0200
+Subject: iio: magnetometer: yas530: Change data type of hard_offsets to signed
+
+From: Jakob Hauser <jahau@rocketmail.com>
+
+[ Upstream commit e137fafc8985cf152a4bb6f18ae83ebb06816df1 ]
+
+The "hard_offsets" are currently unsigned u8 but they should be signed as they
+can get negative. They are signed in function yas5xx_meaure_offsets() and in the
+Yamaha drivers [1][2].
+
+[1] https://github.com/NovaFusion/android_kernel_samsung_golden/blob/cm-12.1/drivers/sensor/compass/yas.h#L156
+[2] https://github.com/msm8916-mainline/android_kernel_qcom_msm8916/blob/GT-I9195I/drivers/iio/magnetometer/yas_mag_drv-yas532.c#L91
+
+Fixes: de8860b1ed47 ("iio: magnetometer: Add driver for Yamaha YAS530")
+Signed-off-by: Jakob Hauser <jahau@rocketmail.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/40f052bf6491457d0c5c0ed4c3534dc6fa251c3c.1660337264.git.jahau@rocketmail.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/magnetometer/yamaha-yas530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/iio/magnetometer/yamaha-yas530.c b/drivers/iio/magnetometer/yamaha-yas530.c
+index b2bc637150bf..40192aa46b04 100644
+--- a/drivers/iio/magnetometer/yamaha-yas530.c
++++ b/drivers/iio/magnetometer/yamaha-yas530.c
+@@ -132,7 +132,7 @@ struct yas5xx {
+ unsigned int version;
+ char name[16];
+ struct yas5xx_calibration calibration;
+- u8 hard_offsets[3];
++ s8 hard_offsets[3];
+ struct iio_mount_matrix orientation;
+ struct regmap *map;
+ struct regulator_bulk_data regs[2];
+--
+2.35.1
+
--- /dev/null
+From 7c5e377abf5291491ee8ee052328bca335c3e12d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 11:18:40 +0200
+Subject: iio: Use per-device lockdep class for mlock
+
+From: Vincent Whitchurch <vincent.whitchurch@axis.com>
+
+[ Upstream commit 2bc9cd66eb25d0fefbb081421d6586495e25840e ]
+
+If an IIO driver uses callbacks from another IIO driver and calls
+iio_channel_start_all_cb() from one of its buffer setup ops, then
+lockdep complains due to the lock nesting, as in the below example with
+lmp91000.
+
+Since the locks are being taken on different IIO devices, there is no
+actual deadlock. Fix the warning by telling lockdep to use a different
+class for each iio_device.
+
+ ============================================
+ WARNING: possible recursive locking detected
+ --------------------------------------------
+ python3/23 is trying to acquire lock:
+ (&indio_dev->mlock){+.+.}-{3:3}, at: iio_update_buffers
+
+ but task is already holding lock:
+ (&indio_dev->mlock){+.+.}-{3:3}, at: enable_store
+
+ other info that might help us debug this:
+ Possible unsafe locking scenario:
+
+ CPU0
+ ----
+ lock(&indio_dev->mlock);
+ lock(&indio_dev->mlock);
+
+ *** DEADLOCK ***
+
+ May be due to missing lock nesting notation
+
+ 5 locks held by python3/23:
+ #0: (sb_writers#5){.+.+}-{0:0}, at: ksys_write
+ #1: (&of->mutex){+.+.}-{3:3}, at: kernfs_fop_write_iter
+ #2: (kn->active#14){.+.+}-{0:0}, at: kernfs_fop_write_iter
+ #3: (&indio_dev->mlock){+.+.}-{3:3}, at: enable_store
+ #4: (&iio_dev_opaque->info_exist_lock){+.+.}-{3:3}, at: iio_update_buffers
+
+ Call Trace:
+ __mutex_lock
+ iio_update_buffers
+ iio_channel_start_all_cb
+ lmp91000_buffer_postenable
+ __iio_update_buffers
+ enable_store
+
+Fixes: 67e17300dc1d76 ("iio: potentiostat: add LMP91000 support")
+Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20220829091840.2791846-1-vincent.whitchurch@axis.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/industrialio-core.c | 5 +++++
+ include/linux/iio/iio-opaque.h | 2 ++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
+index 0c81c7630fb9..9aca2612d894 100644
+--- a/drivers/iio/industrialio-core.c
++++ b/drivers/iio/industrialio-core.c
+@@ -1631,6 +1631,8 @@ static void iio_dev_release(struct device *device)
+
+ iio_device_detach_buffers(indio_dev);
+
++ lockdep_unregister_key(&iio_dev_opaque->mlock_key);
++
+ ida_free(&iio_ida, iio_dev_opaque->id);
+ kfree(iio_dev_opaque);
+ }
+@@ -1691,6 +1693,9 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv)
+ INIT_LIST_HEAD(&iio_dev_opaque->buffer_list);
+ INIT_LIST_HEAD(&iio_dev_opaque->ioctl_handlers);
+
++ lockdep_register_key(&iio_dev_opaque->mlock_key);
++ lockdep_set_class(&indio_dev->mlock, &iio_dev_opaque->mlock_key);
++
+ return indio_dev;
+ }
+ EXPORT_SYMBOL(iio_device_alloc);
+diff --git a/include/linux/iio/iio-opaque.h b/include/linux/iio/iio-opaque.h
+index c9504e9da571..50aad0f58cb4 100644
+--- a/include/linux/iio/iio-opaque.h
++++ b/include/linux/iio/iio-opaque.h
+@@ -8,6 +8,7 @@
+ * @indio_dev: public industrial I/O device information
+ * @id: used to identify device internally
+ * @driver_module: used to make it harder to undercut users
++ * @mlock_key: lockdep class for iio_dev lock
+ * @info_exist_lock: lock to prevent use during removal
+ * @trig_readonly: mark the current trigger immutable
+ * @event_interface: event chrdevs associated with interrupt lines
+@@ -36,6 +37,7 @@ struct iio_dev_opaque {
+ struct iio_dev indio_dev;
+ int id;
+ struct module *driver_module;
++ struct lock_class_key mlock_key;
+ struct mutex info_exist_lock;
+ bool trig_readonly;
+ struct iio_event_interface *event_interface;
+--
+2.35.1
+
--- /dev/null
+From 078224ccbaa07b32dff1f41a148bec6ee494f047 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Aug 2022 17:18:42 -0400
+Subject: ima: fix blocking of security.ima xattrs of unsupported algorithms
+
+From: Mimi Zohar <zohar@linux.ibm.com>
+
+[ Upstream commit 5926586f291b53cb8a0c9631fc19489be1186e2d ]
+
+Limit validating the hash algorithm to just security.ima xattr, not
+the security.evm xattr or any of the protected EVM security xattrs,
+nor posix acls.
+
+Fixes: 50f742dd9147 ("IMA: block writes of the security.ima xattr with unsupported algorithms")
+Reported-by: Christian Brauner <brauner@kernel.org>
+Acked-by: Christian Brauner (Microsoft) <brauner@kernel.org>
+Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ security/integrity/ima/ima_appraise.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
+index ed04bb7c7512..08b49bd1e8ca 100644
+--- a/security/integrity/ima/ima_appraise.c
++++ b/security/integrity/ima/ima_appraise.c
+@@ -644,22 +644,26 @@ int ima_inode_setxattr(struct dentry *dentry, const char *xattr_name,
+ const struct evm_ima_xattr_data *xvalue = xattr_value;
+ int digsig = 0;
+ int result;
++ int err;
+
+ result = ima_protect_xattr(dentry, xattr_name, xattr_value,
+ xattr_value_len);
+ if (result == 1) {
+ if (!xattr_value_len || (xvalue->type >= IMA_XATTR_LAST))
+ return -EINVAL;
++
++ err = validate_hash_algo(dentry, xvalue, xattr_value_len);
++ if (err)
++ return err;
++
+ digsig = (xvalue->type == EVM_IMA_XATTR_DIGSIG);
+ } else if (!strcmp(xattr_name, XATTR_NAME_EVM) && xattr_value_len > 0) {
+ digsig = (xvalue->type == EVM_XATTR_PORTABLE_DIGSIG);
+ }
+ if (result == 1 || evm_revalidate_status(xattr_name)) {
+- result = validate_hash_algo(dentry, xvalue, xattr_value_len);
+- if (result)
+- return result;
+-
+ ima_reset_appraise_flags(d_backing_inode(dentry), digsig);
++ if (result == 1)
++ result = 0;
+ }
+ return result;
+ }
+--
+2.35.1
+
--- /dev/null
+From 5fbf8f705f3c00af4d5629920c9416c8b6c26f83 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 19:44:10 +0800
+Subject: iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device
+ to identity
+
+From: Yicong Yang <yangyicong@hisilicon.com>
+
+[ Upstream commit 24b6c7798a0122012ca848ea0d25e973334266b0 ]
+
+The DMA operations of HiSilicon PTT device can only work properly with
+identical mappings. So add a quirk for the device to force the domain
+as passthrough.
+
+Acked-by: Will Deacon <will@kernel.org>
+Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
+Reviewed-by: John Garry <john.garry@huawei.com>
+Link: https://lore.kernel.org/r/20220816114414.4092-2-yangyicong@huawei.com
+Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+index 79edfdca6607..e7da4a47ce52 100644
+--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+@@ -2832,6 +2832,26 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
+ }
+ }
+
++/*
++ * HiSilicon PCIe tune and trace device can be used to trace TLP headers on the
++ * PCIe link and save the data to memory by DMA. The hardware is restricted to
++ * use identity mapping only.
++ */
++#define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
++ (pdev)->device == 0xa12e)
++
++static int arm_smmu_def_domain_type(struct device *dev)
++{
++ if (dev_is_pci(dev)) {
++ struct pci_dev *pdev = to_pci_dev(dev);
++
++ if (IS_HISI_PTT_DEVICE(pdev))
++ return IOMMU_DOMAIN_IDENTITY;
++ }
++
++ return 0;
++}
++
+ static struct iommu_ops arm_smmu_ops = {
+ .capable = arm_smmu_capable,
+ .domain_alloc = arm_smmu_domain_alloc,
+@@ -2857,6 +2877,7 @@ static struct iommu_ops arm_smmu_ops = {
+ .sva_unbind = arm_smmu_sva_unbind,
+ .sva_get_pasid = arm_smmu_sva_get_pasid,
+ .page_response = arm_smmu_page_response,
++ .def_domain_type = arm_smmu_def_domain_type,
+ .pgsize_bitmap = -1UL, /* Restricted during device attach */
+ .owner = THIS_MODULE,
+ };
+--
+2.35.1
+
--- /dev/null
+From 40a066b65a01f448f82c5e1982074d7894f0dd1a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 12:47:20 +0100
+Subject: iommu/iova: Fix module config properly
+
+From: Robin Murphy <robin.murphy@arm.com>
+
+[ Upstream commit 4f58330fcc8482aa90674e1f40f601e82f18ed4a ]
+
+IOMMU_IOVA is intended to be an optional library for users to select as
+and when they desire. Since it can be a module now, this means that
+built-in code which has chosen not to select it should not fail to link
+if it happens to have selected as a module by someone else. Replace
+IS_ENABLED() with IS_REACHABLE() to do the right thing.
+
+CC: Thierry Reding <thierry.reding@gmail.com>
+Reported-by: John Garry <john.garry@huawei.com>
+Fixes: 15bbdec3931e ("iommu: Make the iova library a module")
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Reviewed-by: Thierry Reding <treding@nvidia.com>
+Link: https://lore.kernel.org/r/548c2f683ca379aface59639a8f0cccc3a1ac050.1663069227.git.robin.murphy@arm.com
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/iova.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/linux/iova.h b/include/linux/iova.h
+index 71d8a2de6635..6b6cc104e300 100644
+--- a/include/linux/iova.h
++++ b/include/linux/iova.h
+@@ -133,7 +133,7 @@ static inline unsigned long iova_pfn(struct iova_domain *iovad, dma_addr_t iova)
+ return iova >> iova_shift(iovad);
+ }
+
+-#if IS_ENABLED(CONFIG_IOMMU_IOVA)
++#if IS_REACHABLE(CONFIG_IOMMU_IOVA)
+ int iova_cache_get(void);
+ void iova_cache_put(void);
+
+--
+2.35.1
+
--- /dev/null
+From f8111244b70af64594e0bff446effc588bf361bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 4 Aug 2022 17:32:39 +0300
+Subject: iommu/omap: Fix buffer overflow in debugfs
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 184233a5202786b20220acd2d04ddf909ef18f29 ]
+
+There are two issues here:
+
+1) The "len" variable needs to be checked before the very first write.
+ Otherwise if omap2_iommu_dump_ctx() with "bytes" less than 32 it is a
+ buffer overflow.
+2) The snprintf() function returns the number of bytes that *would* have
+ been copied if there were enough space. But we want to know the
+ number of bytes which were *actually* copied so use scnprintf()
+ instead.
+
+Fixes: bd4396f09a4a ("iommu/omap: Consolidate OMAP IOMMU modules")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Robin Murphy <robin.murphy@arm.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Link: https://lore.kernel.org/r/YuvYh1JbE3v+abd5@kili
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iommu/omap-iommu-debug.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/iommu/omap-iommu-debug.c b/drivers/iommu/omap-iommu-debug.c
+index a99afb5d9011..259f65291d90 100644
+--- a/drivers/iommu/omap-iommu-debug.c
++++ b/drivers/iommu/omap-iommu-debug.c
+@@ -32,12 +32,12 @@ static inline bool is_omap_iommu_detached(struct omap_iommu *obj)
+ ssize_t bytes; \
+ const char *str = "%20s: %08x\n"; \
+ const int maxcol = 32; \
+- bytes = snprintf(p, maxcol, str, __stringify(name), \
++ if (len < maxcol) \
++ goto out; \
++ bytes = scnprintf(p, maxcol, str, __stringify(name), \
+ iommu_read_reg(obj, MMU_##name)); \
+ p += bytes; \
+ len -= bytes; \
+- if (len < maxcol) \
+- goto out; \
+ } while (0)
+
+ static ssize_t
+--
+2.35.1
+
--- /dev/null
+From d99782fda3fabd559cb77312330dad2b26cc23f1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 7 Aug 2022 09:48:09 +0900
+Subject: kbuild: remove the target in signal traps when interrupted
+
+From: Masahiro Yamada <masahiroy@kernel.org>
+
+[ Upstream commit a7f3257da8a86b96fb9bf1bba40ae0bbd7f1885a ]
+
+When receiving some signal, GNU Make automatically deletes the target if
+it has already been changed by the interrupted recipe.
+
+If the target is possibly incomplete due to interruption, it must be
+deleted so that it will be remade from scratch on the next run of make.
+Otherwise, the target would remain corrupted permanently because its
+timestamp had already been updated.
+
+Thanks to this behavior of Make, you can stop the build any time by
+pressing Ctrl-C, and just run 'make' to resume it.
+
+Kbuild also relies on this feature, but it is equivalently important
+for any build systems that make decisions based on timestamps (if you
+want to support Ctrl-C reliably).
+
+However, this does not always work as claimed; Make immediately dies
+with Ctrl-C if its stderr goes into a pipe.
+
+ [Test Makefile]
+
+ foo:
+ echo hello > $@
+ sleep 3
+ echo world >> $@
+
+ [Test Result]
+
+ $ make # hit Ctrl-C
+ echo hello > foo
+ sleep 3
+ ^Cmake: *** Deleting file 'foo'
+ make: *** [Makefile:3: foo] Interrupt
+
+ $ make 2>&1 | cat # hit Ctrl-C
+ echo hello > foo
+ sleep 3
+ ^C$ # 'foo' is often left-over
+
+The reason is because SIGINT is sent to the entire process group.
+In this example, SIGINT kills 'cat', and 'make' writes the message to
+the closed pipe, then dies with SIGPIPE before cleaning the target.
+
+A typical bad scenario (as reported by [1], [2]) is to save build log
+by using the 'tee' command:
+
+ $ make 2>&1 | tee log
+
+This can be problematic for any build systems based on Make, so I hope
+it will be fixed in GNU Make. The maintainer of GNU Make stated this is
+a long-standing issue and difficult to fix [3]. It has not been fixed
+yet as of writing.
+
+So, we cannot rely on Make cleaning the target. We can do it by
+ourselves, in signal traps.
+
+As far as I understand, Make takes care of SIGHUP, SIGINT, SIGQUIT, and
+SITERM for the target removal. I added the traps for them, and also for
+SIGPIPE just in case cmd_* rule prints something to stdout or stderr
+(but I did not observe an actual case where SIGPIPE was triggered).
+
+[Note 1]
+
+The trap handler might be worth explaining.
+
+ rm -f $@; trap - $(sig); kill -s $(sig) $$
+
+This lets the shell kill itself by the signal it caught, so the parent
+process can tell the child has exited on the signal. Generally, this is
+a proper manner for handling signals, in case the calling program (like
+Bash) may monitor WIFSIGNALED() and WTERMSIG() for WCE although this may
+not be a big deal here because GNU Make handles SIGHUP, SIGINT, SIGQUIT
+in WUE and SIGTERM in IUE.
+
+ IUE - Immediate Unconditional Exit
+ WUE - Wait and Unconditional Exit
+ WCE - Wait and Cooperative Exit
+
+For details, see "Proper handling of SIGINT/SIGQUIT" [4].
+
+[Note 2]
+
+Reverting 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd
+files") would directly address [1], but it only saves if_changed_dep.
+As reported in [2], all commands that use redirection can potentially
+leave an empty (i.e. broken) target.
+
+[Note 3]
+
+Another (even safer) approach might be to always write to a temporary
+file, and rename it to $@ at the end of the recipe.
+
+ <command> > $(tmp-target)
+ mv $(tmp-target) $@
+
+It would require a lot of Makefile changes, and result in ugly code,
+so I did not take it.
+
+[Note 4]
+
+A little more thoughts about a pattern rule with multiple targets (or
+a grouped target).
+
+ %.x %.y: %.z
+ <recipe>
+
+When interrupted, GNU Make deletes both %.x and %.y, while this solution
+only deletes $@. Probably, this is not a big deal. The next run of make
+will execute the rule again to create $@ along with the other files.
+
+[1]: https://lore.kernel.org/all/YLeot94yAaM4xbMY@gmail.com/
+[2]: https://lore.kernel.org/all/20220510221333.2770571-1-robh@kernel.org/
+[3]: https://lists.gnu.org/archive/html/help-make/2021-06/msg00001.html
+[4]: https://www.cons.org/cracauer/sigint.html
+
+Fixes: 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files")
+Reported-by: Ingo Molnar <mingo@kernel.org>
+Reported-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
+Tested-by: Ingo Molnar <mingo@kernel.org>
+Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ scripts/Kbuild.include | 23 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
+index cdec22088423..914ea5eb16a8 100644
+--- a/scripts/Kbuild.include
++++ b/scripts/Kbuild.include
+@@ -96,8 +96,29 @@ echo-cmd = $(if $($(quiet)cmd_$(1)),\
+ quiet_redirect :=
+ silent_redirect := exec >/dev/null;
+
++# Delete the target on interruption
++#
++# GNU Make automatically deletes the target if it has already been changed by
++# the interrupted recipe. So, you can safely stop the build by Ctrl-C (Make
++# will delete incomplete targets), and resume it later.
++#
++# However, this does not work when the stderr is piped to another program, like
++# $ make >&2 | tee log
++# Make dies with SIGPIPE before cleaning the targets.
++#
++# To address it, we clean the target in signal traps.
++#
++# Make deletes the target when it catches SIGHUP, SIGINT, SIGQUIT, SIGTERM.
++# So, we cover them, and also SIGPIPE just in case.
++#
++# Of course, this is unneeded for phony targets.
++delete-on-interrupt = \
++ $(if $(filter-out $(PHONY), $@), \
++ $(foreach sig, HUP INT QUIT TERM PIPE, \
++ trap 'rm -f $@; trap - $(sig); kill -s $(sig) $$$$' $(sig);))
++
+ # printing commands
+-cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(cmd_$(1))
++cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(delete-on-interrupt) $(cmd_$(1))
+
+ ###
+ # if_changed - execute command if any prerequisite is newer than
+--
+2.35.1
+
--- /dev/null
+From bb8bf36093a61aa1e53310f0e59402636a56eec9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 14:41:12 +0200
+Subject: kbuild: rpm-pkg: fix breakage when V=1 is used
+
+From: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
+
+[ Upstream commit 2e07005f4813a9ff6e895787e0c2d1fea859b033 ]
+
+Doing make V=1 binrpm-pkg results in:
+
+ Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.EgV6qJ
+ + umask 022
+ + cd .
+ + /bin/rm -rf /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x
+ + /bin/mkdir -p /home/scgl/rpmbuild/BUILDROOT
+ + /bin/mkdir /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x
+ + mkdir -p /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x/boot
+ + make -f ./Makefile image_name
+ + cp test -e include/generated/autoconf.h -a -e include/config/auto.conf || ( \ echo >&2; \ echo >&2 " ERROR: Kernel configuration is invalid."; \ echo >&2 " include/generated/autoconf.h or include/config/auto.conf are missing.";\ echo >&2 " Run 'make oldconfig && make prepare' on kernel src to fix it."; \ echo >&2 ; \ /bin/false) arch/s390/boot/bzImage /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x/boot/vmlinuz-6.0.0-rc5+
+ cp: invalid option -- 'e'
+ Try 'cp --help' for more information.
+ error: Bad exit status from /var/tmp/rpm-tmp.EgV6qJ (%install)
+
+Because the make call to get the image name is verbose and prints
+additional information.
+
+Fixes: 993bdde94547 ("kbuild: add image_name to no-sync-config-targets")
+Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
+Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ scripts/package/mkspec | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/scripts/package/mkspec b/scripts/package/mkspec
+index 7c477ca7dc98..951cc60e5a90 100755
+--- a/scripts/package/mkspec
++++ b/scripts/package/mkspec
+@@ -85,10 +85,10 @@ $S
+ mkdir -p %{buildroot}/boot
+ %ifarch ia64
+ mkdir -p %{buildroot}/boot/efi
+- cp \$($MAKE image_name) %{buildroot}/boot/efi/vmlinuz-$KERNELRELEASE
++ cp \$($MAKE -s image_name) %{buildroot}/boot/efi/vmlinuz-$KERNELRELEASE
+ ln -s efi/vmlinuz-$KERNELRELEASE %{buildroot}/boot/
+ %else
+- cp \$($MAKE image_name) %{buildroot}/boot/vmlinuz-$KERNELRELEASE
++ cp \$($MAKE -s image_name) %{buildroot}/boot/vmlinuz-$KERNELRELEASE
+ %endif
+ $M $MAKE %{?_smp_mflags} INSTALL_MOD_PATH=%{buildroot} modules_install
+ $MAKE %{?_smp_mflags} INSTALL_HDR_PATH=%{buildroot}/usr headers_install
+--
+2.35.1
+
--- /dev/null
+From 45cd0539b8b629b90a3b63f05af3e03b190f6ad0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 17:06:56 +0100
+Subject: kselftest/arm64: Fix validatation termination record after
+ EXTRA_CONTEXT
+
+From: Mark Brown <broonie@kernel.org>
+
+[ Upstream commit 5c152c2f66f9368394b89ac90dc7483476ef7b88 ]
+
+When arm64 signal context data overflows the base struct sigcontext it gets
+placed in an extra buffer pointed to by a record of type EXTRA_CONTEXT in
+the base struct sigcontext which is required to be the last record in the
+base struct sigframe. The current validation code attempts to check this
+by using GET_RESV_NEXT_HEAD() to step forward from the current record to
+the next but that is a macro which assumes it is being provided with a
+struct _aarch64_ctx and uses the size there to skip forward to the next
+record. Instead validate_extra_context() passes it a struct extra_context
+which has a separate size field. This compiles but results in us trying
+to validate a termination record in completely the wrong place, at best
+failing validation and at worst just segfaulting. Fix this by passing
+the struct _aarch64_ctx we meant to into the macro.
+
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Link: https://lore.kernel.org/r/20220829160703.874492-4-broonie@kernel.org
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/arm64/signal/testcases/testcases.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c
+index 8c2a57fc2f9c..341b3d5200bd 100644
+--- a/tools/testing/selftests/arm64/signal/testcases/testcases.c
++++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c
+@@ -33,7 +33,7 @@ bool validate_extra_context(struct extra_context *extra, char **err)
+ return false;
+
+ fprintf(stderr, "Validating EXTRA...\n");
+- term = GET_RESV_NEXT_HEAD(extra);
++ term = GET_RESV_NEXT_HEAD(&extra->head);
+ if (!term || term->magic || term->size) {
+ *err = "Missing terminator after EXTRA context";
+ return false;
+--
+2.35.1
+
--- /dev/null
+From 51b10feea42fbc06adb530d6ff180f2ab0473d48 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 23:15:57 +0000
+Subject: KVM: nVMX: Ignore SIPI that arrives in L2 when vCPU is not in WFS
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit c2086eca86585bfd8132dd91e802497a202185c8 ]
+
+Fall through to handling other pending exception/events for L2 if SIPI
+is pending while the CPU is not in Wait-for-SIPI. KVM correctly ignores
+the event, but incorrectly returns immediately, e.g. a SIPI coincident
+with another event could lead to KVM incorrectly routing the event to L1
+instead of L2.
+
+Fixes: bf0cd88ce363 ("KVM: x86: emulate wait-for-SIPI and SIPI-VMExit")
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Link: https://lore.kernel.org/r/20220830231614.3580124-11-seanjc@google.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/vmx/nested.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
+index f28085b89f47..94b4b3d306ce 100644
+--- a/arch/x86/kvm/vmx/nested.c
++++ b/arch/x86/kvm/vmx/nested.c
+@@ -3931,10 +3931,12 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ return -EBUSY;
+
+ clear_bit(KVM_APIC_SIPI, &apic->pending_events);
+- if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
++ if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
+ nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0,
+ apic->sipi_vector & 0xFFUL);
+- return 0;
++ return 0;
++ }
++ /* Fallthrough, the SIPI is completely ignored. */
+ }
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From c09b39bc2c9bfd8e2bdf4966c48c353b4e4a5127 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 23:15:54 +0000
+Subject: KVM: nVMX: Prioritize TSS T-flag #DBs over Monitor Trap Flag
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit b9d44f9091ac6c325fc2f7b7671b462fb36abbed ]
+
+Service TSS T-flag #DBs prior to pending MTFs, as such #DBs are higher
+priority than MTF. KVM itself doesn't emulate TSS #DBs, and any such
+exceptions injected from L1 will be handled by hardware (or morphed to
+a fault-like exception if injection fails), but theoretically userspace
+could pend a TSS T-flag #DB in conjunction with a pending MTF.
+
+Note, there's no known use case this fixes, it's purely to be technically
+correct with respect to Intel's SDM.
+
+Cc: Oliver Upton <oupton@google.com>
+Cc: Peter Shier <pshier@google.com>
+Fixes: 5ef8acbdd687 ("KVM: nVMX: Emulate MTF when performing instruction emulation")
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Link: https://lore.kernel.org/r/20220830231614.3580124-8-seanjc@google.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/vmx/nested.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
+index cdbe827ec960..f28085b89f47 100644
+--- a/arch/x86/kvm/vmx/nested.c
++++ b/arch/x86/kvm/vmx/nested.c
+@@ -3938,15 +3938,17 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ }
+
+ /*
+- * Process any exceptions that are not debug traps before MTF.
++ * Process exceptions that are higher priority than Monitor Trap Flag:
++ * fault-like exceptions, TSS T flag #DB (not emulated by KVM, but
++ * could theoretically come in from userspace), and ICEBP (INT1).
+ *
+ * Note that only a pending nested run can block a pending exception.
+ * Otherwise an injected NMI/interrupt should either be
+ * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO,
+ * while delivering the pending exception.
+ */
+-
+- if (vcpu->arch.exception.pending && !vmx_get_pending_dbg_trap(vcpu)) {
++ if (vcpu->arch.exception.pending &&
++ !(vmx_get_pending_dbg_trap(vcpu) & ~DR6_BT)) {
+ if (vmx->nested.nested_run_pending)
+ return -EBUSY;
+ if (!nested_vmx_check_exception(vcpu, &exit_qual))
+--
+2.35.1
+
--- /dev/null
+From 9d78e1016b5b9581ab29294a2b3759df469bf66f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 23:15:53 +0000
+Subject: KVM: nVMX: Treat General Detect #DB (DR7.GD=1) as fault-like
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit 8d178f460772ecdee8e6d72389b43a8d35a14ff5 ]
+
+Exclude General Detect #DBs, which have fault-like behavior but also have
+a non-zero payload (DR6.BD=1), from nVMX's handling of pending debug
+traps. Opportunistically rewrite the comment to better document what is
+being checked, i.e. "has a non-zero payload" vs. "has a payload", and to
+call out the many caveats surrounding #DBs that KVM dodges one way or
+another.
+
+Cc: Oliver Upton <oupton@google.com>
+Cc: Peter Shier <pshier@google.com>
+Fixes: 684c0422da71 ("KVM: nVMX: Handle pending #DB when injecting INIT VM-exit")
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Link: https://lore.kernel.org/r/20220830231614.3580124-7-seanjc@google.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/vmx/nested.c | 36 +++++++++++++++++++++++++-----------
+ 1 file changed, 25 insertions(+), 11 deletions(-)
+
+diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
+index 91b182fafb43..cdbe827ec960 100644
+--- a/arch/x86/kvm/vmx/nested.c
++++ b/arch/x86/kvm/vmx/nested.c
+@@ -3852,16 +3852,29 @@ static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
+ }
+
+ /*
+- * Returns true if a debug trap is pending delivery.
++ * Returns true if a debug trap is (likely) pending delivery. Infer the class
++ * of a #DB (trap-like vs. fault-like) from the exception payload (to-be-DR6).
++ * Using the payload is flawed because code breakpoints (fault-like) and data
++ * breakpoints (trap-like) set the same bits in DR6 (breakpoint detected), i.e.
++ * this will return false positives if a to-be-injected code breakpoint #DB is
++ * pending (from KVM's perspective, but not "pending" across an instruction
++ * boundary). ICEBP, a.k.a. INT1, is also not reflected here even though it
++ * too is trap-like.
+ *
+- * In KVM, debug traps bear an exception payload. As such, the class of a #DB
+- * exception may be inferred from the presence of an exception payload.
++ * KVM "works" despite these flaws as ICEBP isn't currently supported by the
++ * emulator, Monitor Trap Flag is not marked pending on intercepted #DBs (the
++ * #DB has already happened), and MTF isn't marked pending on code breakpoints
++ * from the emulator (because such #DBs are fault-like and thus don't trigger
++ * actions that fire on instruction retire).
+ */
+-static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu)
++static inline unsigned long vmx_get_pending_dbg_trap(struct kvm_vcpu *vcpu)
+ {
+- return vcpu->arch.exception.pending &&
+- vcpu->arch.exception.nr == DB_VECTOR &&
+- vcpu->arch.exception.payload;
++ if (!vcpu->arch.exception.pending ||
++ vcpu->arch.exception.nr != DB_VECTOR)
++ return 0;
++
++ /* General Detect #DBs are always fault-like. */
++ return vcpu->arch.exception.payload & ~DR6_BD;
+ }
+
+ /*
+@@ -3873,9 +3886,10 @@ static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu)
+ */
+ static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu)
+ {
+- if (vmx_pending_dbg_trap(vcpu))
+- vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
+- vcpu->arch.exception.payload);
++ unsigned long pending_dbg = vmx_get_pending_dbg_trap(vcpu);
++
++ if (pending_dbg)
++ vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, pending_dbg);
+ }
+
+ static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
+@@ -3932,7 +3946,7 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ * while delivering the pending exception.
+ */
+
+- if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) {
++ if (vcpu->arch.exception.pending && !vmx_get_pending_dbg_trap(vcpu)) {
+ if (vmx->nested.nested_run_pending)
+ return -EBUSY;
+ if (!nested_vmx_check_exception(vcpu, &exit_qual))
+--
+2.35.1
+
--- /dev/null
+From 51bde6bcdd0364a3924d8b07b3036199f0482059 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 23:15:58 +0000
+Subject: KVM: nVMX: Unconditionally clear mtf_pending on nested VM-Exit
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit 593a5c2e3c12a2f65967739267093255c47e9fe0 ]
+
+Clear mtf_pending on nested VM-Exit instead of handling the clear on a
+case-by-case basis in vmx_check_nested_events(). The pending MTF should
+never survive nested VM-Exit, as it is a property of KVM's run of the
+current L2, i.e. should never affect the next L2 run by L1. In practice,
+this is likely a nop as getting to L1 with nested_run_pending is
+impossible, and KVM doesn't correctly handle morphing a pending exception
+that occurs on a prior injected exception (need for re-injected exception
+being the other case where MTF isn't cleared). However, KVM will
+hopefully soon correctly deal with a pending exception on top of an
+injected exception.
+
+Add a TODO to document that KVM has an inversion priority bug between
+SMIs and MTF (and trap-like #DBS), and that KVM also doesn't properly
+save/restore MTF across SMI/RSM.
+
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Link: https://lore.kernel.org/r/20220830231614.3580124-12-seanjc@google.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Stable-dep-of: 7709aba8f716 ("KVM: x86: Morph pending exceptions to pending VM-Exits at queue time")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/vmx/nested.c | 21 ++++++++++++---------
+ 1 file changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
+index 94b4b3d306ce..e9b1447faacd 100644
+--- a/arch/x86/kvm/vmx/nested.c
++++ b/arch/x86/kvm/vmx/nested.c
+@@ -3904,16 +3904,8 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ unsigned long exit_qual;
+ bool block_nested_events =
+ vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
+- bool mtf_pending = vmx->nested.mtf_pending;
+ struct kvm_lapic *apic = vcpu->arch.apic;
+
+- /*
+- * Clear the MTF state. If a higher priority VM-exit is delivered first,
+- * this state is discarded.
+- */
+- if (!block_nested_events)
+- vmx->nested.mtf_pending = false;
+-
+ if (lapic_in_kernel(vcpu) &&
+ test_bit(KVM_APIC_INIT, &apic->pending_events)) {
+ if (block_nested_events)
+@@ -3922,6 +3914,9 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ clear_bit(KVM_APIC_INIT, &apic->pending_events);
+ if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED)
+ nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
++
++ /* MTF is discarded if the vCPU is in WFS. */
++ vmx->nested.mtf_pending = false;
+ return 0;
+ }
+
+@@ -3944,6 +3939,11 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ * fault-like exceptions, TSS T flag #DB (not emulated by KVM, but
+ * could theoretically come in from userspace), and ICEBP (INT1).
+ *
++ * TODO: SMIs have higher priority than MTF and trap-like #DBs (except
++ * for TSS T flag #DBs). KVM also doesn't save/restore pending MTF
++ * across SMI/RSM as it should; that needs to be addressed in order to
++ * prioritize SMI over MTF and trap-like #DBs.
++ *
+ * Note that only a pending nested run can block a pending exception.
+ * Otherwise an injected NMI/interrupt should either be
+ * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO,
+@@ -3959,7 +3959,7 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
+ return 0;
+ }
+
+- if (mtf_pending) {
++ if (vmx->nested.mtf_pending) {
+ if (block_nested_events)
+ return -EBUSY;
+ nested_vmx_update_pending_dbg(vcpu);
+@@ -4558,6 +4558,9 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+ struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+
++ /* Pending MTF traps are discarded on VM-Exit. */
++ vmx->nested.mtf_pending = false;
++
+ /* trying to cancel vmlaunch/vmresume is a bug */
+ WARN_ON_ONCE(vmx->nested.nested_run_pending);
+
+--
+2.35.1
+
--- /dev/null
+From 01c5c8919a68ca331ff3b80f161bfc28c321c8c0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 23:15:59 +0000
+Subject: KVM: VMX: Inject #PF on ENCLS as "emulated" #PF
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit bfcb08a0b9e99b959814a329fabace22c3df046d ]
+
+Treat #PFs that occur during emulation of ENCLS as, wait for it, emulated
+page faults. Practically speaking, this is a glorified nop as the
+exception is never of the nested flavor, and it's extremely unlikely the
+guest is relying on the side effect of an implicit INVLPG on the faulting
+address.
+
+Fixes: 70210c044b4e ("KVM: VMX: Add SGX ENCLS[ECREATE] handler to enforce CPUID restrictions")
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Link: https://lore.kernel.org/r/20220830231614.3580124-13-seanjc@google.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/vmx/sgx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/x86/kvm/vmx/sgx.c b/arch/x86/kvm/vmx/sgx.c
+index 6693ebdc0770..ebe6e21cad24 100644
+--- a/arch/x86/kvm/vmx/sgx.c
++++ b/arch/x86/kvm/vmx/sgx.c
+@@ -133,7 +133,7 @@ static int sgx_inject_fault(struct kvm_vcpu *vcpu, gva_t gva, int trapnr)
+ ex.address = gva;
+ ex.error_code_valid = true;
+ ex.nested_page_fault = false;
+- kvm_inject_page_fault(vcpu, &ex);
++ kvm_inject_emulated_page_fault(vcpu, &ex);
+ } else {
+ kvm_inject_gp(vcpu, 0);
+ }
+--
+2.35.1
+
--- /dev/null
+From 1bd4e2dd2308823eb419528af6ff7ef407a9fcd5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 15:37:08 +0200
+Subject: KVM: x86: Check for existing Hyper-V vCPU in kvm_hv_vcpu_init()
+
+From: Sean Christopherson <seanjc@google.com>
+
+[ Upstream commit 1cac8d9f6bd25df3713103e44e2d9ca0c2e03c33 ]
+
+When potentially allocating/initializing the Hyper-V vCPU struct, check
+for an existing instance in kvm_hv_vcpu_init() instead of requiring
+callers to perform the check. Relying on callers to do the check is
+risky as it's all too easy for KVM to overwrite vcpu->arch.hyperv and
+leak memory, and it adds additional burden on callers without much
+benefit.
+
+No functional change intended.
+
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Reviewed-by: Wei Liu <wei.liu@kernel.org>
+Link: https://lore.kernel.org/r/20220830133737.1539624-5-vkuznets@redhat.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Stable-dep-of: 3be29eb7b525 ("KVM: x86: Report error when setting CPUID if Hyper-V allocation fails")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/hyperv.c | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
+index 762b43f0d919..fccc2abddd75 100644
+--- a/arch/x86/kvm/hyperv.c
++++ b/arch/x86/kvm/hyperv.c
+@@ -929,9 +929,12 @@ static void stimer_init(struct kvm_vcpu_hv_stimer *stimer, int timer_index)
+
+ static int kvm_hv_vcpu_init(struct kvm_vcpu *vcpu)
+ {
+- struct kvm_vcpu_hv *hv_vcpu;
++ struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
+ int i;
+
++ if (hv_vcpu)
++ return 0;
++
+ hv_vcpu = kzalloc(sizeof(struct kvm_vcpu_hv), GFP_KERNEL_ACCOUNT);
+ if (!hv_vcpu)
+ return -ENOMEM;
+@@ -955,11 +958,9 @@ int kvm_hv_activate_synic(struct kvm_vcpu *vcpu, bool dont_zero_synic_pages)
+ struct kvm_vcpu_hv_synic *synic;
+ int r;
+
+- if (!to_hv_vcpu(vcpu)) {
+- r = kvm_hv_vcpu_init(vcpu);
+- if (r)
+- return r;
+- }
++ r = kvm_hv_vcpu_init(vcpu);
++ if (r)
++ return r;
+
+ synic = to_hv_synic(vcpu);
+
+@@ -1677,10 +1678,8 @@ int kvm_hv_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data, bool host)
+ if (!host && !vcpu->arch.hyperv_enabled)
+ return 1;
+
+- if (!to_hv_vcpu(vcpu)) {
+- if (kvm_hv_vcpu_init(vcpu))
+- return 1;
+- }
++ if (kvm_hv_vcpu_init(vcpu))
++ return 1;
+
+ if (kvm_hv_msr_partition_wide(msr)) {
+ int r;
+@@ -1700,10 +1699,8 @@ int kvm_hv_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
+ if (!host && !vcpu->arch.hyperv_enabled)
+ return 1;
+
+- if (!to_hv_vcpu(vcpu)) {
+- if (kvm_hv_vcpu_init(vcpu))
+- return 1;
+- }
++ if (kvm_hv_vcpu_init(vcpu))
++ return 1;
+
+ if (kvm_hv_msr_partition_wide(msr)) {
+ int r;
+@@ -1992,7 +1989,7 @@ void kvm_hv_set_cpuid(struct kvm_vcpu *vcpu)
+ return;
+ }
+
+- if (!to_hv_vcpu(vcpu) && kvm_hv_vcpu_init(vcpu))
++ if (kvm_hv_vcpu_init(vcpu))
+ return;
+
+ hv_vcpu = to_hv_vcpu(vcpu);
+--
+2.35.1
+
--- /dev/null
+From 8571e283c27ecb4b6270781434f9bdc9e736a5b4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Aug 2022 14:32:37 +0800
+Subject: KVM: x86/mmu: fix memoryleak in kvm_mmu_vendor_module_init()
+
+From: Miaohe Lin <linmiaohe@huawei.com>
+
+[ Upstream commit d7c9bfb9caaffd496ae44b258ec7c793677d3eeb ]
+
+When register_shrinker() fails, KVM doesn't release the percpu counter
+kvm_total_used_mmu_pages leading to memoryleak. Fix this issue by calling
+percpu_counter_destroy() when register_shrinker() fails.
+
+Fixes: ab271bd4dfd5 ("x86: kvm: propagate register_shrinker return code")
+Signed-off-by: Miaohe Lin <linmiaohe@huawei.com>
+Link: https://lore.kernel.org/r/20220823063237.47299-1-linmiaohe@huawei.com
+[sean: tweak shortlog and changelog]
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kvm/mmu/mmu.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
+index ba1749a770eb..23839c90f44c 100644
+--- a/arch/x86/kvm/mmu/mmu.c
++++ b/arch/x86/kvm/mmu/mmu.c
+@@ -6147,10 +6147,12 @@ int kvm_mmu_vendor_module_init(void)
+
+ ret = register_shrinker(&mmu_shrinker);
+ if (ret)
+- goto out;
++ goto out_shrinker;
+
+ return 0;
+
++out_shrinker:
++ percpu_counter_destroy(&kvm_total_used_mmu_pages);
+ out:
+ mmu_destroy_caches();
+ return ret;
+--
+2.35.1
+
--- /dev/null
+From 5ac94a5fd4929d28796da6d80caf84811b7b736f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 15 Aug 2022 10:02:27 +0200
+Subject: leds: lm3601x: Don't use mutex after it was destroyed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+[ Upstream commit 32f7eed0c763a9b89f6b357ec54b48398fc7b99e ]
+
+The mutex might still be in use until the devm cleanup callback
+devm_led_classdev_flash_release() is called. This only happens some time
+after lm3601x_remove() completed.
+
+Fixes: e63a744871a3 ("leds: lm3601x: Convert class registration to device managed")
+Acked-by: Pavel Machek <pavel@ucw.cz>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/leds/flash/leds-lm3601x.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/leds/flash/leds-lm3601x.c b/drivers/leds/flash/leds-lm3601x.c
+index d0e1d4814042..3d1272748201 100644
+--- a/drivers/leds/flash/leds-lm3601x.c
++++ b/drivers/leds/flash/leds-lm3601x.c
+@@ -444,8 +444,6 @@ static int lm3601x_remove(struct i2c_client *client)
+ {
+ struct lm3601x_led *led = i2c_get_clientdata(client);
+
+- mutex_destroy(&led->lock);
+-
+ return regmap_update_bits(led->regmap, LM3601X_ENABLE_REG,
+ LM3601X_ENABLE_MASK,
+ LM3601X_MODE_STANDBY);
+--
+2.35.1
+
--- /dev/null
+From d1f2c6898f9c1b741d58bd74bffa5eb2ac75839b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 12:30:52 -0700
+Subject: libbpf: Fix crash if SEC("freplace") programs don't have
+ attach_prog_fd set
+
+From: Andrii Nakryiko <andrii@kernel.org>
+
+[ Upstream commit 749c202cb6ea40f4d7ac95c4a1217a7b506f43a8 ]
+
+Fix SIGSEGV caused by libbpf trying to find attach type in vmlinux BTF
+for freplace programs. It's wrong to search in vmlinux BTF and libbpf
+doesn't even mark vmlinux BTF as required for freplace programs. So
+trying to search anything in obj->vmlinux_btf might cause NULL
+dereference if nothing else in BPF object requires vmlinux BTF.
+
+Instead, error out if freplace (EXT) program doesn't specify
+attach_prog_fd during at the load time.
+
+Fixes: 91abb4a6d79d ("libbpf: Support attachment of BPF tracing programs to kernel modules")
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Link: https://lore.kernel.org/bpf/20220909193053.577111-3-andrii@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/lib/bpf/libbpf.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/tools/lib/bpf/libbpf.c b/tools/lib/bpf/libbpf.c
+index 050622649797..5a853959ff8e 100644
+--- a/tools/lib/bpf/libbpf.c
++++ b/tools/lib/bpf/libbpf.c
+@@ -8472,11 +8472,15 @@ static int libbpf_find_attach_btf_id(struct bpf_program *prog, int *btf_obj_fd,
+ attach_name = name + sec->len;
+
+ /* BPF program's BTF ID */
+- if (attach_prog_fd) {
++ if (prog->type == BPF_PROG_TYPE_EXT || attach_prog_fd) {
++ if (!attach_prog_fd) {
++ pr_warn("prog '%s': attach program FD is not set\n", prog->name);
++ return -EINVAL;
++ }
+ err = libbpf_find_prog_btf_id(attach_name, attach_prog_fd);
+ if (err < 0) {
+- pr_warn("failed to find BPF program (FD %d) BTF ID for '%s': %d\n",
+- attach_prog_fd, attach_name, err);
++ pr_warn("prog '%s': failed to find BPF program (FD %d) BTF ID for '%s': %d\n",
++ prog->name, attach_prog_fd, attach_name, err);
+ return err;
+ }
+ *btf_obj_fd = 0;
+@@ -8493,7 +8497,8 @@ static int libbpf_find_attach_btf_id(struct bpf_program *prog, int *btf_obj_fd,
+ err = find_kernel_btf_id(prog->obj, attach_name, attach_type, btf_obj_fd, btf_type_id);
+ }
+ if (err) {
+- pr_warn("failed to find kernel BTF type ID of '%s': %d\n", attach_name, err);
++ pr_warn("prog '%s': failed to find kernel BTF type ID of '%s': %d\n",
++ prog->name, attach_name, err);
+ return err;
+ }
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From 286e78954ac96101725e25aa9d3fb8cfbcd15b5e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 16:48:09 +0800
+Subject: libbpf: Fix NULL pointer exception in API btf_dump__dump_type_data
+
+From: Xin Liu <liuxin350@huawei.com>
+
+[ Upstream commit 7620bffbf72cd66a5d18e444a143b5b5989efa87 ]
+
+We found that function btf_dump__dump_type_data can be called by the
+user as an API, but in this function, the `opts` parameter may be used
+as a null pointer.This causes `opts->indent_str` to trigger a NULL
+pointer exception.
+
+Fixes: 2ce8450ef5a3 ("libbpf: add bpf_object__open_{file, mem} w/ extensible opts")
+Signed-off-by: Xin Liu <liuxin350@huawei.com>
+Signed-off-by: Weibin Kong <kongweibin2@huawei.com>
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Link: https://lore.kernel.org/bpf/20220917084809.30770-1-liuxin350@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/lib/bpf/btf_dump.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/lib/bpf/btf_dump.c b/tools/lib/bpf/btf_dump.c
+index 841cc68e3f42..81bfeedc49ee 100644
+--- a/tools/lib/bpf/btf_dump.c
++++ b/tools/lib/bpf/btf_dump.c
+@@ -2294,7 +2294,7 @@ int btf_dump__dump_type_data(struct btf_dump *d, __u32 id,
+ d->typed_dump->indent_lvl = OPTS_GET(opts, indent_level, 0);
+
+ /* default indent string is a tab */
+- if (!opts->indent_str)
++ if (!OPTS_GET(opts, indent_str, NULL))
+ d->typed_dump->indent_str[0] = '\t';
+ else
+ strncat(d->typed_dump->indent_str, opts->indent_str,
+--
+2.35.1
+
--- /dev/null
+From ecf058f65c9f7b16cdbd64fa1b8fae22681f0eac Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 17:07:08 +0800
+Subject: libbpf: Fix overrun in netlink attribute iteration
+
+From: Xin Liu <liuxin350@huawei.com>
+
+[ Upstream commit 51e05a8cf8eb34da7473823b7f236a77adfef0b4 ]
+
+I accidentally found that a change in commit 1045b03e07d8 ("netlink: fix
+overrun in attribute iteration") was not synchronized to the function
+`nla_ok` in tools/lib/bpf/nlattr.c, I think it is necessary to modify,
+this patch will do it.
+
+Signed-off-by: Xin Liu <liuxin350@huawei.com>
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Link: https://lore.kernel.org/bpf/20220930090708.62394-1-liuxin350@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/lib/bpf/nlattr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/lib/bpf/nlattr.c b/tools/lib/bpf/nlattr.c
+index f57e77a6e40f..3900d052ed19 100644
+--- a/tools/lib/bpf/nlattr.c
++++ b/tools/lib/bpf/nlattr.c
+@@ -32,7 +32,7 @@ static struct nlattr *nla_next(const struct nlattr *nla, int *remaining)
+
+ static int nla_ok(const struct nlattr *nla, int remaining)
+ {
+- return remaining >= sizeof(*nla) &&
++ return remaining >= (int)sizeof(*nla) &&
+ nla->nla_len >= sizeof(*nla) &&
+ nla->nla_len <= remaining;
+ }
+--
+2.35.1
+
--- /dev/null
+From ced1bbadad7673b78e5550d71dfd658e2232a490 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 17:53:17 +0300
+Subject: locks: fix TOCTOU race when granting write lease
+
+From: Amir Goldstein <amir73il@gmail.com>
+
+[ Upstream commit d6da19c9cace63290ccfccb1fc35151ffefc0bec ]
+
+Thread A trying to acquire a write lease checks the value of i_readcount
+and i_writecount in check_conflicting_open() to verify that its own fd
+is the only fd referencing the file.
+
+Thread B trying to open the file for read will call break_lease() in
+do_dentry_open() before incrementing i_readcount, which leaves a small
+window where thread A can acquire the write lease and then thread B
+completes the open of the file for read without breaking the write lease
+that was acquired by thread A.
+
+Fix this race by incrementing i_readcount before checking for existing
+leases, same as the case with i_writecount.
+
+Use a helper put_file_access() to decrement i_readcount or i_writecount
+in do_dentry_open() and __fput().
+
+Fixes: 387e3746d01c ("locks: eliminate false positive conflicts for write lease")
+Reviewed-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Amir Goldstein <amir73il@gmail.com>
+Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/file_table.c | 7 +------
+ fs/internal.h | 10 ++++++++++
+ fs/open.c | 11 ++++-------
+ 3 files changed, 15 insertions(+), 13 deletions(-)
+
+diff --git a/fs/file_table.c b/fs/file_table.c
+index e8c9016703ad..6f297f9782fc 100644
+--- a/fs/file_table.c
++++ b/fs/file_table.c
+@@ -284,12 +284,7 @@ static void __fput(struct file *file)
+ }
+ fops_put(file->f_op);
+ put_pid(file->f_owner.pid);
+- if ((mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ)
+- i_readcount_dec(inode);
+- if (mode & FMODE_WRITER) {
+- put_write_access(inode);
+- __mnt_drop_write(mnt);
+- }
++ put_file_access(file);
+ dput(dentry);
+ if (unlikely(mode & FMODE_NEED_UNMOUNT))
+ dissolve_on_fput(mnt);
+diff --git a/fs/internal.h b/fs/internal.h
+index 4f1fe6d08866..9075490f21a6 100644
+--- a/fs/internal.h
++++ b/fs/internal.h
+@@ -100,6 +100,16 @@ extern void chroot_fs_refs(const struct path *, const struct path *);
+ extern struct file *alloc_empty_file(int, const struct cred *);
+ extern struct file *alloc_empty_file_noaccount(int, const struct cred *);
+
++static inline void put_file_access(struct file *file)
++{
++ if ((file->f_mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ) {
++ i_readcount_dec(file->f_inode);
++ } else if (file->f_mode & FMODE_WRITER) {
++ put_write_access(file->f_inode);
++ __mnt_drop_write(file->f_path.mnt);
++ }
++}
++
+ /*
+ * super.c
+ */
+diff --git a/fs/open.c b/fs/open.c
+index 1ba1d2ab2ef0..5e322f188e83 100644
+--- a/fs/open.c
++++ b/fs/open.c
+@@ -786,7 +786,9 @@ static int do_dentry_open(struct file *f,
+ return 0;
+ }
+
+- if (f->f_mode & FMODE_WRITE && !special_file(inode->i_mode)) {
++ if ((f->f_mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ) {
++ i_readcount_inc(inode);
++ } else if (f->f_mode & FMODE_WRITE && !special_file(inode->i_mode)) {
+ error = get_write_access(inode);
+ if (unlikely(error))
+ goto cleanup_file;
+@@ -826,8 +828,6 @@ static int do_dentry_open(struct file *f,
+ goto cleanup_all;
+ }
+ f->f_mode |= FMODE_OPENED;
+- if ((f->f_mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ)
+- i_readcount_inc(inode);
+ if ((f->f_mode & FMODE_READ) &&
+ likely(f->f_op->read || f->f_op->read_iter))
+ f->f_mode |= FMODE_CAN_READ;
+@@ -880,10 +880,7 @@ static int do_dentry_open(struct file *f,
+ if (WARN_ON_ONCE(error > 0))
+ error = -EINVAL;
+ fops_put(f->f_op);
+- if (f->f_mode & FMODE_WRITER) {
+- put_write_access(inode);
+- __mnt_drop_write(f->f_path.mnt);
+- }
++ put_file_access(f);
+ cleanup_file:
+ path_put(&f->f_path);
+ f->f_path.mnt = NULL;
+--
+2.35.1
+
--- /dev/null
+From 16789525e16932613c7aa406e3fc543d348cebf5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 12:13:35 +0200
+Subject: mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sg
+
+From: Jack Wang <jinpu.wang@ionos.com>
+
+[ Upstream commit 6b207ce8a96a71e966831e3a13c38143ba9a73c1 ]
+
+dma_map_sg return 0 on error, fix the error check, and return -EIO
+to caller.
+
+Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager")
+Signed-off-by: Jack Wang <jinpu.wang@ionos.com>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mailbox/bcm-flexrm-mailbox.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c
+index 78073ad1f2f1..b7e9fd53d47d 100644
+--- a/drivers/mailbox/bcm-flexrm-mailbox.c
++++ b/drivers/mailbox/bcm-flexrm-mailbox.c
+@@ -632,15 +632,15 @@ static int flexrm_spu_dma_map(struct device *dev, struct brcm_message *msg)
+
+ rc = dma_map_sg(dev, msg->spu.src, sg_nents(msg->spu.src),
+ DMA_TO_DEVICE);
+- if (rc < 0)
+- return rc;
++ if (!rc)
++ return -EIO;
+
+ rc = dma_map_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst),
+ DMA_FROM_DEVICE);
+- if (rc < 0) {
++ if (!rc) {
+ dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src),
+ DMA_TO_DEVICE);
+- return rc;
++ return -EIO;
+ }
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From de58616df806bf710e5d7454e0d55d77d51be957 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 08:08:12 +0100
+Subject: mailbox: mpfs: account for mbox offsets while sending
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+[ Upstream commit 0d1aadfe10ba17ebdeb96abb9638eb0f623f9b55 ]
+
+The mailbox offset is not only used for receiving messages, but it is
+also used by messages sent to the system controller by Linux that have a
+payload, such as the "digital signature service". It is also overloaded
+by certain other services (reprogramming of the FPGA fabric, see Link:)
+to have a meaning other than the offset the system controller should
+read from.
+When the driver was written, no such services of the latter type were
+in use & those of the former used an offset of zero so this has gone
+un-noticed.
+
+Link: https://www.microsemi.com/document-portal/doc_download/1245815-polarfire-fpga-and-polarfire-soc-fpga-system-services-user-guide # Section 5.2
+Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox")
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mailbox/mailbox-mpfs.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
+index e432a8f0d148..cfacb3f320a6 100644
+--- a/drivers/mailbox/mailbox-mpfs.c
++++ b/drivers/mailbox/mailbox-mpfs.c
+@@ -100,21 +100,20 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
+
+ for (index = 0; index < (msg->cmd_data_size / 4); index++)
+ writel_relaxed(word_buf[index],
+- mbox->mbox_base + index * 0x4);
++ mbox->mbox_base + msg->mbox_offset + index * 0x4);
+ if (extra_bits) {
+ u8 i;
+ u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
+ u8 *byte_buf = msg->cmd_data + byte_off;
+
+- val = readl_relaxed(mbox->mbox_base + index * 0x4);
++ val = readl_relaxed(mbox->mbox_base + msg->mbox_offset + index * 0x4);
+
+ for (i = 0u; i < extra_bits; i++) {
+ val &= ~(0xffu << (i * 8u));
+ val |= (byte_buf[i] << (i * 8u));
+ }
+
+- writel_relaxed(val,
+- mbox->mbox_base + index * 0x4);
++ writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
+ }
+ }
+
+--
+2.35.1
+
--- /dev/null
+From f778913987a5be7788625f29e54b1913b537842c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 08:08:11 +0100
+Subject: mailbox: mpfs: fix handling of the reg property
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+[ Upstream commit 2e10289d1f304f5082a4dda55a677b72b3bdb581 ]
+
+The "data" region of the PolarFire SoC's system controller mailbox is
+not one continuous register space - the system controller's QSPI sits
+between the control and data registers. Split the "data" reg into two
+parts: "data" & "control". Optionally get the "data" register address
+from the 3rd reg property in the devicetree & fall back to using the
+old base + MAILBOX_REG_OFFSET that the current code uses.
+
+Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox")
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mailbox/mailbox-mpfs.c | 24 ++++++++++++++----------
+ 1 file changed, 14 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
+index 4e34854d1238..e432a8f0d148 100644
+--- a/drivers/mailbox/mailbox-mpfs.c
++++ b/drivers/mailbox/mailbox-mpfs.c
+@@ -62,6 +62,7 @@ struct mpfs_mbox {
+ struct mbox_controller controller;
+ struct device *dev;
+ int irq;
++ void __iomem *ctrl_base;
+ void __iomem *mbox_base;
+ void __iomem *int_reg;
+ struct mbox_chan chans[1];
+@@ -73,7 +74,7 @@ static bool mpfs_mbox_busy(struct mpfs_mbox *mbox)
+ {
+ u32 status;
+
+- status = readl_relaxed(mbox->mbox_base + SERVICES_SR_OFFSET);
++ status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);
+
+ return status & SCB_STATUS_BUSY_MASK;
+ }
+@@ -99,14 +100,13 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
+
+ for (index = 0; index < (msg->cmd_data_size / 4); index++)
+ writel_relaxed(word_buf[index],
+- mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4);
++ mbox->mbox_base + index * 0x4);
+ if (extra_bits) {
+ u8 i;
+ u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
+ u8 *byte_buf = msg->cmd_data + byte_off;
+
+- val = readl_relaxed(mbox->mbox_base +
+- MAILBOX_REG_OFFSET + index * 0x4);
++ val = readl_relaxed(mbox->mbox_base + index * 0x4);
+
+ for (i = 0u; i < extra_bits; i++) {
+ val &= ~(0xffu << (i * 8u));
+@@ -114,14 +114,14 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
+ }
+
+ writel_relaxed(val,
+- mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4);
++ mbox->mbox_base + index * 0x4);
+ }
+ }
+
+ opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+ tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
+ tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
+- writel_relaxed(tx_trigger, mbox->mbox_base + SERVICES_CR_OFFSET);
++ writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
+
+ return 0;
+ }
+@@ -141,7 +141,7 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan)
+ if (!mpfs_mbox_busy(mbox)) {
+ for (i = 0; i < num_words; i++) {
+ response->resp_msg[i] =
+- readl_relaxed(mbox->mbox_base + MAILBOX_REG_OFFSET
++ readl_relaxed(mbox->mbox_base
+ + mbox->resp_offset + i * 0x4);
+ }
+ }
+@@ -200,14 +200,18 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
+ if (!mbox)
+ return -ENOMEM;
+
+- mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
+- if (IS_ERR(mbox->mbox_base))
+- return PTR_ERR(mbox->mbox_base);
++ mbox->ctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
++ if (IS_ERR(mbox->ctrl_base))
++ return PTR_ERR(mbox->ctrl_base);
+
+ mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s);
+ if (IS_ERR(mbox->int_reg))
+ return PTR_ERR(mbox->int_reg);
+
++ mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 2, ®s);
++ if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs
++ mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET;
++
+ mbox->irq = platform_get_irq(pdev, 0);
+ if (mbox->irq < 0)
+ return mbox->irq;
+--
+2.35.1
+
--- /dev/null
+From 6cfc59304492f77ac462a5e70c80bc43d98fee1d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Dec 2021 20:06:19 +0000
+Subject: md: add support for REQ_NOWAIT
+
+From: Vishal Verma <vverma@digitalocean.com>
+
+[ Upstream commit f51d46d0e7cb5b8494aa534d276a9d8915a2443d ]
+
+commit 021a24460dc2 ("block: add QUEUE_FLAG_NOWAIT") added support
+for checking whether a given bdev supports handling of REQ_NOWAIT or not.
+Since then commit 6abc49468eea ("dm: add support for REQ_NOWAIT and enable
+it for linear target") added support for REQ_NOWAIT for dm. This uses
+a similar approach to incorporate REQ_NOWAIT for md based bios.
+
+This patch was tested using t/io_uring tool within FIO. A nvme drive
+was partitioned into 2 partitions and a simple raid 0 configuration
+/dev/md0 was created.
+
+md0 : active raid0 nvme4n1p1[1] nvme4n1p2[0]
+ 937423872 blocks super 1.2 512k chunks
+
+Before patch:
+
+$ ./t/io_uring /dev/md0 -p 0 -a 0 -d 1 -r 100
+
+Running top while the above runs:
+
+$ ps -eL | grep $(pidof io_uring)
+
+ 38396 38396 pts/2 00:00:00 io_uring
+ 38396 38397 pts/2 00:00:15 io_uring
+ 38396 38398 pts/2 00:00:13 iou-wrk-38397
+
+We can see iou-wrk-38397 io worker thread created which gets created
+when io_uring sees that the underlying device (/dev/md0 in this case)
+doesn't support nowait.
+
+After patch:
+
+$ ./t/io_uring /dev/md0 -p 0 -a 0 -d 1 -r 100
+
+Running top while the above runs:
+
+$ ps -eL | grep $(pidof io_uring)
+
+ 38341 38341 pts/2 00:10:22 io_uring
+ 38341 38342 pts/2 00:10:37 io_uring
+
+After running this patch, we don't see any io worker thread
+being created which indicated that io_uring saw that the
+underlying device does support nowait. This is the exact behaviour
+noticed on a dm device which also supports nowait.
+
+For all the other raid personalities except raid0, we would need
+to train pieces which involves make_request fn in order for them
+to correctly handle REQ_NOWAIT.
+
+Reviewed-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Vishal Verma <vverma@digitalocean.com>
+Signed-off-by: Song Liu <song@kernel.org>
+Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/md.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/md/md.c b/drivers/md/md.c
+index 04e1e294b4b1..ea21a9ddf15f 100644
+--- a/drivers/md/md.c
++++ b/drivers/md/md.c
+@@ -417,6 +417,12 @@ void md_handle_request(struct mddev *mddev, struct bio *bio)
+ rcu_read_lock();
+ if (is_suspended(mddev, bio)) {
+ DEFINE_WAIT(__wait);
++ /* Bail out if REQ_NOWAIT is set for the bio */
++ if (bio->bi_opf & REQ_NOWAIT) {
++ rcu_read_unlock();
++ bio_wouldblock_error(bio);
++ return;
++ }
+ for (;;) {
+ prepare_to_wait(&mddev->sb_wait, &__wait,
+ TASK_UNINTERRUPTIBLE);
+@@ -5792,6 +5798,7 @@ int md_run(struct mddev *mddev)
+ int err;
+ struct md_rdev *rdev;
+ struct md_personality *pers;
++ bool nowait = true;
+
+ if (list_empty(&mddev->disks))
+ /* cannot run an array with no devices.. */
+@@ -5862,8 +5869,13 @@ int md_run(struct mddev *mddev)
+ }
+ }
+ sysfs_notify_dirent_safe(rdev->sysfs_state);
++ nowait = nowait && blk_queue_nowait(bdev_get_queue(rdev->bdev));
+ }
+
++ /* Set the NOWAIT flags if all underlying devices support it */
++ if (nowait)
++ blk_queue_flag_set(QUEUE_FLAG_NOWAIT, mddev->queue);
++
+ if (!bioset_initialized(&mddev->bio_set)) {
+ err = bioset_init(&mddev->bio_set, BIO_POOL_SIZE, 0, BIOSET_NEED_BVECS);
+ if (err)
+@@ -6996,6 +7008,15 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev)
+ set_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags);
+ if (!mddev->thread)
+ md_update_sb(mddev, 1);
++ /*
++ * If the new disk does not support REQ_NOWAIT,
++ * disable on the whole MD.
++ */
++ if (!blk_queue_nowait(bdev_get_queue(rdev->bdev))) {
++ pr_info("%s: Disabling nowait because %s does not support nowait\n",
++ mdname(mddev), bdevname(rdev->bdev, b));
++ blk_queue_flag_clear(QUEUE_FLAG_NOWAIT, mddev->queue);
++ }
+ /*
+ * Kick recovery, maybe this spare has to be added to the
+ * array immediately.
+--
+2.35.1
+
--- /dev/null
+From 28b9a9d78bb0d4e03cc8948d89d30b4efe7a03d8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Apr 2022 10:57:09 -0600
+Subject: md/raid5: Add __rcu annotation to struct disk_info
+
+From: Logan Gunthorpe <logang@deltatee.com>
+
+[ Upstream commit b0920ede081b3f1659872f80ce552305610675a6 ]
+
+rdev and replacement are protected in some circumstances with
+rcu_dereference and synchronize_rcu (in raid5_remove_disk()). However,
+they were not annotated with __rcu so a sparse warning is emitted for
+every rcu_dereference() call.
+
+Add the __rcu annotation and fix up the initialization with
+RCU_INIT_POINTER, all pointer modifications with rcu_assign_pointer(),
+a few cases where the pointer value is tested with rcu_access_pointer()
+and one case where READ_ONCE() is used instead of rcu_dereference(),
+a case in print_raid5_conf() that should have rcu_dereference() and
+rcu_read_[un]lock() calls.
+
+Additional sparse issues will be fixed up in further commits.
+
+Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Song Liu <song@kernel.org>
+Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid5.c | 46 ++++++++++++++++++++++++++--------------------
+ drivers/md/raid5.h | 3 ++-
+ 2 files changed, 28 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index 19e497a7e747..01c326dc57d5 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -6285,7 +6285,7 @@ static inline sector_t raid5_sync_request(struct mddev *mddev, sector_t sector_n
+ */
+ rcu_read_lock();
+ for (i = 0; i < conf->raid_disks; i++) {
+- struct md_rdev *rdev = READ_ONCE(conf->disks[i].rdev);
++ struct md_rdev *rdev = rcu_dereference(conf->disks[i].rdev);
+
+ if (rdev == NULL || test_bit(Faulty, &rdev->flags))
+ still_degraded = 1;
+@@ -7313,11 +7313,11 @@ static struct r5conf *setup_conf(struct mddev *mddev)
+ if (test_bit(Replacement, &rdev->flags)) {
+ if (disk->replacement)
+ goto abort;
+- disk->replacement = rdev;
++ RCU_INIT_POINTER(disk->replacement, rdev);
+ } else {
+ if (disk->rdev)
+ goto abort;
+- disk->rdev = rdev;
++ RCU_INIT_POINTER(disk->rdev, rdev);
+ }
+
+ if (test_bit(In_sync, &rdev->flags)) {
+@@ -7623,11 +7623,11 @@ static int raid5_run(struct mddev *mddev)
+ rdev = conf->disks[i].replacement;
+ conf->disks[i].replacement = NULL;
+ clear_bit(Replacement, &rdev->flags);
+- conf->disks[i].rdev = rdev;
++ rcu_assign_pointer(conf->disks[i].rdev, rdev);
+ }
+ if (!rdev)
+ continue;
+- if (conf->disks[i].replacement &&
++ if (rcu_access_pointer(conf->disks[i].replacement) &&
+ conf->reshape_progress != MaxSector) {
+ /* replacements and reshape simply do not mix. */
+ pr_warn("md: cannot handle concurrent replacement and reshape.\n");
+@@ -7832,8 +7832,8 @@ static void raid5_status(struct seq_file *seq, struct mddev *mddev)
+
+ static void print_raid5_conf (struct r5conf *conf)
+ {
++ struct md_rdev *rdev;
+ int i;
+- struct disk_info *tmp;
+
+ pr_debug("RAID conf printout:\n");
+ if (!conf) {
+@@ -7844,14 +7844,16 @@ static void print_raid5_conf (struct r5conf *conf)
+ conf->raid_disks,
+ conf->raid_disks - conf->mddev->degraded);
+
++ rcu_read_lock();
+ for (i = 0; i < conf->raid_disks; i++) {
+ char b[BDEVNAME_SIZE];
+- tmp = conf->disks + i;
+- if (tmp->rdev)
++ rdev = rcu_dereference(conf->disks[i].rdev);
++ if (rdev)
+ pr_debug(" disk %d, o:%d, dev:%s\n",
+- i, !test_bit(Faulty, &tmp->rdev->flags),
+- bdevname(tmp->rdev->bdev, b));
++ i, !test_bit(Faulty, &rdev->flags),
++ bdevname(rdev->bdev, b));
+ }
++ rcu_read_unlock();
+ }
+
+ static int raid5_spare_active(struct mddev *mddev)
+@@ -7902,8 +7904,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
+ struct r5conf *conf = mddev->private;
+ int err = 0;
+ int number = rdev->raid_disk;
+- struct md_rdev **rdevp;
++ struct md_rdev __rcu **rdevp;
+ struct disk_info *p = conf->disks + number;
++ struct md_rdev *tmp;
+
+ print_raid5_conf(conf);
+ if (test_bit(Journal, &rdev->flags) && conf->log) {
+@@ -7921,9 +7924,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
+ log_exit(conf);
+ return 0;
+ }
+- if (rdev == p->rdev)
++ if (rdev == rcu_access_pointer(p->rdev))
+ rdevp = &p->rdev;
+- else if (rdev == p->replacement)
++ else if (rdev == rcu_access_pointer(p->replacement))
+ rdevp = &p->replacement;
+ else
+ return 0;
+@@ -7943,7 +7946,8 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
+ if (!test_bit(Faulty, &rdev->flags) &&
+ mddev->recovery_disabled != conf->recovery_disabled &&
+ !has_failed(conf) &&
+- (!p->replacement || p->replacement == rdev) &&
++ (!rcu_access_pointer(p->replacement) ||
++ rcu_access_pointer(p->replacement) == rdev) &&
+ number < conf->raid_disks) {
+ err = -EBUSY;
+ goto abort;
+@@ -7954,7 +7958,7 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
+ if (atomic_read(&rdev->nr_pending)) {
+ /* lost the race, try later */
+ err = -EBUSY;
+- *rdevp = rdev;
++ rcu_assign_pointer(*rdevp, rdev);
+ }
+ }
+ if (!err) {
+@@ -7962,17 +7966,19 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
+ if (err)
+ goto abort;
+ }
+- if (p->replacement) {
++
++ tmp = rcu_access_pointer(p->replacement);
++ if (tmp) {
+ /* We must have just cleared 'rdev' */
+- p->rdev = p->replacement;
+- clear_bit(Replacement, &p->replacement->flags);
++ rcu_assign_pointer(p->rdev, tmp);
++ clear_bit(Replacement, &tmp->flags);
+ smp_mb(); /* Make sure other CPUs may see both as identical
+ * but will never see neither - if they are careful
+ */
+- p->replacement = NULL;
++ rcu_assign_pointer(p->replacement, NULL);
+
+ if (!err)
+- err = log_modify(conf, p->rdev, true);
++ err = log_modify(conf, tmp, true);
+ }
+
+ clear_bit(WantReplacement, &rdev->flags);
+diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h
+index 5c05acf20e1f..666943926554 100644
+--- a/drivers/md/raid5.h
++++ b/drivers/md/raid5.h
+@@ -472,7 +472,8 @@ enum {
+ */
+
+ struct disk_info {
+- struct md_rdev *rdev, *replacement;
++ struct md_rdev __rcu *rdev;
++ struct md_rdev __rcu *replacement;
+ struct page *extra_page; /* extra page to use in prexor */
+ };
+
+--
+2.35.1
+
--- /dev/null
+From c867909009873e62155c82758b6f8bd23d78a89f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 09:46:27 -0600
+Subject: md/raid5: Ensure stripe_fill happens on non-read IO with journal
+
+From: Logan Gunthorpe <logang@deltatee.com>
+
+[ Upstream commit e2eed85bc75138a9eeb63863d20f8904ac42a577 ]
+
+When doing degrade/recover tests using the journal a kernel BUG
+is hit at drivers/md/raid5.c:4381 in handle_parity_checks5():
+
+ BUG_ON(!test_bit(R5_UPTODATE, &dev->flags));
+
+This was found to occur because handle_stripe_fill() was skipped
+for stripes in the journal due to a condition in that function.
+Thus blocks were not fetched and R5_UPTODATE was not set when
+the code reached handle_parity_checks5().
+
+To fix this, don't skip handle_stripe_fill() unless the stripe is
+for read.
+
+Fixes: 07e83364845e ("md/r5cache: shift complex rmw from read path to write path")
+Link: https://lore.kernel.org/linux-raid/e05c4239-41a9-d2f7-3cfa-4aa9d2cea8c1@deltatee.com/
+Suggested-by: Song Liu <song@kernel.org>
+Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
+Signed-off-by: Song Liu <song@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index 1b2f6e62507d..7a2cc1ec532b 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -3933,7 +3933,7 @@ static void handle_stripe_fill(struct stripe_head *sh,
+ * back cache (prexor with orig_page, and then xor with
+ * page) in the read path
+ */
+- if (s->injournal && s->failed) {
++ if (s->to_read && s->injournal && s->failed) {
+ if (test_bit(STRIPE_R5C_CACHING, &sh->state))
+ r5c_make_stripe_write_out(sh);
+ goto out;
+--
+2.35.1
+
--- /dev/null
+From 8055ff9b84c2f6ffe6c9cda9587ac6caf828ac32 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 10:15:14 -0600
+Subject: md/raid5: Remove unnecessary bio_put() in raid5_read_one_chunk()
+
+From: David Sloan <david.sloan@eideticom.com>
+
+[ Upstream commit c66a6f41e09ad386fd2cce22b9cded837bbbc704 ]
+
+When running chunk-sized reads on disks with badblocks duplicate bio
+free/puts are observed:
+
+ =============================================================================
+ BUG bio-200 (Not tainted): Object already free
+ -----------------------------------------------------------------------------
+ Allocated in mempool_alloc_slab+0x17/0x20 age=3 cpu=2 pid=7504
+ __slab_alloc.constprop.0+0x5a/0xb0
+ kmem_cache_alloc+0x31e/0x330
+ mempool_alloc_slab+0x17/0x20
+ mempool_alloc+0x100/0x2b0
+ bio_alloc_bioset+0x181/0x460
+ do_mpage_readpage+0x776/0xd00
+ mpage_readahead+0x166/0x320
+ blkdev_readahead+0x15/0x20
+ read_pages+0x13f/0x5f0
+ page_cache_ra_unbounded+0x18d/0x220
+ force_page_cache_ra+0x181/0x1c0
+ page_cache_sync_ra+0x65/0xb0
+ filemap_get_pages+0x1df/0xaf0
+ filemap_read+0x1e1/0x700
+ blkdev_read_iter+0x1e5/0x330
+ vfs_read+0x42a/0x570
+ Freed in mempool_free_slab+0x17/0x20 age=3 cpu=2 pid=7504
+ kmem_cache_free+0x46d/0x490
+ mempool_free_slab+0x17/0x20
+ mempool_free+0x66/0x190
+ bio_free+0x78/0x90
+ bio_put+0x100/0x1a0
+ raid5_make_request+0x2259/0x2450
+ md_handle_request+0x402/0x600
+ md_submit_bio+0xd9/0x120
+ __submit_bio+0x11f/0x1b0
+ submit_bio_noacct_nocheck+0x204/0x480
+ submit_bio_noacct+0x32e/0xc70
+ submit_bio+0x98/0x1a0
+ mpage_readahead+0x250/0x320
+ blkdev_readahead+0x15/0x20
+ read_pages+0x13f/0x5f0
+ page_cache_ra_unbounded+0x18d/0x220
+ Slab 0xffffea000481b600 objects=21 used=0 fp=0xffff8881206d8940 flags=0x17ffffc0010201(locked|slab|head|node=0|zone=2|lastcpupid=0x1fffff)
+ CPU: 0 PID: 34525 Comm: kworker/u24:2 Not tainted 6.0.0-rc2-localyes-265166-gf11c5343fa3f #143
+ Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.13.0-1ubuntu1.1 04/01/2014
+ Workqueue: raid5wq raid5_do_work
+ Call Trace:
+ <TASK>
+ dump_stack_lvl+0x5a/0x78
+ dump_stack+0x10/0x16
+ print_trailer+0x158/0x165
+ object_err+0x35/0x50
+ free_debug_processing.cold+0xb7/0xbe
+ __slab_free+0x1ae/0x330
+ kmem_cache_free+0x46d/0x490
+ mempool_free_slab+0x17/0x20
+ mempool_free+0x66/0x190
+ bio_free+0x78/0x90
+ bio_put+0x100/0x1a0
+ mpage_end_io+0x36/0x150
+ bio_endio+0x2fd/0x360
+ md_end_io_acct+0x7e/0x90
+ bio_endio+0x2fd/0x360
+ handle_failed_stripe+0x960/0xb80
+ handle_stripe+0x1348/0x3760
+ handle_active_stripes.constprop.0+0x72a/0xaf0
+ raid5_do_work+0x177/0x330
+ process_one_work+0x616/0xb20
+ worker_thread+0x2bd/0x6f0
+ kthread+0x179/0x1b0
+ ret_from_fork+0x22/0x30
+ </TASK>
+
+The double free is caused by an unnecessary bio_put() in the
+if(is_badblock(...)) error path in raid5_read_one_chunk().
+
+The error path was moved ahead of bio_alloc_clone() in c82aa1b76787c
+("md/raid5: move checking badblock before clone bio in
+raid5_read_one_chunk"). The previous code checked and freed align_bio
+which required a bio_put. After the move that is no longer needed as
+raid_bio is returned to the control of the common io path which
+performs its own endio resulting in a double free on bad device blocks.
+
+Fixes: c82aa1b76787c ("md/raid5: move checking badblock before clone bio in raid5_read_one_chunk")
+Signed-off-by: David Sloan <david.sloan@eideticom.com>
+Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Acked-by: Guoqing Jiang <Guoqing.jiang@linux.dev>
+Signed-off-by: Song Liu <song@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid5.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index 7a2cc1ec532b..d9ad66c2c8e1 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -5427,7 +5427,6 @@ static int raid5_read_one_chunk(struct mddev *mddev, struct bio *raid_bio)
+
+ if (is_badblock(rdev, sector, bio_sectors(raid_bio), &first_bad,
+ &bad_sectors)) {
+- bio_put(raid_bio);
+ rdev_dec_pending(rdev, mddev);
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From a95a08cf6ada7594444ca7b01c710bfb01065623 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 10:28:37 -0600
+Subject: md/raid5: Wait for MD_SB_CHANGE_PENDING in raid5d
+
+From: Logan Gunthorpe <logang@deltatee.com>
+
+[ Upstream commit 5e2cf333b7bd5d3e62595a44d598a254c697cd74 ]
+
+A complicated deadlock exists when using the journal and an elevated
+group_thrtead_cnt. It was found with loop devices, but its not clear
+whether it can be seen with real disks. The deadlock can occur simply
+by writing data with an fio script.
+
+When the deadlock occurs, multiple threads will hang in different ways:
+
+ 1) The group threads will hang in the blk-wbt code with bios waiting to
+ be submitted to the block layer:
+
+ io_schedule+0x70/0xb0
+ rq_qos_wait+0x153/0x210
+ wbt_wait+0x115/0x1b0
+ io_schedule+0x70/0xb0
+ rq_qos_wait+0x153/0x210
+ wbt_wait+0x115/0x1b0
+ __rq_qos_throttle+0x38/0x60
+ blk_mq_submit_bio+0x589/0xcd0
+ wbt_wait+0x115/0x1b0
+ __rq_qos_throttle+0x38/0x60
+ blk_mq_submit_bio+0x589/0xcd0
+ __submit_bio+0xe6/0x100
+ submit_bio_noacct_nocheck+0x42e/0x470
+ submit_bio_noacct+0x4c2/0xbb0
+ ops_run_io+0x46b/0x1a30
+ handle_stripe+0xcd3/0x36b0
+ handle_active_stripes.constprop.0+0x6f6/0xa60
+ raid5_do_work+0x177/0x330
+
+ Or:
+ io_schedule+0x70/0xb0
+ rq_qos_wait+0x153/0x210
+ wbt_wait+0x115/0x1b0
+ __rq_qos_throttle+0x38/0x60
+ blk_mq_submit_bio+0x589/0xcd0
+ __submit_bio+0xe6/0x100
+ submit_bio_noacct_nocheck+0x42e/0x470
+ submit_bio_noacct+0x4c2/0xbb0
+ flush_deferred_bios+0x136/0x170
+ raid5_do_work+0x262/0x330
+
+ 2) The r5l_reclaim thread will hang in the same way, submitting a
+ bio to the block layer:
+
+ io_schedule+0x70/0xb0
+ rq_qos_wait+0x153/0x210
+ wbt_wait+0x115/0x1b0
+ __rq_qos_throttle+0x38/0x60
+ blk_mq_submit_bio+0x589/0xcd0
+ __submit_bio+0xe6/0x100
+ submit_bio_noacct_nocheck+0x42e/0x470
+ submit_bio_noacct+0x4c2/0xbb0
+ submit_bio+0x3f/0xf0
+ md_super_write+0x12f/0x1b0
+ md_update_sb.part.0+0x7c6/0xff0
+ md_update_sb+0x30/0x60
+ r5l_do_reclaim+0x4f9/0x5e0
+ r5l_reclaim_thread+0x69/0x30b
+
+ However, before hanging, the MD_SB_CHANGE_PENDING flag will be
+ set for sb_flags in r5l_write_super_and_discard_space(). This
+ flag will never be cleared because the submit_bio() call never
+ returns.
+
+ 3) Due to the MD_SB_CHANGE_PENDING flag being set, handle_stripe()
+ will do no processing on any pending stripes and re-set
+ STRIPE_HANDLE. This will cause the raid5d thread to enter an
+ infinite loop, constantly trying to handle the same stripes
+ stuck in the queue.
+
+ The raid5d thread has a blk_plug that holds a number of bios
+ that are also stuck waiting seeing the thread is in a loop
+ that never schedules. These bios have been accounted for by
+ blk-wbt thus preventing the other threads above from
+ continuing when they try to submit bios. --Deadlock.
+
+To fix this, add the same wait_event() that is used in raid5_do_work()
+to raid5d() such that if MD_SB_CHANGE_PENDING is set, the thread will
+schedule and wait until the flag is cleared. The schedule action will
+flush the plug which will allow the r5l_reclaim thread to continue,
+thus preventing the deadlock.
+
+However, md_check_recovery() calls can also clear MD_SB_CHANGE_PENDING
+from the same thread and can thus deadlock if the thread is put to
+sleep. So avoid waiting if md_check_recovery() is being called in the
+loop.
+
+It's not clear when the deadlock was introduced, but the similar
+wait_event() call in raid5_do_work() was added in 2017 by this
+commit:
+
+ 16d997b78b15 ("md/raid5: simplfy delaying of writes while metadata
+ is updated.")
+
+Link: https://lore.kernel.org/r/7f3b87b6-b52a-f737-51d7-a4eec5c44112@deltatee.com
+Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
+Signed-off-by: Song Liu <song@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid5.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index d9ad66c2c8e1..7a849a4b7085 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -36,6 +36,7 @@
+ */
+
+ #include <linux/blkdev.h>
++#include <linux/delay.h>
+ #include <linux/kthread.h>
+ #include <linux/raid/pq.h>
+ #include <linux/async_tx.h>
+@@ -6518,7 +6519,18 @@ static void raid5d(struct md_thread *thread)
+ spin_unlock_irq(&conf->device_lock);
+ md_check_recovery(mddev);
+ spin_lock_irq(&conf->device_lock);
++
++ /*
++ * Waiting on MD_SB_CHANGE_PENDING below may deadlock
++ * seeing md_check_recovery() is needed to clear
++ * the flag when using mdmon.
++ */
++ continue;
+ }
++
++ wait_event_lock_irq(mddev->sb_wait,
++ !test_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags),
++ conf->device_lock);
+ }
+ pr_debug("%d stripes handled\n", handled);
+
+--
+2.35.1
+
--- /dev/null
+From e979c86f0bbad529f6976924cb1a2efb352ba946 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 12 May 2022 08:19:13 +0200
+Subject: md: remove most calls to bdevname
+
+From: Christoph Hellwig <hch@lst.de>
+
+[ Upstream commit 913cce5a1e588e3470ea064fe4ea336037d3a454 ]
+
+Use the %pg format specifier to save on stack consumption and code size.
+
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Song Liu <song@kernel.org>
+Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/md-linear.c | 5 +-
+ drivers/md/md-multipath.c | 15 ++--
+ drivers/md/md.c | 152 ++++++++++++++++----------------------
+ drivers/md/raid0.c | 28 +++----
+ drivers/md/raid1.c | 24 +++---
+ drivers/md/raid10.c | 54 ++++++--------
+ drivers/md/raid5-cache.c | 5 +-
+ drivers/md/raid5-ppl.c | 27 +++----
+ drivers/md/raid5.c | 37 ++++------
+ 9 files changed, 147 insertions(+), 200 deletions(-)
+
+diff --git a/drivers/md/md-linear.c b/drivers/md/md-linear.c
+index 1ff51647a682..40bdc6aecd0b 100644
+--- a/drivers/md/md-linear.c
++++ b/drivers/md/md-linear.c
+@@ -215,7 +215,6 @@ static void linear_free(struct mddev *mddev, void *priv)
+
+ static bool linear_make_request(struct mddev *mddev, struct bio *bio)
+ {
+- char b[BDEVNAME_SIZE];
+ struct dev_info *tmp_dev;
+ sector_t start_sector, end_sector, data_offset;
+ sector_t bio_sector = bio->bi_iter.bi_sector;
+@@ -266,10 +265,10 @@ static bool linear_make_request(struct mddev *mddev, struct bio *bio)
+ return true;
+
+ out_of_bounds:
+- pr_err("md/linear:%s: make_request: Sector %llu out of bounds on dev %s: %llu sectors, offset %llu\n",
++ pr_err("md/linear:%s: make_request: Sector %llu out of bounds on dev %pg: %llu sectors, offset %llu\n",
+ mdname(mddev),
+ (unsigned long long)bio->bi_iter.bi_sector,
+- bdevname(tmp_dev->rdev->bdev, b),
++ tmp_dev->rdev->bdev,
+ (unsigned long long)tmp_dev->rdev->sectors,
+ (unsigned long long)start_sector);
+ bio_io_error(bio);
+diff --git a/drivers/md/md-multipath.c b/drivers/md/md-multipath.c
+index e7d6486f090f..2147a158e080 100644
+--- a/drivers/md/md-multipath.c
++++ b/drivers/md/md-multipath.c
+@@ -87,10 +87,9 @@ static void multipath_end_request(struct bio *bio)
+ /*
+ * oops, IO error:
+ */
+- char b[BDEVNAME_SIZE];
+ md_error (mp_bh->mddev, rdev);
+- pr_info("multipath: %s: rescheduling sector %llu\n",
+- bdevname(rdev->bdev,b),
++ pr_info("multipath: %pg: rescheduling sector %llu\n",
++ rdev->bdev,
+ (unsigned long long)bio->bi_iter.bi_sector);
+ multipath_reschedule_retry(mp_bh);
+ } else
+@@ -157,7 +156,6 @@ static void multipath_status(struct seq_file *seq, struct mddev *mddev)
+ static void multipath_error (struct mddev *mddev, struct md_rdev *rdev)
+ {
+ struct mpconf *conf = mddev->private;
+- char b[BDEVNAME_SIZE];
+
+ if (conf->raid_disks - mddev->degraded <= 1) {
+ /*
+@@ -180,9 +178,9 @@ static void multipath_error (struct mddev *mddev, struct md_rdev *rdev)
+ }
+ set_bit(Faulty, &rdev->flags);
+ set_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags);
+- pr_err("multipath: IO failure on %s, disabling IO path.\n"
++ pr_err("multipath: IO failure on %pg, disabling IO path.\n"
+ "multipath: Operation continuing on %d IO paths.\n",
+- bdevname(rdev->bdev, b),
++ rdev->bdev,
+ conf->raid_disks - mddev->degraded);
+ }
+
+@@ -200,12 +198,11 @@ static void print_multipath_conf (struct mpconf *conf)
+ conf->raid_disks);
+
+ for (i = 0; i < conf->raid_disks; i++) {
+- char b[BDEVNAME_SIZE];
+ tmp = conf->multipaths + i;
+ if (tmp->rdev)
+- pr_debug(" disk%d, o:%d, dev:%s\n",
++ pr_debug(" disk%d, o:%d, dev:%pg\n",
+ i,!test_bit(Faulty, &tmp->rdev->flags),
+- bdevname(tmp->rdev->bdev,b));
++ tmp->rdev->bdev);
+ }
+ }
+
+diff --git a/drivers/md/md.c b/drivers/md/md.c
+index 79b685fb8207..89943840afed 100644
+--- a/drivers/md/md.c
++++ b/drivers/md/md.c
+@@ -1025,8 +1025,6 @@ EXPORT_SYMBOL_GPL(sync_page_io);
+
+ static int read_disk_sb(struct md_rdev *rdev, int size)
+ {
+- char b[BDEVNAME_SIZE];
+-
+ if (rdev->sb_loaded)
+ return 0;
+
+@@ -1036,8 +1034,8 @@ static int read_disk_sb(struct md_rdev *rdev, int size)
+ return 0;
+
+ fail:
+- pr_err("md: disabled device %s, could not read superblock.\n",
+- bdevname(rdev->bdev,b));
++ pr_err("md: disabled device %pg, could not read superblock.\n",
++ rdev->bdev);
+ return -EINVAL;
+ }
+
+@@ -1183,7 +1181,6 @@ EXPORT_SYMBOL(md_check_no_bitmap);
+ */
+ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_version)
+ {
+- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE];
+ mdp_super_t *sb;
+ int ret;
+ bool spare_disk = true;
+@@ -1202,19 +1199,19 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor
+
+ ret = -EINVAL;
+
+- bdevname(rdev->bdev, b);
+ sb = page_address(rdev->sb_page);
+
+ if (sb->md_magic != MD_SB_MAGIC) {
+- pr_warn("md: invalid raid superblock magic on %s\n", b);
++ pr_warn("md: invalid raid superblock magic on %pg\n",
++ rdev->bdev);
+ goto abort;
+ }
+
+ if (sb->major_version != 0 ||
+ sb->minor_version < 90 ||
+ sb->minor_version > 91) {
+- pr_warn("Bad version number %d.%d on %s\n",
+- sb->major_version, sb->minor_version, b);
++ pr_warn("Bad version number %d.%d on %pg\n",
++ sb->major_version, sb->minor_version, rdev->bdev);
+ goto abort;
+ }
+
+@@ -1222,7 +1219,7 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor
+ goto abort;
+
+ if (md_csum_fold(calc_sb_csum(sb)) != md_csum_fold(sb->sb_csum)) {
+- pr_warn("md: invalid superblock checksum on %s\n", b);
++ pr_warn("md: invalid superblock checksum on %pg\n", rdev->bdev);
+ goto abort;
+ }
+
+@@ -1254,13 +1251,13 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor
+ __u64 ev1, ev2;
+ mdp_super_t *refsb = page_address(refdev->sb_page);
+ if (!md_uuid_equal(refsb, sb)) {
+- pr_warn("md: %s has different UUID to %s\n",
+- b, bdevname(refdev->bdev,b2));
++ pr_warn("md: %pg has different UUID to %pg\n",
++ rdev->bdev, refdev->bdev);
+ goto abort;
+ }
+ if (!md_sb_equal(refsb, sb)) {
+- pr_warn("md: %s has same UUID but different superblock to %s\n",
+- b, bdevname(refdev->bdev, b2));
++ pr_warn("md: %pg has same UUID but different superblock to %pg\n",
++ rdev->bdev, refdev->bdev);
+ goto abort;
+ }
+ ev1 = md_event(sb);
+@@ -1624,7 +1621,6 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_
+ int ret;
+ sector_t sb_start;
+ sector_t sectors;
+- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE];
+ int bmask;
+ bool spare_disk = true;
+
+@@ -1669,13 +1665,13 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_
+ return -EINVAL;
+
+ if (calc_sb_1_csum(sb) != sb->sb_csum) {
+- pr_warn("md: invalid superblock checksum on %s\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: invalid superblock checksum on %pg\n",
++ rdev->bdev);
+ return -EINVAL;
+ }
+ if (le64_to_cpu(sb->data_size) < 10) {
+- pr_warn("md: data_size too small on %s\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: data_size too small on %pg\n",
++ rdev->bdev);
+ return -EINVAL;
+ }
+ if (sb->pad0 ||
+@@ -1781,9 +1777,9 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_
+ sb->level != refsb->level ||
+ sb->layout != refsb->layout ||
+ sb->chunksize != refsb->chunksize) {
+- pr_warn("md: %s has strangely different superblock to %s\n",
+- bdevname(rdev->bdev,b),
+- bdevname(refdev->bdev,b2));
++ pr_warn("md: %pg has strangely different superblock to %pg\n",
++ rdev->bdev,
++ refdev->bdev);
+ return -EINVAL;
+ }
+ ev1 = le64_to_cpu(sb->events);
+@@ -2372,7 +2368,6 @@ EXPORT_SYMBOL(md_integrity_register);
+ int md_integrity_add_rdev(struct md_rdev *rdev, struct mddev *mddev)
+ {
+ struct blk_integrity *bi_mddev;
+- char name[BDEVNAME_SIZE];
+
+ if (!mddev->gendisk)
+ return 0;
+@@ -2383,8 +2378,8 @@ int md_integrity_add_rdev(struct md_rdev *rdev, struct mddev *mddev)
+ return 0;
+
+ if (blk_integrity_compare(mddev->gendisk, rdev->bdev->bd_disk) != 0) {
+- pr_err("%s: incompatible integrity profile for %s\n",
+- mdname(mddev), bdevname(rdev->bdev, name));
++ pr_err("%s: incompatible integrity profile for %pg\n",
++ mdname(mddev), rdev->bdev);
+ return -ENXIO;
+ }
+
+@@ -2493,11 +2488,9 @@ static void rdev_delayed_delete(struct work_struct *ws)
+
+ static void unbind_rdev_from_array(struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+-
+ bd_unlink_disk_holder(rdev->bdev, rdev->mddev->gendisk);
+ list_del_rcu(&rdev->same_set);
+- pr_debug("md: unbind<%s>\n", bdevname(rdev->bdev,b));
++ pr_debug("md: unbind<%pg>\n", rdev->bdev);
+ mddev_destroy_serial_pool(rdev->mddev, rdev, false);
+ rdev->mddev = NULL;
+ sysfs_remove_link(&rdev->kobj, "block");
+@@ -2550,9 +2543,7 @@ void md_autodetect_dev(dev_t dev);
+
+ static void export_rdev(struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+-
+- pr_debug("md: export_rdev(%s)\n", bdevname(rdev->bdev,b));
++ pr_debug("md: export_rdev(%pg)\n", rdev->bdev);
+ md_rdev_clear(rdev);
+ #ifndef MODULE
+ if (test_bit(AutoDetected, &rdev->flags))
+@@ -2810,8 +2801,6 @@ void md_update_sb(struct mddev *mddev, int force_change)
+ rewrite:
+ md_bitmap_update_sb(mddev->bitmap);
+ rdev_for_each(rdev, mddev) {
+- char b[BDEVNAME_SIZE];
+-
+ if (rdev->sb_loaded != 1)
+ continue; /* no noise on spare devices */
+
+@@ -2819,8 +2808,8 @@ void md_update_sb(struct mddev *mddev, int force_change)
+ md_super_write(mddev,rdev,
+ rdev->sb_start, rdev->sb_size,
+ rdev->sb_page);
+- pr_debug("md: (write) %s's sb offset: %llu\n",
+- bdevname(rdev->bdev, b),
++ pr_debug("md: (write) %pg's sb offset: %llu\n",
++ rdev->bdev,
+ (unsigned long long)rdev->sb_start);
+ rdev->sb_events = mddev->events;
+ if (rdev->badblocks.size) {
+@@ -2832,8 +2821,8 @@ void md_update_sb(struct mddev *mddev, int force_change)
+ }
+
+ } else
+- pr_debug("md: %s (skipping faulty)\n",
+- bdevname(rdev->bdev, b));
++ pr_debug("md: %pg (skipping faulty)\n",
++ rdev->bdev);
+
+ if (mddev->level == LEVEL_MULTIPATH)
+ /* only need to write one superblock... */
+@@ -3706,7 +3695,6 @@ EXPORT_SYMBOL_GPL(md_rdev_init);
+ */
+ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int super_minor)
+ {
+- char b[BDEVNAME_SIZE];
+ int err;
+ struct md_rdev *rdev;
+ sector_t size;
+@@ -3730,8 +3718,8 @@ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int supe
+
+ size = i_size_read(rdev->bdev->bd_inode) >> BLOCK_SIZE_BITS;
+ if (!size) {
+- pr_warn("md: %s has zero or unknown size, marking faulty!\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: %pg has zero or unknown size, marking faulty!\n",
++ rdev->bdev);
+ err = -EINVAL;
+ goto abort_free;
+ }
+@@ -3740,14 +3728,14 @@ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int supe
+ err = super_types[super_format].
+ load_super(rdev, NULL, super_minor);
+ if (err == -EINVAL) {
+- pr_warn("md: %s does not have a valid v%d.%d superblock, not importing!\n",
+- bdevname(rdev->bdev,b),
++ pr_warn("md: %pg does not have a valid v%d.%d superblock, not importing!\n",
++ rdev->bdev,
+ super_format, super_minor);
+ goto abort_free;
+ }
+ if (err < 0) {
+- pr_warn("md: could not read %s's sb, not importing!\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: could not read %pg's sb, not importing!\n",
++ rdev->bdev);
+ goto abort_free;
+ }
+ }
+@@ -3770,7 +3758,6 @@ static int analyze_sbs(struct mddev *mddev)
+ {
+ int i;
+ struct md_rdev *rdev, *freshest, *tmp;
+- char b[BDEVNAME_SIZE];
+
+ freshest = NULL;
+ rdev_for_each_safe(rdev, tmp, mddev)
+@@ -3782,8 +3769,8 @@ static int analyze_sbs(struct mddev *mddev)
+ case 0:
+ break;
+ default:
+- pr_warn("md: fatal superblock inconsistency in %s -- removing from array\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: fatal superblock inconsistency in %pg -- removing from array\n",
++ rdev->bdev);
+ md_kick_rdev_from_array(rdev);
+ }
+
+@@ -3801,8 +3788,8 @@ static int analyze_sbs(struct mddev *mddev)
+ if (mddev->max_disks &&
+ (rdev->desc_nr >= mddev->max_disks ||
+ i > mddev->max_disks)) {
+- pr_warn("md: %s: %s: only %d devices permitted\n",
+- mdname(mddev), bdevname(rdev->bdev, b),
++ pr_warn("md: %s: %pg: only %d devices permitted\n",
++ mdname(mddev), rdev->bdev,
+ mddev->max_disks);
+ md_kick_rdev_from_array(rdev);
+ continue;
+@@ -3810,8 +3797,8 @@ static int analyze_sbs(struct mddev *mddev)
+ if (rdev != freshest) {
+ if (super_types[mddev->major_version].
+ validate_super(mddev, rdev)) {
+- pr_warn("md: kicking non-fresh %s from array!\n",
+- bdevname(rdev->bdev,b));
++ pr_warn("md: kicking non-fresh %pg from array!\n",
++ rdev->bdev);
+ md_kick_rdev_from_array(rdev);
+ continue;
+ }
+@@ -5919,7 +5906,6 @@ int md_run(struct mddev *mddev)
+ /* Warn if this is a potentially silly
+ * configuration.
+ */
+- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE];
+ struct md_rdev *rdev2;
+ int warned = 0;
+
+@@ -5928,10 +5914,10 @@ int md_run(struct mddev *mddev)
+ if (rdev < rdev2 &&
+ rdev->bdev->bd_disk ==
+ rdev2->bdev->bd_disk) {
+- pr_warn("%s: WARNING: %s appears to be on the same physical disk as %s.\n",
++ pr_warn("%s: WARNING: %pg appears to be on the same physical disk as %pg.\n",
+ mdname(mddev),
+- bdevname(rdev->bdev,b),
+- bdevname(rdev2->bdev,b2));
++ rdev->bdev,
++ rdev2->bdev);
+ warned = 1;
+ }
+ }
+@@ -6454,8 +6440,7 @@ static void autorun_array(struct mddev *mddev)
+ pr_info("md: running: ");
+
+ rdev_for_each(rdev, mddev) {
+- char b[BDEVNAME_SIZE];
+- pr_cont("<%s>", bdevname(rdev->bdev,b));
++ pr_cont("<%pg>", rdev->bdev);
+ }
+ pr_cont("\n");
+
+@@ -6482,7 +6467,6 @@ static void autorun_devices(int part)
+ {
+ struct md_rdev *rdev0, *rdev, *tmp;
+ struct mddev *mddev;
+- char b[BDEVNAME_SIZE];
+
+ pr_info("md: autorun ...\n");
+ while (!list_empty(&pending_raid_disks)) {
+@@ -6492,12 +6476,12 @@ static void autorun_devices(int part)
+ rdev0 = list_entry(pending_raid_disks.next,
+ struct md_rdev, same_set);
+
+- pr_debug("md: considering %s ...\n", bdevname(rdev0->bdev,b));
++ pr_debug("md: considering %pg ...\n", rdev0->bdev);
+ INIT_LIST_HEAD(&candidates);
+ rdev_for_each_list(rdev, tmp, &pending_raid_disks)
+ if (super_90_load(rdev, rdev0, 0) >= 0) {
+- pr_debug("md: adding %s ...\n",
+- bdevname(rdev->bdev,b));
++ pr_debug("md: adding %pg ...\n",
++ rdev->bdev);
+ list_move(&rdev->same_set, &candidates);
+ }
+ /*
+@@ -6514,8 +6498,8 @@ static void autorun_devices(int part)
+ unit = MINOR(dev);
+ }
+ if (rdev0->preferred_minor != unit) {
+- pr_warn("md: unit number in %s is bad: %d\n",
+- bdevname(rdev0->bdev, b), rdev0->preferred_minor);
++ pr_warn("md: unit number in %pg is bad: %d\n",
++ rdev0->bdev, rdev0->preferred_minor);
+ break;
+ }
+
+@@ -6528,8 +6512,8 @@ static void autorun_devices(int part)
+ pr_warn("md: %s locked, cannot run\n", mdname(mddev));
+ else if (mddev->raid_disks || mddev->major_version
+ || !list_empty(&mddev->disks)) {
+- pr_warn("md: %s already running, cannot run %s\n",
+- mdname(mddev), bdevname(rdev0->bdev,b));
++ pr_warn("md: %s already running, cannot run %pg\n",
++ mdname(mddev), rdev0->bdev);
+ mddev_unlock(mddev);
+ } else {
+ pr_debug("md: created %s\n", mdname(mddev));
+@@ -6703,7 +6687,6 @@ static int get_disk_info(struct mddev *mddev, void __user * arg)
+
+ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info)
+ {
+- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE];
+ struct md_rdev *rdev;
+ dev_t dev = MKDEV(info->major,info->minor);
+
+@@ -6733,9 +6716,9 @@ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info)
+ err = super_types[mddev->major_version]
+ .load_super(rdev, rdev0, mddev->minor_version);
+ if (err < 0) {
+- pr_warn("md: %s has different UUID to %s\n",
+- bdevname(rdev->bdev,b),
+- bdevname(rdev0->bdev,b2));
++ pr_warn("md: %pg has different UUID to %pg\n",
++ rdev->bdev,
++ rdev0->bdev);
+ export_rdev(rdev);
+ return -EINVAL;
+ }
+@@ -6910,7 +6893,6 @@ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info)
+
+ static int hot_remove_disk(struct mddev *mddev, dev_t dev)
+ {
+- char b[BDEVNAME_SIZE];
+ struct md_rdev *rdev;
+
+ if (!mddev->pers)
+@@ -6945,14 +6927,13 @@ static int hot_remove_disk(struct mddev *mddev, dev_t dev)
+
+ return 0;
+ busy:
+- pr_debug("md: cannot remove active disk %s from %s ...\n",
+- bdevname(rdev->bdev,b), mdname(mddev));
++ pr_debug("md: cannot remove active disk %pg from %s ...\n",
++ rdev->bdev, mdname(mddev));
+ return -EBUSY;
+ }
+
+ static int hot_add_disk(struct mddev *mddev, dev_t dev)
+ {
+- char b[BDEVNAME_SIZE];
+ int err;
+ struct md_rdev *rdev;
+
+@@ -6985,8 +6966,8 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev)
+ rdev->sectors = rdev->sb_start;
+
+ if (test_bit(Faulty, &rdev->flags)) {
+- pr_warn("md: can not hot-add faulty %s disk to %s!\n",
+- bdevname(rdev->bdev,b), mdname(mddev));
++ pr_warn("md: can not hot-add faulty %pg disk to %s!\n",
++ rdev->bdev, mdname(mddev));
+ err = -EINVAL;
+ goto abort_export;
+ }
+@@ -7013,8 +6994,8 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev)
+ * disable on the whole MD.
+ */
+ if (!blk_queue_nowait(bdev_get_queue(rdev->bdev))) {
+- pr_info("%s: Disabling nowait because %s does not support nowait\n",
+- mdname(mddev), bdevname(rdev->bdev, b));
++ pr_info("%s: Disabling nowait because %pg does not support nowait\n",
++ mdname(mddev), rdev->bdev);
+ blk_queue_flag_clear(QUEUE_FLAG_NOWAIT, mddev->queue);
+ }
+ /*
+@@ -8016,10 +7997,8 @@ static void status_unused(struct seq_file *seq)
+ seq_printf(seq, "unused devices: ");
+
+ list_for_each_entry(rdev, &pending_raid_disks, same_set) {
+- char b[BDEVNAME_SIZE];
+ i++;
+- seq_printf(seq, "%s ",
+- bdevname(rdev->bdev,b));
++ seq_printf(seq, "%pg ", rdev->bdev);
+ }
+ if (!i)
+ seq_printf(seq, "<none>");
+@@ -8259,9 +8238,8 @@ static int md_seq_show(struct seq_file *seq, void *v)
+ sectors = 0;
+ rcu_read_lock();
+ rdev_for_each_rcu(rdev, mddev) {
+- char b[BDEVNAME_SIZE];
+- seq_printf(seq, " %s[%d]",
+- bdevname(rdev->bdev,b), rdev->desc_nr);
++ seq_printf(seq, " %pg[%d]", rdev->bdev, rdev->desc_nr);
++
+ if (test_bit(WriteMostly, &rdev->flags))
+ seq_printf(seq, "(W)");
+ if (test_bit(Journal, &rdev->flags))
+@@ -9656,7 +9634,6 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+ struct mdp_superblock_1 *sb = page_address(rdev->sb_page);
+ struct md_rdev *rdev2, *tmp;
+ int role, ret;
+- char b[BDEVNAME_SIZE];
+
+ /*
+ * If size is changed in another node then we need to
+@@ -9680,7 +9657,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+
+ if (test_bit(Candidate, &rdev2->flags)) {
+ if (role == MD_DISK_ROLE_FAULTY) {
+- pr_info("md: Removing Candidate device %s because add failed\n", bdevname(rdev2->bdev,b));
++ pr_info("md: Removing Candidate device %pg because add failed\n",
++ rdev2->bdev);
+ md_kick_rdev_from_array(rdev2);
+ continue;
+ }
+@@ -9697,8 +9675,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+ MD_FEATURE_RESHAPE_ACTIVE)) {
+ rdev2->saved_raid_disk = role;
+ ret = remove_and_add_spares(mddev, rdev2);
+- pr_info("Activated spare: %s\n",
+- bdevname(rdev2->bdev,b));
++ pr_info("Activated spare: %pg\n",
++ rdev2->bdev);
+ /* wakeup mddev->thread here, so array could
+ * perform resync with the new activated disk */
+ set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
+diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c
+index 8495045eb989..a7fa2c2e7748 100644
+--- a/drivers/md/raid0.c
++++ b/drivers/md/raid0.c
+@@ -37,7 +37,6 @@ static void dump_zones(struct mddev *mddev)
+ int j, k;
+ sector_t zone_size = 0;
+ sector_t zone_start = 0;
+- char b[BDEVNAME_SIZE];
+ struct r0conf *conf = mddev->private;
+ int raid_disks = conf->strip_zone[0].nb_dev;
+ pr_debug("md: RAID0 configuration for %s - %d zone%s\n",
+@@ -48,9 +47,8 @@ static void dump_zones(struct mddev *mddev)
+ int len = 0;
+
+ for (k = 0; k < conf->strip_zone[j].nb_dev; k++)
+- len += snprintf(line+len, 200-len, "%s%s", k?"/":"",
+- bdevname(conf->devlist[j*raid_disks
+- + k]->bdev, b));
++ len += snprintf(line+len, 200-len, "%s%pg", k?"/":"",
++ conf->devlist[j * raid_disks + k]->bdev);
+ pr_debug("md: zone%d=[%s]\n", j, line);
+
+ zone_size = conf->strip_zone[j].zone_end - zone_start;
+@@ -69,8 +67,6 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf)
+ struct md_rdev *smallest, *rdev1, *rdev2, *rdev, **dev;
+ struct strip_zone *zone;
+ int cnt;
+- char b[BDEVNAME_SIZE];
+- char b2[BDEVNAME_SIZE];
+ struct r0conf *conf = kzalloc(sizeof(*conf), GFP_KERNEL);
+ unsigned blksize = 512;
+
+@@ -78,9 +74,9 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf)
+ if (!conf)
+ return -ENOMEM;
+ rdev_for_each(rdev1, mddev) {
+- pr_debug("md/raid0:%s: looking at %s\n",
++ pr_debug("md/raid0:%s: looking at %pg\n",
+ mdname(mddev),
+- bdevname(rdev1->bdev, b));
++ rdev1->bdev);
+ c = 0;
+
+ /* round size to chunk_size */
+@@ -92,12 +88,12 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf)
+ rdev1->bdev->bd_disk->queue));
+
+ rdev_for_each(rdev2, mddev) {
+- pr_debug("md/raid0:%s: comparing %s(%llu)"
+- " with %s(%llu)\n",
++ pr_debug("md/raid0:%s: comparing %pg(%llu)"
++ " with %pg(%llu)\n",
+ mdname(mddev),
+- bdevname(rdev1->bdev,b),
++ rdev1->bdev,
+ (unsigned long long)rdev1->sectors,
+- bdevname(rdev2->bdev,b2),
++ rdev2->bdev,
+ (unsigned long long)rdev2->sectors);
+ if (rdev2 == rdev1) {
+ pr_debug("md/raid0:%s: END\n",
+@@ -225,15 +221,15 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf)
+ for (j=0; j<cnt; j++) {
+ rdev = conf->devlist[j];
+ if (rdev->sectors <= zone->dev_start) {
+- pr_debug("md/raid0:%s: checking %s ... nope\n",
++ pr_debug("md/raid0:%s: checking %pg ... nope\n",
+ mdname(mddev),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ continue;
+ }
+- pr_debug("md/raid0:%s: checking %s ..."
++ pr_debug("md/raid0:%s: checking %pg ..."
+ " contained as device %d\n",
+ mdname(mddev),
+- bdevname(rdev->bdev, b), c);
++ rdev->bdev, c);
+ dev[c] = rdev;
+ c++;
+ if (!smallest || rdev->sectors < smallest->sectors) {
+diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
+index 9fa479493642..eb6b4e7bcfa5 100644
+--- a/drivers/md/raid1.c
++++ b/drivers/md/raid1.c
+@@ -398,10 +398,9 @@ static void raid1_end_read_request(struct bio *bio)
+ /*
+ * oops, read error:
+ */
+- char b[BDEVNAME_SIZE];
+- pr_err_ratelimited("md/raid1:%s: %s: rescheduling sector %llu\n",
++ pr_err_ratelimited("md/raid1:%s: %pg: rescheduling sector %llu\n",
+ mdname(conf->mddev),
+- bdevname(rdev->bdev, b),
++ rdev->bdev,
+ (unsigned long long)r1_bio->sector);
+ set_bit(R1BIO_ReadError, &r1_bio->state);
+ reschedule_retry(r1_bio);
+@@ -1264,10 +1263,10 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio,
+ mirror = conf->mirrors + rdisk;
+
+ if (r1bio_existed)
+- pr_info_ratelimited("md/raid1:%s: redirecting sector %llu to other mirror: %s\n",
++ pr_info_ratelimited("md/raid1:%s: redirecting sector %llu to other mirror: %pg\n",
+ mdname(mddev),
+ (unsigned long long)r1_bio->sector,
+- bdevname(mirror->rdev->bdev, b));
++ mirror->rdev->bdev);
+
+ if (test_bit(WriteMostly, &mirror->rdev->flags) &&
+ bitmap) {
+@@ -1619,7 +1618,6 @@ static void raid1_status(struct seq_file *seq, struct mddev *mddev)
+
+ static void raid1_error(struct mddev *mddev, struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+ struct r1conf *conf = mddev->private;
+ unsigned long flags;
+
+@@ -1653,9 +1651,9 @@ static void raid1_error(struct mddev *mddev, struct md_rdev *rdev)
+ set_bit(MD_RECOVERY_INTR, &mddev->recovery);
+ set_mask_bits(&mddev->sb_flags, 0,
+ BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING));
+- pr_crit("md/raid1:%s: Disk failure on %s, disabling device.\n"
++ pr_crit("md/raid1:%s: Disk failure on %pg, disabling device.\n"
+ "md/raid1:%s: Operation continuing on %d devices.\n",
+- mdname(mddev), bdevname(rdev->bdev, b),
++ mdname(mddev), rdev->bdev,
+ mdname(mddev), conf->raid_disks - mddev->degraded);
+ }
+
+@@ -1673,13 +1671,12 @@ static void print_conf(struct r1conf *conf)
+
+ rcu_read_lock();
+ for (i = 0; i < conf->raid_disks; i++) {
+- char b[BDEVNAME_SIZE];
+ struct md_rdev *rdev = rcu_dereference(conf->mirrors[i].rdev);
+ if (rdev)
+- pr_debug(" disk %d, wo:%d, o:%d, dev:%s\n",
++ pr_debug(" disk %d, wo:%d, o:%d, dev:%pg\n",
+ i, !test_bit(In_sync, &rdev->flags),
+ !test_bit(Faulty, &rdev->flags),
+- bdevname(rdev->bdev,b));
++ rdev->bdev);
+ }
+ rcu_read_unlock();
+ }
+@@ -2318,7 +2315,6 @@ static void fix_read_error(struct r1conf *conf, int read_disk,
+ }
+ d = start;
+ while (d != read_disk) {
+- char b[BDEVNAME_SIZE];
+ if (d==0)
+ d = conf->raid_disks * 2;
+ d--;
+@@ -2331,11 +2327,11 @@ static void fix_read_error(struct r1conf *conf, int read_disk,
+ if (r1_sync_page_io(rdev, sect, s,
+ conf->tmppage, READ)) {
+ atomic_add(s, &rdev->corrected_errors);
+- pr_info("md/raid1:%s: read error corrected (%d sectors at %llu on %s)\n",
++ pr_info("md/raid1:%s: read error corrected (%d sectors at %llu on %pg)\n",
+ mdname(mddev), s,
+ (unsigned long long)(sect +
+ rdev->data_offset),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ }
+ rdev_dec_pending(rdev, mddev);
+ } else
+diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
+index c4c1a3a7d7ab..27fc8dfbd24e 100644
+--- a/drivers/md/raid10.c
++++ b/drivers/md/raid10.c
+@@ -390,10 +390,9 @@ static void raid10_end_read_request(struct bio *bio)
+ /*
+ * oops, read error - keep the refcount on the rdev
+ */
+- char b[BDEVNAME_SIZE];
+- pr_err_ratelimited("md/raid10:%s: %s: rescheduling sector %llu\n",
++ pr_err_ratelimited("md/raid10:%s: %pg: rescheduling sector %llu\n",
+ mdname(conf->mddev),
+- bdevname(rdev->bdev, b),
++ rdev->bdev,
+ (unsigned long long)r10_bio->sector);
+ set_bit(R10BIO_ReadError, &r10_bio->state);
+ reschedule_retry(r10_bio);
+@@ -1169,9 +1168,9 @@ static void raid10_read_request(struct mddev *mddev, struct bio *bio,
+ return;
+ }
+ if (err_rdev)
+- pr_err_ratelimited("md/raid10:%s: %s: redirecting sector %llu to another mirror\n",
++ pr_err_ratelimited("md/raid10:%s: %pg: redirecting sector %llu to another mirror\n",
+ mdname(mddev),
+- bdevname(rdev->bdev, b),
++ rdev->bdev,
+ (unsigned long long)r10_bio->sector);
+ if (max_sectors < bio_sectors(bio)) {
+ struct bio *split = bio_split(bio, max_sectors,
+@@ -1947,7 +1946,6 @@ static int enough(struct r10conf *conf, int ignore)
+
+ static void raid10_error(struct mddev *mddev, struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+ struct r10conf *conf = mddev->private;
+ unsigned long flags;
+
+@@ -1977,9 +1975,9 @@ static void raid10_error(struct mddev *mddev, struct md_rdev *rdev)
+ set_mask_bits(&mddev->sb_flags, 0,
+ BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING));
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+- pr_crit("md/raid10:%s: Disk failure on %s, disabling device.\n"
++ pr_crit("md/raid10:%s: Disk failure on %pg, disabling device.\n"
+ "md/raid10:%s: Operation continuing on %d devices.\n",
+- mdname(mddev), bdevname(rdev->bdev, b),
++ mdname(mddev), rdev->bdev,
+ mdname(mddev), conf->geo.raid_disks - mddev->degraded);
+ }
+
+@@ -1999,13 +1997,12 @@ static void print_conf(struct r10conf *conf)
+ /* This is only called with ->reconfix_mutex held, so
+ * rcu protection of rdev is not needed */
+ for (i = 0; i < conf->geo.raid_disks; i++) {
+- char b[BDEVNAME_SIZE];
+ rdev = conf->mirrors[i].rdev;
+ if (rdev)
+- pr_debug(" disk %d, wo:%d, o:%d, dev:%s\n",
++ pr_debug(" disk %d, wo:%d, o:%d, dev:%pg\n",
+ i, !test_bit(In_sync, &rdev->flags),
+ !test_bit(Faulty, &rdev->flags),
+- bdevname(rdev->bdev,b));
++ rdev->bdev);
+ }
+ }
+
+@@ -2665,14 +2662,11 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10
+ check_decay_read_errors(mddev, rdev);
+ atomic_inc(&rdev->read_errors);
+ if (atomic_read(&rdev->read_errors) > max_read_errors) {
+- char b[BDEVNAME_SIZE];
+- bdevname(rdev->bdev, b);
+-
+- pr_notice("md/raid10:%s: %s: Raid device exceeded read_error threshold [cur %d:max %d]\n",
+- mdname(mddev), b,
++ pr_notice("md/raid10:%s: %pg: Raid device exceeded read_error threshold [cur %d:max %d]\n",
++ mdname(mddev), rdev->bdev,
+ atomic_read(&rdev->read_errors), max_read_errors);
+- pr_notice("md/raid10:%s: %s: Failing raid device\n",
+- mdname(mddev), b);
++ pr_notice("md/raid10:%s: %pg: Failing raid device\n",
++ mdname(mddev), rdev->bdev);
+ md_error(mddev, rdev);
+ r10_bio->devs[r10_bio->read_slot].bio = IO_BLOCKED;
+ return;
+@@ -2742,8 +2736,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10
+ /* write it back and re-read */
+ rcu_read_lock();
+ while (sl != r10_bio->read_slot) {
+- char b[BDEVNAME_SIZE];
+-
+ if (sl==0)
+ sl = conf->copies;
+ sl--;
+@@ -2762,24 +2754,22 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10
+ s, conf->tmppage, WRITE)
+ == 0) {
+ /* Well, this device is dead */
+- pr_notice("md/raid10:%s: read correction write failed (%d sectors at %llu on %s)\n",
++ pr_notice("md/raid10:%s: read correction write failed (%d sectors at %llu on %pg)\n",
+ mdname(mddev), s,
+ (unsigned long long)(
+ sect +
+ choose_data_offset(r10_bio,
+ rdev)),
+- bdevname(rdev->bdev, b));
+- pr_notice("md/raid10:%s: %s: failing drive\n",
++ rdev->bdev);
++ pr_notice("md/raid10:%s: %pg: failing drive\n",
+ mdname(mddev),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ }
+ rdev_dec_pending(rdev, mddev);
+ rcu_read_lock();
+ }
+ sl = start;
+ while (sl != r10_bio->read_slot) {
+- char b[BDEVNAME_SIZE];
+-
+ if (sl==0)
+ sl = conf->copies;
+ sl--;
+@@ -2799,23 +2789,23 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10
+ READ)) {
+ case 0:
+ /* Well, this device is dead */
+- pr_notice("md/raid10:%s: unable to read back corrected sectors (%d sectors at %llu on %s)\n",
++ pr_notice("md/raid10:%s: unable to read back corrected sectors (%d sectors at %llu on %pg)\n",
+ mdname(mddev), s,
+ (unsigned long long)(
+ sect +
+ choose_data_offset(r10_bio, rdev)),
+- bdevname(rdev->bdev, b));
+- pr_notice("md/raid10:%s: %s: failing drive\n",
++ rdev->bdev);
++ pr_notice("md/raid10:%s: %pg: failing drive\n",
+ mdname(mddev),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ break;
+ case 1:
+- pr_info("md/raid10:%s: read error corrected (%d sectors at %llu on %s)\n",
++ pr_info("md/raid10:%s: read error corrected (%d sectors at %llu on %pg)\n",
+ mdname(mddev), s,
+ (unsigned long long)(
+ sect +
+ choose_data_offset(r10_bio, rdev)),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ atomic_add(s, &rdev->corrected_errors);
+ }
+
+diff --git a/drivers/md/raid5-cache.c b/drivers/md/raid5-cache.c
+index 0b5dcaabbc15..0323eb8fa949 100644
+--- a/drivers/md/raid5-cache.c
++++ b/drivers/md/raid5-cache.c
+@@ -3067,11 +3067,10 @@ int r5l_init_log(struct r5conf *conf, struct md_rdev *rdev)
+ {
+ struct request_queue *q = bdev_get_queue(rdev->bdev);
+ struct r5l_log *log;
+- char b[BDEVNAME_SIZE];
+ int ret;
+
+- pr_debug("md/raid:%s: using device %s as journal\n",
+- mdname(conf->mddev), bdevname(rdev->bdev, b));
++ pr_debug("md/raid:%s: using device %pg as journal\n",
++ mdname(conf->mddev), rdev->bdev);
+
+ if (PAGE_SIZE != 4096)
+ return -EINVAL;
+diff --git a/drivers/md/raid5-ppl.c b/drivers/md/raid5-ppl.c
+index 3ddc2aa0b530..fc42e28205d8 100644
+--- a/drivers/md/raid5-ppl.c
++++ b/drivers/md/raid5-ppl.c
+@@ -807,7 +807,6 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e,
+ int data_disks;
+ int i;
+ int ret = 0;
+- char b[BDEVNAME_SIZE];
+ unsigned int pp_size = le32_to_cpu(e->pp_size);
+ unsigned int data_size = le32_to_cpu(e->data_size);
+
+@@ -901,8 +900,8 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e,
+ break;
+ }
+
+- pr_debug("%s:%*s reading data member disk %s sector %llu\n",
+- __func__, indent, "", bdevname(rdev->bdev, b),
++ pr_debug("%s:%*s reading data member disk %pg sector %llu\n",
++ __func__, indent, "", rdev->bdev,
+ (unsigned long long)sector);
+ if (!sync_page_io(rdev, sector, block_size, page2,
+ REQ_OP_READ, 0, false)) {
+@@ -946,10 +945,10 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e,
+ parity_rdev = conf->disks[sh.pd_idx].rdev;
+
+ BUG_ON(parity_rdev->bdev->bd_dev != log->rdev->bdev->bd_dev);
+- pr_debug("%s:%*s write parity at sector %llu, disk %s\n",
++ pr_debug("%s:%*s write parity at sector %llu, disk %pg\n",
+ __func__, indent, "",
+ (unsigned long long)parity_sector,
+- bdevname(parity_rdev->bdev, b));
++ parity_rdev->bdev);
+ if (!sync_page_io(parity_rdev, parity_sector, block_size,
+ page1, REQ_OP_WRITE, 0, false)) {
+ pr_debug("%s:%*s parity write error!\n", __func__,
+@@ -1261,7 +1260,6 @@ void ppl_exit_log(struct r5conf *conf)
+
+ static int ppl_validate_rdev(struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+ int ppl_data_sectors;
+ int ppl_size_new;
+
+@@ -1278,8 +1276,8 @@ static int ppl_validate_rdev(struct md_rdev *rdev)
+ RAID5_STRIPE_SECTORS((struct r5conf *)rdev->mddev->private));
+
+ if (ppl_data_sectors <= 0) {
+- pr_warn("md/raid:%s: PPL space too small on %s\n",
+- mdname(rdev->mddev), bdevname(rdev->bdev, b));
++ pr_warn("md/raid:%s: PPL space too small on %pg\n",
++ mdname(rdev->mddev), rdev->bdev);
+ return -ENOSPC;
+ }
+
+@@ -1289,16 +1287,16 @@ static int ppl_validate_rdev(struct md_rdev *rdev)
+ rdev->ppl.sector + ppl_size_new > rdev->data_offset) ||
+ (rdev->ppl.sector >= rdev->data_offset &&
+ rdev->data_offset + rdev->sectors > rdev->ppl.sector)) {
+- pr_warn("md/raid:%s: PPL space overlaps with data on %s\n",
+- mdname(rdev->mddev), bdevname(rdev->bdev, b));
++ pr_warn("md/raid:%s: PPL space overlaps with data on %pg\n",
++ mdname(rdev->mddev), rdev->bdev);
+ return -EINVAL;
+ }
+
+ if (!rdev->mddev->external &&
+ ((rdev->ppl.offset > 0 && rdev->ppl.offset < (rdev->sb_size >> 9)) ||
+ (rdev->ppl.offset <= 0 && rdev->ppl.offset + ppl_size_new > 0))) {
+- pr_warn("md/raid:%s: PPL space overlaps with superblock on %s\n",
+- mdname(rdev->mddev), bdevname(rdev->bdev, b));
++ pr_warn("md/raid:%s: PPL space overlaps with superblock on %pg\n",
++ mdname(rdev->mddev), rdev->bdev);
+ return -EINVAL;
+ }
+
+@@ -1468,14 +1466,13 @@ int ppl_modify_log(struct r5conf *conf, struct md_rdev *rdev, bool add)
+ struct ppl_conf *ppl_conf = conf->log_private;
+ struct ppl_log *log;
+ int ret = 0;
+- char b[BDEVNAME_SIZE];
+
+ if (!rdev)
+ return -EINVAL;
+
+- pr_debug("%s: disk: %d operation: %s dev: %s\n",
++ pr_debug("%s: disk: %d operation: %s dev: %pg\n",
+ __func__, rdev->raid_disk, add ? "add" : "remove",
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+
+ if (rdev->raid_disk < 0)
+ return 0;
+diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
+index 01c326dc57d5..1b2f6e62507d 100644
+--- a/drivers/md/raid5.c
++++ b/drivers/md/raid5.c
+@@ -2665,7 +2665,6 @@ static void raid5_end_read_request(struct bio * bi)
+ struct stripe_head *sh = bi->bi_private;
+ struct r5conf *conf = sh->raid_conf;
+ int disks = sh->disks, i;
+- char b[BDEVNAME_SIZE];
+ struct md_rdev *rdev = NULL;
+ sector_t s;
+
+@@ -2703,10 +2702,10 @@ static void raid5_end_read_request(struct bio * bi)
+ * any error
+ */
+ pr_info_ratelimited(
+- "md/raid:%s: read error corrected (%lu sectors at %llu on %s)\n",
++ "md/raid:%s: read error corrected (%lu sectors at %llu on %pg)\n",
+ mdname(conf->mddev), RAID5_STRIPE_SECTORS(conf),
+ (unsigned long long)s,
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ atomic_add(RAID5_STRIPE_SECTORS(conf), &rdev->corrected_errors);
+ clear_bit(R5_ReadError, &sh->dev[i].flags);
+ clear_bit(R5_ReWrite, &sh->dev[i].flags);
+@@ -2723,7 +2722,6 @@ static void raid5_end_read_request(struct bio * bi)
+ if (atomic_read(&rdev->read_errors))
+ atomic_set(&rdev->read_errors, 0);
+ } else {
+- const char *bdn = bdevname(rdev->bdev, b);
+ int retry = 0;
+ int set_bad = 0;
+
+@@ -2732,25 +2730,25 @@ static void raid5_end_read_request(struct bio * bi)
+ atomic_inc(&rdev->read_errors);
+ if (test_bit(R5_ReadRepl, &sh->dev[i].flags))
+ pr_warn_ratelimited(
+- "md/raid:%s: read error on replacement device (sector %llu on %s).\n",
++ "md/raid:%s: read error on replacement device (sector %llu on %pg).\n",
+ mdname(conf->mddev),
+ (unsigned long long)s,
+- bdn);
++ rdev->bdev);
+ else if (conf->mddev->degraded >= conf->max_degraded) {
+ set_bad = 1;
+ pr_warn_ratelimited(
+- "md/raid:%s: read error not correctable (sector %llu on %s).\n",
++ "md/raid:%s: read error not correctable (sector %llu on %pg).\n",
+ mdname(conf->mddev),
+ (unsigned long long)s,
+- bdn);
++ rdev->bdev);
+ } else if (test_bit(R5_ReWrite, &sh->dev[i].flags)) {
+ /* Oh, no!!! */
+ set_bad = 1;
+ pr_warn_ratelimited(
+- "md/raid:%s: read error NOT corrected!! (sector %llu on %s).\n",
++ "md/raid:%s: read error NOT corrected!! (sector %llu on %pg).\n",
+ mdname(conf->mddev),
+ (unsigned long long)s,
+- bdn);
++ rdev->bdev);
+ } else if (atomic_read(&rdev->read_errors)
+ > conf->max_nr_stripes) {
+ if (!test_bit(Faulty, &rdev->flags)) {
+@@ -2758,8 +2756,8 @@ static void raid5_end_read_request(struct bio * bi)
+ mdname(conf->mddev),
+ atomic_read(&rdev->read_errors),
+ conf->max_nr_stripes);
+- pr_warn("md/raid:%s: Too many read errors, failing device %s.\n",
+- mdname(conf->mddev), bdn);
++ pr_warn("md/raid:%s: Too many read errors, failing device %pg.\n",
++ mdname(conf->mddev), rdev->bdev);
+ }
+ } else
+ retry = 1;
+@@ -2872,13 +2870,12 @@ static void raid5_end_write_request(struct bio *bi)
+
+ static void raid5_error(struct mddev *mddev, struct md_rdev *rdev)
+ {
+- char b[BDEVNAME_SIZE];
+ struct r5conf *conf = mddev->private;
+ unsigned long flags;
+ pr_debug("raid456: error called\n");
+
+- pr_crit("md/raid:%s: Disk failure on %s, disabling device.\n",
+- mdname(mddev), bdevname(rdev->bdev, b));
++ pr_crit("md/raid:%s: Disk failure on %pg, disabling device.\n",
++ mdname(mddev), rdev->bdev);
+
+ spin_lock_irqsave(&conf->device_lock, flags);
+ set_bit(Faulty, &rdev->flags);
+@@ -7321,9 +7318,8 @@ static struct r5conf *setup_conf(struct mddev *mddev)
+ }
+
+ if (test_bit(In_sync, &rdev->flags)) {
+- char b[BDEVNAME_SIZE];
+- pr_info("md/raid:%s: device %s operational as raid disk %d\n",
+- mdname(mddev), bdevname(rdev->bdev, b), raid_disk);
++ pr_info("md/raid:%s: device %pg operational as raid disk %d\n",
++ mdname(mddev), rdev->bdev, raid_disk);
+ } else if (rdev->saved_raid_disk != raid_disk)
+ /* Cannot rely on bitmap to complete recovery */
+ conf->fullsync = 1;
+@@ -7846,12 +7842,11 @@ static void print_raid5_conf (struct r5conf *conf)
+
+ rcu_read_lock();
+ for (i = 0; i < conf->raid_disks; i++) {
+- char b[BDEVNAME_SIZE];
+ rdev = rcu_dereference(conf->disks[i].rdev);
+ if (rdev)
+- pr_debug(" disk %d, o:%d, dev:%s\n",
++ pr_debug(" disk %d, o:%d, dev:%pg\n",
+ i, !test_bit(Faulty, &rdev->flags),
+- bdevname(rdev->bdev, b));
++ rdev->bdev);
+ }
+ rcu_read_unlock();
+ }
+--
+2.35.1
+
--- /dev/null
+From f3f3969728bbf0a32ac0666d91dcf7a01db28f50 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Apr 2022 13:45:58 -0600
+Subject: md: Replace role magic numbers with defined constants
+
+From: David Sloan <david.sloan@eideticom.com>
+
+[ Upstream commit 9151ad5d8676a89cf1b6a4051037ab3ca077d938 ]
+
+There are several instances where magic numbers are used in md.c instead
+of the defined constants in md_p.h. This patch set improves code
+readability by replacing all occurrences of 0xffff, 0xfffe, and 0xfffd when
+relating to md roles with their equivalent defined constant.
+
+Signed-off-by: David Sloan <david.sloan@eideticom.com>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Signed-off-by: Song Liu <song@kernel.org>
+Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/md.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/md/md.c b/drivers/md/md.c
+index ea21a9ddf15f..79b685fb8207 100644
+--- a/drivers/md/md.c
++++ b/drivers/md/md.c
+@@ -2654,11 +2654,11 @@ static bool does_sb_need_changing(struct mddev *mddev)
+ rdev_for_each(rdev, mddev) {
+ role = le16_to_cpu(sb->dev_roles[rdev->desc_nr]);
+ /* Device activated? */
+- if (role == 0xffff && rdev->raid_disk >=0 &&
++ if (role == MD_DISK_ROLE_SPARE && rdev->raid_disk >= 0 &&
+ !test_bit(Faulty, &rdev->flags))
+ return true;
+ /* Device turned faulty? */
+- if (test_bit(Faulty, &rdev->flags) && (role < 0xfffd))
++ if (test_bit(Faulty, &rdev->flags) && (role < MD_DISK_ROLE_MAX))
+ return true;
+ }
+
+@@ -9679,7 +9679,7 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+ role = le16_to_cpu(sb->dev_roles[rdev2->desc_nr]);
+
+ if (test_bit(Candidate, &rdev2->flags)) {
+- if (role == 0xfffe) {
++ if (role == MD_DISK_ROLE_FAULTY) {
+ pr_info("md: Removing Candidate device %s because add failed\n", bdevname(rdev2->bdev,b));
+ md_kick_rdev_from_array(rdev2);
+ continue;
+@@ -9692,7 +9692,7 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+ /*
+ * got activated except reshape is happening.
+ */
+- if (rdev2->raid_disk == -1 && role != 0xffff &&
++ if (rdev2->raid_disk == -1 && role != MD_DISK_ROLE_SPARE &&
+ !(le32_to_cpu(sb->feature_map) &
+ MD_FEATURE_RESHAPE_ACTIVE)) {
+ rdev2->saved_raid_disk = role;
+@@ -9709,7 +9709,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
+ * as faulty. The recovery is performed by the
+ * one who initiated the error.
+ */
+- if ((role == 0xfffe) || (role == 0xfffd)) {
++ if (role == MD_DISK_ROLE_FAULTY ||
++ role == MD_DISK_ROLE_JOURNAL) {
+ md_error(mddev, rdev2);
+ clear_bit(Blocked, &rdev2->flags);
+ }
+--
+2.35.1
+
--- /dev/null
+From 712be03fb6d4cfae8b85c8bbc383e6465a2362b1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Aug 2022 11:51:04 -0700
+Subject: md: Replace snprintf with scnprintf
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Saurabh Sengar <ssengar@linux.microsoft.com>
+
+[ Upstream commit 1727fd5015d8f93474148f94e34cda5aa6ad4a43 ]
+
+Current code produces a warning as shown below when total characters
+in the constituent block device names plus the slashes exceeds 200.
+snprintf() returns the number of characters generated from the given
+input, which could cause the expression “200 – len” to wrap around
+to a large positive number. Fix this by using scnprintf() instead,
+which returns the actual number of characters written into the buffer.
+
+[ 1513.267938] ------------[ cut here ]------------
+[ 1513.267943] WARNING: CPU: 15 PID: 37247 at <snip>/lib/vsprintf.c:2509 vsnprintf+0x2c8/0x510
+[ 1513.267944] Modules linked in: <snip>
+[ 1513.267969] CPU: 15 PID: 37247 Comm: mdadm Not tainted 5.4.0-1085-azure #90~18.04.1-Ubuntu
+[ 1513.267969] Hardware name: Microsoft Corporation Virtual Machine/Virtual Machine, BIOS Hyper-V UEFI Release v4.1 05/09/2022
+[ 1513.267971] RIP: 0010:vsnprintf+0x2c8/0x510
+<-snip->
+[ 1513.267982] Call Trace:
+[ 1513.267986] snprintf+0x45/0x70
+[ 1513.267990] ? disk_name+0x71/0xa0
+[ 1513.267993] dump_zones+0x114/0x240 [raid0]
+[ 1513.267996] ? _cond_resched+0x19/0x40
+[ 1513.267998] raid0_run+0x19e/0x270 [raid0]
+[ 1513.268000] md_run+0x5e0/0xc50
+[ 1513.268003] ? security_capable+0x3f/0x60
+[ 1513.268005] do_md_run+0x19/0x110
+[ 1513.268006] md_ioctl+0x195e/0x1f90
+[ 1513.268007] blkdev_ioctl+0x91f/0x9f0
+[ 1513.268010] block_ioctl+0x3d/0x50
+[ 1513.268012] do_vfs_ioctl+0xa9/0x640
+[ 1513.268014] ? __fput+0x162/0x260
+[ 1513.268016] ksys_ioctl+0x75/0x80
+[ 1513.268017] __x64_sys_ioctl+0x1a/0x20
+[ 1513.268019] do_syscall_64+0x5e/0x200
+[ 1513.268021] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+
+Fixes: 766038846e875 ("md/raid0: replace printk() with pr_*()")
+Reviewed-by: Michael Kelley <mikelley@microsoft.com>
+Acked-by: Guoqing Jiang <guoqing.jiang@linux.dev>
+Signed-off-by: Saurabh Sengar <ssengar@linux.microsoft.com>
+Signed-off-by: Song Liu <song@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c
+index a7fa2c2e7748..81a34051fb17 100644
+--- a/drivers/md/raid0.c
++++ b/drivers/md/raid0.c
+@@ -47,7 +47,7 @@ static void dump_zones(struct mddev *mddev)
+ int len = 0;
+
+ for (k = 0; k < conf->strip_zone[j].nb_dev; k++)
+- len += snprintf(line+len, 200-len, "%s%pg", k?"/":"",
++ len += scnprintf(line+len, 200-len, "%s%pg", k?"/":"",
+ conf->devlist[j * raid_disks + k]->bdev);
+ pr_debug("md: zone%d=[%s]\n", j, line);
+
+--
+2.35.1
+
--- /dev/null
+From 4af166a02028cf3e2c114ce4973c7e9dcd8b6faa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Jul 2022 04:23:38 +0200
+Subject: media: cx88: Fix a null-ptr-deref bug in buffer_prepare()
+
+From: Zheyu Ma <zheyuma97@gmail.com>
+
+[ Upstream commit 2b064d91440b33fba5b452f2d1b31f13ae911d71 ]
+
+When the driver calls cx88_risc_buffer() to prepare the buffer, the
+function call may fail, resulting in a empty buffer and null-ptr-deref
+later in buffer_queue().
+
+The following log can reveal it:
+
+[ 41.822762] general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN PTI
+[ 41.824488] KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007]
+[ 41.828027] RIP: 0010:buffer_queue+0xc2/0x500
+[ 41.836311] Call Trace:
+[ 41.836945] __enqueue_in_driver+0x141/0x360
+[ 41.837262] vb2_start_streaming+0x62/0x4a0
+[ 41.838216] vb2_core_streamon+0x1da/0x2c0
+[ 41.838516] __vb2_init_fileio+0x981/0xbc0
+[ 41.839141] __vb2_perform_fileio+0xbf9/0x1120
+[ 41.840072] vb2_fop_read+0x20e/0x400
+[ 41.840346] v4l2_read+0x215/0x290
+[ 41.840603] vfs_read+0x162/0x4c0
+
+Fix this by checking the return value of cx88_risc_buffer()
+
+[hverkuil: fix coding style issues]
+
+Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/pci/cx88/cx88-vbi.c | 9 +++---
+ drivers/media/pci/cx88/cx88-video.c | 43 +++++++++++++++--------------
+ 2 files changed, 26 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/pci/cx88/cx88-vbi.c b/drivers/media/pci/cx88/cx88-vbi.c
+index a075788c64d4..469aeaa725ad 100644
+--- a/drivers/media/pci/cx88/cx88-vbi.c
++++ b/drivers/media/pci/cx88/cx88-vbi.c
+@@ -144,11 +144,10 @@ static int buffer_prepare(struct vb2_buffer *vb)
+ return -EINVAL;
+ vb2_set_plane_payload(vb, 0, size);
+
+- cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl,
+- 0, VBI_LINE_LENGTH * lines,
+- VBI_LINE_LENGTH, 0,
+- lines);
+- return 0;
++ return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl,
++ 0, VBI_LINE_LENGTH * lines,
++ VBI_LINE_LENGTH, 0,
++ lines);
+ }
+
+ static void buffer_finish(struct vb2_buffer *vb)
+diff --git a/drivers/media/pci/cx88/cx88-video.c b/drivers/media/pci/cx88/cx88-video.c
+index c17ad9f7d822..99c55109c1e0 100644
+--- a/drivers/media/pci/cx88/cx88-video.c
++++ b/drivers/media/pci/cx88/cx88-video.c
+@@ -431,6 +431,7 @@ static int queue_setup(struct vb2_queue *q,
+
+ static int buffer_prepare(struct vb2_buffer *vb)
+ {
++ int ret;
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
+ struct cx88_core *core = dev->core;
+@@ -445,35 +446,35 @@ static int buffer_prepare(struct vb2_buffer *vb)
+
+ switch (core->field) {
+ case V4L2_FIELD_TOP:
+- cx88_risc_buffer(dev->pci, &buf->risc,
+- sgt->sgl, 0, UNSET,
+- buf->bpl, 0, core->height);
++ ret = cx88_risc_buffer(dev->pci, &buf->risc,
++ sgt->sgl, 0, UNSET,
++ buf->bpl, 0, core->height);
+ break;
+ case V4L2_FIELD_BOTTOM:
+- cx88_risc_buffer(dev->pci, &buf->risc,
+- sgt->sgl, UNSET, 0,
+- buf->bpl, 0, core->height);
++ ret = cx88_risc_buffer(dev->pci, &buf->risc,
++ sgt->sgl, UNSET, 0,
++ buf->bpl, 0, core->height);
+ break;
+ case V4L2_FIELD_SEQ_TB:
+- cx88_risc_buffer(dev->pci, &buf->risc,
+- sgt->sgl,
+- 0, buf->bpl * (core->height >> 1),
+- buf->bpl, 0,
+- core->height >> 1);
++ ret = cx88_risc_buffer(dev->pci, &buf->risc,
++ sgt->sgl,
++ 0, buf->bpl * (core->height >> 1),
++ buf->bpl, 0,
++ core->height >> 1);
+ break;
+ case V4L2_FIELD_SEQ_BT:
+- cx88_risc_buffer(dev->pci, &buf->risc,
+- sgt->sgl,
+- buf->bpl * (core->height >> 1), 0,
+- buf->bpl, 0,
+- core->height >> 1);
++ ret = cx88_risc_buffer(dev->pci, &buf->risc,
++ sgt->sgl,
++ buf->bpl * (core->height >> 1), 0,
++ buf->bpl, 0,
++ core->height >> 1);
+ break;
+ case V4L2_FIELD_INTERLACED:
+ default:
+- cx88_risc_buffer(dev->pci, &buf->risc,
+- sgt->sgl, 0, buf->bpl,
+- buf->bpl, buf->bpl,
+- core->height >> 1);
++ ret = cx88_risc_buffer(dev->pci, &buf->risc,
++ sgt->sgl, 0, buf->bpl,
++ buf->bpl, buf->bpl,
++ core->height >> 1);
+ break;
+ }
+ dprintk(2,
+@@ -481,7 +482,7 @@ static int buffer_prepare(struct vb2_buffer *vb)
+ buf, buf->vb.vb2_buf.index, __func__,
+ core->width, core->height, dev->fmt->depth, dev->fmt->fourcc,
+ (unsigned long)buf->risc.dma);
+- return 0;
++ return ret;
+ }
+
+ static void buffer_finish(struct vb2_buffer *vb)
+--
+2.35.1
+
--- /dev/null
+From 08b221e19cfb0ccc7b07006c1927776732faea09 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 20 Jul 2022 16:30:03 +0200
+Subject: media: exynos4-is: fimc-is: Add of_node_put() when breaking out of
+ loop
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 211f8304fa21aaedc2c247f0c9d6c7f1aaa61ad7 ]
+
+In fimc_is_register_subdevs(), we need to call of_node_put() for
+the reference 'i2c_bus' when breaking out of the
+for_each_compatible_node() which has increased the refcount.
+
+Fixes: 9a761e436843 ("[media] exynos4-is: Add Exynos4x12 FIMC-IS driver")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/platform/exynos4-is/fimc-is.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c
+index e3072d69c49f..a7704ff069d6 100644
+--- a/drivers/media/platform/exynos4-is/fimc-is.c
++++ b/drivers/media/platform/exynos4-is/fimc-is.c
+@@ -213,6 +213,7 @@ static int fimc_is_register_subdevs(struct fimc_is *is)
+
+ if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
+ of_node_put(child);
++ of_node_put(i2c_bus);
+ return ret;
+ }
+ index++;
+--
+2.35.1
+
--- /dev/null
+From 6eec54c3ed342a9726da2d9ee5706e5372330342 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 18 Aug 2022 08:57:53 +0200
+Subject: media: meson: vdec: add missing clk_disable_unprepare on error in
+ vdec_hevc_start()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Xu Qiang <xuqiang36@huawei.com>
+
+[ Upstream commit 4029372233e13e281f8c387f279f9f064ced3810 ]
+
+Add the missing clk_disable_unprepare() before return
+from vdec_hevc_start() in the error handling case.
+
+Fixes: 823a7300340e (“media: meson: vdec: add common HEVC decoder support”)
+Signed-off-by: Xu Qiang <xuqiang36@huawei.com>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/staging/media/meson/vdec/vdec_hevc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/meson/vdec/vdec_hevc.c b/drivers/staging/media/meson/vdec/vdec_hevc.c
+index 9530e580e57a..afced435c907 100644
+--- a/drivers/staging/media/meson/vdec/vdec_hevc.c
++++ b/drivers/staging/media/meson/vdec/vdec_hevc.c
+@@ -167,8 +167,12 @@ static int vdec_hevc_start(struct amvdec_session *sess)
+
+ clk_set_rate(core->vdec_hevc_clk, 666666666);
+ ret = clk_prepare_enable(core->vdec_hevc_clk);
+- if (ret)
++ if (ret) {
++ if (core->platform->revision == VDEC_REVISION_G12A ||
++ core->platform->revision == VDEC_REVISION_SM1)
++ clk_disable_unprepare(core->vdec_hevcf_clk);
+ return ret;
++ }
+
+ if (core->platform->revision == VDEC_REVISION_SM1)
+ regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
+--
+2.35.1
+
--- /dev/null
+From 9b009baa3f30ff8daf5136c8dac3a7972e60e205 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 10:58:19 +0200
+Subject: media: platform: fix some double free in meson-ge2d and mtk-jpeg and
+ s5p-mfc
+
+From: Hangyu Hua <hbh25y@gmail.com>
+
+[ Upstream commit c65c3f3a2cbf21ed429d9b9c725bdb5dc6abf4cf ]
+
+video_unregister_device will release device internally. There is no need to
+call video_device_release after video_unregister_device.
+
+Signed-off-by: Hangyu Hua <hbh25y@gmail.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/platform/meson/ge2d/ge2d.c | 1 -
+ drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c | 1 -
+ drivers/media/platform/s5p-mfc/s5p_mfc.c | 3 +--
+ 3 files changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/meson/ge2d/ge2d.c b/drivers/media/platform/meson/ge2d/ge2d.c
+index a373dea9866b..a885cbc99e38 100644
+--- a/drivers/media/platform/meson/ge2d/ge2d.c
++++ b/drivers/media/platform/meson/ge2d/ge2d.c
+@@ -1032,7 +1032,6 @@ static int ge2d_remove(struct platform_device *pdev)
+
+ video_unregister_device(ge2d->vfd);
+ v4l2_m2m_release(ge2d->m2m_dev);
+- video_device_release(ge2d->vfd);
+ v4l2_device_unregister(&ge2d->v4l2_dev);
+ clk_disable_unprepare(ge2d->clk);
+
+diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+index a89c7b206eef..470f8f167744 100644
+--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
++++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+@@ -1457,7 +1457,6 @@ static int mtk_jpeg_remove(struct platform_device *pdev)
+
+ pm_runtime_disable(&pdev->dev);
+ video_unregister_device(jpeg->vdev);
+- video_device_release(jpeg->vdev);
+ v4l2_m2m_release(jpeg->m2m_dev);
+ v4l2_device_unregister(&jpeg->v4l2_dev);
+ mtk_jpeg_clk_release(jpeg);
+diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
+index f336a9543273..4fc135d9f38b 100644
+--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
++++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
+@@ -1406,6 +1406,7 @@ static int s5p_mfc_probe(struct platform_device *pdev)
+ /* Deinit MFC if probe had failed */
+ err_enc_reg:
+ video_unregister_device(dev->vfd_dec);
++ dev->vfd_dec = NULL;
+ err_dec_reg:
+ video_device_release(dev->vfd_enc);
+ err_enc_alloc:
+@@ -1451,8 +1452,6 @@ static int s5p_mfc_remove(struct platform_device *pdev)
+
+ video_unregister_device(dev->vfd_enc);
+ video_unregister_device(dev->vfd_dec);
+- video_device_release(dev->vfd_enc);
+- video_device_release(dev->vfd_dec);
+ v4l2_device_unregister(&dev->v4l2_dev);
+ s5p_mfc_unconfigure_dma_memory(dev);
+
+--
+2.35.1
+
--- /dev/null
+From 7c53bdcd01fcf761c8aec9242f3e1177ba1dcdf5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Jul 2022 18:12:36 +0800
+Subject: media: tm6000: Fix unused value in vidioc_try_fmt_vid_cap()
+
+From: Zeng Jingxiang <linuszeng@tencent.com>
+
+[ Upstream commit d682869daa23938b5e8919db45c4b5b227749712 ]
+
+Coverity warns of an unused value:
+
+assigned_value: Assign the value of the variable f->fmt.pix.field
+to field here, but that stored value is overwritten.
+before it can be used.
+919 field = f->fmt.pix.field;
+920
+
+value_overwrite: Overwriting previous write to field with
+the value of V4L2_FIELD_INTERLACED.
+921 field = V4L2_FIELD_INTERLACED;
+
+Fixes: ed57256f6fe8 ("[media] tm6000: fix G/TRY_FMT")
+Signed-off-by: Zeng Jingxiang <linuszeng@tencent.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/usb/tm6000/tm6000-video.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/media/usb/tm6000/tm6000-video.c b/drivers/media/usb/tm6000/tm6000-video.c
+index e293f6f3d1bc..f80734dc4902 100644
+--- a/drivers/media/usb/tm6000/tm6000-video.c
++++ b/drivers/media/usb/tm6000/tm6000-video.c
+@@ -916,8 +916,6 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+ return -EINVAL;
+ }
+
+- field = f->fmt.pix.field;
+-
+ field = V4L2_FIELD_INTERLACED;
+
+ tm6000_get_std_res(dev);
+--
+2.35.1
+
--- /dev/null
+From c932d38f8ea544afc83442667063682cc528ce29 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 8 Jan 2022 18:04:39 +0100
+Subject: media: uvcvideo: Fix memory leak in uvc_gpio_parse
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: José Expósito <jose.exposito89@gmail.com>
+
+[ Upstream commit f0f078457f18f10696888f8d0e6aba9deb9cde92 ]
+
+Previously the unit buffer was allocated before checking the IRQ for
+privacy GPIO. In case of error, the unit buffer was leaked.
+
+Allocate the unit buffer after the IRQ to avoid it.
+
+Addresses-Coverity-ID: 1474639 ("Resource leak")
+
+Fixes: 2886477ff987 ("media: uvcvideo: Implement UVC_EXT_GPIO_UNIT")
+Signed-off-by: José Expósito <jose.exposito89@gmail.com>
+Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/usb/uvc/uvc_driver.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c
+index 9a791d8ef200..72fff7264b54 100644
+--- a/drivers/media/usb/uvc/uvc_driver.c
++++ b/drivers/media/usb/uvc/uvc_driver.c
+@@ -1534,10 +1534,6 @@ static int uvc_gpio_parse(struct uvc_device *dev)
+ if (IS_ERR_OR_NULL(gpio_privacy))
+ return PTR_ERR_OR_ZERO(gpio_privacy);
+
+- unit = uvc_alloc_entity(UVC_EXT_GPIO_UNIT, UVC_EXT_GPIO_UNIT_ID, 0, 1);
+- if (!unit)
+- return -ENOMEM;
+-
+ irq = gpiod_to_irq(gpio_privacy);
+ if (irq < 0) {
+ if (irq != EPROBE_DEFER)
+@@ -1546,6 +1542,10 @@ static int uvc_gpio_parse(struct uvc_device *dev)
+ return irq;
+ }
+
++ unit = uvc_alloc_entity(UVC_EXT_GPIO_UNIT, UVC_EXT_GPIO_UNIT_ID, 0, 1);
++ if (!unit)
++ return -ENOMEM;
++
+ unit->gpio.gpio_privacy = gpio_privacy;
+ unit->gpio.irq = irq;
+ unit->gpio.bControlSize = 1;
+--
+2.35.1
+
--- /dev/null
+From 0ea9cf170b69819d1f1a05cd2ddbf4e957fcd355 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Jul 2022 10:53:31 +0200
+Subject: media: uvcvideo: Use entity get_cur in uvc_ctrl_set
+
+From: Yunke Cao <yunkec@google.com>
+
+[ Upstream commit 5f36851c36b30f713f588ed2b60aa7b4512e2c76 ]
+
+Entity controls should get_cur using an entity-defined function
+instead of via a query. Fix this in uvc_ctrl_set.
+
+Fixes: 65900c581d01 ("media: uvcvideo: Allow entity-defined get_info and get_cur")
+Signed-off-by: Yunke Cao <yunkec@google.com>
+Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/usb/uvc/uvc_ctrl.c | 83 ++++++++++++++++++--------------
+ 1 file changed, 46 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c
+index b3dde98499f4..5bb29fc49538 100644
+--- a/drivers/media/usb/uvc/uvc_ctrl.c
++++ b/drivers/media/usb/uvc/uvc_ctrl.c
+@@ -988,36 +988,56 @@ static s32 __uvc_ctrl_get_value(struct uvc_control_mapping *mapping,
+ return value;
+ }
+
+-static int __uvc_ctrl_get(struct uvc_video_chain *chain,
+- struct uvc_control *ctrl, struct uvc_control_mapping *mapping,
+- s32 *value)
++static int __uvc_ctrl_load_cur(struct uvc_video_chain *chain,
++ struct uvc_control *ctrl)
+ {
++ u8 *data;
+ int ret;
+
+- if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0)
+- return -EACCES;
++ if (ctrl->loaded)
++ return 0;
+
+- if (!ctrl->loaded) {
+- if (ctrl->entity->get_cur) {
+- ret = ctrl->entity->get_cur(chain->dev,
+- ctrl->entity,
+- ctrl->info.selector,
+- uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
+- ctrl->info.size);
+- } else {
+- ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR,
+- ctrl->entity->id,
+- chain->dev->intfnum,
+- ctrl->info.selector,
+- uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
+- ctrl->info.size);
+- }
+- if (ret < 0)
+- return ret;
++ data = uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT);
+
++ if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0) {
++ memset(data, 0, ctrl->info.size);
+ ctrl->loaded = 1;
++
++ return 0;
+ }
+
++ if (ctrl->entity->get_cur)
++ ret = ctrl->entity->get_cur(chain->dev, ctrl->entity,
++ ctrl->info.selector, data,
++ ctrl->info.size);
++ else
++ ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR,
++ ctrl->entity->id, chain->dev->intfnum,
++ ctrl->info.selector, data,
++ ctrl->info.size);
++
++ if (ret < 0)
++ return ret;
++
++ ctrl->loaded = 1;
++
++ return ret;
++}
++
++static int __uvc_ctrl_get(struct uvc_video_chain *chain,
++ struct uvc_control *ctrl,
++ struct uvc_control_mapping *mapping,
++ s32 *value)
++{
++ int ret;
++
++ if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0)
++ return -EACCES;
++
++ ret = __uvc_ctrl_load_cur(chain, ctrl);
++ if (ret < 0)
++ return ret;
++
+ *value = __uvc_ctrl_get_value(mapping,
+ uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT));
+
+@@ -1667,21 +1687,10 @@ int uvc_ctrl_set(struct uvc_fh *handle,
+ * needs to be loaded from the device to perform the read-modify-write
+ * operation.
+ */
+- if (!ctrl->loaded && (ctrl->info.size * 8) != mapping->size) {
+- if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0) {
+- memset(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
+- 0, ctrl->info.size);
+- } else {
+- ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR,
+- ctrl->entity->id, chain->dev->intfnum,
+- ctrl->info.selector,
+- uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
+- ctrl->info.size);
+- if (ret < 0)
+- return ret;
+- }
+-
+- ctrl->loaded = 1;
++ if ((ctrl->info.size * 8) != mapping->size) {
++ ret = __uvc_ctrl_load_cur(chain, ctrl);
++ if (ret < 0)
++ return ret;
+ }
+
+ /* Backup the current value in case we need to rollback later. */
+--
+2.35.1
+
--- /dev/null
+From ace84817f2c2c26a618b45d8726bf94a4939f2c5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 1 Jun 2022 06:25:14 +0200
+Subject: media: xilinx: vipp: Fix refcount leak in xvip_graph_dma_init
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 1c78f19c3a0ea312a8178a6bfd8934eb93e9b10a ]
+
+of_get_child_by_name() returns a node pointer with refcount
+incremented, we should use of_node_put() on it when not need anymore.
+Add missing of_node_put() to avoid refcount leak.
+
+Fixes: df3305156f98 ("[media] v4l: xilinx: Add Xilinx Video IP core")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/platform/xilinx/xilinx-vipp.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c b/drivers/media/platform/xilinx/xilinx-vipp.c
+index 2ce31d7ce1a6..5896a662da3b 100644
+--- a/drivers/media/platform/xilinx/xilinx-vipp.c
++++ b/drivers/media/platform/xilinx/xilinx-vipp.c
+@@ -472,7 +472,7 @@ static int xvip_graph_dma_init(struct xvip_composite_device *xdev)
+ {
+ struct device_node *ports;
+ struct device_node *port;
+- int ret;
++ int ret = 0;
+
+ ports = of_get_child_by_name(xdev->dev->of_node, "ports");
+ if (ports == NULL) {
+@@ -482,13 +482,14 @@ static int xvip_graph_dma_init(struct xvip_composite_device *xdev)
+
+ for_each_child_of_node(ports, port) {
+ ret = xvip_graph_dma_init_one(xdev, port);
+- if (ret < 0) {
++ if (ret) {
+ of_node_put(port);
+- return ret;
++ break;
+ }
+ }
+
+- return 0;
++ of_node_put(ports);
++ return ret;
+ }
+
+ static void xvip_graph_cleanup(struct xvip_composite_device *xdev)
+--
+2.35.1
+
--- /dev/null
+From fb51955f332d4a38cbda5756754bc40766f73435 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 19 Jul 2022 16:56:39 +0800
+Subject: memory: of: Fix refcount leak bug in of_get_ddr_timings()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 05215fb32010d4afb68fbdbb4d237df6e2d4567b ]
+
+We should add the of_node_put() when breaking out of
+for_each_child_of_node() as it will automatically increase
+and decrease the refcount.
+
+Fixes: e6b42eb6a66c ("memory: emif: add device tree support to emif driver")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220719085640.1210583-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/memory/of_memory.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
+index d9f5437d3bce..d0a80aefdea8 100644
+--- a/drivers/memory/of_memory.c
++++ b/drivers/memory/of_memory.c
+@@ -134,6 +134,7 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr,
+ for_each_child_of_node(np_ddr, np_tim) {
+ if (of_device_is_compatible(np_tim, tim_compat)) {
+ if (of_do_get_timings(np_tim, &timings[i])) {
++ of_node_put(np_tim);
+ devm_kfree(dev, timings);
+ goto default_timings;
+ }
+--
+2.35.1
+
--- /dev/null
+From bc66a75ba86d8a41901ed346fd5c855aeceb8913 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 19 Jul 2022 16:56:40 +0800
+Subject: memory: of: Fix refcount leak bug in of_lpddr3_get_ddr_timings()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 48af14fb0eaa63d9aa68f59fb0b205ec55a95636 ]
+
+We should add the of_node_put() when breaking out of
+for_each_child_of_node() as it will automatically increase
+and decrease the refcount.
+
+Fixes: 976897dd96db ("memory: Extend of_memory with LPDDR3 support")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220719085640.1210583-2-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/memory/of_memory.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
+index d0a80aefdea8..1791614f324b 100644
+--- a/drivers/memory/of_memory.c
++++ b/drivers/memory/of_memory.c
+@@ -283,6 +283,7 @@ const struct lpddr3_timings
+ if (of_device_is_compatible(np_tim, tim_compat)) {
+ if (of_lpddr3_do_get_timings(np_tim, &timings[i])) {
+ devm_kfree(dev, timings);
++ of_node_put(np_tim);
+ goto default_timings;
+ }
+ i++;
+--
+2.35.1
+
--- /dev/null
+From 7e3c0c5182ac7d6f3bb58f7c927ab0f279457813 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 16 Jul 2022 11:13:24 +0800
+Subject: memory: pl353-smc: Fix refcount leak bug in pl353_smc_probe()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 61b3c876c1cbdb1efd1f52a1f348580e6e14efb6 ]
+
+The break of for_each_available_child_of_node() needs a
+corresponding of_node_put() when the reference 'child' is not
+used anymore. Here we do not need to call of_node_put() in
+fail path as '!match' means no break.
+
+While the of_platform_device_create() will created a new
+reference by 'child' but it has considered the refcounting.
+
+Fixes: fee10bd22678 ("memory: pl353: Add driver for arm pl353 static memory controller")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220716031324.447680-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/memory/pl353-smc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
+index f84b98278745..d39ee7d06665 100644
+--- a/drivers/memory/pl353-smc.c
++++ b/drivers/memory/pl353-smc.c
+@@ -122,6 +122,7 @@ static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
+ }
+
+ of_platform_device_create(child, NULL, &adev->dev);
++ of_node_put(child);
+
+ return 0;
+
+--
+2.35.1
+
--- /dev/null
+From f8b88f47280d66334234afb0e1683e229a938d5a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 31 Jul 2022 14:06:23 +0200
+Subject: mfd: fsl-imx25: Fix an error handling path in mx25_tsadc_setup_irq()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 3fa9e4cfb55da512ebfd57336fde468830719298 ]
+
+If devm_of_platform_populate() fails, some resources need to be
+released.
+
+Introduce a mx25_tsadc_unset_irq() function that undoes
+mx25_tsadc_setup_irq() and call it both from the new error handling path
+of the probe and in the remove function.
+
+Fixes: a55196eff6d6 ("mfd: fsl-imx25: Use devm_of_platform_populate()")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/d404e04828fc06bcfddf81f9f3e9b4babbe35415.1659269156.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/fsl-imx25-tsadc.c | 32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c
+index 37e5e02a1d05..85f7982d26d2 100644
+--- a/drivers/mfd/fsl-imx25-tsadc.c
++++ b/drivers/mfd/fsl-imx25-tsadc.c
+@@ -84,6 +84,19 @@ static int mx25_tsadc_setup_irq(struct platform_device *pdev,
+ return 0;
+ }
+
++static int mx25_tsadc_unset_irq(struct platform_device *pdev)
++{
++ struct mx25_tsadc *tsadc = platform_get_drvdata(pdev);
++ int irq = platform_get_irq(pdev, 0);
++
++ if (irq) {
++ irq_set_chained_handler_and_data(irq, NULL, NULL);
++ irq_domain_remove(tsadc->domain);
++ }
++
++ return 0;
++}
++
+ static void mx25_tsadc_setup_clk(struct platform_device *pdev,
+ struct mx25_tsadc *tsadc)
+ {
+@@ -171,18 +184,21 @@ static int mx25_tsadc_probe(struct platform_device *pdev)
+
+ platform_set_drvdata(pdev, tsadc);
+
+- return devm_of_platform_populate(dev);
++ ret = devm_of_platform_populate(dev);
++ if (ret)
++ goto err_irq;
++
++ return 0;
++
++err_irq:
++ mx25_tsadc_unset_irq(pdev);
++
++ return ret;
+ }
+
+ static int mx25_tsadc_remove(struct platform_device *pdev)
+ {
+- struct mx25_tsadc *tsadc = platform_get_drvdata(pdev);
+- int irq = platform_get_irq(pdev, 0);
+-
+- if (irq) {
+- irq_set_chained_handler_and_data(irq, NULL, NULL);
+- irq_domain_remove(tsadc->domain);
+- }
++ mx25_tsadc_unset_irq(pdev);
+
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From 2273603a92b212956376db113404fa7169cf9bd4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Aug 2022 13:53:05 +0300
+Subject: mfd: fsl-imx25: Fix check for platform_get_irq() errors
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 75db7907355ca5e2ff606e9dd3e86b6c3a455fe2 ]
+
+The mx25_tsadc_remove() function assumes all non-zero returns are success
+but the platform_get_irq() function returns negative on error and
+positive non-zero values on success. It never returns zero, but if it
+did then treat that as a success.
+
+Fixes: 18f773937968 ("mfd: fsl-imx25: Clean up irq settings during removal")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Martin Kaiser <martin@kaiser.cx>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/YvTfkbVQWYKMKS/t@kili
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/fsl-imx25-tsadc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c
+index 85f7982d26d2..823595bcc9b7 100644
+--- a/drivers/mfd/fsl-imx25-tsadc.c
++++ b/drivers/mfd/fsl-imx25-tsadc.c
+@@ -69,7 +69,7 @@ static int mx25_tsadc_setup_irq(struct platform_device *pdev,
+ int irq;
+
+ irq = platform_get_irq(pdev, 0);
+- if (irq <= 0)
++ if (irq < 0)
+ return irq;
+
+ tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,
+@@ -89,7 +89,7 @@ static int mx25_tsadc_unset_irq(struct platform_device *pdev)
+ struct mx25_tsadc *tsadc = platform_get_drvdata(pdev);
+ int irq = platform_get_irq(pdev, 0);
+
+- if (irq) {
++ if (irq >= 0) {
+ irq_set_chained_handler_and_data(irq, NULL, NULL);
+ irq_domain_remove(tsadc->domain);
+ }
+--
+2.35.1
+
--- /dev/null
+From d92279030634dac8ed90ad89387025f4881655a1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Aug 2022 14:42:02 +0300
+Subject: mfd: intel_soc_pmic: Fix an error handling path in
+ intel_soc_pmic_i2c_probe()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 48749cabba109397b4e7dd556e85718ec0ec114d ]
+
+The commit in Fixes: has added a pwm_add_table() call in the probe() and
+a pwm_remove_table() call in the remove(), but forget to update the error
+handling path of the probe.
+
+Add the missing pwm_remove_table() call.
+
+Fixes: a3aa9a93df9f ("mfd: intel_soc_pmic_core: ADD PWM lookup table for CRC PMIC based PWM")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20220801114211.36267-1-andriy.shevchenko@linux.intel.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/intel_soc_pmic_core.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
+index ddd64f9e3341..926653e1f603 100644
+--- a/drivers/mfd/intel_soc_pmic_core.c
++++ b/drivers/mfd/intel_soc_pmic_core.c
+@@ -95,6 +95,7 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
+ return 0;
+
+ err_del_irq_chip:
++ pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
+ regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
+ return ret;
+ }
+--
+2.35.1
+
--- /dev/null
+From 063013bb5c1d0b642ca7944b070cd7d0cbc645be Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 31 Jul 2022 11:55:38 +0200
+Subject: mfd: lp8788: Fix an error handling path in lp8788_irq_init() and
+ lp8788_irq_init()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 557244f6284f30613f2d61f14b579303165876c3 ]
+
+In lp8788_irq_init(), if an error occurs after a successful
+irq_domain_add_linear() call, it must be undone by a corresponding
+irq_domain_remove() call.
+
+irq_domain_remove() should also be called in lp8788_irq_exit() for the same
+reason.
+
+Fixes: eea6b7cc53aa ("mfd: Add lp8788 mfd driver")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/bcd5a72c9c1c383dd6324680116426e32737655a.1659261275.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/lp8788-irq.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/mfd/lp8788-irq.c b/drivers/mfd/lp8788-irq.c
+index 348439a3fbbd..39006297f3d2 100644
+--- a/drivers/mfd/lp8788-irq.c
++++ b/drivers/mfd/lp8788-irq.c
+@@ -175,6 +175,7 @@ int lp8788_irq_init(struct lp8788 *lp, int irq)
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ "lp8788-irq", irqd);
+ if (ret) {
++ irq_domain_remove(lp->irqdm);
+ dev_err(lp->dev, "failed to create a thread for IRQ_N\n");
+ return ret;
+ }
+@@ -188,4 +189,6 @@ void lp8788_irq_exit(struct lp8788 *lp)
+ {
+ if (lp->irq)
+ free_irq(lp->irq, lp->irqdm);
++ if (lp->irqdm)
++ irq_domain_remove(lp->irqdm);
+ }
+--
+2.35.1
+
--- /dev/null
+From dcd218d477f043dc824e731bc08a83d19aee5c5f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 31 Jul 2022 11:55:27 +0200
+Subject: mfd: lp8788: Fix an error handling path in lp8788_probe()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit becfdcd75126b20b8ec10066c5e85b34f8994ad5 ]
+
+Should an error occurs in mfd_add_devices(), some resources need to be
+released, as already done in the .remove() function.
+
+Add an error handling path and a lp8788_irq_exit() call to undo a previous
+lp8788_irq_init().
+
+Fixes: eea6b7cc53aa ("mfd: Add lp8788 mfd driver")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/18398722da9df9490722d853e4797350189ae79b.1659261275.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/lp8788.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/lp8788.c b/drivers/mfd/lp8788.c
+index c223d2c6a363..998e8cc408a0 100644
+--- a/drivers/mfd/lp8788.c
++++ b/drivers/mfd/lp8788.c
+@@ -195,8 +195,16 @@ static int lp8788_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+ if (ret)
+ return ret;
+
+- return mfd_add_devices(lp->dev, -1, lp8788_devs,
+- ARRAY_SIZE(lp8788_devs), NULL, 0, NULL);
++ ret = mfd_add_devices(lp->dev, -1, lp8788_devs,
++ ARRAY_SIZE(lp8788_devs), NULL, 0, NULL);
++ if (ret)
++ goto err_exit_irq;
++
++ return 0;
++
++err_exit_irq:
++ lp8788_irq_exit(lp);
++ return ret;
+ }
+
+ static int lp8788_remove(struct i2c_client *cl)
+--
+2.35.1
+
--- /dev/null
+From 8b7adbd79ec0577d3e8c621864c403758c3239ea Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 17:11:12 +0800
+Subject: mfd: sm501: Add check for platform_driver_register()
+
+From: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+
+[ Upstream commit 8325a6c24ad78b8c1acc3c42b098ee24105d68e5 ]
+
+As platform_driver_register() can return error numbers,
+it should be better to check platform_driver_register()
+and deal with the exception.
+
+Fixes: b6d6454fdb66 ("[PATCH] mfd: SM501 core driver")
+Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20220913091112.1739138-1-jiasheng@iscas.ac.cn
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mfd/sm501.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
+index bc0a2c38653e..3ac4508a6742 100644
+--- a/drivers/mfd/sm501.c
++++ b/drivers/mfd/sm501.c
+@@ -1720,7 +1720,12 @@ static struct platform_driver sm501_plat_driver = {
+
+ static int __init sm501_base_init(void)
+ {
+- platform_driver_register(&sm501_plat_driver);
++ int ret;
++
++ ret = platform_driver_register(&sm501_plat_driver);
++ if (ret < 0)
++ return ret;
++
+ return pci_register_driver(&sm501_pci_driver);
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 9e2877d16b6f319f4041e1d8b7005c9b73cb79f4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 22 Aug 2022 16:39:32 -0500
+Subject: micrel: ksz8851: fixes struct pointer issue
+
+From: Jerry Ray <jerry.ray@microchip.com>
+
+[ Upstream commit fef5de753ff01887cfa50990532c3890fccb9338 ]
+
+Issue found during code review. This bug has no impact as long as the
+ks8851_net structure is the first element of the ks8851_net_spi structure.
+As long as the offset to the ks8851_net struct is zero, the container_of()
+macro is subtracting 0 and therefore no damage done. But if the
+ks8851_net_spi struct is ever modified such that the ks8851_net struct
+within it is no longer the first element of the struct, then the bug would
+manifest itself and cause problems.
+
+struct ks8851_net is contained within ks8851_net_spi.
+ks is contained within kss.
+kss is the priv_data of the netdev structure.
+
+Signed-off-by: Jerry Ray <jerry.ray@microchip.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/micrel/ks8851_spi.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/micrel/ks8851_spi.c b/drivers/net/ethernet/micrel/ks8851_spi.c
+index 479406ecbaa3..13c76352ae8d 100644
+--- a/drivers/net/ethernet/micrel/ks8851_spi.c
++++ b/drivers/net/ethernet/micrel/ks8851_spi.c
+@@ -413,7 +413,8 @@ static int ks8851_probe_spi(struct spi_device *spi)
+
+ spi->bits_per_word = 8;
+
+- ks = netdev_priv(netdev);
++ kss = netdev_priv(netdev);
++ ks = &kss->ks8851;
+
+ ks->lock = ks8851_lock_spi;
+ ks->unlock = ks8851_unlock_spi;
+@@ -433,8 +434,6 @@ static int ks8851_probe_spi(struct spi_device *spi)
+ IRQ_RXPSI) /* RX process stop */
+ ks->rc_ier = STD_IRQ;
+
+- kss = to_ks8851_spi(ks);
+-
+ kss->spidev = spi;
+ mutex_init(&kss->lock);
+ INIT_WORK(&kss->tx_work, ks8851_tx_work);
+--
+2.35.1
+
--- /dev/null
+From 591ea84c4c08a0a9d387876363104cbdd472d93a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 16:05:56 -0700
+Subject: MIPS: BCM47XX: Cast memcmp() of function to (void *)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Kees Cook <keescook@chromium.org>
+
+[ Upstream commit 0dedcf6e3301836eb70cfa649052e7ce4fcd13ba ]
+
+Clang is especially sensitive about argument type matching when using
+__overloaded functions (like memcmp(), etc). Help it see that function
+pointers are just "void *". Avoids this error:
+
+arch/mips/bcm47xx/prom.c:89:8: error: no matching function for call to 'memcmp'
+ if (!memcmp(prom_init, prom_init + mem, 32))
+ ^~~~~~
+include/linux/string.h:156:12: note: candidate function not viable: no known conversion from 'void (void)' to 'const void *' for 1st argument extern int memcmp(const void *,const void *,__kernel_size_t);
+
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: "Rafał Miłecki" <zajec5@gmail.com>
+Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Cc: linux-mips@vger.kernel.org
+Cc: Nathan Chancellor <nathan@kernel.org>
+Cc: Nick Desaulniers <ndesaulniers@google.com>
+Cc: llvm@lists.linux.dev
+Reported-by: kernel test robot <lkp@intel.com>
+Link: https://lore.kernel.org/lkml/202209080652.sz2d68e5-lkp@intel.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/bcm47xx/prom.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
+index 0a63721d0fbf..5a33d6b48d77 100644
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -86,7 +86,7 @@ static __init void prom_init_mem(void)
+ pr_debug("Assume 128MB RAM\n");
+ break;
+ }
+- if (!memcmp(prom_init, prom_init + mem, 32))
++ if (!memcmp((void *)prom_init, (void *)prom_init + mem, 32))
+ break;
+ }
+ lowmem = mem;
+@@ -159,7 +159,7 @@ void __init bcm47xx_prom_highmem_init(void)
+
+ off = EXTVBASE + __pa(off);
+ for (extmem = 128 << 20; extmem < 512 << 20; extmem <<= 1) {
+- if (!memcmp(prom_init, (void *)(off + extmem), 16))
++ if (!memcmp((void *)prom_init, (void *)(off + extmem), 16))
+ break;
+ }
+ extmem -= lowmem;
+--
+2.35.1
+
--- /dev/null
+From c54faefbdb88bc05912a72a49c5e064389f5078c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 11:29:17 +0800
+Subject: MIPS: SGI-IP27: Fix platform-device leak in bridge_platform_create()
+
+From: Lin Yujun <linyujun809@huawei.com>
+
+[ Upstream commit 11bec9cba4de06b3c0e9e4041453c2caaa1cbec1 ]
+
+In error case in bridge_platform_create after calling
+platform_device_add()/platform_device_add_data()/
+platform_device_add_resources(), release the failed
+'pdev' or it will be leak, call platform_device_put()
+to fix this problem.
+
+Besides, 'pdev' is divided into 'pdev_wd' and 'pdev_bd',
+use platform_device_unregister() to release sgi_w1
+resources when xtalk-bridge registration fails.
+
+Fixes: 5dc76a96e95a ("MIPS: PCI: use information from 1-wire PROM for IOC3 detection")
+Signed-off-by: Lin Yujun <linyujun809@huawei.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/sgi-ip27/ip27-xtalk.c | 70 +++++++++++++++++++++++----------
+ 1 file changed, 50 insertions(+), 20 deletions(-)
+
+diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
+index e762886d1dda..5143d1cf8984 100644
+--- a/arch/mips/sgi-ip27/ip27-xtalk.c
++++ b/arch/mips/sgi-ip27/ip27-xtalk.c
+@@ -27,15 +27,18 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+ {
+ struct xtalk_bridge_platform_data *bd;
+ struct sgi_w1_platform_data *wd;
+- struct platform_device *pdev;
++ struct platform_device *pdev_wd;
++ struct platform_device *pdev_bd;
+ struct resource w1_res;
+ unsigned long offset;
+
+ offset = NODE_OFFSET(nasid);
+
+ wd = kzalloc(sizeof(*wd), GFP_KERNEL);
+- if (!wd)
+- goto no_mem;
++ if (!wd) {
++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
++ return;
++ }
+
+ snprintf(wd->dev_id, sizeof(wd->dev_id), "bridge-%012lx",
+ offset + (widget << SWIN_SIZE_BITS));
+@@ -46,24 +49,35 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+ w1_res.end = w1_res.start + 3;
+ w1_res.flags = IORESOURCE_MEM;
+
+- pdev = platform_device_alloc("sgi_w1", PLATFORM_DEVID_AUTO);
+- if (!pdev) {
+- kfree(wd);
+- goto no_mem;
++ pdev_wd = platform_device_alloc("sgi_w1", PLATFORM_DEVID_AUTO);
++ if (!pdev_wd) {
++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
++ goto err_kfree_wd;
++ }
++ if (platform_device_add_resources(pdev_wd, &w1_res, 1)) {
++ pr_warn("xtalk:n%d/%x bridge failed to add platform resources.\n", nasid, widget);
++ goto err_put_pdev_wd;
++ }
++ if (platform_device_add_data(pdev_wd, wd, sizeof(*wd))) {
++ pr_warn("xtalk:n%d/%x bridge failed to add platform data.\n", nasid, widget);
++ goto err_put_pdev_wd;
++ }
++ if (platform_device_add(pdev_wd)) {
++ pr_warn("xtalk:n%d/%x bridge failed to add platform device.\n", nasid, widget);
++ goto err_put_pdev_wd;
+ }
+- platform_device_add_resources(pdev, &w1_res, 1);
+- platform_device_add_data(pdev, wd, sizeof(*wd));
+ /* platform_device_add_data() duplicates the data */
+ kfree(wd);
+- platform_device_add(pdev);
+
+ bd = kzalloc(sizeof(*bd), GFP_KERNEL);
+- if (!bd)
+- goto no_mem;
+- pdev = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO);
+- if (!pdev) {
+- kfree(bd);
+- goto no_mem;
++ if (!bd) {
++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
++ goto err_unregister_pdev_wd;
++ }
++ pdev_bd = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO);
++ if (!pdev_bd) {
++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
++ goto err_kfree_bd;
+ }
+
+
+@@ -84,15 +98,31 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+ bd->io.flags = IORESOURCE_IO;
+ bd->io_offset = offset;
+
+- platform_device_add_data(pdev, bd, sizeof(*bd));
++ if (platform_device_add_data(pdev_bd, bd, sizeof(*bd))) {
++ pr_warn("xtalk:n%d/%x bridge failed to add platform data.\n", nasid, widget);
++ goto err_put_pdev_bd;
++ }
++ if (platform_device_add(pdev_bd)) {
++ pr_warn("xtalk:n%d/%x bridge failed to add platform device.\n", nasid, widget);
++ goto err_put_pdev_bd;
++ }
+ /* platform_device_add_data() duplicates the data */
+ kfree(bd);
+- platform_device_add(pdev);
+ pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget);
+ return;
+
+-no_mem:
+- pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
++err_put_pdev_bd:
++ platform_device_put(pdev_bd);
++err_kfree_bd:
++ kfree(bd);
++err_unregister_pdev_wd:
++ platform_device_unregister(pdev_wd);
++ return;
++err_put_pdev_wd:
++ platform_device_put(pdev_wd);
++err_kfree_wd:
++ kfree(wd);
++ return;
+ }
+
+ static int probe_one_port(nasid_t nasid, int widget, int masterwid)
+--
+2.35.1
+
--- /dev/null
+From 0e71ab91e36a8ba59f3012fb385c5d1d484cbb36 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 23 Apr 2022 15:24:03 +0200
+Subject: MIPS: SGI-IP27: Free some unused memory
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 33d7085682b4aa212ebfadbc21da81dfefaaac16 ]
+
+platform_device_add_data() duplicates the memory it is passed. So we can
+free some memory to save a few bytes that would remain unused otherwise.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Stable-dep-of: 11bec9cba4de ("MIPS: SGI-IP27: Fix platform-device leak in bridge_platform_create()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/sgi-ip27/ip27-xtalk.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
+index 000ede156bdc..e762886d1dda 100644
+--- a/arch/mips/sgi-ip27/ip27-xtalk.c
++++ b/arch/mips/sgi-ip27/ip27-xtalk.c
+@@ -53,6 +53,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+ }
+ platform_device_add_resources(pdev, &w1_res, 1);
+ platform_device_add_data(pdev, wd, sizeof(*wd));
++ /* platform_device_add_data() duplicates the data */
++ kfree(wd);
+ platform_device_add(pdev);
+
+ bd = kzalloc(sizeof(*bd), GFP_KERNEL);
+@@ -83,6 +85,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+ bd->io_offset = offset;
+
+ platform_device_add_data(pdev, bd, sizeof(*bd));
++ /* platform_device_add_data() duplicates the data */
++ kfree(bd);
+ platform_device_add(pdev);
+ pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget);
+ return;
+--
+2.35.1
+
--- /dev/null
+From 1993ea2b257a21a46c583a5bf349e90e6125e926 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 16:26:00 +0800
+Subject: misc: ocxl: fix possible refcount leak in afu_ioctl()
+
+From: Hangyu Hua <hbh25y@gmail.com>
+
+[ Upstream commit c3b69ba5114c860d730870c03ab4ee45276e5e35 ]
+
+eventfd_ctx_put need to be called to put the refcount that gotten by
+eventfd_ctx_fdget when ocxl_irq_set_handler fails.
+
+Fixes: 060146614643 ("ocxl: move event_fd handling to frontend")
+Acked-by: Frederic Barrat <fbarrat@linux.ibm.com>
+Signed-off-by: Hangyu Hua <hbh25y@gmail.com>
+Link: https://lore.kernel.org/r/20220824082600.36159-1-hbh25y@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/misc/ocxl/file.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/misc/ocxl/file.c b/drivers/misc/ocxl/file.c
+index d278f8ba2c76..134806c2e67e 100644
+--- a/drivers/misc/ocxl/file.c
++++ b/drivers/misc/ocxl/file.c
+@@ -259,6 +259,8 @@ static long afu_ioctl(struct file *file, unsigned int cmd,
+ if (IS_ERR(ev_ctx))
+ return PTR_ERR(ev_ctx);
+ rc = ocxl_irq_set_handler(ctx, irq_id, irq_handler, irq_free, ev_ctx);
++ if (rc)
++ eventfd_ctx_put(ev_ctx);
+ break;
+
+ case OCXL_IOCTL_GET_METADATA:
+--
+2.35.1
+
--- /dev/null
+From 4c0d24e029eec6c170f04c49fe690ef4bb4e450c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 21:39:38 +0800
+Subject: mISDN: fix use-after-free bugs in l1oip timer handlers
+
+From: Duoming Zhou <duoming@zju.edu.cn>
+
+[ Upstream commit 2568a7e0832ee30b0a351016d03062ab4e0e0a3f ]
+
+The l1oip_cleanup() traverses the l1oip_ilist and calls
+release_card() to cleanup module and stack. However,
+release_card() calls del_timer() to delete the timers
+such as keep_tl and timeout_tl. If the timer handler is
+running, the del_timer() will not stop it and result in
+UAF bugs. One of the processes is shown below:
+
+ (cleanup routine) | (timer handler)
+release_card() | l1oip_timeout()
+ ... |
+ del_timer() | ...
+ ... |
+ kfree(hc) //FREE |
+ | hc->timeout_on = 0 //USE
+
+Fix by calling del_timer_sync() in release_card(), which
+makes sure the timer handlers have finished before the
+resources, such as l1oip and so on, have been deallocated.
+
+What's more, the hc->workq and hc->socket_thread can kick
+those timers right back in. We add a bool flag to show
+if card is released. Then, check this flag in hc->workq
+and hc->socket_thread.
+
+Fixes: 3712b42d4b1b ("Add layer1 over IP support")
+Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/isdn/mISDN/l1oip.h | 1 +
+ drivers/isdn/mISDN/l1oip_core.c | 13 +++++++------
+ 2 files changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/isdn/mISDN/l1oip.h b/drivers/isdn/mISDN/l1oip.h
+index 7ea10db20e3a..48133d022812 100644
+--- a/drivers/isdn/mISDN/l1oip.h
++++ b/drivers/isdn/mISDN/l1oip.h
+@@ -59,6 +59,7 @@ struct l1oip {
+ int bundle; /* bundle channels in one frm */
+ int codec; /* codec to use for transmis. */
+ int limit; /* limit number of bchannels */
++ bool shutdown; /* if card is released */
+
+ /* timer */
+ struct timer_list keep_tl;
+diff --git a/drivers/isdn/mISDN/l1oip_core.c b/drivers/isdn/mISDN/l1oip_core.c
+index 2c40412466e6..a77195e378b7 100644
+--- a/drivers/isdn/mISDN/l1oip_core.c
++++ b/drivers/isdn/mISDN/l1oip_core.c
+@@ -275,7 +275,7 @@ l1oip_socket_send(struct l1oip *hc, u8 localcodec, u8 channel, u32 chanmask,
+ p = frame;
+
+ /* restart timer */
+- if (time_before(hc->keep_tl.expires, jiffies + 5 * HZ))
++ if (time_before(hc->keep_tl.expires, jiffies + 5 * HZ) && !hc->shutdown)
+ mod_timer(&hc->keep_tl, jiffies + L1OIP_KEEPALIVE * HZ);
+ else
+ hc->keep_tl.expires = jiffies + L1OIP_KEEPALIVE * HZ;
+@@ -601,7 +601,9 @@ l1oip_socket_parse(struct l1oip *hc, struct sockaddr_in *sin, u8 *buf, int len)
+ goto multiframe;
+
+ /* restart timer */
+- if (time_before(hc->timeout_tl.expires, jiffies + 5 * HZ) || !hc->timeout_on) {
++ if ((time_before(hc->timeout_tl.expires, jiffies + 5 * HZ) ||
++ !hc->timeout_on) &&
++ !hc->shutdown) {
+ hc->timeout_on = 1;
+ mod_timer(&hc->timeout_tl, jiffies + L1OIP_TIMEOUT * HZ);
+ } else /* only adjust timer */
+@@ -1232,11 +1234,10 @@ release_card(struct l1oip *hc)
+ {
+ int ch;
+
+- if (timer_pending(&hc->keep_tl))
+- del_timer(&hc->keep_tl);
++ hc->shutdown = true;
+
+- if (timer_pending(&hc->timeout_tl))
+- del_timer(&hc->timeout_tl);
++ del_timer_sync(&hc->keep_tl);
++ del_timer_sync(&hc->timeout_tl);
+
+ cancel_work_sync(&hc->workq);
+
+--
+2.35.1
+
--- /dev/null
+From e9fcda63f5eb19d797e2d3ba351ae585a152b977 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 09:33:57 +0200
+Subject: mmc: au1xmmc: Fix an error handling path in au1xmmc_probe()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 5cbedf52608cc3cbc1c2a9a861fb671620427a20 ]
+
+If clk_prepare_enable() fails, there is no point in calling
+clk_disable_unprepare() in the error handling path.
+
+Move the out_clk label at the right place.
+
+Fixes: b6507596dfd6 ("MIPS: Alchemy: au1xmmc: use clk framework")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Link: https://lore.kernel.org/r/21d99886d07fa7fcbec74992657dabad98c935c4.1661412818.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/au1xmmc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
+index 0acc237843f7..f5f9cb7a2da5 100644
+--- a/drivers/mmc/host/au1xmmc.c
++++ b/drivers/mmc/host/au1xmmc.c
+@@ -1095,8 +1095,9 @@ static int au1xmmc_probe(struct platform_device *pdev)
+ if (host->platdata && host->platdata->cd_setup &&
+ !(mmc->caps & MMC_CAP_NEEDS_POLL))
+ host->platdata->cd_setup(mmc, 0);
+-out_clk:
++
+ clk_disable_unprepare(host->clk);
++out_clk:
+ clk_put(host->clk);
+ out_irq:
+ free_irq(host->irq, host);
+--
+2.35.1
+
--- /dev/null
+From bbdc35c6d1859dfcd2183ac3038ae826b411c655 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 21:43:22 -0400
+Subject: mmc: sdhci-msm: add compatible string check for sdm670
+
+From: Richard Acayan <mailingradian@gmail.com>
+
+[ Upstream commit 4de95950d970c71a9e82a24573bb7a44fd95baa1 ]
+
+The Snapdragon 670 has the same quirk as Snapdragon 845 (needing to
+restore the dll config). Add a compatible string check to detect the need
+for this.
+
+Signed-off-by: Richard Acayan <mailingradian@gmail.com>
+Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220923014322.33620-3-mailingradian@gmail.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-msm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
+index ff9f5b63c337..83d38e44fc25 100644
+--- a/drivers/mmc/host/sdhci-msm.c
++++ b/drivers/mmc/host/sdhci-msm.c
+@@ -2437,6 +2437,7 @@ static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
+ static const struct of_device_id sdhci_msm_dt_match[] = {
+ {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
+ {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
++ {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
+ {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
+ {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
+ {},
+--
+2.35.1
+
--- /dev/null
+From 8fd86118419ff1ad1b108044e3370256ddc77f30 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 21:06:40 +0200
+Subject: mmc: wmt-sdmmc: Fix an error handling path in wmt_mci_probe()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit cb58188ad90a61784a56a64f5107faaf2ad323e7 ]
+
+A dma_free_coherent() call is missing in the error handling path of the
+probe, as already done in the remove function.
+
+Fixes: 3a96dff0f828 ("mmc: SD/MMC Host Controller for Wondermedia WM8505/WM8650")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
+Link: https://lore.kernel.org/r/53fc6ffa5d1c428fefeae7d313cf4a669c3a1e98.1663873255.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/wmt-sdmmc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/wmt-sdmmc.c b/drivers/mmc/host/wmt-sdmmc.c
+index cf10949fb0ac..8df722ec57ed 100644
+--- a/drivers/mmc/host/wmt-sdmmc.c
++++ b/drivers/mmc/host/wmt-sdmmc.c
+@@ -849,7 +849,7 @@ static int wmt_mci_probe(struct platform_device *pdev)
+ if (IS_ERR(priv->clk_sdmmc)) {
+ dev_err(&pdev->dev, "Error getting clock\n");
+ ret = PTR_ERR(priv->clk_sdmmc);
+- goto fail5;
++ goto fail5_and_a_half;
+ }
+
+ ret = clk_prepare_enable(priv->clk_sdmmc);
+@@ -866,6 +866,9 @@ static int wmt_mci_probe(struct platform_device *pdev)
+ return 0;
+ fail6:
+ clk_put(priv->clk_sdmmc);
++fail5_and_a_half:
++ dma_free_coherent(&pdev->dev, mmc->max_blk_count * 16,
++ priv->dma_desc_buffer, priv->dma_desc_device_addr);
+ fail5:
+ free_irq(dma_irq, priv);
+ fail4:
+--
+2.35.1
+
--- /dev/null
+From f0e25b8d6c398b72a22b2025d26930403d2e8653 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 22 Jul 2022 17:16:44 +0800
+Subject: mtd: devices: docg3: check the return value of devm_ioremap() in the
+ probe
+
+From: William Dean <williamsukatube@gmail.com>
+
+[ Upstream commit 26e784433e6c65735cd6d93a8db52531970d9a60 ]
+
+The function devm_ioremap() in docg3_probe() can fail, so
+its return value should be checked.
+
+Fixes: 82402aeb8c81e ("mtd: docg3: Use devm_*() functions")
+Reported-by: Hacash Robot <hacashRobot@santino.com>
+Signed-off-by: William Dean <williamsukatube@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220722091644.2937953-1-williamsukatube@163.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/devices/docg3.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c
+index 5b0ae5ddad74..27c08f22dec8 100644
+--- a/drivers/mtd/devices/docg3.c
++++ b/drivers/mtd/devices/docg3.c
+@@ -1974,9 +1974,14 @@ static int __init docg3_probe(struct platform_device *pdev)
+ dev_err(dev, "No I/O memory resource defined\n");
+ return ret;
+ }
+- base = devm_ioremap(dev, ress->start, DOC_IOSPACE_SIZE);
+
+ ret = -ENOMEM;
++ base = devm_ioremap(dev, ress->start, DOC_IOSPACE_SIZE);
++ if (!base) {
++ dev_err(dev, "devm_ioremap dev failed\n");
++ return ret;
++ }
++
+ cascade = devm_kcalloc(dev, DOC_MAX_NBFLOORS, sizeof(*cascade),
+ GFP_KERNEL);
+ if (!cascade)
+--
+2.35.1
+
--- /dev/null
+From 45df7912030b09861e51458b2508b8d15f02af57 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Jul 2022 20:43:28 +0200
+Subject: mtd: rawnand: fsl_elbc: Fix none ECC mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Pali Rohár <pali@kernel.org>
+
+[ Upstream commit 049e43b9fd8fd2966940485da163d67e96ee3fea ]
+
+Commit f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") added
+support for specifying ECC mode via DTS and skipping autodetection.
+
+But it broke explicit specification of HW ECC mode in DTS as correct
+settings for HW ECC mode are applied only when NONE mode or nothing was
+specified in DTS file.
+
+Also it started aliasing NONE mode to be same as when ECC mode was not
+specified and disallowed usage of ON_DIE mode.
+
+Fix all these issues. Use autodetection of ECC mode only in case when mode
+was really not specified in DTS file by checking that ecc value is invalid.
+Set HW ECC settings either when HW ECC was specified in DTS or it was
+autodetected. And do not fail when ON_DIE mode is set.
+
+Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work")
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Reviewed-by: Marek Behún <kabel@kernel.org>
+Reviewed-by: Marek Behún <kabel@kernel.org>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220707184328.3845-1-pali@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/nand/raw/fsl_elbc_nand.c | 28 ++++++++++++++++------------
+ 1 file changed, 16 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
+index aab93b9e6052..a18d121396aa 100644
+--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
++++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
+@@ -726,36 +726,40 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+ unsigned int al;
+
+- switch (chip->ecc.engine_type) {
+ /*
+ * if ECC was not chosen in DT, decide whether to use HW or SW ECC from
+ * CS Base Register
+ */
+- case NAND_ECC_ENGINE_TYPE_NONE:
++ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) {
+ /* If CS Base Register selects full hardware ECC then use it */
+ if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
+ BR_DECC_CHK_GEN) {
+- chip->ecc.read_page = fsl_elbc_read_page;
+- chip->ecc.write_page = fsl_elbc_write_page;
+- chip->ecc.write_subpage = fsl_elbc_write_subpage;
+-
+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+- mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops);
+- chip->ecc.size = 512;
+- chip->ecc.bytes = 3;
+- chip->ecc.strength = 1;
+ } else {
+ /* otherwise fall back to default software ECC */
+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+ chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+ }
++ }
++
++ switch (chip->ecc.engine_type) {
++ /* if HW ECC was chosen, setup ecc and oob layout */
++ case NAND_ECC_ENGINE_TYPE_ON_HOST:
++ chip->ecc.read_page = fsl_elbc_read_page;
++ chip->ecc.write_page = fsl_elbc_write_page;
++ chip->ecc.write_subpage = fsl_elbc_write_subpage;
++ mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops);
++ chip->ecc.size = 512;
++ chip->ecc.bytes = 3;
++ chip->ecc.strength = 1;
+ break;
+
+- /* if SW ECC was chosen in DT, we do not need to set anything here */
++ /* if none or SW ECC was chosen, we do not need to set anything here */
++ case NAND_ECC_ENGINE_TYPE_NONE:
+ case NAND_ECC_ENGINE_TYPE_SOFT:
++ case NAND_ECC_ENGINE_TYPE_ON_DIE:
+ break;
+
+- /* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */
+ default:
+ return -EINVAL;
+ }
+--
+2.35.1
+
--- /dev/null
+From 383f663eb3caf52cf57718947960aa9b21c48645 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 01:12:24 +0200
+Subject: mtd: rawnand: intel: Don't re-define NAND_DATA_IFACE_CHECK_ONLY
+
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+[ Upstream commit ebe0cd60fcffd499f8020fde9b3b74acba9c22af ]
+
+NAND_DATA_IFACE_CHECK_ONLY is already defined in
+include/linux/mtd/rawnand.h which is also included by the driver. Drop
+the re-definition from the intel-nand-controller driver.
+
+Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-6-martin.blumenstingl@googlemail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/nand/raw/intel-nand-controller.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c
+index 056835fd4562..3df16d5ecae8 100644
+--- a/drivers/mtd/nand/raw/intel-nand-controller.c
++++ b/drivers/mtd/nand/raw/intel-nand-controller.c
+@@ -100,8 +100,6 @@
+
+ #define HSNAND_ECC_OFFSET 0x008
+
+-#define NAND_DATA_IFACE_CHECK_ONLY -1
+-
+ #define MAX_CS 2
+
+ #define USEC_PER_SEC 1000000L
+--
+2.35.1
+
--- /dev/null
+From 1f915e8ec580ee476c6cc3e0f7786228a2a40554 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 01:12:22 +0200
+Subject: mtd: rawnand: intel: Read the chip-select line from the correct OF
+ node
+
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+[ Upstream commit bfc618fcc3f167ad082053e81e9d664e724c6288 ]
+
+The chip select has to be read from the flash node which is a child node
+of the NAND controller.
+
+Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-4-martin.blumenstingl@googlemail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/nand/raw/intel-nand-controller.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c
+index e91b879b32bd..3df3f32423f9 100644
+--- a/drivers/mtd/nand/raw/intel-nand-controller.c
++++ b/drivers/mtd/nand/raw/intel-nand-controller.c
+@@ -16,6 +16,7 @@
+ #include <linux/mtd/rawnand.h>
+ #include <linux/mtd/nand.h>
+
++#include <linux/of.h>
+ #include <linux/platform_device.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
+@@ -580,6 +581,7 @@ static int ebu_nand_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+ struct ebu_nand_controller *ebu_host;
++ struct device_node *chip_np;
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ struct resource *res;
+@@ -604,7 +606,12 @@ static int ebu_nand_probe(struct platform_device *pdev)
+ if (IS_ERR(ebu_host->hsnand))
+ return PTR_ERR(ebu_host->hsnand);
+
+- ret = device_property_read_u32(dev, "reg", &cs);
++ chip_np = of_get_next_child(dev->of_node, NULL);
++ if (!chip_np)
++ return dev_err_probe(dev, -EINVAL,
++ "Could not find child node for the NAND chip\n");
++
++ ret = of_property_read_u32(chip_np, "reg", &cs);
+ if (ret) {
+ dev_err(dev, "failed to get chip select: %d\n", ret);
+ return ret;
+@@ -660,7 +667,7 @@ static int ebu_nand_probe(struct platform_device *pdev)
+ writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN,
+ ebu_host->ebu + EBU_ADDR_SEL(cs));
+
+- nand_set_flash_node(&ebu_host->chip, dev->of_node);
++ nand_set_flash_node(&ebu_host->chip, chip_np);
+
+ mtd = nand_to_mtd(&ebu_host->chip);
+ if (!mtd->name) {
+--
+2.35.1
+
--- /dev/null
+From 0db1aadb8ffd2bac18dea85bee41a7a7077e902b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 01:12:23 +0200
+Subject: mtd: rawnand: intel: Remove undocumented compatible string
+
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+[ Upstream commit 68c02ebaa34d41063ccbbc789a352537ddc3cd8a ]
+
+The "intel,nand-controller" compatible string is not part of the
+dt-bindings. Remove it from the driver as it's not supposed to be used
+without any documentation for it.
+
+Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-5-martin.blumenstingl@googlemail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/nand/raw/intel-nand-controller.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c
+index 3df3f32423f9..056835fd4562 100644
+--- a/drivers/mtd/nand/raw/intel-nand-controller.c
++++ b/drivers/mtd/nand/raw/intel-nand-controller.c
+@@ -723,7 +723,6 @@ static int ebu_nand_remove(struct platform_device *pdev)
+ }
+
+ static const struct of_device_id ebu_nand_match[] = {
+- { .compatible = "intel,nand-controller" },
+ { .compatible = "intel,lgm-ebunand" },
+ {}
+ };
+--
+2.35.1
+
--- /dev/null
+From aa78be8933ee70aa4a210ffbf7a6faa96db875d4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 Jul 2022 10:12:12 +0300
+Subject: mtd: rawnand: meson: fix bit map use in meson_nfc_ecc_correct()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 3e4ad3212cf22687410b1e8f4e68feec50646113 ]
+
+The meson_nfc_ecc_correct() function accidentally does a right shift
+instead of a left shift so it only works for BIT(0). Also use
+BIT_ULL() because "correct_bitmap" is a u64 and we want to avoid
+shift wrapping bugs.
+
+Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Liang Yang <liang.yang@amlogic.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/YuI2zF1hP65+LE7r@kili
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/nand/raw/meson_nand.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
+index 032180183339..b97adeee4cc1 100644
+--- a/drivers/mtd/nand/raw/meson_nand.c
++++ b/drivers/mtd/nand/raw/meson_nand.c
+@@ -454,7 +454,7 @@ static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
+ if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
+ mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
+ *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
+- *correct_bitmap |= 1 >> i;
++ *correct_bitmap |= BIT_ULL(i);
+ continue;
+ }
+ if ((nand->options & NAND_NEED_SCRAMBLING) &&
+@@ -800,7 +800,7 @@ static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
+ u8 *data = buf + i * ecc->size;
+ u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
+
+- if (correct_bitmap & (1 << i))
++ if (correct_bitmap & BIT_ULL(i))
+ continue;
+ ret = nand_check_erased_ecc_chunk(data, ecc->size,
+ oob, ecc->bytes + 2,
+--
+2.35.1
+
--- /dev/null
+From 9c8215d1c2ee24dba0fef37a3da1145ea578b8b2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 01:35:02 +0900
+Subject: nbd: Fix hung when signal interrupts nbd_start_device_ioctl()
+
+From: Shigeru Yoshida <syoshida@redhat.com>
+
+[ Upstream commit 1de7c3cf48fc41cd95adb12bd1ea9033a917798a ]
+
+syzbot reported hung task [1]. The following program is a simplified
+version of the reproducer:
+
+int main(void)
+{
+ int sv[2], fd;
+
+ if (socketpair(AF_UNIX, SOCK_STREAM, 0, sv) < 0)
+ return 1;
+ if ((fd = open("/dev/nbd0", 0)) < 0)
+ return 1;
+ if (ioctl(fd, NBD_SET_SIZE_BLOCKS, 0x81) < 0)
+ return 1;
+ if (ioctl(fd, NBD_SET_SOCK, sv[0]) < 0)
+ return 1;
+ if (ioctl(fd, NBD_DO_IT) < 0)
+ return 1;
+ return 0;
+}
+
+When signal interrupt nbd_start_device_ioctl() waiting the condition
+atomic_read(&config->recv_threads) == 0, the task can hung because it
+waits the completion of the inflight IOs.
+
+This patch fixes the issue by clearing queue, not just shutdown, when
+signal interrupt nbd_start_device_ioctl().
+
+Link: https://syzkaller.appspot.com/bug?id=7d89a3ffacd2b83fdd39549bc4d8e0a89ef21239 [1]
+Reported-by: syzbot+38e6c55d4969a14c1534@syzkaller.appspotmail.com
+Signed-off-by: Shigeru Yoshida <syoshida@redhat.com>
+Reviewed-by: Josef Bacik <josef@toxicpanda.com>
+Link: https://lore.kernel.org/r/20220907163502.577561-1-syoshida@redhat.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/block/nbd.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
+index b391ca062add..ec2b5dd2ce4a 100644
+--- a/drivers/block/nbd.c
++++ b/drivers/block/nbd.c
+@@ -1351,10 +1351,12 @@ static int nbd_start_device_ioctl(struct nbd_device *nbd, struct block_device *b
+ mutex_unlock(&nbd->config_lock);
+ ret = wait_event_interruptible(config->recv_wq,
+ atomic_read(&config->recv_threads) == 0);
+- if (ret)
++ if (ret) {
+ sock_shutdown(nbd);
+- flush_workqueue(nbd->recv_workq);
++ nbd_clear_que(nbd);
++ }
+
++ flush_workqueue(nbd->recv_workq);
+ mutex_lock(&nbd->config_lock);
+ nbd_bdev_reset(bdev);
+ /* user requested, ignore socket errors */
+--
+2.35.1
+
--- /dev/null
+From 41256a0a4ccd2d4af869bcfa02798dc3a0cc85ca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 15:54:07 +0800
+Subject: net: broadcom: Fix return type for implementation of
+
+From: GUO Zihua <guozihua@huawei.com>
+
+[ Upstream commit 12f7bd252221d4f9e000e20530e50129241e3a67 ]
+
+Since Linux now supports CFI, it will be a good idea to fix mismatched
+return type for implementation of hooks. Otherwise this might get
+cought out by CFI and cause a panic.
+
+bcm4908_enet_start_xmit() would return either NETDEV_TX_BUSY or
+NETDEV_TX_OK, so change the return type to netdev_tx_t directly.
+
+Signed-off-by: GUO Zihua <guozihua@huawei.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20220902075407.52358-1-guozihua@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/broadcom/bcm4908_enet.c b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+index 376f81796a29..f92ce8f8d751 100644
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -507,7 +507,7 @@ static int bcm4908_enet_stop(struct net_device *netdev)
+ return 0;
+ }
+
+-static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++static netdev_tx_t bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+ {
+ struct bcm4908_enet *enet = netdev_priv(netdev);
+ struct bcm4908_enet_dma_ring *ring = &enet->tx_ring;
+--
+2.35.1
+
--- /dev/null
+From 8646cc3e481d3524314bcfd1b34802962a1eb291 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 12:47:19 -0700
+Subject: net: davicom: Fix return type of dm9000_start_xmit
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 0191580b000d50089a0b351f7cdbec4866e3d0d2 ]
+
+The ndo_start_xmit field in net_device_ops is expected to be of type
+netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev).
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of dm9000_start_xmit should be changed from int to
+netdev_tx_t.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://github.com/ClangBuiltLinux/linux/issues/1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Reviewed-by: Nathan Chancellor <nathan@kernel.org>
+Link: https://lore.kernel.org/r/20220912194722.809525-1-nhuck@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/davicom/dm9000.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
+index e842de6f6635..a2ce9d7ad750 100644
+--- a/drivers/net/ethernet/davicom/dm9000.c
++++ b/drivers/net/ethernet/davicom/dm9000.c
+@@ -1012,7 +1012,7 @@ static void dm9000_send_packet(struct net_device *dev,
+ * Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+-static int
++static netdev_tx_t
+ dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
+ {
+ unsigned long flags;
+--
+2.35.1
+
--- /dev/null
+From f5596fa312d27f162dce2b342be8ce02474f24bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 12:53:07 -0700
+Subject: net: ethernet: litex: Fix return type of liteeth_start_xmit
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 40662333dd7c64664247a6138bc33f3974e3a331 ]
+
+The ndo_start_xmit field in net_device_ops is expected to be of type
+netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev).
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of liteeth_start_xmit should be changed from int to
+netdev_tx_t.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://github.com/ClangBuiltLinux/linux/issues/1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Reviewed-by: Nathan Chancellor <nathan@kernel.org>
+Acked-by: Gabriel Somlo <gsomlo@gmail.com>
+Link: https://lore.kernel.org/r/20220912195307.812229-1-nhuck@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/litex/litex_liteeth.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/litex/litex_liteeth.c b/drivers/net/ethernet/litex/litex_liteeth.c
+index 5bb1cc8a2ce1..0aa855f838f2 100644
+--- a/drivers/net/ethernet/litex/litex_liteeth.c
++++ b/drivers/net/ethernet/litex/litex_liteeth.c
+@@ -152,7 +152,8 @@ static int liteeth_stop(struct net_device *netdev)
+ return 0;
+ }
+
+-static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++static netdev_tx_t liteeth_start_xmit(struct sk_buff *skb,
++ struct net_device *netdev)
+ {
+ struct liteeth *priv = netdev_priv(netdev);
+ void __iomem *txbuffer;
+--
+2.35.1
+
--- /dev/null
+From 3b7056aae5d8efcd31e6feee0d668591ce6eaa53 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 12:50:19 -0700
+Subject: net: ethernet: ti: davinci_emac: Fix return type of emac_dev_xmit
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 5972ca946098487c5155fe13654743f9010f5ed5 ]
+
+The ndo_start_xmit field in net_device_ops is expected to be of type
+netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev).
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of emac_dev_xmit should be changed from int to
+netdev_tx_t.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://github.com/ClangBuiltLinux/linux/issues/1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Reviewed-by: Nathan Chancellor <nathan@kernel.org>
+Link: https://lore.kernel.org/r/20220912195023.810319-1-nhuck@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ti/davinci_emac.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
+index d243ca5dfde0..4d3bd6e1db55 100644
+--- a/drivers/net/ethernet/ti/davinci_emac.c
++++ b/drivers/net/ethernet/ti/davinci_emac.c
+@@ -950,7 +950,7 @@ static void emac_tx_handler(void *token, int len, int status)
+ *
+ * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
+ */
+-static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
++static netdev_tx_t emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
+ {
+ struct device *emac_dev = &ndev->dev;
+ int ret_code;
+--
+2.35.1
+
--- /dev/null
+From b20a5d70c548c7e53cb1620eca05cdf405ed03b3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Aug 2022 15:14:06 +0530
+Subject: net: ethernet: ti: davinci_mdio: Add workaround for errata i2329
+
+From: Ravi Gunasekaran <r-gunasekaran@ti.com>
+
+[ Upstream commit d04807b80691c6041ca8e3dcf1870d1bf1082c22 ]
+
+On the CPSW and ICSS peripherals, there is a possibility that the MDIO
+interface returns corrupt data on MDIO reads or writes incorrect data
+on MDIO writes. There is also a possibility for the MDIO interface to
+become unavailable until the next peripheral reset.
+
+The workaround is to configure the MDIO in manual mode and disable the
+MDIO state machine and emulate the MDIO protocol by reading and writing
+appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
+to manipulate the MDIO clock and data pins.
+
+More details about the errata i2329 and the workaround is available in:
+https://www.ti.com/lit/er/sprz487a/sprz487a.pdf
+
+Add implementation to disable MDIO state machine, configure MDIO in manual
+mode and achieve MDIO read and writes via MDIO Bitbanging
+
+Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
+Reported-by: kernel test robot <lkp@intel.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ti/davinci_mdio.c | 242 +++++++++++++++++++++++--
+ 1 file changed, 231 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
+index a4efd5e35158..995633e1ec5e 100644
+--- a/drivers/net/ethernet/ti/davinci_mdio.c
++++ b/drivers/net/ethernet/ti/davinci_mdio.c
+@@ -26,6 +26,8 @@
+ #include <linux/of_device.h>
+ #include <linux/of_mdio.h>
+ #include <linux/pinctrl/consumer.h>
++#include <linux/mdio-bitbang.h>
++#include <linux/sys_soc.h>
+
+ /*
+ * This timeout definition is a worst-case ultra defensive measure against
+@@ -41,6 +43,7 @@
+
+ struct davinci_mdio_of_param {
+ int autosuspend_delay_ms;
++ bool manual_mode;
+ };
+
+ struct davinci_mdio_regs {
+@@ -49,6 +52,15 @@ struct davinci_mdio_regs {
+ #define CONTROL_IDLE BIT(31)
+ #define CONTROL_ENABLE BIT(30)
+ #define CONTROL_MAX_DIV (0xffff)
++#define CONTROL_CLKDIV GENMASK(15, 0)
++
++#define MDIO_MAN_MDCLK_O BIT(2)
++#define MDIO_MAN_OE BIT(1)
++#define MDIO_MAN_PIN BIT(0)
++#define MDIO_MANUALMODE BIT(31)
++
++#define MDIO_PIN 0
++
+
+ u32 alive;
+ u32 link;
+@@ -59,7 +71,9 @@ struct davinci_mdio_regs {
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclr;
+- u32 __reserved_1[20];
++ u32 manualif;
++ u32 poll;
++ u32 __reserved_1[18];
+
+ struct {
+ u32 access;
+@@ -79,6 +93,7 @@ static const struct mdio_platform_data default_pdata = {
+
+ struct davinci_mdio_data {
+ struct mdio_platform_data pdata;
++ struct mdiobb_ctrl bb_ctrl;
+ struct davinci_mdio_regs __iomem *regs;
+ struct clk *clk;
+ struct device *dev;
+@@ -90,6 +105,7 @@ struct davinci_mdio_data {
+ */
+ bool skip_scan;
+ u32 clk_div;
++ bool manual_mode;
+ };
+
+ static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
+@@ -128,9 +144,122 @@ static void davinci_mdio_enable(struct davinci_mdio_data *data)
+ writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
+ }
+
+-static int davinci_mdio_reset(struct mii_bus *bus)
++static void davinci_mdio_disable(struct davinci_mdio_data *data)
++{
++ u32 reg;
++
++ /* Disable MDIO state machine */
++ reg = readl(&data->regs->control);
++
++ reg &= ~CONTROL_CLKDIV;
++ reg |= data->clk_div;
++
++ reg &= ~CONTROL_ENABLE;
++ writel(reg, &data->regs->control);
++}
++
++static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
++{
++ u32 reg;
++ /* set manual mode */
++ reg = readl(&data->regs->poll);
++ reg |= MDIO_MANUALMODE;
++ writel(reg, &data->regs->poll);
++}
++
++static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
++{
++ struct davinci_mdio_data *data;
++ u32 reg;
++
++ data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
++ reg = readl(&data->regs->manualif);
++
++ if (level)
++ reg |= MDIO_MAN_MDCLK_O;
++ else
++ reg &= ~MDIO_MAN_MDCLK_O;
++
++ writel(reg, &data->regs->manualif);
++}
++
++static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
++{
++ struct davinci_mdio_data *data;
++ u32 reg;
++
++ data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
++ reg = readl(&data->regs->manualif);
++
++ if (output)
++ reg |= MDIO_MAN_OE;
++ else
++ reg &= ~MDIO_MAN_OE;
++
++ writel(reg, &data->regs->manualif);
++}
++
++static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
++{
++ struct davinci_mdio_data *data;
++ u32 reg;
++
++ data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
++ reg = readl(&data->regs->manualif);
++
++ if (value)
++ reg |= MDIO_MAN_PIN;
++ else
++ reg &= ~MDIO_MAN_PIN;
++
++ writel(reg, &data->regs->manualif);
++}
++
++static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
++{
++ struct davinci_mdio_data *data;
++ unsigned long reg;
++
++ data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
++ reg = readl(&data->regs->manualif);
++ return test_bit(MDIO_PIN, ®);
++}
++
++static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg)
++{
++ int ret;
++
++ ret = pm_runtime_resume_and_get(bus->parent);
++ if (ret < 0)
++ return ret;
++
++ ret = mdiobb_read(bus, phy, reg);
++
++ pm_runtime_mark_last_busy(bus->parent);
++ pm_runtime_put_autosuspend(bus->parent);
++
++ return ret;
++}
++
++static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg,
++ u16 val)
++{
++ int ret;
++
++ ret = pm_runtime_resume_and_get(bus->parent);
++ if (ret < 0)
++ return ret;
++
++ ret = mdiobb_write(bus, phy, reg, val);
++
++ pm_runtime_mark_last_busy(bus->parent);
++ pm_runtime_put_autosuspend(bus->parent);
++
++ return ret;
++}
++
++static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
+ {
+- struct davinci_mdio_data *data = bus->priv;
+ u32 phy_mask, ver;
+ int ret;
+
+@@ -140,6 +269,11 @@ static int davinci_mdio_reset(struct mii_bus *bus)
+ return ret;
+ }
+
++ if (data->manual_mode) {
++ davinci_mdio_disable(data);
++ davinci_mdio_enable_manual_mode(data);
++ }
++
+ /* wait for scan logic to settle */
+ msleep(PHY_MAX_ADDR * data->access_time);
+
+@@ -173,6 +307,23 @@ static int davinci_mdio_reset(struct mii_bus *bus)
+ return 0;
+ }
+
++static int davinci_mdio_reset(struct mii_bus *bus)
++{
++ struct davinci_mdio_data *data = bus->priv;
++
++ return davinci_mdio_common_reset(data);
++}
++
++static int davinci_mdiobb_reset(struct mii_bus *bus)
++{
++ struct mdiobb_ctrl *ctrl = bus->priv;
++ struct davinci_mdio_data *data;
++
++ data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
++
++ return davinci_mdio_common_reset(data);
++}
++
+ /* wait until hardware is ready for another user access */
+ static inline int wait_for_user_access(struct davinci_mdio_data *data)
+ {
+@@ -324,6 +475,28 @@ static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
+ return 0;
+ }
+
++struct k3_mdio_soc_data {
++ bool manual_mode;
++};
++
++static const struct k3_mdio_soc_data am65_mdio_soc_data = {
++ .manual_mode = true,
++};
++
++static const struct soc_device_attribute k3_mdio_socinfo[] = {
++ { .family = "AM62X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
++ { .family = "AM64X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
++ { .family = "AM64X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
++ { .family = "AM65X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
++ { .family = "AM65X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
++ { .family = "J7200", .revision = "SR1.0", .data = &am65_mdio_soc_data },
++ { .family = "J7200", .revision = "SR2.0", .data = &am65_mdio_soc_data },
++ { .family = "J721E", .revision = "SR1.0", .data = &am65_mdio_soc_data },
++ { .family = "J721E", .revision = "SR2.0", .data = &am65_mdio_soc_data },
++ { .family = "J721S2", .revision = "SR1.0", .data = &am65_mdio_soc_data},
++ { /* sentinel */ },
++};
++
+ #if IS_ENABLED(CONFIG_OF)
+ static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
+ .autosuspend_delay_ms = 100,
+@@ -337,6 +510,14 @@ static const struct of_device_id davinci_mdio_of_mtable[] = {
+ MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
+ #endif
+
++static const struct mdiobb_ops davinci_mdiobb_ops = {
++ .owner = THIS_MODULE,
++ .set_mdc = davinci_set_mdc,
++ .set_mdio_dir = davinci_set_mdio_dir,
++ .set_mdio_data = davinci_set_mdio_data,
++ .get_mdio_data = davinci_get_mdio_data,
++};
++
+ static int davinci_mdio_probe(struct platform_device *pdev)
+ {
+ struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
+@@ -351,7 +532,26 @@ static int davinci_mdio_probe(struct platform_device *pdev)
+ if (!data)
+ return -ENOMEM;
+
+- data->bus = devm_mdiobus_alloc(dev);
++ data->manual_mode = false;
++ data->bb_ctrl.ops = &davinci_mdiobb_ops;
++
++ if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
++ const struct soc_device_attribute *soc_match_data;
++
++ soc_match_data = soc_device_match(k3_mdio_socinfo);
++ if (soc_match_data && soc_match_data->data) {
++ const struct k3_mdio_soc_data *socdata =
++ soc_match_data->data;
++
++ data->manual_mode = socdata->manual_mode;
++ }
++ }
++
++ if (data->manual_mode)
++ data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
++ else
++ data->bus = devm_mdiobus_alloc(dev);
++
+ if (!data->bus) {
+ dev_err(dev, "failed to alloc mii bus\n");
+ return -ENOMEM;
+@@ -377,11 +577,20 @@ static int davinci_mdio_probe(struct platform_device *pdev)
+ }
+
+ data->bus->name = dev_name(dev);
+- data->bus->read = davinci_mdio_read;
+- data->bus->write = davinci_mdio_write;
+- data->bus->reset = davinci_mdio_reset;
++
++ if (data->manual_mode) {
++ data->bus->read = davinci_mdiobb_read;
++ data->bus->write = davinci_mdiobb_write;
++ data->bus->reset = davinci_mdiobb_reset;
++
++ dev_info(dev, "Configuring MDIO in manual mode\n");
++ } else {
++ data->bus->read = davinci_mdio_read;
++ data->bus->write = davinci_mdio_write;
++ data->bus->reset = davinci_mdio_reset;
++ data->bus->priv = data;
++ }
+ data->bus->parent = dev;
+- data->bus->priv = data;
+
+ data->clk = devm_clk_get(dev, "fck");
+ if (IS_ERR(data->clk)) {
+@@ -439,9 +648,13 @@ static int davinci_mdio_remove(struct platform_device *pdev)
+ {
+ struct davinci_mdio_data *data = platform_get_drvdata(pdev);
+
+- if (data->bus)
++ if (data->bus) {
+ mdiobus_unregister(data->bus);
+
++ if (data->manual_mode)
++ free_mdio_bitbang(data->bus);
++ }
++
+ pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+@@ -458,7 +671,9 @@ static int davinci_mdio_runtime_suspend(struct device *dev)
+ ctrl = readl(&data->regs->control);
+ ctrl &= ~CONTROL_ENABLE;
+ writel(ctrl, &data->regs->control);
+- wait_for_idle(data);
++
++ if (!data->manual_mode)
++ wait_for_idle(data);
+
+ return 0;
+ }
+@@ -467,7 +682,12 @@ static int davinci_mdio_runtime_resume(struct device *dev)
+ {
+ struct davinci_mdio_data *data = dev_get_drvdata(dev);
+
+- davinci_mdio_enable(data);
++ if (data->manual_mode) {
++ davinci_mdio_disable(data);
++ davinci_mdio_enable_manual_mode(data);
++ } else {
++ davinci_mdio_enable(data);
++ }
+ return 0;
+ }
+ #endif
+--
+2.35.1
+
--- /dev/null
+From 2af0df628320c7f902a32c61cca76c011ee3a09a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 13:55:13 +0000
+Subject: net: fs_enet: Fix wrong check in do_pd_setup
+
+From: Zheng Yongjun <zhengyongjun3@huawei.com>
+
+[ Upstream commit ec3f06b542a960806a81345042e4eee3f8c5dec4 ]
+
+Should check of_iomap return value 'fep->fec.fecp' instead of 'fep->fcc.fccp'
+
+Fixes: 976de6a8c304 ("fs_enet: Be an of_platform device when CONFIG_PPC_CPM_NEW_BINDING is set.")
+Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
+Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
+index 99fe2c210d0f..61f4b6e50d29 100644
+--- a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
++++ b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
+@@ -98,7 +98,7 @@ static int do_pd_setup(struct fs_enet_private *fep)
+ return -EINVAL;
+
+ fep->fec.fecp = of_iomap(ofdev->dev.of_node, 0);
+- if (!fep->fcc.fccp)
++ if (!fep->fec.fecp)
+ return -EINVAL;
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From 6689b130d62d73df20a6f833d282d82e1c4b5a78 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 14:37:49 +0300
+Subject: net: ftmac100: fix endianness-related issues from 'sparse'
+
+From: Sergei Antonov <saproj@gmail.com>
+
+[ Upstream commit 9df696b3b3a4c96c3219eb87c7bf03fb50e490b8 ]
+
+Sparse found a number of endianness-related issues of these kinds:
+
+.../ftmac100.c:192:32: warning: restricted __le32 degrades to integer
+
+.../ftmac100.c:208:23: warning: incorrect type in assignment (different base types)
+.../ftmac100.c:208:23: expected unsigned int rxdes0
+.../ftmac100.c:208:23: got restricted __le32 [usertype]
+
+.../ftmac100.c:249:23: warning: invalid assignment: &=
+.../ftmac100.c:249:23: left side has type unsigned int
+.../ftmac100.c:249:23: right side has type restricted __le32
+
+.../ftmac100.c:527:16: warning: cast to restricted __le32
+
+Change type of some fields from 'unsigned int' to '__le32' to fix it.
+
+Signed-off-by: Sergei Antonov <saproj@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20220902113749.1408562-1-saproj@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/faraday/ftmac100.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/faraday/ftmac100.h b/drivers/net/ethernet/faraday/ftmac100.h
+index fe986f1673fc..8af32f9070f4 100644
+--- a/drivers/net/ethernet/faraday/ftmac100.h
++++ b/drivers/net/ethernet/faraday/ftmac100.h
+@@ -122,9 +122,9 @@
+ * Transmit descriptor, aligned to 16 bytes
+ */
+ struct ftmac100_txdes {
+- unsigned int txdes0;
+- unsigned int txdes1;
+- unsigned int txdes2; /* TXBUF_BADR */
++ __le32 txdes0;
++ __le32 txdes1;
++ __le32 txdes2; /* TXBUF_BADR */
+ unsigned int txdes3; /* not used by HW */
+ } __attribute__ ((aligned(16)));
+
+@@ -143,9 +143,9 @@ struct ftmac100_txdes {
+ * Receive descriptor, aligned to 16 bytes
+ */
+ struct ftmac100_rxdes {
+- unsigned int rxdes0;
+- unsigned int rxdes1;
+- unsigned int rxdes2; /* RXBUF_BADR */
++ __le32 rxdes0;
++ __le32 rxdes1;
++ __le32 rxdes2; /* RXBUF_BADR */
+ unsigned int rxdes3; /* not used by HW */
+ } __attribute__ ((aligned(16)));
+
+--
+2.35.1
+
--- /dev/null
+From 17bc69650875be86a2a3b57164739459b674a1f4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 2 Oct 2022 01:43:44 +0900
+Subject: net/ieee802154: reject zero-sized raw_sendmsg()
+
+From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+
+[ Upstream commit 3a4d061c699bd3eedc80dc97a4b2a2e1af83c6f5 ]
+
+syzbot is hitting skb_assert_len() warning at raw_sendmsg() for ieee802154
+socket. What commit dc633700f00f726e ("net/af_packet: check len when
+min_header_len equals to 0") does also applies to ieee802154 socket.
+
+Link: https://syzkaller.appspot.com/bug?extid=5ea725c25d06fb9114c4
+Reported-by: syzbot <syzbot+5ea725c25d06fb9114c4@syzkaller.appspotmail.com>
+Fixes: fd1894224407c484 ("bpf: Don't redirect packets with invalid pkt_len")
+Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/ieee802154/socket.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/net/ieee802154/socket.c b/net/ieee802154/socket.c
+index fd5862f9e26a..f160cfc3e8f0 100644
+--- a/net/ieee802154/socket.c
++++ b/net/ieee802154/socket.c
+@@ -251,6 +251,9 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t size)
+ return -EOPNOTSUPP;
+ }
+
++ if (!size)
++ return -EINVAL;
++
+ lock_sock(sk);
+ if (!sk->sk_bound_dev_if)
+ dev = dev_getfirstbyhwtype(sock_net(sk), ARPHRD_IEEE802154);
+--
+2.35.1
+
--- /dev/null
+From 9a22812255df954891f4ea1a56dd39ed2092443a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Aug 2022 21:37:54 +0800
+Subject: net: If sock is dead don't access sock's sk_wq in
+ sk_stream_wait_memory
+
+From: Liu Jian <liujian56@huawei.com>
+
+[ Upstream commit 3f8ef65af927db247418d4e1db49164d7a158fc5 ]
+
+Fixes the below NULL pointer dereference:
+
+ [...]
+ [ 14.471200] Call Trace:
+ [ 14.471562] <TASK>
+ [ 14.471882] lock_acquire+0x245/0x2e0
+ [ 14.472416] ? remove_wait_queue+0x12/0x50
+ [ 14.473014] ? _raw_spin_lock_irqsave+0x17/0x50
+ [ 14.473681] _raw_spin_lock_irqsave+0x3d/0x50
+ [ 14.474318] ? remove_wait_queue+0x12/0x50
+ [ 14.474907] remove_wait_queue+0x12/0x50
+ [ 14.475480] sk_stream_wait_memory+0x20d/0x340
+ [ 14.476127] ? do_wait_intr_irq+0x80/0x80
+ [ 14.476704] do_tcp_sendpages+0x287/0x600
+ [ 14.477283] tcp_bpf_push+0xab/0x260
+ [ 14.477817] tcp_bpf_sendmsg_redir+0x297/0x500
+ [ 14.478461] ? __local_bh_enable_ip+0x77/0xe0
+ [ 14.479096] tcp_bpf_send_verdict+0x105/0x470
+ [ 14.479729] tcp_bpf_sendmsg+0x318/0x4f0
+ [ 14.480311] sock_sendmsg+0x2d/0x40
+ [ 14.480822] ____sys_sendmsg+0x1b4/0x1c0
+ [ 14.481390] ? copy_msghdr_from_user+0x62/0x80
+ [ 14.482048] ___sys_sendmsg+0x78/0xb0
+ [ 14.482580] ? vmf_insert_pfn_prot+0x91/0x150
+ [ 14.483215] ? __do_fault+0x2a/0x1a0
+ [ 14.483738] ? do_fault+0x15e/0x5d0
+ [ 14.484246] ? __handle_mm_fault+0x56b/0x1040
+ [ 14.484874] ? lock_is_held_type+0xdf/0x130
+ [ 14.485474] ? find_held_lock+0x2d/0x90
+ [ 14.486046] ? __sys_sendmsg+0x41/0x70
+ [ 14.486587] __sys_sendmsg+0x41/0x70
+ [ 14.487105] ? intel_pmu_drain_pebs_core+0x350/0x350
+ [ 14.487822] do_syscall_64+0x34/0x80
+ [ 14.488345] entry_SYSCALL_64_after_hwframe+0x63/0xcd
+ [...]
+
+The test scenario has the following flow:
+
+thread1 thread2
+----------- ---------------
+ tcp_bpf_sendmsg
+ tcp_bpf_send_verdict
+ tcp_bpf_sendmsg_redir sock_close
+ tcp_bpf_push_locked __sock_release
+ tcp_bpf_push //inet_release
+ do_tcp_sendpages sock->ops->release
+ sk_stream_wait_memory // tcp_close
+ sk_wait_event sk->sk_prot->close
+ release_sock(__sk);
+ ***
+ lock_sock(sk);
+ __tcp_close
+ sock_orphan(sk)
+ sk->sk_wq = NULL
+ release_sock
+ ****
+ lock_sock(__sk);
+ remove_wait_queue(sk_sleep(sk), &wait);
+ sk_sleep(sk)
+ //NULL pointer dereference
+ &rcu_dereference_raw(sk->sk_wq)->wait
+
+While waiting for memory in thread1, the socket is released with its wait
+queue because thread2 has closed it. This caused by tcp_bpf_send_verdict
+didn't increase the f_count of psock->sk_redir->sk_socket->file in thread1.
+
+We should check if SOCK_DEAD flag is set on wakeup in sk_stream_wait_memory
+before accessing the wait queue.
+
+Suggested-by: Jakub Sitnicki <jakub@cloudflare.com>
+Signed-off-by: Liu Jian <liujian56@huawei.com>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Cc: Eric Dumazet <edumazet@google.com>
+Link: https://lore.kernel.org/bpf/20220823133755.314697-2-liujian56@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/core/stream.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/net/core/stream.c b/net/core/stream.c
+index a166a32b411f..a61130504827 100644
+--- a/net/core/stream.c
++++ b/net/core/stream.c
+@@ -159,7 +159,8 @@ int sk_stream_wait_memory(struct sock *sk, long *timeo_p)
+ *timeo_p = current_timeo;
+ }
+ out:
+- remove_wait_queue(sk_sleep(sk), &wait);
++ if (!sock_flag(sk, SOCK_DEAD))
++ remove_wait_queue(sk_sleep(sk), &wait);
+ return err;
+
+ do_error:
+--
+2.35.1
+
--- /dev/null
+From c9acc00e94eae1dbd33df4fe43429b96580bb0f5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 14:43:40 -0700
+Subject: net: korina: Fix return type of korina_send_packet
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 106c67ce46f3c82dd276e983668a91d6ed631173 ]
+
+The ndo_start_xmit field in net_device_ops is expected to be of type
+netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev).
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of korina_send_packet should be changed from int to
+netdev_tx_t.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://github.com/ClangBuiltLinux/linux/issues/1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Reviewed-by: Nathan Chancellor <nathan@kernel.org>
+Link: https://lore.kernel.org/r/20220912214344.928925-1-nhuck@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/korina.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/korina.c b/drivers/net/ethernet/korina.c
+index 3e9f324f1061..2e6f51a0eab0 100644
+--- a/drivers/net/ethernet/korina.c
++++ b/drivers/net/ethernet/korina.c
+@@ -416,7 +416,8 @@ static void korina_abort_rx(struct net_device *dev)
+ }
+
+ /* transmit packet */
+-static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
++static netdev_tx_t korina_send_packet(struct sk_buff *skb,
++ struct net_device *dev)
+ {
+ struct korina_private *lp = netdev_priv(dev);
+ u32 chain_prev, chain_next;
+--
+2.35.1
+
--- /dev/null
+From abcd491a3f636737f779be7a75c0dc3eb4f9e6c3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 16:15:21 +0800
+Subject: net: lantiq_etop: Fix return type for implementation of
+ ndo_start_xmit
+
+From: GUO Zihua <guozihua@huawei.com>
+
+[ Upstream commit c8ef3c94bda0e21123202d057d4a299698fa0ed9 ]
+
+Since Linux now supports CFI, it will be a good idea to fix mismatched
+return type for implementation of hooks. Otherwise this might get
+cought out by CFI and cause a panic.
+
+ltq_etop_tx() would return either NETDEV_TX_BUSY or NETDEV_TX_OK, so
+change the return type to netdev_tx_t directly.
+
+Signed-off-by: GUO Zihua <guozihua@huawei.com>
+Link: https://lore.kernel.org/r/20220902081521.59867-1-guozihua@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/lantiq_etop.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
+index 62f8c5212182..7664116b3a62 100644
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -451,7 +451,7 @@ ltq_etop_stop(struct net_device *dev)
+ return 0;
+ }
+
+-static int
++static netdev_tx_t
+ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
+ {
+ int queue = skb_get_queue_mapping(skb);
+--
+2.35.1
+
--- /dev/null
+From 6f06423ecc43c95caf020091970f5f49b5e854a9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Oct 2022 17:19:27 +0100
+Subject: net: mvpp2: fix mvpp2 debugfs leak
+
+From: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+
+[ Upstream commit 0152dfee235e87660f52a117fc9f70dc55956bb4 ]
+
+When mvpp2 is unloaded, the driver specific debugfs directory is not
+removed, which technically leads to a memory leak. However, this
+directory is only created when the first device is probed, so the
+hardware is present. Removing the module is only something a developer
+would to when e.g. testing out changes, so the module would be
+reloaded. So this memory leak is minor.
+
+The original attempt in commit fe2c9c61f668 ("net: mvpp2: debugfs: fix
+memory leak when using debugfs_lookup()") that was labelled as a memory
+leak fix was not, it fixed a refcount leak, but in doing so created a
+problem when the module is reloaded - the directory already exists, but
+mvpp2_root is NULL, so we lose all debugfs entries. This fix has been
+reverted.
+
+This is the alternative fix, where we remove the offending directory
+whenever the driver is unloaded.
+
+Fixes: 21da57a23125 ("net: mvpp2: add a debugfs interface for the Header Parser")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Reviewed-by: Marcin Wojtas <mw@semihalf.com>
+Link: https://lore.kernel.org/r/E1ofOAB-00CzkG-UO@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c | 10 ++++++++--
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 13 ++++++++++++-
+ 3 files changed, 21 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+index cf8acabb90ac..72608a47d4e0 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+@@ -1529,6 +1529,7 @@ u32 mvpp2_read(struct mvpp2 *priv, u32 offset);
+ void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name);
+
+ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
++void mvpp2_dbgfs_exit(void);
+
+ void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
+
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c
+index 4a3baa7e0142..75e83ea2a926 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c
+@@ -691,6 +691,13 @@ static int mvpp2_dbgfs_port_init(struct dentry *parent,
+ return 0;
+ }
+
++static struct dentry *mvpp2_root;
++
++void mvpp2_dbgfs_exit(void)
++{
++ debugfs_remove(mvpp2_root);
++}
++
+ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv)
+ {
+ debugfs_remove_recursive(priv->dbgfs_dir);
+@@ -700,10 +707,9 @@ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv)
+
+ void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name)
+ {
+- struct dentry *mvpp2_dir, *mvpp2_root;
++ struct dentry *mvpp2_dir;
+ int ret, i;
+
+- mvpp2_root = debugfs_lookup(MVPP2_DRIVER_NAME, NULL);
+ if (!mvpp2_root)
+ mvpp2_root = debugfs_create_dir(MVPP2_DRIVER_NAME, NULL);
+
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+index 2baa909290b3..ae586f8895fc 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -7710,7 +7710,18 @@ static struct platform_driver mvpp2_driver = {
+ },
+ };
+
+-module_platform_driver(mvpp2_driver);
++static int __init mvpp2_driver_init(void)
++{
++ return platform_driver_register(&mvpp2_driver);
++}
++module_init(mvpp2_driver_init);
++
++static void __exit mvpp2_driver_exit(void)
++{
++ platform_driver_unregister(&mvpp2_driver);
++ mvpp2_dbgfs_exit();
++}
++module_exit(mvpp2_driver_exit);
+
+ MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
+ MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
+--
+2.35.1
+
--- /dev/null
+From 1c05d8c6c0048f4ad9fb52403673dc623d31d698 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 00:25:37 +0900
+Subject: net: rds: don't hold sock lock when cancelling work from
+ rds_tcp_reset_callbacks()
+
+From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+
+[ Upstream commit a91b750fd6629354460282bbf5146c01b05c4859 ]
+
+syzbot is reporting lockdep warning at rds_tcp_reset_callbacks() [1], for
+commit ac3615e7f3cffe2a ("RDS: TCP: Reduce code duplication in
+rds_tcp_reset_callbacks()") added cancel_delayed_work_sync() into a section
+protected by lock_sock() without realizing that rds_send_xmit() might call
+lock_sock().
+
+We don't need to protect cancel_delayed_work_sync() using lock_sock(), for
+even if rds_{send,recv}_worker() re-queued this work while __flush_work()
+ from cancel_delayed_work_sync() was waiting for this work to complete,
+retried rds_{send,recv}_worker() is no-op due to the absence of RDS_CONN_UP
+bit.
+
+Link: https://syzkaller.appspot.com/bug?extid=78c55c7bc6f66e53dce2 [1]
+Reported-by: syzbot <syzbot+78c55c7bc6f66e53dce2@syzkaller.appspotmail.com>
+Co-developed-by: Hillf Danton <hdanton@sina.com>
+Signed-off-by: Hillf Danton <hdanton@sina.com>
+Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+Tested-by: syzbot <syzbot+78c55c7bc6f66e53dce2@syzkaller.appspotmail.com>
+Fixes: ac3615e7f3cffe2a ("RDS: TCP: Reduce code duplication in rds_tcp_reset_callbacks()")
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/rds/tcp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/rds/tcp.c b/net/rds/tcp.c
+index 5327d130c4b5..b560d06e6d96 100644
+--- a/net/rds/tcp.c
++++ b/net/rds/tcp.c
+@@ -166,10 +166,10 @@ void rds_tcp_reset_callbacks(struct socket *sock,
+ */
+ atomic_set(&cp->cp_state, RDS_CONN_RESETTING);
+ wait_event(cp->cp_waitq, !test_bit(RDS_IN_XMIT, &cp->cp_flags));
+- lock_sock(osock->sk);
+ /* reset receive side state for rds_tcp_data_recv() for osock */
+ cancel_delayed_work_sync(&cp->cp_send_w);
+ cancel_delayed_work_sync(&cp->cp_recv_w);
++ lock_sock(osock->sk);
+ if (tc->t_tinc) {
+ rds_inc_put(&tc->t_tinc->ti_inc);
+ tc->t_tinc = NULL;
+--
+2.35.1
+
--- /dev/null
+From 1de434e9137dba6a0d3bfe65a208d2211090bc6b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 1 Oct 2022 13:57:13 +0300
+Subject: net: wwan: iosm: Call mutex_init before locking it
+
+From: Maxim Mikityanskiy <maxtram95@gmail.com>
+
+[ Upstream commit ba0fbdb95da5ddd8db457ce6ba09d16dd979a294 ]
+
+wwan_register_ops calls wwan_create_default_link, which ends up in the
+ipc_wwan_newlink callback that locks ipc_wwan->if_mutex. However, this
+mutex is not yet initialized by that point. Fix it by moving mutex_init
+above the wwan_register_ops call. This also makes the order of
+operations in ipc_wwan_init symmetric to ipc_wwan_deinit.
+
+Fixes: 83068395bbfc ("net: iosm: create default link via WWAN core")
+Signed-off-by: Maxim Mikityanskiy <maxtram95@gmail.com>
+Reviewed-by: M Chetan Kumar <m.chetan.kumar@intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wwan/iosm/iosm_ipc_wwan.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wwan/iosm/iosm_ipc_wwan.c b/drivers/net/wwan/iosm/iosm_ipc_wwan.c
+index b571d9cedba4..92f064a8f837 100644
+--- a/drivers/net/wwan/iosm/iosm_ipc_wwan.c
++++ b/drivers/net/wwan/iosm/iosm_ipc_wwan.c
+@@ -322,15 +322,16 @@ struct iosm_wwan *ipc_wwan_init(struct iosm_imem *ipc_imem, struct device *dev)
+ ipc_wwan->dev = dev;
+ ipc_wwan->ipc_imem = ipc_imem;
+
++ mutex_init(&ipc_wwan->if_mutex);
++
+ /* WWAN core will create a netdev for the default IP MUX channel */
+ if (wwan_register_ops(ipc_wwan->dev, &iosm_wwan_ops, ipc_wwan,
+ IP_MUX_SESSION_DEFAULT)) {
++ mutex_destroy(&ipc_wwan->if_mutex);
+ kfree(ipc_wwan);
+ return NULL;
+ }
+
+- mutex_init(&ipc_wwan->if_mutex);
+-
+ return ipc_wwan;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 265d5178efc85ea9d1fe947ed6bb2cba01cf5052 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 14:44:55 -0700
+Subject: net: wwan: iosm: Fix return type of ipc_wwan_link_transmit
+
+From: Nathan Huckleberry <nhuck@google.com>
+
+[ Upstream commit 0c9441c430104dcf2cd066aae74dbeefb9f9e1bf ]
+
+The ndo_start_xmit field in net_device_ops is expected to be of type
+netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev).
+
+The mismatched return type breaks forward edge kCFI since the underlying
+function definition does not match the function hook definition.
+
+The return type of ipc_wwan_link_transmit should be changed from int to
+netdev_tx_t.
+
+Reported-by: Dan Carpenter <error27@gmail.com>
+Link: https://github.com/ClangBuiltLinux/linux/issues/1703
+Cc: llvm@lists.linux.dev
+Signed-off-by: Nathan Huckleberry <nhuck@google.com>
+Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
+Link: https://lore.kernel.org/r/20220912214455.929028-1-nhuck@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wwan/iosm/iosm_ipc_wwan.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wwan/iosm/iosm_ipc_wwan.c b/drivers/net/wwan/iosm/iosm_ipc_wwan.c
+index 92f064a8f837..bd509a9fa709 100644
+--- a/drivers/net/wwan/iosm/iosm_ipc_wwan.c
++++ b/drivers/net/wwan/iosm/iosm_ipc_wwan.c
+@@ -102,8 +102,8 @@ static int ipc_wwan_link_stop(struct net_device *netdev)
+ }
+
+ /* Transmit a packet */
+-static int ipc_wwan_link_transmit(struct sk_buff *skb,
+- struct net_device *netdev)
++static netdev_tx_t ipc_wwan_link_transmit(struct sk_buff *skb,
++ struct net_device *netdev)
+ {
+ struct iosm_netdev_priv *priv = wwan_netdev_drvpriv(netdev);
+ struct iosm_wwan *ipc_wwan = priv->ipc_wwan;
+--
+2.35.1
+
--- /dev/null
+From a5d560287e22035061d8bd1cbc98cfb20e45e892 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 6 May 2022 11:12:59 -0700
+Subject: net: wwan: t7xx: Add control DMA interface
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Haijun Liu <haijun.liu@mediatek.com>
+
+[ Upstream commit 39d439047f1dc88f98b755d6f3a53a4ef8f0de21 ]
+
+Cross Layer DMA (CLDMA) Hardware interface (HIF) enables the control
+path of Host-Modem data transfers. CLDMA HIF layer provides a common
+interface to the Port Layer.
+
+CLDMA manages 8 independent RX/TX physical channels with data flow
+control in HW queues. CLDMA uses ring buffers of General Packet
+Descriptors (GPD) for TX/RX. GPDs can represent multiple or single
+data buffers (DB).
+
+CLDMA HIF initializes GPD rings, registers ISR handlers for CLDMA
+interrupts, and initializes CLDMA HW registers.
+
+CLDMA TX flow:
+1. Port Layer write
+2. Get DB address
+3. Configure GPD
+4. Triggering processing via HW register write
+
+CLDMA RX flow:
+1. CLDMA HW sends a RX "done" to host
+2. Driver starts thread to safely read GPD
+3. DB is sent to Port layer
+4. Create a new buffer for GPD ring
+
+Note: This patch does not enable compilation since it has dependencies
+such as t7xx_pcie_mac_clear_int()/t7xx_pcie_mac_set_int() and
+struct t7xx_pci_dev which are added by the core patch.
+
+Signed-off-by: Haijun Liu <haijun.liu@mediatek.com>
+Signed-off-by: Chandrashekar Devegowda <chandrashekar.devegowda@intel.com>
+Co-developed-by: Ricardo Martinez <ricardo.martinez@linux.intel.com>
+Signed-off-by: Ricardo Martinez <ricardo.martinez@linux.intel.com>
+Reviewed-by: Loic Poulain <loic.poulain@linaro.org>
+Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Stable-dep-of: 2ac6cdd581f4 ("drm/dp_mst: fix drm_dp_dpcd_read return value checks")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wwan/t7xx/t7xx_cldma.c | 281 ++++++
+ drivers/net/wwan/t7xx/t7xx_cldma.h | 180 ++++
+ drivers/net/wwan/t7xx/t7xx_hif_cldma.c | 1192 ++++++++++++++++++++++++
+ drivers/net/wwan/t7xx/t7xx_hif_cldma.h | 126 +++
+ drivers/net/wwan/t7xx/t7xx_reg.h | 33 +
+ 5 files changed, 1812 insertions(+)
+ create mode 100644 drivers/net/wwan/t7xx/t7xx_cldma.c
+ create mode 100644 drivers/net/wwan/t7xx/t7xx_cldma.h
+ create mode 100644 drivers/net/wwan/t7xx/t7xx_hif_cldma.c
+ create mode 100644 drivers/net/wwan/t7xx/t7xx_hif_cldma.h
+ create mode 100644 drivers/net/wwan/t7xx/t7xx_reg.h
+
+diff --git a/drivers/net/wwan/t7xx/t7xx_cldma.c b/drivers/net/wwan/t7xx/t7xx_cldma.c
+new file mode 100644
+index 000000000000..9f43f256db1d
+--- /dev/null
++++ b/drivers/net/wwan/t7xx/t7xx_cldma.c
+@@ -0,0 +1,281 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2021, MediaTek Inc.
++ * Copyright (c) 2021-2022, Intel Corporation.
++ *
++ * Authors:
++ * Haijun Liu <haijun.liu@mediatek.com>
++ * Moises Veleta <moises.veleta@intel.com>
++ * Ricardo Martinez <ricardo.martinez@linux.intel.com>
++ *
++ * Contributors:
++ * Amir Hanania <amir.hanania@intel.com>
++ * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
++ * Eliot Lee <eliot.lee@intel.com>
++ * Sreehari Kancharla <sreehari.kancharla@intel.com>
++ */
++
++#include <linux/bits.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/types.h>
++
++#include "t7xx_cldma.h"
++
++#define ADDR_SIZE 8
++
++void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
++{
++ u32 val;
++
++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
++ val |= IP_BUSY_WAKEUP;
++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
++}
++
++/**
++ * t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
++ * @hw_info: Pointer to struct t7xx_cldma_hw.
++ *
++ * Restore HW after resume. Writes uplink configuration for CLDMA HW.
++ */
++void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
++{
++ u32 ul_cfg;
++
++ ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
++ ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
++
++ if (hw_info->hw_mode == MODE_BIT_64)
++ ul_cfg |= UL_CFG_BIT_MODE_64;
++ else if (hw_info->hw_mode == MODE_BIT_40)
++ ul_cfg |= UL_CFG_BIT_MODE_40;
++ else if (hw_info->hw_mode == MODE_BIT_36)
++ ul_cfg |= UL_CFG_BIT_MODE_36;
++
++ iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
++ /* Disable TX and RX invalid address check */
++ iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
++ iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
++}
++
++void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
++ hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ iowrite32(val, reg);
++}
++
++void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
++{
++ /* Enable the TX & RX interrupts */
++ iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
++ iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
++ /* Enable the empty queue interrupt */
++ iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
++ iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
++}
++
++void t7xx_cldma_hw_reset(void __iomem *ao_base)
++{
++ u32 val;
++
++ val = ioread32(ao_base + REG_INFRA_RST2_SET);
++ val |= RST2_PMIC_SW_RST_SET;
++ iowrite32(val, ao_base + REG_INFRA_RST2_SET);
++ val = ioread32(ao_base + REG_INFRA_RST4_SET);
++ val |= RST4_CLDMA1_SW_RST_SET;
++ iowrite32(val, ao_base + REG_INFRA_RST4_SET);
++ udelay(1);
++
++ val = ioread32(ao_base + REG_INFRA_RST4_CLR);
++ val |= RST4_CLDMA1_SW_RST_CLR;
++ iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
++ val = ioread32(ao_base + REG_INFRA_RST2_CLR);
++ val |= RST2_PMIC_SW_RST_CLR;
++ iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
++}
++
++bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno)
++{
++ u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE;
++
++ return ioread64(hw_info->ap_pdn_base + offset);
++}
++
++void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address,
++ enum mtk_txrx tx_rx)
++{
++ u32 offset = qno * ADDR_SIZE;
++ void __iomem *reg;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 :
++ hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;
++ iowrite64(address, reg + offset);
++}
++
++void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *base = hw_info->ap_pdn_base;
++
++ if (tx_rx == MTK_RX)
++ iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
++ else
++ iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
++}
++
++unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 mask, val;
++
++ mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS :
++ hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;
++ val = ioread32(reg);
++
++ return val & mask;
++}
++
++void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
++{
++ unsigned int ch_id;
++
++ ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
++ ch_id &= bitmask;
++ /* Clear the ch IDs in the TX interrupt status register */
++ iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
++ ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
++}
++
++void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
++{
++ unsigned int ch_id;
++
++ ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
++ ch_id &= bitmask;
++ /* Clear the ch IDs in the RX interrupt status register */
++ iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
++ ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
++}
++
++unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;
++ val = ioread32(reg);
++ return val & bitmask;
++}
++
++void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ iowrite32(val, reg);
++}
++
++void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ iowrite32(val << EQ_STA_BIT_OFFSET, reg);
++}
++
++void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ iowrite32(val, reg);
++}
++
++void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
++ iowrite32(val << EQ_STA_BIT_OFFSET, reg);
++}
++
++/**
++ * t7xx_cldma_hw_init() - Initialize CLDMA HW.
++ * @hw_info: Pointer to struct t7xx_cldma_hw.
++ *
++ * Write uplink and downlink configuration to CLDMA HW.
++ */
++void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info)
++{
++ u32 ul_cfg, dl_cfg;
++
++ ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
++ dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
++ /* Configure the DRAM address mode */
++ ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
++ dl_cfg &= ~DL_CFG_BIT_MODE_MASK;
++
++ if (hw_info->hw_mode == MODE_BIT_64) {
++ ul_cfg |= UL_CFG_BIT_MODE_64;
++ dl_cfg |= DL_CFG_BIT_MODE_64;
++ } else if (hw_info->hw_mode == MODE_BIT_40) {
++ ul_cfg |= UL_CFG_BIT_MODE_40;
++ dl_cfg |= DL_CFG_BIT_MODE_40;
++ } else if (hw_info->hw_mode == MODE_BIT_36) {
++ ul_cfg |= UL_CFG_BIT_MODE_36;
++ dl_cfg |= DL_CFG_BIT_MODE_36;
++ }
++
++ iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
++ dl_cfg |= DL_CFG_UP_HW_LAST;
++ iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
++ iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
++ iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
++ iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
++ iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
++}
++
++void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :
++ hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;
++ iowrite32(CLDMA_ALL_Q, reg);
++}
++
++void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
++{
++ void __iomem *reg;
++
++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
++ iowrite32(TXRX_STATUS_BITMASK, reg);
++ iowrite32(EMPTY_STATUS_BITMASK, reg);
++}
+diff --git a/drivers/net/wwan/t7xx/t7xx_cldma.h b/drivers/net/wwan/t7xx/t7xx_cldma.h
+new file mode 100644
+index 000000000000..8949e8377fb0
+--- /dev/null
++++ b/drivers/net/wwan/t7xx/t7xx_cldma.h
+@@ -0,0 +1,180 @@
++/* SPDX-License-Identifier: GPL-2.0-only
++ *
++ * Copyright (c) 2021, MediaTek Inc.
++ * Copyright (c) 2021-2022, Intel Corporation.
++ *
++ * Authors:
++ * Haijun Liu <haijun.liu@mediatek.com>
++ * Moises Veleta <moises.veleta@intel.com>
++ * Ricardo Martinez <ricardo.martinez@linux.intel.com>
++ *
++ * Contributors:
++ * Amir Hanania <amir.hanania@intel.com>
++ * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
++ * Sreehari Kancharla <sreehari.kancharla@intel.com>
++ */
++
++#ifndef __T7XX_CLDMA_H__
++#define __T7XX_CLDMA_H__
++
++#include <linux/bits.h>
++#include <linux/types.h>
++
++#define CLDMA_TXQ_NUM 8
++#define CLDMA_RXQ_NUM 8
++#define CLDMA_ALL_Q GENMASK(7, 0)
++
++/* Interrupt status bits */
++#define EMPTY_STATUS_BITMASK GENMASK(15, 8)
++#define TXRX_STATUS_BITMASK GENMASK(7, 0)
++#define EQ_STA_BIT_OFFSET 8
++#define L2_INT_BIT_COUNT 16
++#define EQ_STA_BIT(index) (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK)
++
++#define TQ_ERR_INT_BITMASK GENMASK(23, 16)
++#define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
++
++#define RQ_ERR_INT_BITMASK GENMASK(23, 16)
++#define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
++
++#define CLDMA0_AO_BASE 0x10049000
++#define CLDMA0_PD_BASE 0x1021d000
++#define CLDMA1_AO_BASE 0x1004b000
++#define CLDMA1_PD_BASE 0x1021f000
++
++#define CLDMA_R_AO_BASE 0x10023000
++#define CLDMA_R_PD_BASE 0x1023d000
++
++/* CLDMA TX */
++#define REG_CLDMA_UL_START_ADDRL_0 0x0004
++#define REG_CLDMA_UL_START_ADDRH_0 0x0008
++#define REG_CLDMA_UL_CURRENT_ADDRL_0 0x0044
++#define REG_CLDMA_UL_CURRENT_ADDRH_0 0x0048
++#define REG_CLDMA_UL_STATUS 0x0084
++#define REG_CLDMA_UL_START_CMD 0x0088
++#define REG_CLDMA_UL_RESUME_CMD 0x008c
++#define REG_CLDMA_UL_STOP_CMD 0x0090
++#define REG_CLDMA_UL_ERROR 0x0094
++#define REG_CLDMA_UL_CFG 0x0098
++#define UL_CFG_BIT_MODE_36 BIT(5)
++#define UL_CFG_BIT_MODE_40 BIT(6)
++#define UL_CFG_BIT_MODE_64 BIT(7)
++#define UL_CFG_BIT_MODE_MASK GENMASK(7, 5)
++
++#define REG_CLDMA_UL_MEM 0x009c
++#define UL_MEM_CHECK_DIS BIT(0)
++
++/* CLDMA RX */
++#define REG_CLDMA_DL_START_CMD 0x05bc
++#define REG_CLDMA_DL_RESUME_CMD 0x05c0
++#define REG_CLDMA_DL_STOP_CMD 0x05c4
++#define REG_CLDMA_DL_MEM 0x0508
++#define DL_MEM_CHECK_DIS BIT(0)
++
++#define REG_CLDMA_DL_CFG 0x0404
++#define DL_CFG_UP_HW_LAST BIT(2)
++#define DL_CFG_BIT_MODE_36 BIT(10)
++#define DL_CFG_BIT_MODE_40 BIT(11)
++#define DL_CFG_BIT_MODE_64 BIT(12)
++#define DL_CFG_BIT_MODE_MASK GENMASK(12, 10)
++
++#define REG_CLDMA_DL_START_ADDRL_0 0x0478
++#define REG_CLDMA_DL_START_ADDRH_0 0x047c
++#define REG_CLDMA_DL_CURRENT_ADDRL_0 0x04b8
++#define REG_CLDMA_DL_CURRENT_ADDRH_0 0x04bc
++#define REG_CLDMA_DL_STATUS 0x04f8
++
++/* CLDMA MISC */
++#define REG_CLDMA_L2TISAR0 0x0810
++#define REG_CLDMA_L2TISAR1 0x0814
++#define REG_CLDMA_L2TIMR0 0x0818
++#define REG_CLDMA_L2TIMR1 0x081c
++#define REG_CLDMA_L2TIMCR0 0x0820
++#define REG_CLDMA_L2TIMCR1 0x0824
++#define REG_CLDMA_L2TIMSR0 0x0828
++#define REG_CLDMA_L2TIMSR1 0x082c
++#define REG_CLDMA_L3TISAR0 0x0830
++#define REG_CLDMA_L3TISAR1 0x0834
++#define REG_CLDMA_L2RISAR0 0x0850
++#define REG_CLDMA_L2RISAR1 0x0854
++#define REG_CLDMA_L3RISAR0 0x0870
++#define REG_CLDMA_L3RISAR1 0x0874
++#define REG_CLDMA_IP_BUSY 0x08b4
++#define IP_BUSY_WAKEUP BIT(0)
++#define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0)
++#define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0)
++
++/* CLDMA MISC */
++#define REG_CLDMA_L2RIMR0 0x0858
++#define REG_CLDMA_L2RIMR1 0x085c
++#define REG_CLDMA_L2RIMCR0 0x0860
++#define REG_CLDMA_L2RIMCR1 0x0864
++#define REG_CLDMA_L2RIMSR0 0x0868
++#define REG_CLDMA_L2RIMSR1 0x086c
++#define REG_CLDMA_BUSY_MASK 0x0954
++#define BUSY_MASK_PCIE BIT(0)
++#define BUSY_MASK_AP BIT(1)
++#define BUSY_MASK_MD BIT(2)
++
++#define REG_CLDMA_INT_MASK 0x0960
++
++/* CLDMA RESET */
++#define REG_INFRA_RST4_SET 0x0730
++#define RST4_CLDMA1_SW_RST_SET BIT(20)
++
++#define REG_INFRA_RST4_CLR 0x0734
++#define RST4_CLDMA1_SW_RST_CLR BIT(20)
++
++#define REG_INFRA_RST2_SET 0x0140
++#define RST2_PMIC_SW_RST_SET BIT(18)
++
++#define REG_INFRA_RST2_CLR 0x0144
++#define RST2_PMIC_SW_RST_CLR BIT(18)
++
++enum mtk_txrx {
++ MTK_TX,
++ MTK_RX,
++};
++
++enum t7xx_hw_mode {
++ MODE_BIT_32,
++ MODE_BIT_36,
++ MODE_BIT_40,
++ MODE_BIT_64,
++};
++
++struct t7xx_cldma_hw {
++ enum t7xx_hw_mode hw_mode;
++ void __iomem *ap_ao_base;
++ void __iomem *ap_pdn_base;
++ u32 phy_interrupt_id;
++};
++
++void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx);
++unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info);
++void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info);
++void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
++void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
++void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info,
++ unsigned int qno, u64 address, enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_reset(void __iomem *ao_base);
++void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
++unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
++ enum mtk_txrx tx_rx);
++void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info);
++void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info);
++bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno);
++#endif
+diff --git a/drivers/net/wwan/t7xx/t7xx_hif_cldma.c b/drivers/net/wwan/t7xx/t7xx_hif_cldma.c
+new file mode 100644
+index 000000000000..c756b1d0b519
+--- /dev/null
++++ b/drivers/net/wwan/t7xx/t7xx_hif_cldma.c
+@@ -0,0 +1,1192 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2021, MediaTek Inc.
++ * Copyright (c) 2021-2022, Intel Corporation.
++ *
++ * Authors:
++ * Amir Hanania <amir.hanania@intel.com>
++ * Haijun Liu <haijun.liu@mediatek.com>
++ * Moises Veleta <moises.veleta@intel.com>
++ * Ricardo Martinez <ricardo.martinez@linux.intel.com>
++ * Sreehari Kancharla <sreehari.kancharla@intel.com>
++ *
++ * Contributors:
++ * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
++ * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
++ * Eliot Lee <eliot.lee@intel.com>
++ */
++
++#include <linux/bits.h>
++#include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dmapool.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-direction.h>
++#include <linux/gfp.h>
++#include <linux/io.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/iopoll.h>
++#include <linux/irqreturn.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/list.h>
++#include <linux/netdevice.h>
++#include <linux/pci.h>
++#include <linux/sched.h>
++#include <linux/skbuff.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++
++#include "t7xx_cldma.h"
++#include "t7xx_hif_cldma.h"
++#include "t7xx_mhccif.h"
++#include "t7xx_pci.h"
++#include "t7xx_pcie_mac.h"
++#include "t7xx_reg.h"
++#include "t7xx_state_monitor.h"
++
++#define MAX_TX_BUDGET 16
++#define MAX_RX_BUDGET 16
++
++#define CHECK_Q_STOP_TIMEOUT_US 1000000
++#define CHECK_Q_STOP_STEP_US 10000
++
++#define CLDMA_JUMBO_BUFF_SZ 64528 /* 63kB + CCCI header */
++
++static void md_cd_queue_struct_reset(struct cldma_queue *queue, struct cldma_ctrl *md_ctrl,
++ enum mtk_txrx tx_rx, unsigned int index)
++{
++ queue->dir = tx_rx;
++ queue->index = index;
++ queue->md_ctrl = md_ctrl;
++ queue->tr_ring = NULL;
++ queue->tr_done = NULL;
++ queue->tx_next = NULL;
++}
++
++static void md_cd_queue_struct_init(struct cldma_queue *queue, struct cldma_ctrl *md_ctrl,
++ enum mtk_txrx tx_rx, unsigned int index)
++{
++ md_cd_queue_struct_reset(queue, md_ctrl, tx_rx, index);
++ init_waitqueue_head(&queue->req_wq);
++ spin_lock_init(&queue->ring_lock);
++}
++
++static void t7xx_cldma_gpd_set_data_ptr(struct cldma_gpd *gpd, dma_addr_t data_ptr)
++{
++ gpd->data_buff_bd_ptr_h = cpu_to_le32(upper_32_bits(data_ptr));
++ gpd->data_buff_bd_ptr_l = cpu_to_le32(lower_32_bits(data_ptr));
++}
++
++static void t7xx_cldma_gpd_set_next_ptr(struct cldma_gpd *gpd, dma_addr_t next_ptr)
++{
++ gpd->next_gpd_ptr_h = cpu_to_le32(upper_32_bits(next_ptr));
++ gpd->next_gpd_ptr_l = cpu_to_le32(lower_32_bits(next_ptr));
++}
++
++static int t7xx_cldma_alloc_and_map_skb(struct cldma_ctrl *md_ctrl, struct cldma_request *req,
++ size_t size)
++{
++ req->skb = __dev_alloc_skb(size, GFP_KERNEL);
++ if (!req->skb)
++ return -ENOMEM;
++
++ req->mapped_buff = dma_map_single(md_ctrl->dev, req->skb->data,
++ skb_data_area_size(req->skb), DMA_FROM_DEVICE);
++ if (dma_mapping_error(md_ctrl->dev, req->mapped_buff)) {
++ dev_kfree_skb_any(req->skb);
++ req->skb = NULL;
++ req->mapped_buff = 0;
++ dev_err(md_ctrl->dev, "DMA mapping failed\n");
++ return -ENOMEM;
++ }
++
++ return 0;
++}
++
++static int t7xx_cldma_gpd_rx_from_q(struct cldma_queue *queue, int budget, bool *over_budget)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ unsigned int hwo_polling_count = 0;
++ struct t7xx_cldma_hw *hw_info;
++ bool rx_not_done = true;
++ unsigned long flags;
++ int count = 0;
++
++ hw_info = &md_ctrl->hw_info;
++
++ do {
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ struct sk_buff *skb;
++ int ret;
++
++ req = queue->tr_done;
++ if (!req)
++ return -ENODATA;
++
++ gpd = req->gpd;
++ if ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) {
++ dma_addr_t gpd_addr;
++
++ if (!pci_device_is_present(to_pci_dev(md_ctrl->dev))) {
++ dev_err(md_ctrl->dev, "PCIe Link disconnected\n");
++ return -ENODEV;
++ }
++
++ gpd_addr = ioread64(hw_info->ap_pdn_base + REG_CLDMA_DL_CURRENT_ADDRL_0 +
++ queue->index * sizeof(u64));
++ if (req->gpd_addr == gpd_addr || hwo_polling_count++ >= 100)
++ return 0;
++
++ udelay(1);
++ continue;
++ }
++
++ hwo_polling_count = 0;
++ skb = req->skb;
++
++ if (req->mapped_buff) {
++ dma_unmap_single(md_ctrl->dev, req->mapped_buff,
++ skb_data_area_size(skb), DMA_FROM_DEVICE);
++ req->mapped_buff = 0;
++ }
++
++ skb->len = 0;
++ skb_reset_tail_pointer(skb);
++ skb_put(skb, le16_to_cpu(gpd->data_buff_len));
++
++ ret = md_ctrl->recv_skb(queue, skb);
++ /* Break processing, will try again later */
++ if (ret < 0)
++ return ret;
++
++ req->skb = NULL;
++ t7xx_cldma_gpd_set_data_ptr(gpd, 0);
++
++ spin_lock_irqsave(&queue->ring_lock, flags);
++ queue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++ req = queue->rx_refill;
++
++ ret = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, queue->tr_ring->pkt_size);
++ if (ret)
++ return ret;
++
++ gpd = req->gpd;
++ t7xx_cldma_gpd_set_data_ptr(gpd, req->mapped_buff);
++ gpd->data_buff_len = 0;
++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO;
++
++ spin_lock_irqsave(&queue->ring_lock, flags);
++ queue->rx_refill = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++
++ rx_not_done = ++count < budget || !need_resched();
++ } while (rx_not_done);
++
++ *over_budget = true;
++ return 0;
++}
++
++static int t7xx_cldma_gpd_rx_collect(struct cldma_queue *queue, int budget)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ struct t7xx_cldma_hw *hw_info;
++ unsigned int pending_rx_int;
++ bool over_budget = false;
++ unsigned long flags;
++ int ret;
++
++ hw_info = &md_ctrl->hw_info;
++
++ do {
++ ret = t7xx_cldma_gpd_rx_from_q(queue, budget, &over_budget);
++ if (ret == -ENODATA)
++ return 0;
++ else if (ret)
++ return ret;
++
++ pending_rx_int = 0;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (md_ctrl->rxq_active & BIT(queue->index)) {
++ if (!t7xx_cldma_hw_queue_status(hw_info, queue->index, MTK_RX))
++ t7xx_cldma_hw_resume_queue(hw_info, queue->index, MTK_RX);
++
++ pending_rx_int = t7xx_cldma_hw_int_status(hw_info, BIT(queue->index),
++ MTK_RX);
++ if (pending_rx_int) {
++ t7xx_cldma_hw_rx_done(hw_info, pending_rx_int);
++
++ if (over_budget) {
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ return -EAGAIN;
++ }
++ }
++ }
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ } while (pending_rx_int);
++
++ return 0;
++}
++
++static void t7xx_cldma_rx_done(struct work_struct *work)
++{
++ struct cldma_queue *queue = container_of(work, struct cldma_queue, cldma_work);
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ int value;
++
++ value = t7xx_cldma_gpd_rx_collect(queue, queue->budget);
++ if (value && md_ctrl->rxq_active & BIT(queue->index)) {
++ queue_work(queue->worker, &queue->cldma_work);
++ return;
++ }
++
++ t7xx_cldma_clear_ip_busy(&md_ctrl->hw_info);
++ t7xx_cldma_hw_irq_en_txrx(&md_ctrl->hw_info, queue->index, MTK_RX);
++ t7xx_cldma_hw_irq_en_eq(&md_ctrl->hw_info, queue->index, MTK_RX);
++}
++
++static int t7xx_cldma_gpd_tx_collect(struct cldma_queue *queue)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ unsigned int dma_len, count = 0;
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ unsigned long flags;
++ dma_addr_t dma_free;
++ struct sk_buff *skb;
++
++ while (!kthread_should_stop()) {
++ spin_lock_irqsave(&queue->ring_lock, flags);
++ req = queue->tr_done;
++ if (!req) {
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++ break;
++ }
++ gpd = req->gpd;
++ if ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) {
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++ break;
++ }
++ queue->budget++;
++ dma_free = req->mapped_buff;
++ dma_len = le16_to_cpu(gpd->data_buff_len);
++ skb = req->skb;
++ req->skb = NULL;
++ queue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++
++ count++;
++ dma_unmap_single(md_ctrl->dev, dma_free, dma_len, DMA_TO_DEVICE);
++ dev_kfree_skb_any(skb);
++ }
++
++ if (count)
++ wake_up_nr(&queue->req_wq, count);
++
++ return count;
++}
++
++static void t7xx_cldma_txq_empty_hndl(struct cldma_queue *queue)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ struct cldma_request *req;
++ dma_addr_t ul_curr_addr;
++ unsigned long flags;
++ bool pending_gpd;
++
++ if (!(md_ctrl->txq_active & BIT(queue->index)))
++ return;
++
++ spin_lock_irqsave(&queue->ring_lock, flags);
++ req = list_prev_entry_circular(queue->tx_next, &queue->tr_ring->gpd_ring, entry);
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++
++ pending_gpd = (req->gpd->flags & GPD_FLAGS_HWO) && req->skb;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (pending_gpd) {
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++
++ /* Check current processing TGPD, 64-bit address is in a table by Q index */
++ ul_curr_addr = ioread64(hw_info->ap_pdn_base + REG_CLDMA_UL_CURRENT_ADDRL_0 +
++ queue->index * sizeof(u64));
++ if (req->gpd_addr != ul_curr_addr) {
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ dev_err(md_ctrl->dev, "CLDMA%d queue %d is not empty\n",
++ md_ctrl->hif_id, queue->index);
++ return;
++ }
++
++ t7xx_cldma_hw_resume_queue(hw_info, queue->index, MTK_TX);
++ }
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++}
++
++static void t7xx_cldma_tx_done(struct work_struct *work)
++{
++ struct cldma_queue *queue = container_of(work, struct cldma_queue, cldma_work);
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ struct t7xx_cldma_hw *hw_info;
++ unsigned int l2_tx_int;
++ unsigned long flags;
++
++ hw_info = &md_ctrl->hw_info;
++ t7xx_cldma_gpd_tx_collect(queue);
++ l2_tx_int = t7xx_cldma_hw_int_status(hw_info, BIT(queue->index) | EQ_STA_BIT(queue->index),
++ MTK_TX);
++ if (l2_tx_int & EQ_STA_BIT(queue->index)) {
++ t7xx_cldma_hw_tx_done(hw_info, EQ_STA_BIT(queue->index));
++ t7xx_cldma_txq_empty_hndl(queue);
++ }
++
++ if (l2_tx_int & BIT(queue->index)) {
++ t7xx_cldma_hw_tx_done(hw_info, BIT(queue->index));
++ queue_work(queue->worker, &queue->cldma_work);
++ return;
++ }
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (md_ctrl->txq_active & BIT(queue->index)) {
++ t7xx_cldma_clear_ip_busy(hw_info);
++ t7xx_cldma_hw_irq_en_eq(hw_info, queue->index, MTK_TX);
++ t7xx_cldma_hw_irq_en_txrx(hw_info, queue->index, MTK_TX);
++ }
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++}
++
++static void t7xx_cldma_ring_free(struct cldma_ctrl *md_ctrl,
++ struct cldma_ring *ring, enum dma_data_direction tx_rx)
++{
++ struct cldma_request *req_cur, *req_next;
++
++ list_for_each_entry_safe(req_cur, req_next, &ring->gpd_ring, entry) {
++ if (req_cur->mapped_buff && req_cur->skb) {
++ dma_unmap_single(md_ctrl->dev, req_cur->mapped_buff,
++ skb_data_area_size(req_cur->skb), tx_rx);
++ req_cur->mapped_buff = 0;
++ }
++
++ dev_kfree_skb_any(req_cur->skb);
++
++ if (req_cur->gpd)
++ dma_pool_free(md_ctrl->gpd_dmapool, req_cur->gpd, req_cur->gpd_addr);
++
++ list_del(&req_cur->entry);
++ kfree(req_cur);
++ }
++}
++
++static struct cldma_request *t7xx_alloc_rx_request(struct cldma_ctrl *md_ctrl, size_t pkt_size)
++{
++ struct cldma_request *req;
++ int val;
++
++ req = kzalloc(sizeof(*req), GFP_KERNEL);
++ if (!req)
++ return NULL;
++
++ req->gpd = dma_pool_zalloc(md_ctrl->gpd_dmapool, GFP_KERNEL, &req->gpd_addr);
++ if (!req->gpd)
++ goto err_free_req;
++
++ val = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, pkt_size);
++ if (val)
++ goto err_free_pool;
++
++ return req;
++
++err_free_pool:
++ dma_pool_free(md_ctrl->gpd_dmapool, req->gpd, req->gpd_addr);
++
++err_free_req:
++ kfree(req);
++
++ return NULL;
++}
++
++static int t7xx_cldma_rx_ring_init(struct cldma_ctrl *md_ctrl, struct cldma_ring *ring)
++{
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ int i;
++
++ INIT_LIST_HEAD(&ring->gpd_ring);
++ ring->length = MAX_RX_BUDGET;
++
++ for (i = 0; i < ring->length; i++) {
++ req = t7xx_alloc_rx_request(md_ctrl, ring->pkt_size);
++ if (!req) {
++ t7xx_cldma_ring_free(md_ctrl, ring, DMA_FROM_DEVICE);
++ return -ENOMEM;
++ }
++
++ gpd = req->gpd;
++ t7xx_cldma_gpd_set_data_ptr(gpd, req->mapped_buff);
++ gpd->rx_data_allow_len = cpu_to_le16(ring->pkt_size);
++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO;
++ INIT_LIST_HEAD(&req->entry);
++ list_add_tail(&req->entry, &ring->gpd_ring);
++ }
++
++ /* Link previous GPD to next GPD, circular */
++ list_for_each_entry(req, &ring->gpd_ring, entry) {
++ t7xx_cldma_gpd_set_next_ptr(gpd, req->gpd_addr);
++ gpd = req->gpd;
++ }
++
++ return 0;
++}
++
++static struct cldma_request *t7xx_alloc_tx_request(struct cldma_ctrl *md_ctrl)
++{
++ struct cldma_request *req;
++
++ req = kzalloc(sizeof(*req), GFP_KERNEL);
++ if (!req)
++ return NULL;
++
++ req->gpd = dma_pool_zalloc(md_ctrl->gpd_dmapool, GFP_KERNEL, &req->gpd_addr);
++ if (!req->gpd) {
++ kfree(req);
++ return NULL;
++ }
++
++ return req;
++}
++
++static int t7xx_cldma_tx_ring_init(struct cldma_ctrl *md_ctrl, struct cldma_ring *ring)
++{
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ int i;
++
++ INIT_LIST_HEAD(&ring->gpd_ring);
++ ring->length = MAX_TX_BUDGET;
++
++ for (i = 0; i < ring->length; i++) {
++ req = t7xx_alloc_tx_request(md_ctrl);
++ if (!req) {
++ t7xx_cldma_ring_free(md_ctrl, ring, DMA_TO_DEVICE);
++ return -ENOMEM;
++ }
++
++ gpd = req->gpd;
++ gpd->flags = GPD_FLAGS_IOC;
++ INIT_LIST_HEAD(&req->entry);
++ list_add_tail(&req->entry, &ring->gpd_ring);
++ }
++
++ /* Link previous GPD to next GPD, circular */
++ list_for_each_entry(req, &ring->gpd_ring, entry) {
++ t7xx_cldma_gpd_set_next_ptr(gpd, req->gpd_addr);
++ gpd = req->gpd;
++ }
++
++ return 0;
++}
++
++/**
++ * t7xx_cldma_q_reset() - Reset CLDMA request pointers to their initial values.
++ * @queue: Pointer to the queue structure.
++ *
++ * Called with ring_lock (unless called during initialization phase)
++ */
++static void t7xx_cldma_q_reset(struct cldma_queue *queue)
++{
++ struct cldma_request *req;
++
++ req = list_first_entry(&queue->tr_ring->gpd_ring, struct cldma_request, entry);
++ queue->tr_done = req;
++ queue->budget = queue->tr_ring->length;
++
++ if (queue->dir == MTK_TX)
++ queue->tx_next = req;
++ else
++ queue->rx_refill = req;
++}
++
++static void t7xx_cldma_rxq_init(struct cldma_queue *queue)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++
++ queue->dir = MTK_RX;
++ queue->tr_ring = &md_ctrl->rx_ring[queue->index];
++ t7xx_cldma_q_reset(queue);
++}
++
++static void t7xx_cldma_txq_init(struct cldma_queue *queue)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++
++ queue->dir = MTK_TX;
++ queue->tr_ring = &md_ctrl->tx_ring[queue->index];
++ t7xx_cldma_q_reset(queue);
++}
++
++static void t7xx_cldma_enable_irq(struct cldma_ctrl *md_ctrl)
++{
++ t7xx_pcie_mac_set_int(md_ctrl->t7xx_dev, md_ctrl->hw_info.phy_interrupt_id);
++}
++
++static void t7xx_cldma_disable_irq(struct cldma_ctrl *md_ctrl)
++{
++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, md_ctrl->hw_info.phy_interrupt_id);
++}
++
++static void t7xx_cldma_irq_work_cb(struct cldma_ctrl *md_ctrl)
++{
++ unsigned long l2_tx_int_msk, l2_rx_int_msk, l2_tx_int, l2_rx_int, val;
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ int i;
++
++ /* L2 raw interrupt status */
++ l2_tx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
++ l2_rx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
++ l2_tx_int_msk = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TIMR0);
++ l2_rx_int_msk = ioread32(hw_info->ap_ao_base + REG_CLDMA_L2RIMR0);
++ l2_tx_int &= ~l2_tx_int_msk;
++ l2_rx_int &= ~l2_rx_int_msk;
++
++ if (l2_tx_int) {
++ if (l2_tx_int & (TQ_ERR_INT_BITMASK | TQ_ACTIVE_START_ERR_INT_BITMASK)) {
++ /* Read and clear L3 TX interrupt status */
++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0);
++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0);
++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1);
++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1);
++ }
++
++ t7xx_cldma_hw_tx_done(hw_info, l2_tx_int);
++ if (l2_tx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) {
++ for_each_set_bit(i, &l2_tx_int, L2_INT_BIT_COUNT) {
++ if (i < CLDMA_TXQ_NUM) {
++ t7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_TX);
++ t7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_TX);
++ queue_work(md_ctrl->txq[i].worker,
++ &md_ctrl->txq[i].cldma_work);
++ } else {
++ t7xx_cldma_txq_empty_hndl(&md_ctrl->txq[i - CLDMA_TXQ_NUM]);
++ }
++ }
++ }
++ }
++
++ if (l2_rx_int) {
++ if (l2_rx_int & (RQ_ERR_INT_BITMASK | RQ_ACTIVE_START_ERR_INT_BITMASK)) {
++ /* Read and clear L3 RX interrupt status */
++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0);
++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0);
++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1);
++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1);
++ }
++
++ t7xx_cldma_hw_rx_done(hw_info, l2_rx_int);
++ if (l2_rx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) {
++ l2_rx_int |= l2_rx_int >> CLDMA_RXQ_NUM;
++ for_each_set_bit(i, &l2_rx_int, CLDMA_RXQ_NUM) {
++ t7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_RX);
++ t7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_RX);
++ queue_work(md_ctrl->rxq[i].worker, &md_ctrl->rxq[i].cldma_work);
++ }
++ }
++ }
++}
++
++static bool t7xx_cldma_qs_are_active(struct cldma_ctrl *md_ctrl)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ unsigned int tx_active;
++ unsigned int rx_active;
++
++ if (!pci_device_is_present(to_pci_dev(md_ctrl->dev)))
++ return false;
++
++ tx_active = t7xx_cldma_hw_queue_status(hw_info, CLDMA_ALL_Q, MTK_TX);
++ rx_active = t7xx_cldma_hw_queue_status(hw_info, CLDMA_ALL_Q, MTK_RX);
++
++ return tx_active || rx_active;
++}
++
++/**
++ * t7xx_cldma_stop() - Stop CLDMA.
++ * @md_ctrl: CLDMA context structure.
++ *
++ * Stop TX and RX queues. Disable L1 and L2 interrupts.
++ * Clear status registers.
++ *
++ * Return:
++ * * 0 - Success.
++ * * -ERROR - Error code from polling cldma_queues_active.
++ */
++int t7xx_cldma_stop(struct cldma_ctrl *md_ctrl)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ bool active;
++ int i, ret;
++
++ md_ctrl->rxq_active = 0;
++ t7xx_cldma_hw_stop_all_qs(hw_info, MTK_RX);
++ md_ctrl->txq_active = 0;
++ t7xx_cldma_hw_stop_all_qs(hw_info, MTK_TX);
++ md_ctrl->txq_started = 0;
++ t7xx_cldma_disable_irq(md_ctrl);
++ t7xx_cldma_hw_stop(hw_info, MTK_RX);
++ t7xx_cldma_hw_stop(hw_info, MTK_TX);
++ t7xx_cldma_hw_tx_done(hw_info, CLDMA_L2TISAR0_ALL_INT_MASK);
++ t7xx_cldma_hw_rx_done(hw_info, CLDMA_L2RISAR0_ALL_INT_MASK);
++
++ if (md_ctrl->is_late_init) {
++ for (i = 0; i < CLDMA_TXQ_NUM; i++)
++ flush_work(&md_ctrl->txq[i].cldma_work);
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++)
++ flush_work(&md_ctrl->rxq[i].cldma_work);
++ }
++
++ ret = read_poll_timeout(t7xx_cldma_qs_are_active, active, !active, CHECK_Q_STOP_STEP_US,
++ CHECK_Q_STOP_TIMEOUT_US, true, md_ctrl);
++ if (ret)
++ dev_err(md_ctrl->dev, "Could not stop CLDMA%d queues", md_ctrl->hif_id);
++
++ return ret;
++}
++
++static void t7xx_cldma_late_release(struct cldma_ctrl *md_ctrl)
++{
++ int i;
++
++ if (!md_ctrl->is_late_init)
++ return;
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++)
++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->tx_ring[i], DMA_TO_DEVICE);
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++)
++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->rx_ring[i], DMA_FROM_DEVICE);
++
++ dma_pool_destroy(md_ctrl->gpd_dmapool);
++ md_ctrl->gpd_dmapool = NULL;
++ md_ctrl->is_late_init = false;
++}
++
++void t7xx_cldma_reset(struct cldma_ctrl *md_ctrl)
++{
++ unsigned long flags;
++ int i;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ md_ctrl->txq_active = 0;
++ md_ctrl->rxq_active = 0;
++ t7xx_cldma_disable_irq(md_ctrl);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++) {
++ cancel_work_sync(&md_ctrl->txq[i].cldma_work);
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ md_cd_queue_struct_reset(&md_ctrl->txq[i], md_ctrl, MTK_TX, i);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ }
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++) {
++ cancel_work_sync(&md_ctrl->rxq[i].cldma_work);
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ md_cd_queue_struct_reset(&md_ctrl->rxq[i], md_ctrl, MTK_RX, i);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ }
++
++ t7xx_cldma_late_release(md_ctrl);
++}
++
++/**
++ * t7xx_cldma_start() - Start CLDMA.
++ * @md_ctrl: CLDMA context structure.
++ *
++ * Set TX/RX start address.
++ * Start all RX queues and enable L2 interrupt.
++ */
++void t7xx_cldma_start(struct cldma_ctrl *md_ctrl)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (md_ctrl->is_late_init) {
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ int i;
++
++ t7xx_cldma_enable_irq(md_ctrl);
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++) {
++ if (md_ctrl->txq[i].tr_done)
++ t7xx_cldma_hw_set_start_addr(hw_info, i,
++ md_ctrl->txq[i].tr_done->gpd_addr,
++ MTK_TX);
++ }
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++) {
++ if (md_ctrl->rxq[i].tr_done)
++ t7xx_cldma_hw_set_start_addr(hw_info, i,
++ md_ctrl->rxq[i].tr_done->gpd_addr,
++ MTK_RX);
++ }
++
++ /* Enable L2 interrupt */
++ t7xx_cldma_hw_start_queue(hw_info, CLDMA_ALL_Q, MTK_RX);
++ t7xx_cldma_hw_start(hw_info);
++ md_ctrl->txq_started = 0;
++ md_ctrl->txq_active |= TXRX_STATUS_BITMASK;
++ md_ctrl->rxq_active |= TXRX_STATUS_BITMASK;
++ }
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++}
++
++static void t7xx_cldma_clear_txq(struct cldma_ctrl *md_ctrl, int qnum)
++{
++ struct cldma_queue *txq = &md_ctrl->txq[qnum];
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ unsigned long flags;
++
++ spin_lock_irqsave(&txq->ring_lock, flags);
++ t7xx_cldma_q_reset(txq);
++ list_for_each_entry(req, &txq->tr_ring->gpd_ring, entry) {
++ gpd = req->gpd;
++ gpd->flags &= ~GPD_FLAGS_HWO;
++ t7xx_cldma_gpd_set_data_ptr(gpd, 0);
++ gpd->data_buff_len = 0;
++ dev_kfree_skb_any(req->skb);
++ req->skb = NULL;
++ }
++ spin_unlock_irqrestore(&txq->ring_lock, flags);
++}
++
++static int t7xx_cldma_clear_rxq(struct cldma_ctrl *md_ctrl, int qnum)
++{
++ struct cldma_queue *rxq = &md_ctrl->rxq[qnum];
++ struct cldma_request *req;
++ struct cldma_gpd *gpd;
++ unsigned long flags;
++ int ret = 0;
++
++ spin_lock_irqsave(&rxq->ring_lock, flags);
++ t7xx_cldma_q_reset(rxq);
++ list_for_each_entry(req, &rxq->tr_ring->gpd_ring, entry) {
++ gpd = req->gpd;
++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO;
++ gpd->data_buff_len = 0;
++
++ if (req->skb) {
++ req->skb->len = 0;
++ skb_reset_tail_pointer(req->skb);
++ }
++ }
++
++ list_for_each_entry(req, &rxq->tr_ring->gpd_ring, entry) {
++ if (req->skb)
++ continue;
++
++ ret = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, rxq->tr_ring->pkt_size);
++ if (ret)
++ break;
++
++ t7xx_cldma_gpd_set_data_ptr(req->gpd, req->mapped_buff);
++ }
++ spin_unlock_irqrestore(&rxq->ring_lock, flags);
++
++ return ret;
++}
++
++void t7xx_cldma_clear_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx)
++{
++ int i;
++
++ if (tx_rx == MTK_TX) {
++ for (i = 0; i < CLDMA_TXQ_NUM; i++)
++ t7xx_cldma_clear_txq(md_ctrl, i);
++ } else {
++ for (i = 0; i < CLDMA_RXQ_NUM; i++)
++ t7xx_cldma_clear_rxq(md_ctrl, i);
++ }
++}
++
++void t7xx_cldma_stop_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ unsigned long flags;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ t7xx_cldma_hw_irq_dis_eq(hw_info, CLDMA_ALL_Q, tx_rx);
++ t7xx_cldma_hw_irq_dis_txrx(hw_info, CLDMA_ALL_Q, tx_rx);
++ if (tx_rx == MTK_RX)
++ md_ctrl->rxq_active &= ~TXRX_STATUS_BITMASK;
++ else
++ md_ctrl->txq_active &= ~TXRX_STATUS_BITMASK;
++ t7xx_cldma_hw_stop_all_qs(hw_info, tx_rx);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++}
++
++static int t7xx_cldma_gpd_handle_tx_request(struct cldma_queue *queue, struct cldma_request *tx_req,
++ struct sk_buff *skb)
++{
++ struct cldma_ctrl *md_ctrl = queue->md_ctrl;
++ struct cldma_gpd *gpd = tx_req->gpd;
++ unsigned long flags;
++
++ /* Update GPD */
++ tx_req->mapped_buff = dma_map_single(md_ctrl->dev, skb->data, skb->len, DMA_TO_DEVICE);
++
++ if (dma_mapping_error(md_ctrl->dev, tx_req->mapped_buff)) {
++ dev_err(md_ctrl->dev, "DMA mapping failed\n");
++ return -ENOMEM;
++ }
++
++ t7xx_cldma_gpd_set_data_ptr(gpd, tx_req->mapped_buff);
++ gpd->data_buff_len = cpu_to_le16(skb->len);
++
++ /* This lock must cover TGPD setting, as even without a resume operation,
++ * CLDMA can send next HWO=1 if last TGPD just finished.
++ */
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (md_ctrl->txq_active & BIT(queue->index))
++ gpd->flags |= GPD_FLAGS_HWO;
++
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++
++ tx_req->skb = skb;
++ return 0;
++}
++
++/* Called with cldma_lock */
++static void t7xx_cldma_hw_start_send(struct cldma_ctrl *md_ctrl, int qno,
++ struct cldma_request *prev_req)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++
++ /* Check whether the device was powered off (CLDMA start address is not set) */
++ if (!t7xx_cldma_tx_addr_is_set(hw_info, qno)) {
++ t7xx_cldma_hw_init(hw_info);
++ t7xx_cldma_hw_set_start_addr(hw_info, qno, prev_req->gpd_addr, MTK_TX);
++ md_ctrl->txq_started &= ~BIT(qno);
++ }
++
++ if (!t7xx_cldma_hw_queue_status(hw_info, qno, MTK_TX)) {
++ if (md_ctrl->txq_started & BIT(qno))
++ t7xx_cldma_hw_resume_queue(hw_info, qno, MTK_TX);
++ else
++ t7xx_cldma_hw_start_queue(hw_info, qno, MTK_TX);
++
++ md_ctrl->txq_started |= BIT(qno);
++ }
++}
++
++/**
++ * t7xx_cldma_set_recv_skb() - Set the callback to handle RX packets.
++ * @md_ctrl: CLDMA context structure.
++ * @recv_skb: Receiving skb callback.
++ */
++void t7xx_cldma_set_recv_skb(struct cldma_ctrl *md_ctrl,
++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb))
++{
++ md_ctrl->recv_skb = recv_skb;
++}
++
++/**
++ * t7xx_cldma_send_skb() - Send control data to modem.
++ * @md_ctrl: CLDMA context structure.
++ * @qno: Queue number.
++ * @skb: Socket buffer.
++ *
++ * Return:
++ * * 0 - Success.
++ * * -ENOMEM - Allocation failure.
++ * * -EINVAL - Invalid queue request.
++ * * -EIO - Queue is not active.
++ * * -ETIMEDOUT - Timeout waiting for the device to wake up.
++ */
++int t7xx_cldma_send_skb(struct cldma_ctrl *md_ctrl, int qno, struct sk_buff *skb)
++{
++ struct cldma_request *tx_req;
++ struct cldma_queue *queue;
++ unsigned long flags;
++ int ret;
++
++ if (qno >= CLDMA_TXQ_NUM)
++ return -EINVAL;
++
++ queue = &md_ctrl->txq[qno];
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ if (!(md_ctrl->txq_active & BIT(qno))) {
++ ret = -EIO;
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ goto allow_sleep;
++ }
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++
++ do {
++ spin_lock_irqsave(&queue->ring_lock, flags);
++ tx_req = queue->tx_next;
++ if (queue->budget > 0 && !tx_req->skb) {
++ struct list_head *gpd_ring = &queue->tr_ring->gpd_ring;
++
++ queue->budget--;
++ t7xx_cldma_gpd_handle_tx_request(queue, tx_req, skb);
++ queue->tx_next = list_next_entry_circular(tx_req, gpd_ring, entry);
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++
++ /* Protect the access to the modem for queues operations (resume/start)
++ * which access shared locations by all the queues.
++ * cldma_lock is independent of ring_lock which is per queue.
++ */
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ t7xx_cldma_hw_start_send(md_ctrl, qno, tx_req);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++
++ break;
++ }
++ spin_unlock_irqrestore(&queue->ring_lock, flags);
++
++ if (!t7xx_cldma_hw_queue_status(&md_ctrl->hw_info, qno, MTK_TX)) {
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ t7xx_cldma_hw_resume_queue(&md_ctrl->hw_info, qno, MTK_TX);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++ }
++
++ ret = wait_event_interruptible_exclusive(queue->req_wq, queue->budget > 0);
++ } while (!ret);
++
++allow_sleep:
++ return ret;
++}
++
++static int t7xx_cldma_late_init(struct cldma_ctrl *md_ctrl)
++{
++ char dma_pool_name[32];
++ int i, j, ret;
++
++ if (md_ctrl->is_late_init) {
++ dev_err(md_ctrl->dev, "CLDMA late init was already done\n");
++ return -EALREADY;
++ }
++
++ snprintf(dma_pool_name, sizeof(dma_pool_name), "cldma_req_hif%d", md_ctrl->hif_id);
++
++ md_ctrl->gpd_dmapool = dma_pool_create(dma_pool_name, md_ctrl->dev,
++ sizeof(struct cldma_gpd), GPD_DMAPOOL_ALIGN, 0);
++ if (!md_ctrl->gpd_dmapool) {
++ dev_err(md_ctrl->dev, "DMA pool alloc fail\n");
++ return -ENOMEM;
++ }
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++) {
++ ret = t7xx_cldma_tx_ring_init(md_ctrl, &md_ctrl->tx_ring[i]);
++ if (ret) {
++ dev_err(md_ctrl->dev, "control TX ring init fail\n");
++ goto err_free_tx_ring;
++ }
++ }
++
++ for (j = 0; j < CLDMA_RXQ_NUM; j++) {
++ md_ctrl->rx_ring[j].pkt_size = CLDMA_MTU;
++
++ if (j == CLDMA_RXQ_NUM - 1)
++ md_ctrl->rx_ring[j].pkt_size = CLDMA_JUMBO_BUFF_SZ;
++
++ ret = t7xx_cldma_rx_ring_init(md_ctrl, &md_ctrl->rx_ring[j]);
++ if (ret) {
++ dev_err(md_ctrl->dev, "Control RX ring init fail\n");
++ goto err_free_rx_ring;
++ }
++ }
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++)
++ t7xx_cldma_txq_init(&md_ctrl->txq[i]);
++
++ for (j = 0; j < CLDMA_RXQ_NUM; j++)
++ t7xx_cldma_rxq_init(&md_ctrl->rxq[j]);
++
++ md_ctrl->is_late_init = true;
++ return 0;
++
++err_free_rx_ring:
++ while (j--)
++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->rx_ring[j], DMA_FROM_DEVICE);
++
++err_free_tx_ring:
++ while (i--)
++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->tx_ring[i], DMA_TO_DEVICE);
++
++ return ret;
++}
++
++static void __iomem *t7xx_pcie_addr_transfer(void __iomem *addr, u32 addr_trs1, u32 phy_addr)
++{
++ return addr + phy_addr - addr_trs1;
++}
++
++static void t7xx_hw_info_init(struct cldma_ctrl *md_ctrl)
++{
++ struct t7xx_addr_base *pbase = &md_ctrl->t7xx_dev->base_addr;
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ u32 phy_ao_base, phy_pd_base;
++
++ if (md_ctrl->hif_id != CLDMA_ID_MD)
++ return;
++
++ phy_ao_base = CLDMA1_AO_BASE;
++ phy_pd_base = CLDMA1_PD_BASE;
++ hw_info->phy_interrupt_id = CLDMA1_INT;
++ hw_info->hw_mode = MODE_BIT_64;
++ hw_info->ap_ao_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base,
++ pbase->pcie_dev_reg_trsl_addr, phy_ao_base);
++ hw_info->ap_pdn_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base,
++ pbase->pcie_dev_reg_trsl_addr, phy_pd_base);
++}
++
++static int t7xx_cldma_default_recv_skb(struct cldma_queue *queue, struct sk_buff *skb)
++{
++ dev_kfree_skb_any(skb);
++ return 0;
++}
++
++int t7xx_cldma_alloc(enum cldma_id hif_id, struct t7xx_pci_dev *t7xx_dev)
++{
++ struct device *dev = &t7xx_dev->pdev->dev;
++ struct cldma_ctrl *md_ctrl;
++
++ md_ctrl = devm_kzalloc(dev, sizeof(*md_ctrl), GFP_KERNEL);
++ if (!md_ctrl)
++ return -ENOMEM;
++
++ md_ctrl->t7xx_dev = t7xx_dev;
++ md_ctrl->dev = dev;
++ md_ctrl->hif_id = hif_id;
++ md_ctrl->recv_skb = t7xx_cldma_default_recv_skb;
++ t7xx_hw_info_init(md_ctrl);
++ t7xx_dev->md->md_ctrl[hif_id] = md_ctrl;
++ return 0;
++}
++
++void t7xx_cldma_hif_hw_init(struct cldma_ctrl *md_ctrl)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ unsigned long flags;
++
++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags);
++ t7xx_cldma_hw_stop(hw_info, MTK_TX);
++ t7xx_cldma_hw_stop(hw_info, MTK_RX);
++ t7xx_cldma_hw_rx_done(hw_info, EMPTY_STATUS_BITMASK | TXRX_STATUS_BITMASK);
++ t7xx_cldma_hw_tx_done(hw_info, EMPTY_STATUS_BITMASK | TXRX_STATUS_BITMASK);
++ t7xx_cldma_hw_init(hw_info);
++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);
++}
++
++static irqreturn_t t7xx_cldma_isr_handler(int irq, void *data)
++{
++ struct cldma_ctrl *md_ctrl = data;
++ u32 interrupt;
++
++ interrupt = md_ctrl->hw_info.phy_interrupt_id;
++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, interrupt);
++ t7xx_cldma_irq_work_cb(md_ctrl);
++ t7xx_pcie_mac_clear_int_status(md_ctrl->t7xx_dev, interrupt);
++ t7xx_pcie_mac_set_int(md_ctrl->t7xx_dev, interrupt);
++ return IRQ_HANDLED;
++}
++
++static void t7xx_cldma_destroy_wqs(struct cldma_ctrl *md_ctrl)
++{
++ int i;
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++) {
++ if (md_ctrl->txq[i].worker) {
++ destroy_workqueue(md_ctrl->txq[i].worker);
++ md_ctrl->txq[i].worker = NULL;
++ }
++ }
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++) {
++ if (md_ctrl->rxq[i].worker) {
++ destroy_workqueue(md_ctrl->rxq[i].worker);
++ md_ctrl->rxq[i].worker = NULL;
++ }
++ }
++}
++
++/**
++ * t7xx_cldma_init() - Initialize CLDMA.
++ * @md_ctrl: CLDMA context structure.
++ *
++ * Initialize HIF TX/RX queue structure.
++ * Register CLDMA callback ISR with PCIe driver.
++ *
++ * Return:
++ * * 0 - Success.
++ * * -ERROR - Error code from failure sub-initializations.
++ */
++int t7xx_cldma_init(struct cldma_ctrl *md_ctrl)
++{
++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
++ int i;
++
++ md_ctrl->txq_active = 0;
++ md_ctrl->rxq_active = 0;
++ md_ctrl->is_late_init = false;
++
++ spin_lock_init(&md_ctrl->cldma_lock);
++
++ for (i = 0; i < CLDMA_TXQ_NUM; i++) {
++ md_cd_queue_struct_init(&md_ctrl->txq[i], md_ctrl, MTK_TX, i);
++ md_ctrl->txq[i].worker =
++ alloc_workqueue("md_hif%d_tx%d_worker",
++ WQ_UNBOUND | WQ_MEM_RECLAIM | (i ? 0 : WQ_HIGHPRI),
++ 1, md_ctrl->hif_id, i);
++ if (!md_ctrl->txq[i].worker)
++ goto err_workqueue;
++
++ INIT_WORK(&md_ctrl->txq[i].cldma_work, t7xx_cldma_tx_done);
++ }
++
++ for (i = 0; i < CLDMA_RXQ_NUM; i++) {
++ md_cd_queue_struct_init(&md_ctrl->rxq[i], md_ctrl, MTK_RX, i);
++ INIT_WORK(&md_ctrl->rxq[i].cldma_work, t7xx_cldma_rx_done);
++
++ md_ctrl->rxq[i].worker = alloc_workqueue("md_hif%d_rx%d_worker",
++ WQ_UNBOUND | WQ_MEM_RECLAIM,
++ 1, md_ctrl->hif_id, i);
++ if (!md_ctrl->rxq[i].worker)
++ goto err_workqueue;
++ }
++
++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, hw_info->phy_interrupt_id);
++ md_ctrl->t7xx_dev->intr_handler[hw_info->phy_interrupt_id] = t7xx_cldma_isr_handler;
++ md_ctrl->t7xx_dev->intr_thread[hw_info->phy_interrupt_id] = NULL;
++ md_ctrl->t7xx_dev->callback_param[hw_info->phy_interrupt_id] = md_ctrl;
++ t7xx_pcie_mac_clear_int_status(md_ctrl->t7xx_dev, hw_info->phy_interrupt_id);
++ return 0;
++
++err_workqueue:
++ t7xx_cldma_destroy_wqs(md_ctrl);
++ return -ENOMEM;
++}
++
++void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl)
++{
++ t7xx_cldma_late_release(md_ctrl);
++ t7xx_cldma_late_init(md_ctrl);
++}
++
++void t7xx_cldma_exit(struct cldma_ctrl *md_ctrl)
++{
++ t7xx_cldma_stop(md_ctrl);
++ t7xx_cldma_late_release(md_ctrl);
++ t7xx_cldma_destroy_wqs(md_ctrl);
++}
+diff --git a/drivers/net/wwan/t7xx/t7xx_hif_cldma.h b/drivers/net/wwan/t7xx/t7xx_hif_cldma.h
+new file mode 100644
+index 000000000000..deb239e4f803
+--- /dev/null
++++ b/drivers/net/wwan/t7xx/t7xx_hif_cldma.h
+@@ -0,0 +1,126 @@
++/* SPDX-License-Identifier: GPL-2.0-only
++ *
++ * Copyright (c) 2021, MediaTek Inc.
++ * Copyright (c) 2021-2022, Intel Corporation.
++ *
++ * Authors:
++ * Haijun Liu <haijun.liu@mediatek.com>
++ * Moises Veleta <moises.veleta@intel.com>
++ * Ricardo Martinez <ricardo.martinez@linux.intel.com>
++ * Sreehari Kancharla <sreehari.kancharla@intel.com>
++ *
++ * Contributors:
++ * Amir Hanania <amir.hanania@intel.com>
++ * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
++ * Eliot Lee <eliot.lee@intel.com>
++ */
++
++#ifndef __T7XX_HIF_CLDMA_H__
++#define __T7XX_HIF_CLDMA_H__
++
++#include <linux/bits.h>
++#include <linux/device.h>
++#include <linux/dmapool.h>
++#include <linux/pci.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++#include <linux/types.h>
++
++#include "t7xx_cldma.h"
++#include "t7xx_pci.h"
++
++/**
++ * enum cldma_id - Identifiers for CLDMA HW units.
++ * @CLDMA_ID_MD: Modem control channel.
++ * @CLDMA_ID_AP: Application Processor control channel (not used at the moment).
++ * @CLDMA_NUM: Number of CLDMA HW units available.
++ */
++enum cldma_id {
++ CLDMA_ID_MD,
++ CLDMA_ID_AP,
++ CLDMA_NUM
++};
++
++struct cldma_gpd {
++ u8 flags;
++ u8 not_used1;
++ __le16 rx_data_allow_len;
++ __le32 next_gpd_ptr_h;
++ __le32 next_gpd_ptr_l;
++ __le32 data_buff_bd_ptr_h;
++ __le32 data_buff_bd_ptr_l;
++ __le16 data_buff_len;
++ __le16 not_used2;
++};
++
++struct cldma_request {
++ struct cldma_gpd *gpd; /* Virtual address for CPU */
++ dma_addr_t gpd_addr; /* Physical address for DMA */
++ struct sk_buff *skb;
++ dma_addr_t mapped_buff;
++ struct list_head entry;
++};
++
++struct cldma_ring {
++ struct list_head gpd_ring; /* Ring of struct cldma_request */
++ unsigned int length; /* Number of struct cldma_request */
++ int pkt_size;
++};
++
++struct cldma_queue {
++ struct cldma_ctrl *md_ctrl;
++ enum mtk_txrx dir;
++ unsigned int index;
++ struct cldma_ring *tr_ring;
++ struct cldma_request *tr_done;
++ struct cldma_request *rx_refill;
++ struct cldma_request *tx_next;
++ int budget; /* Same as ring buffer size by default */
++ spinlock_t ring_lock;
++ wait_queue_head_t req_wq; /* Only for TX */
++ struct workqueue_struct *worker;
++ struct work_struct cldma_work;
++};
++
++struct cldma_ctrl {
++ enum cldma_id hif_id;
++ struct device *dev;
++ struct t7xx_pci_dev *t7xx_dev;
++ struct cldma_queue txq[CLDMA_TXQ_NUM];
++ struct cldma_queue rxq[CLDMA_RXQ_NUM];
++ unsigned short txq_active;
++ unsigned short rxq_active;
++ unsigned short txq_started;
++ spinlock_t cldma_lock; /* Protects CLDMA structure */
++ /* Assumes T/R GPD/BD/SPD have the same size */
++ struct dma_pool *gpd_dmapool;
++ struct cldma_ring tx_ring[CLDMA_TXQ_NUM];
++ struct cldma_ring rx_ring[CLDMA_RXQ_NUM];
++ struct t7xx_cldma_hw hw_info;
++ bool is_late_init;
++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb);
++};
++
++#define GPD_FLAGS_HWO BIT(0)
++#define GPD_FLAGS_IOC BIT(7)
++#define GPD_DMAPOOL_ALIGN 16
++
++#define CLDMA_MTU 3584 /* 3.5kB */
++
++int t7xx_cldma_alloc(enum cldma_id hif_id, struct t7xx_pci_dev *t7xx_dev);
++void t7xx_cldma_hif_hw_init(struct cldma_ctrl *md_ctrl);
++int t7xx_cldma_init(struct cldma_ctrl *md_ctrl);
++void t7xx_cldma_exit(struct cldma_ctrl *md_ctrl);
++void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl);
++void t7xx_cldma_start(struct cldma_ctrl *md_ctrl);
++int t7xx_cldma_stop(struct cldma_ctrl *md_ctrl);
++void t7xx_cldma_reset(struct cldma_ctrl *md_ctrl);
++void t7xx_cldma_set_recv_skb(struct cldma_ctrl *md_ctrl,
++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb));
++int t7xx_cldma_send_skb(struct cldma_ctrl *md_ctrl, int qno, struct sk_buff *skb);
++void t7xx_cldma_stop_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx);
++void t7xx_cldma_clear_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx);
++
++#endif /* __T7XX_HIF_CLDMA_H__ */
+diff --git a/drivers/net/wwan/t7xx/t7xx_reg.h b/drivers/net/wwan/t7xx/t7xx_reg.h
+new file mode 100644
+index 000000000000..7dc6c77a59e3
+--- /dev/null
++++ b/drivers/net/wwan/t7xx/t7xx_reg.h
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only
++ *
++ * Copyright (c) 2021, MediaTek Inc.
++ * Copyright (c) 2021-2022, Intel Corporation.
++ *
++ * Authors:
++ * Haijun Liu <haijun.liu@mediatek.com>
++ * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
++ *
++ * Contributors:
++ * Amir Hanania <amir.hanania@intel.com>
++ * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
++ * Eliot Lee <eliot.lee@intel.com>
++ * Moises Veleta <moises.veleta@intel.com>
++ * Ricardo Martinez <ricardo.martinez@linux.intel.com>
++ * Sreehari Kancharla <sreehari.kancharla@intel.com>
++ */
++
++#ifndef __T7XX_REG_H__
++#define __T7XX_REG_H__
++
++enum t7xx_int {
++ DPMAIF_INT,
++ CLDMA0_INT,
++ CLDMA1_INT,
++ CLDMA2_INT,
++ MHCCIF_INT,
++ DPMAIF2_INT,
++ SAP_RGU_INT,
++ CLDMA3_INT,
++};
++
++#endif /* __T7XX_REG_H__ */
+--
+2.35.1
+
--- /dev/null
+From f57ac3b5c210de4729a9b501072ba3a30b55696d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 16:16:12 +0800
+Subject: net: xscale: Fix return type for implementation of ndo_start_xmit
+
+From: GUO Zihua <guozihua@huawei.com>
+
+[ Upstream commit 0dbaf0fa62329d9fe452d9041a707a33f6274f1f ]
+
+Since Linux now supports CFI, it will be a good idea to fix mismatched
+return type for implementation of hooks. Otherwise this might get
+cought out by CFI and cause a panic.
+
+eth_xmit() would return either NETDEV_TX_BUSY or NETDEV_TX_OK, so
+change the return type to netdev_tx_t directly.
+
+Signed-off-by: GUO Zihua <guozihua@huawei.com>
+Link: https://lore.kernel.org/r/20220902081612.60405-1-guozihua@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/xscale/ixp4xx_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+index 931494cc1c39..60ac6963529a 100644
+--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+@@ -829,7 +829,7 @@ static void eth_txdone_irq(void *unused)
+ }
+ }
+
+-static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
++static netdev_tx_t eth_xmit(struct sk_buff *skb, struct net_device *dev)
+ {
+ struct port *port = netdev_priv(dev);
+ unsigned int txreadyq = port->plat->txreadyq;
+--
+2.35.1
+
--- /dev/null
+From 65e3d75fe0062ca6700f3691719eaf9350069f63 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 11:29:40 +0200
+Subject: netfilter: conntrack: fix the gc rescheduling delay
+
+From: Antoine Tenart <atenart@kernel.org>
+
+[ Upstream commit 95eabdd207024312876d0ebed90b4c977e050e85 ]
+
+Commit 2cfadb761d3d ("netfilter: conntrack: revisit gc autotuning")
+changed the eviction rescheduling to the use average expiry of scanned
+entries (within 1-60s) by doing:
+
+ for (...) {
+ expires = clamp(nf_ct_expires(tmp), ...);
+ next_run += expires;
+ next_run /= 2;
+ }
+
+The issue is the above will make the average ('next_run' here) more
+dependent on the last expiration values than the firsts (for sets > 2).
+Depending on the expiration values used to compute the average, the
+result can be quite different than what's expected. To fix this we can
+do the following:
+
+ for (...) {
+ expires = clamp(nf_ct_expires(tmp), ...);
+ next_run += (expires - next_run) / ++count;
+ }
+
+Fixes: 2cfadb761d3d ("netfilter: conntrack: revisit gc autotuning")
+Cc: Florian Westphal <fw@strlen.de>
+Signed-off-by: Antoine Tenart <atenart@kernel.org>
+Signed-off-by: Florian Westphal <fw@strlen.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/netfilter/nf_conntrack_core.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
+index 31399c53dfb1..ee72da164190 100644
+--- a/net/netfilter/nf_conntrack_core.c
++++ b/net/netfilter/nf_conntrack_core.c
+@@ -67,6 +67,7 @@ struct conntrack_gc_work {
+ struct delayed_work dwork;
+ u32 next_bucket;
+ u32 avg_timeout;
++ u32 count;
+ u32 start_time;
+ bool exiting;
+ bool early_drop;
+@@ -1439,6 +1440,7 @@ static void gc_worker(struct work_struct *work)
+ unsigned int expired_count = 0;
+ unsigned long next_run;
+ s32 delta_time;
++ long count;
+
+ gc_work = container_of(work, struct conntrack_gc_work, dwork.work);
+
+@@ -1448,10 +1450,12 @@ static void gc_worker(struct work_struct *work)
+
+ if (i == 0) {
+ gc_work->avg_timeout = GC_SCAN_INTERVAL_INIT;
++ gc_work->count = 1;
+ gc_work->start_time = start_time;
+ }
+
+ next_run = gc_work->avg_timeout;
++ count = gc_work->count;
+
+ end_time = start_time + GC_SCAN_MAX_DURATION;
+
+@@ -1471,8 +1475,8 @@ static void gc_worker(struct work_struct *work)
+
+ hlist_nulls_for_each_entry_rcu(h, n, &ct_hash[i], hnnode) {
+ struct nf_conntrack_net *cnet;
+- unsigned long expires;
+ struct net *net;
++ long expires;
+
+ tmp = nf_ct_tuplehash_to_ctrack(h);
+
+@@ -1486,6 +1490,7 @@ static void gc_worker(struct work_struct *work)
+
+ gc_work->next_bucket = i;
+ gc_work->avg_timeout = next_run;
++ gc_work->count = count;
+
+ delta_time = nfct_time_stamp - gc_work->start_time;
+
+@@ -1501,8 +1506,8 @@ static void gc_worker(struct work_struct *work)
+ }
+
+ expires = clamp(nf_ct_expires(tmp), GC_SCAN_INTERVAL_MIN, GC_SCAN_INTERVAL_CLAMP);
++ expires = (expires - (long)next_run) / ++count;
+ next_run += expires;
+- next_run /= 2u;
+
+ if (nf_conntrack_max95 == 0 || gc_worker_skip_ct(tmp))
+ continue;
+@@ -1540,6 +1545,7 @@ static void gc_worker(struct work_struct *work)
+ delta_time = nfct_time_stamp - end_time;
+ if (delta_time > 0 && i < hashsz) {
+ gc_work->avg_timeout = next_run;
++ gc_work->count = count;
+ gc_work->next_bucket = i;
+ next_run = 0;
+ goto early_exit;
+--
+2.35.1
+
--- /dev/null
+From b70ec3a04fb152445addd00bfee1a7ad154aff36 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 11:29:41 +0200
+Subject: netfilter: conntrack: revisit the gc initial rescheduling bias
+
+From: Antoine Tenart <atenart@kernel.org>
+
+[ Upstream commit 2aa192757005f130b2dd3547dda6e462e761199f ]
+
+The previous commit changed the way the rescheduling delay is computed
+which has a side effect: the bias is now represented as much as the
+other entries in the rescheduling delay which makes the logic to kick in
+only with very large sets, as the initial interval is very large
+(INT_MAX).
+
+Revisit the GC initial bias to allow more frequent GC for smaller sets
+while still avoiding wakeups when a machine is mostly idle. We're moving
+from a large initial value to pretending we have 100 entries expiring at
+the upper bound. This way only a few entries having a small timeout
+won't impact much the rescheduling delay and non-idle machines will have
+enough entries to lower the delay when needed. This also improves
+readability as the initial bias is now linked to what is computed
+instead of being an arbitrary large value.
+
+Fixes: 2cfadb761d3d ("netfilter: conntrack: revisit gc autotuning")
+Suggested-by: Florian Westphal <fw@strlen.de>
+Signed-off-by: Antoine Tenart <atenart@kernel.org>
+Signed-off-by: Florian Westphal <fw@strlen.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/netfilter/nf_conntrack_core.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
+index ee72da164190..9da5ee6c50cd 100644
+--- a/net/netfilter/nf_conntrack_core.c
++++ b/net/netfilter/nf_conntrack_core.c
+@@ -86,10 +86,12 @@ static DEFINE_MUTEX(nf_conntrack_mutex);
+ /* clamp timeouts to this value (TCP unacked) */
+ #define GC_SCAN_INTERVAL_CLAMP (300ul * HZ)
+
+-/* large initial bias so that we don't scan often just because we have
+- * three entries with a 1s timeout.
++/* Initial bias pretending we have 100 entries at the upper bound so we don't
++ * wakeup often just because we have three entries with a 1s timeout while still
++ * allowing non-idle machines to wakeup more often when needed.
+ */
+-#define GC_SCAN_INTERVAL_INIT INT_MAX
++#define GC_SCAN_INITIAL_COUNT 100
++#define GC_SCAN_INTERVAL_INIT GC_SCAN_INTERVAL_MAX
+
+ #define GC_SCAN_MAX_DURATION msecs_to_jiffies(10)
+ #define GC_SCAN_EXPIRED_MAX (64000u / HZ)
+@@ -1450,7 +1452,7 @@ static void gc_worker(struct work_struct *work)
+
+ if (i == 0) {
+ gc_work->avg_timeout = GC_SCAN_INTERVAL_INIT;
+- gc_work->count = 1;
++ gc_work->count = GC_SCAN_INITIAL_COUNT;
+ gc_work->start_time = start_time;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 9b9485f71a466622ccff17a5e99243b85ae86bf9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 13:07:31 +0200
+Subject: netfilter: nft_fib: Fix for rpath check with VRF devices
+
+From: Phil Sutter <phil@nwl.cc>
+
+[ Upstream commit 2a8a7c0eaa8747c16aa4a48d573aa920d5c00a5c ]
+
+Analogous to commit b575b24b8eee3 ("netfilter: Fix rpfilter
+dropping vrf packets by mistake") but for nftables fib expression:
+Add special treatment of VRF devices so that typical reverse path
+filtering via 'fib saddr . iif oif' expression works as expected.
+
+Fixes: f6d0cbcf09c50 ("netfilter: nf_tables: add fib expression")
+Signed-off-by: Phil Sutter <phil@nwl.cc>
+Signed-off-by: Florian Westphal <fw@strlen.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/ipv4/netfilter/nft_fib_ipv4.c | 3 +++
+ net/ipv6/netfilter/nft_fib_ipv6.c | 6 +++++-
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/net/ipv4/netfilter/nft_fib_ipv4.c b/net/ipv4/netfilter/nft_fib_ipv4.c
+index 03df986217b7..9e6f0f1275e2 100644
+--- a/net/ipv4/netfilter/nft_fib_ipv4.c
++++ b/net/ipv4/netfilter/nft_fib_ipv4.c
+@@ -83,6 +83,9 @@ void nft_fib4_eval(const struct nft_expr *expr, struct nft_regs *regs,
+ else
+ oif = NULL;
+
++ if (priv->flags & NFTA_FIB_F_IIF)
++ fl4.flowi4_oif = l3mdev_master_ifindex_rcu(oif);
++
+ if (nft_hook(pkt) == NF_INET_PRE_ROUTING &&
+ nft_fib_is_loopback(pkt->skb, nft_in(pkt))) {
+ nft_fib_store_result(dest, priv, nft_in(pkt));
+diff --git a/net/ipv6/netfilter/nft_fib_ipv6.c b/net/ipv6/netfilter/nft_fib_ipv6.c
+index 92f3235fa287..602743f6dcee 100644
+--- a/net/ipv6/netfilter/nft_fib_ipv6.c
++++ b/net/ipv6/netfilter/nft_fib_ipv6.c
+@@ -37,6 +37,9 @@ static int nft_fib6_flowi_init(struct flowi6 *fl6, const struct nft_fib *priv,
+ if (ipv6_addr_type(&fl6->daddr) & IPV6_ADDR_LINKLOCAL) {
+ lookup_flags |= RT6_LOOKUP_F_IFACE;
+ fl6->flowi6_oif = get_ifindex(dev ? dev : pkt->skb->dev);
++ } else if ((priv->flags & NFTA_FIB_F_IIF) &&
++ (netif_is_l3_master(dev) || netif_is_l3_slave(dev))) {
++ fl6->flowi6_oif = dev->ifindex;
+ }
+
+ if (ipv6_addr_type(&fl6->saddr) & IPV6_ADDR_UNICAST)
+@@ -193,7 +196,8 @@ void nft_fib6_eval(const struct nft_expr *expr, struct nft_regs *regs,
+ if (rt->rt6i_flags & (RTF_REJECT | RTF_ANYCAST | RTF_LOCAL))
+ goto put_rt_err;
+
+- if (oif && oif != rt->rt6i_idev->dev)
++ if (oif && oif != rt->rt6i_idev->dev &&
++ l3mdev_master_ifindex_rcu(rt->rt6i_idev->dev) != oif->ifindex)
+ goto put_rt_err;
+
+ nft_fib_store_result(dest, priv, rt->rt6i_idev->dev);
+--
+2.35.1
+
--- /dev/null
+From fd63a0af6e6858c6602872e31b33ae9e44a96240 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 07:27:04 +0200
+Subject: nfsd: Fix a memory leak in an error handling path
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit fd1ef88049de09bc70d60b549992524cfc0e66ff ]
+
+If this memdup_user() call fails, the memory allocated in a previous call
+a few lines above should be freed. Otherwise it leaks.
+
+Fixes: 6ee95d1c8991 ("nfsd: add support for upcall version 2")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfsd/nfs4recover.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/fs/nfsd/nfs4recover.c b/fs/nfsd/nfs4recover.c
+index c634483d85d2..8f24485e0f04 100644
+--- a/fs/nfsd/nfs4recover.c
++++ b/fs/nfsd/nfs4recover.c
+@@ -815,8 +815,10 @@ __cld_pipe_inprogress_downcall(const struct cld_msg_v2 __user *cmsg,
+ princhash.data = memdup_user(
+ &ci->cc_princhash.cp_data,
+ princhashlen);
+- if (IS_ERR_OR_NULL(princhash.data))
++ if (IS_ERR_OR_NULL(princhash.data)) {
++ kfree(name.data);
+ return -EFAULT;
++ }
+ princhash.len = princhashlen;
+ } else
+ princhash.len = 0;
+--
+2.35.1
+
--- /dev/null
+From 1234a1013aa5254ff21c722d47d02eb28c7de6a0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 15:33:32 -0400
+Subject: NFSD: Fix handling of oversized NFSv4 COMPOUND requests
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit 7518a3dc5ea249d4112156ce71b8b184eb786151 ]
+
+If an NFS server returns NFS4ERR_RESOURCE on the first operation in
+an NFSv4 COMPOUND, there's no way for a client to know where the
+problem is and then simplify the compound to make forward progress.
+
+So instead, make NFSD process as many operations in an oversized
+COMPOUND as it can and then return NFS4ERR_RESOURCE on the first
+operation it did not process.
+
+pynfs NFSv4.0 COMP6 exercises this case, but checks only for the
+COMPOUND status code, not whether the server has processed any
+of the operations.
+
+pynfs NFSv4.1 SEQ6 and SEQ7 exercise the NFSv4.1 case, which detects
+too many operations per COMPOUND by checking against the limits
+negotiated when the session was created.
+
+Suggested-by: Bruce Fields <bfields@fieldses.org>
+Fixes: 0078117c6d91 ("nfsd: return RESOURCE not GARBAGE_ARGS on too many ops")
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfsd/nfs4proc.c | 19 +++++++++++++------
+ fs/nfsd/nfs4xdr.c | 12 +++---------
+ fs/nfsd/xdr4.h | 3 ++-
+ 3 files changed, 18 insertions(+), 16 deletions(-)
+
+diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c
+index f7584787dab2..09dd70f79158 100644
+--- a/fs/nfsd/nfs4proc.c
++++ b/fs/nfsd/nfs4proc.c
+@@ -2493,9 +2493,6 @@ nfsd4_proc_compound(struct svc_rqst *rqstp)
+ status = nfserr_minor_vers_mismatch;
+ if (nfsd_minorversion(nn, args->minorversion, NFSD_TEST) <= 0)
+ goto out;
+- status = nfserr_resource;
+- if (args->opcnt > NFSD_MAX_OPS_PER_COMPOUND)
+- goto out;
+
+ status = nfs41_check_op_ordering(args);
+ if (status) {
+@@ -2508,10 +2505,20 @@ nfsd4_proc_compound(struct svc_rqst *rqstp)
+
+ rqstp->rq_lease_breaker = (void **)&cstate->clp;
+
+- trace_nfsd_compound(rqstp, args->opcnt);
++ trace_nfsd_compound(rqstp, args->client_opcnt);
+ while (!status && resp->opcnt < args->opcnt) {
+ op = &args->ops[resp->opcnt++];
+
++ if (unlikely(resp->opcnt == NFSD_MAX_OPS_PER_COMPOUND)) {
++ /* If there are still more operations to process,
++ * stop here and report NFS4ERR_RESOURCE. */
++ if (cstate->minorversion == 0 &&
++ args->client_opcnt > resp->opcnt) {
++ op->status = nfserr_resource;
++ goto encode_op;
++ }
++ }
++
+ /*
+ * The XDR decode routines may have pre-set op->status;
+ * for example, if there is a miscellaneous XDR error
+@@ -2587,8 +2594,8 @@ nfsd4_proc_compound(struct svc_rqst *rqstp)
+ status = op->status;
+ }
+
+- trace_nfsd_compound_status(args->opcnt, resp->opcnt, status,
+- nfsd4_op_name(op->opnum));
++ trace_nfsd_compound_status(args->client_opcnt, resp->opcnt,
++ status, nfsd4_op_name(op->opnum));
+
+ nfsd4_cstate_clear_replay(cstate);
+ nfsd4_increment_op_stats(op->opnum);
+diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
+index 4504d1246d14..3c66517a6f0f 100644
+--- a/fs/nfsd/nfs4xdr.c
++++ b/fs/nfsd/nfs4xdr.c
+@@ -2349,16 +2349,10 @@ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+
+ if (xdr_stream_decode_u32(argp->xdr, &argp->minorversion) < 0)
+ return false;
+- if (xdr_stream_decode_u32(argp->xdr, &argp->opcnt) < 0)
++ if (xdr_stream_decode_u32(argp->xdr, &argp->client_opcnt) < 0)
+ return false;
+-
+- /*
+- * NFS4ERR_RESOURCE is a more helpful error than GARBAGE_ARGS
+- * here, so we return success at the xdr level so that
+- * nfsd4_proc can handle this is an NFS-level error.
+- */
+- if (argp->opcnt > NFSD_MAX_OPS_PER_COMPOUND)
+- return true;
++ argp->opcnt = min_t(u32, argp->client_opcnt,
++ NFSD_MAX_OPS_PER_COMPOUND);
+
+ if (argp->opcnt > ARRAY_SIZE(argp->iops)) {
+ argp->ops = kzalloc(argp->opcnt * sizeof(*argp->ops), GFP_KERNEL);
+diff --git a/fs/nfsd/xdr4.h b/fs/nfsd/xdr4.h
+index 8812256cd520..50242d8cd09e 100644
+--- a/fs/nfsd/xdr4.h
++++ b/fs/nfsd/xdr4.h
+@@ -688,9 +688,10 @@ struct nfsd4_compoundargs {
+ struct svcxdr_tmpbuf *to_free;
+ struct svc_rqst *rqstp;
+
+- u32 taglen;
+ char * tag;
++ u32 taglen;
+ u32 minorversion;
++ u32 client_opcnt;
+ u32 opcnt;
+ struct nfsd4_op *ops;
+ struct nfsd4_op iops[8];
+--
+2.35.1
+
--- /dev/null
+From 836fc6748961c880c3bd87f0e69c8ce195c4690d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 10:59:16 -0700
+Subject: NFSD: fix use-after-free on source server when doing inter-server
+ copy
+
+From: Dai Ngo <dai.ngo@oracle.com>
+
+[ Upstream commit 019805fea91599b22dfa62ffb29c022f35abeb06 ]
+
+Use-after-free occurred when the laundromat tried to free expired
+cpntf_state entry on the s2s_cp_stateids list after inter-server
+copy completed. The sc_cp_list that the expired copy state was
+inserted on was already freed.
+
+When COPY completes, the Linux client normally sends LOCKU(lock_state x),
+FREE_STATEID(lock_state x) and CLOSE(open_state y) to the source server.
+The nfs4_put_stid call from nfsd4_free_stateid cleans up the copy state
+from the s2s_cp_stateids list before freeing the lock state's stid.
+
+However, sometimes the CLOSE was sent before the FREE_STATEID request.
+When this happens, the nfsd4_close_open_stateid call from nfsd4_close
+frees all lock states on its st_locks list without cleaning up the copy
+state on the sc_cp_list list. When the time the FREE_STATEID arrives the
+server returns BAD_STATEID since the lock state was freed. This causes
+the use-after-free error to occur when the laundromat tries to free
+the expired cpntf_state.
+
+This patch adds a call to nfs4_free_cpntf_statelist in
+nfsd4_close_open_stateid to clean up the copy state before calling
+free_ol_stateid_reaplist to free the lock state's stid on the reaplist.
+
+Signed-off-by: Dai Ngo <dai.ngo@oracle.com>
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfsd/nfs4state.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c
+index f9e2fa9cfbec..7b763f146b62 100644
+--- a/fs/nfsd/nfs4state.c
++++ b/fs/nfsd/nfs4state.c
+@@ -961,6 +961,7 @@ static struct nfs4_ol_stateid * nfs4_alloc_open_stateid(struct nfs4_client *clp)
+
+ static void nfs4_free_deleg(struct nfs4_stid *stid)
+ {
++ WARN_ON(!list_empty(&stid->sc_cp_list));
+ kmem_cache_free(deleg_slab, stid);
+ atomic_long_dec(&num_delegations);
+ }
+@@ -1374,6 +1375,7 @@ static void nfs4_free_ol_stateid(struct nfs4_stid *stid)
+ release_all_access(stp);
+ if (stp->st_stateowner)
+ nfs4_put_stateowner(stp->st_stateowner);
++ WARN_ON(!list_empty(&stid->sc_cp_list));
+ kmem_cache_free(stateid_slab, stid);
+ }
+
+@@ -6389,6 +6391,7 @@ static void nfsd4_close_open_stateid(struct nfs4_ol_stateid *s)
+ struct nfs4_client *clp = s->st_stid.sc_client;
+ bool unhashed;
+ LIST_HEAD(reaplist);
++ struct nfs4_ol_stateid *stp;
+
+ spin_lock(&clp->cl_lock);
+ unhashed = unhash_open_stateid(s, &reaplist);
+@@ -6397,6 +6400,8 @@ static void nfsd4_close_open_stateid(struct nfs4_ol_stateid *s)
+ if (unhashed)
+ put_ol_stateid_locked(s, &reaplist);
+ spin_unlock(&clp->cl_lock);
++ list_for_each_entry(stp, &reaplist, st_locks)
++ nfs4_free_cpntf_statelist(clp->net, &stp->st_stid);
+ free_ol_stateid_reaplist(&reaplist);
+ } else {
+ spin_unlock(&clp->cl_lock);
+--
+2.35.1
+
--- /dev/null
+From 89a4b87496878738d5be4eab574578cf1b8ca755 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 15:10:05 -0400
+Subject: NFSD: Protect against send buffer overflow in NFSv2 READDIR
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit 00b4492686e0497fdb924a9d4c8f6f99377e176c ]
+
+Restore the previous limit on the @count argument to prevent a
+buffer overflow attack.
+
+Fixes: 53b1119a6e50 ("NFSD: Fix READDIR buffer overflow")
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Reviewed-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfsd/nfsproc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/fs/nfsd/nfsproc.c b/fs/nfsd/nfsproc.c
+index 081cca405983..b009da1dcbb5 100644
+--- a/fs/nfsd/nfsproc.c
++++ b/fs/nfsd/nfsproc.c
+@@ -557,12 +557,11 @@ static void nfsd_init_dirlist_pages(struct svc_rqst *rqstp,
+ struct xdr_buf *buf = &resp->dirlist;
+ struct xdr_stream *xdr = &resp->xdr;
+
+- count = clamp(count, (u32)(XDR_UNIT * 2), svc_max_payload(rqstp));
+-
+ memset(buf, 0, sizeof(*buf));
+
+ /* Reserve room for the NULL ptr & eof flag (-2 words) */
+- buf->buflen = count - XDR_UNIT * 2;
++ buf->buflen = clamp(count, (u32)(XDR_UNIT * 2), (u32)PAGE_SIZE);
++ buf->buflen -= XDR_UNIT * 2;
+ buf->pages = rqstp->rq_next_page;
+ rqstp->rq_next_page++;
+
+--
+2.35.1
+
--- /dev/null
+From fa3c361ebb4972a683fde18aa3d2ac98fd738825 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 14:01:50 -0400
+Subject: NFSD: Return nfserr_serverfault if splice_ok but buf->pages have data
+
+From: Anna Schumaker <Anna.Schumaker@Netapp.com>
+
+[ Upstream commit 06981d560606ac48d61e5f4fff6738b925c93173 ]
+
+This was discussed with Chuck as part of this patch set. Returning
+nfserr_resource was decided to not be the best error message here, and
+he suggested changing to nfserr_serverfault instead.
+
+Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
+Link: https://lore.kernel.org/linux-nfs/20220907195259.926736-1-anna@kernel.org/T/#t
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfsd/nfs4xdr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
+index 3c66517a6f0f..d85dd7060e85 100644
+--- a/fs/nfsd/nfs4xdr.c
++++ b/fs/nfsd/nfs4xdr.c
+@@ -3987,7 +3987,7 @@ nfsd4_encode_read(struct nfsd4_compoundres *resp, __be32 nfserr,
+ if (resp->xdr->buf->page_len &&
+ test_bit(RQ_SPLICE_OK, &resp->rqstp->rq_flags)) {
+ WARN_ON_ONCE(1);
+- return nfserr_resource;
++ return nfserr_serverfault;
+ }
+ xdr_commit_encode(xdr);
+
+--
+2.35.1
+
--- /dev/null
+From eae5a6496eb3b883bf48aa6e34f03a59556834d6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 14:38:40 +0200
+Subject: ntfs3: rework xattr handlers and switch to POSIX ACL VFS helpers
+
+From: Christian Brauner <brauner@kernel.org>
+
+[ Upstream commit a26aa12384158116c0d80d50e0bdc7b3323551e2 ]
+
+The xattr code in ntfs3 is currently a bit confused. For example, it
+defines a POSIX ACL i_op->set_acl() method but instead of relying on the
+generic POSIX ACL VFS helpers it defines its own set of xattr helpers
+with the consequence that i_op->set_acl() is currently dead code.
+
+Switch ntfs3 to rely on the VFS POSIX ACL xattr handlers. Also remove
+i_op->{g,s}et_acl() methods from symlink inode operations. Symlinks
+don't support xattrs.
+
+This is a preliminary change for the following patches which move
+handling idmapped mounts directly in posix_acl_xattr_set().
+
+This survives POSIX ACL xfstests.
+
+Fixes: be71b5cba2e6 ("fs/ntfs3: Add attrib operations")
+Signed-off-by: Christian Brauner (Microsoft) <brauner@kernel.org>
+Reviewed-by: Seth Forshee (DigitalOcean) <sforshee@kernel.org>>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/ntfs3/inode.c | 2 -
+ fs/ntfs3/xattr.c | 102 +++--------------------------------------------
+ 2 files changed, 6 insertions(+), 98 deletions(-)
+
+diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
+index b2cc1191be69..64b4a3c29878 100644
+--- a/fs/ntfs3/inode.c
++++ b/fs/ntfs3/inode.c
+@@ -1942,8 +1942,6 @@ const struct inode_operations ntfs_link_inode_operations = {
+ .setattr = ntfs3_setattr,
+ .listxattr = ntfs_listxattr,
+ .permission = ntfs_permission,
+- .get_acl = ntfs_get_acl,
+- .set_acl = ntfs_set_acl,
+ };
+
+ const struct address_space_operations ntfs_aops = {
+diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
+index 4652b9796995..eb799a5cdfad 100644
+--- a/fs/ntfs3/xattr.c
++++ b/fs/ntfs3/xattr.c
+@@ -623,67 +623,6 @@ int ntfs_set_acl(struct user_namespace *mnt_userns, struct inode *inode,
+ return ntfs_set_acl_ex(mnt_userns, inode, acl, type, false);
+ }
+
+-static int ntfs_xattr_get_acl(struct user_namespace *mnt_userns,
+- struct inode *inode, int type, void *buffer,
+- size_t size)
+-{
+- struct posix_acl *acl;
+- int err;
+-
+- if (!(inode->i_sb->s_flags & SB_POSIXACL)) {
+- ntfs_inode_warn(inode, "add mount option \"acl\" to use acl");
+- return -EOPNOTSUPP;
+- }
+-
+- acl = ntfs_get_acl(inode, type, false);
+- if (IS_ERR(acl))
+- return PTR_ERR(acl);
+-
+- if (!acl)
+- return -ENODATA;
+-
+- err = posix_acl_to_xattr(&init_user_ns, acl, buffer, size);
+- posix_acl_release(acl);
+-
+- return err;
+-}
+-
+-static int ntfs_xattr_set_acl(struct user_namespace *mnt_userns,
+- struct inode *inode, int type, const void *value,
+- size_t size)
+-{
+- struct posix_acl *acl;
+- int err;
+-
+- if (!(inode->i_sb->s_flags & SB_POSIXACL)) {
+- ntfs_inode_warn(inode, "add mount option \"acl\" to use acl");
+- return -EOPNOTSUPP;
+- }
+-
+- if (!inode_owner_or_capable(mnt_userns, inode))
+- return -EPERM;
+-
+- if (!value) {
+- acl = NULL;
+- } else {
+- acl = posix_acl_from_xattr(&init_user_ns, value, size);
+- if (IS_ERR(acl))
+- return PTR_ERR(acl);
+-
+- if (acl) {
+- err = posix_acl_valid(&init_user_ns, acl);
+- if (err)
+- goto release_and_out;
+- }
+- }
+-
+- err = ntfs_set_acl(mnt_userns, inode, acl, type);
+-
+-release_and_out:
+- posix_acl_release(acl);
+- return err;
+-}
+-
+ /*
+ * ntfs_init_acl - Initialize the ACLs of a new inode.
+ *
+@@ -850,23 +789,6 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
+ goto out;
+ }
+
+-#ifdef CONFIG_NTFS3_FS_POSIX_ACL
+- if ((name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1 &&
+- !memcmp(name, XATTR_NAME_POSIX_ACL_ACCESS,
+- sizeof(XATTR_NAME_POSIX_ACL_ACCESS))) ||
+- (name_len == sizeof(XATTR_NAME_POSIX_ACL_DEFAULT) - 1 &&
+- !memcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT,
+- sizeof(XATTR_NAME_POSIX_ACL_DEFAULT)))) {
+- /* TODO: init_user_ns? */
+- err = ntfs_xattr_get_acl(
+- &init_user_ns, inode,
+- name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
+- ? ACL_TYPE_ACCESS
+- : ACL_TYPE_DEFAULT,
+- buffer, size);
+- goto out;
+- }
+-#endif
+ /* Deal with NTFS extended attribute. */
+ err = ntfs_get_ea(inode, name, name_len, buffer, size, NULL);
+
+@@ -979,22 +901,6 @@ static noinline int ntfs_setxattr(const struct xattr_handler *handler,
+ goto out;
+ }
+
+-#ifdef CONFIG_NTFS3_FS_POSIX_ACL
+- if ((name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1 &&
+- !memcmp(name, XATTR_NAME_POSIX_ACL_ACCESS,
+- sizeof(XATTR_NAME_POSIX_ACL_ACCESS))) ||
+- (name_len == sizeof(XATTR_NAME_POSIX_ACL_DEFAULT) - 1 &&
+- !memcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT,
+- sizeof(XATTR_NAME_POSIX_ACL_DEFAULT)))) {
+- err = ntfs_xattr_set_acl(
+- mnt_userns, inode,
+- name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
+- ? ACL_TYPE_ACCESS
+- : ACL_TYPE_DEFAULT,
+- value, size);
+- goto out;
+- }
+-#endif
+ /* Deal with NTFS extended attribute. */
+ err = ntfs_set_ea(inode, name, name_len, value, size, flags);
+
+@@ -1082,7 +988,7 @@ static bool ntfs_xattr_user_list(struct dentry *dentry)
+ }
+
+ // clang-format off
+-static const struct xattr_handler ntfs_xattr_handler = {
++static const struct xattr_handler ntfs_other_xattr_handler = {
+ .prefix = "",
+ .get = ntfs_getxattr,
+ .set = ntfs_setxattr,
+@@ -1090,7 +996,11 @@ static const struct xattr_handler ntfs_xattr_handler = {
+ };
+
+ const struct xattr_handler *ntfs_xattr_handlers[] = {
+- &ntfs_xattr_handler,
++#ifdef CONFIG_NTFS3_FS_POSIX_ACL
++ &posix_acl_access_xattr_handler,
++ &posix_acl_default_xattr_handler,
++#endif
++ &ntfs_other_xattr_handler,
+ NULL,
+ };
+ // clang-format on
+--
+2.35.1
+
--- /dev/null
+From e88e60e8a6e5fffa23ab42a64e6a9affc2bf5f93 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 12:45:08 -0700
+Subject: nvme: copy firmware_rev on each init
+
+From: Keith Busch <kbusch@kernel.org>
+
+[ Upstream commit a8eb6c1ba48bddea82e8d74cbe6e119f006be97d ]
+
+The firmware revision can change on after a reset so copy the most
+recent info each time instead of just the first time, otherwise the
+sysfs firmware_rev entry may contain stale data.
+
+Reported-by: Jeff Lien <jeff.lien@wdc.com>
+Signed-off-by: Keith Busch <kbusch@kernel.org>
+Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
+Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
+Reviewed-by: Chao Leng <lengchao@huawei.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/nvme/host/core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
+index 76d8a72f52e2..3527a0667568 100644
+--- a/drivers/nvme/host/core.c
++++ b/drivers/nvme/host/core.c
+@@ -2732,7 +2732,6 @@ static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
+ nvme_init_subnqn(subsys, ctrl, id);
+ memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
+ memcpy(subsys->model, id->mn, sizeof(subsys->model));
+- memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
+ subsys->vendor_id = le16_to_cpu(id->vid);
+ subsys->cmic = id->cmic;
+ subsys->awupf = le16_to_cpu(id->awupf);
+@@ -2939,6 +2938,8 @@ static int nvme_init_identify(struct nvme_ctrl *ctrl)
+ ctrl->quirks |= core_quirks[i].quirks;
+ }
+ }
++ memcpy(ctrl->subsys->firmware_rev, id->fr,
++ sizeof(ctrl->subsys->firmware_rev));
+
+ if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
+ dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
+--
+2.35.1
+
--- /dev/null
+From cd8d0599d75cd9e1bff108597306c12a59db97c9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 00:06:49 +0530
+Subject: nvmet-tcp: add bounds check on Transfer Tag
+
+From: Varun Prakash <varun@chelsio.com>
+
+[ Upstream commit b6a545ffa2c192b1e6da4a7924edac5ba9f4ea2b ]
+
+ttag is used as an index to get cmd in nvmet_tcp_handle_h2c_data_pdu(),
+add a bounds check to avoid out-of-bounds access.
+
+Signed-off-by: Varun Prakash <varun@chelsio.com>
+Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/nvme/target/tcp.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/nvme/target/tcp.c b/drivers/nvme/target/tcp.c
+index fba5a77c58d6..2add26637c87 100644
+--- a/drivers/nvme/target/tcp.c
++++ b/drivers/nvme/target/tcp.c
+@@ -934,10 +934,17 @@ static int nvmet_tcp_handle_h2c_data_pdu(struct nvmet_tcp_queue *queue)
+ struct nvme_tcp_data_pdu *data = &queue->pdu.data;
+ struct nvmet_tcp_cmd *cmd;
+
+- if (likely(queue->nr_cmds))
++ if (likely(queue->nr_cmds)) {
++ if (unlikely(data->ttag >= queue->nr_cmds)) {
++ pr_err("queue %d: received out of bound ttag %u, nr_cmds %u\n",
++ queue->idx, data->ttag, queue->nr_cmds);
++ nvmet_tcp_fatal_error(queue);
++ return -EPROTO;
++ }
+ cmd = &queue->cmds[data->ttag];
+- else
++ } else {
+ cmd = &queue->connect;
++ }
+
+ if (le32_to_cpu(data->data_offset) != cmd->rbytes_done) {
+ pr_err("ttag %u unexpected data offset %u (expected %u)\n",
+--
+2.35.1
+
--- /dev/null
+From 82fc065417fb3b595c2d975a438cc9410c969ea1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 14:54:58 -0700
+Subject: objtool: Preserve special st_shndx indexes in elf_update_symbol
+
+From: Sami Tolvanen <samitolvanen@google.com>
+
+[ Upstream commit 5141d3a06b2da1731ac82091298b766a1f95d3d8 ]
+
+elf_update_symbol fails to preserve the special st_shndx values
+between [SHN_LORESERVE, SHN_HIRESERVE], which results in it
+converting SHN_ABS entries into SHN_UNDEF, for example. Explicitly
+check for the special indexes and ensure these symbols are not
+marked undefined.
+
+Fixes: ead165fa1042 ("objtool: Fix symbol creation")
+Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Link: https://lore.kernel.org/r/20220908215504.3686827-17-samitolvanen@google.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/objtool/elf.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c
+index bc3005ef5af8..4b78df22d42e 100644
+--- a/tools/objtool/elf.c
++++ b/tools/objtool/elf.c
+@@ -555,6 +555,11 @@ static int elf_update_symbol(struct elf *elf, struct section *symtab,
+ Elf64_Xword entsize = symtab->sh.sh_entsize;
+ int max_idx, idx = sym->idx;
+ Elf_Scn *s, *t = NULL;
++ bool is_special_shndx = sym->sym.st_shndx >= SHN_LORESERVE &&
++ sym->sym.st_shndx != SHN_XINDEX;
++
++ if (is_special_shndx)
++ shndx = sym->sym.st_shndx;
+
+ s = elf_getscn(elf->elf, symtab->idx);
+ if (!s) {
+@@ -640,7 +645,7 @@ static int elf_update_symbol(struct elf *elf, struct section *symtab,
+ }
+
+ /* setup extended section index magic and write the symbol */
+- if (shndx >= SHN_UNDEF && shndx < SHN_LORESERVE) {
++ if ((shndx >= SHN_UNDEF && shndx < SHN_LORESERVE) || is_special_shndx) {
+ sym->sym.st_shndx = shndx;
+ if (!shndx_data)
+ shndx = 0;
+--
+2.35.1
+
--- /dev/null
+From 6d6061be4ae666703be4f04edb88f4e75b560c0a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 1 Oct 2022 13:51:02 -0700
+Subject: once: add DO_ONCE_SLOW() for sleepable contexts
+
+From: Eric Dumazet <edumazet@google.com>
+
+[ Upstream commit 62c07983bef9d3e78e71189441e1a470f0d1e653 ]
+
+Christophe Leroy reported a ~80ms latency spike
+happening at first TCP connect() time.
+
+This is because __inet_hash_connect() uses get_random_once()
+to populate a perturbation table which became quite big
+after commit 4c2c8f03a5ab ("tcp: increase source port perturb table to 2^16")
+
+get_random_once() uses DO_ONCE(), which block hard irqs for the duration
+of the operation.
+
+This patch adds DO_ONCE_SLOW() which uses a mutex instead of a spinlock
+for operations where we prefer to stay in process context.
+
+Then __inet_hash_connect() can use get_random_slow_once()
+to populate its perturbation table.
+
+Fixes: 4c2c8f03a5ab ("tcp: increase source port perturb table to 2^16")
+Fixes: 190cc82489f4 ("tcp: change source port randomizarion at connect() time")
+Reported-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Link: https://lore.kernel.org/netdev/CANn89iLAEYBaoYajy0Y9UmGFff5GPxDUoG-ErVB2jDdRNQ5Tug@mail.gmail.com/T/#t
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Cc: Willy Tarreau <w@1wt.eu>
+Tested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/once.h | 28 ++++++++++++++++++++++++++++
+ lib/once.c | 30 ++++++++++++++++++++++++++++++
+ net/ipv4/inet_hashtables.c | 4 ++--
+ 3 files changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/include/linux/once.h b/include/linux/once.h
+index d361fb14ac3a..1528625087b6 100644
+--- a/include/linux/once.h
++++ b/include/linux/once.h
+@@ -5,10 +5,18 @@
+ #include <linux/types.h>
+ #include <linux/jump_label.h>
+
++/* Helpers used from arbitrary contexts.
++ * Hard irqs are blocked, be cautious.
++ */
+ bool __do_once_start(bool *done, unsigned long *flags);
+ void __do_once_done(bool *done, struct static_key_true *once_key,
+ unsigned long *flags, struct module *mod);
+
++/* Variant for process contexts only. */
++bool __do_once_slow_start(bool *done);
++void __do_once_slow_done(bool *done, struct static_key_true *once_key,
++ struct module *mod);
++
+ /* Call a function exactly once. The idea of DO_ONCE() is to perform
+ * a function call such as initialization of random seeds, etc, only
+ * once, where DO_ONCE() can live in the fast-path. After @func has
+@@ -52,9 +60,29 @@ void __do_once_done(bool *done, struct static_key_true *once_key,
+ ___ret; \
+ })
+
++/* Variant of DO_ONCE() for process/sleepable contexts. */
++#define DO_ONCE_SLOW(func, ...) \
++ ({ \
++ bool ___ret = false; \
++ static bool __section(".data.once") ___done = false; \
++ static DEFINE_STATIC_KEY_TRUE(___once_key); \
++ if (static_branch_unlikely(&___once_key)) { \
++ ___ret = __do_once_slow_start(&___done); \
++ if (unlikely(___ret)) { \
++ func(__VA_ARGS__); \
++ __do_once_slow_done(&___done, &___once_key, \
++ THIS_MODULE); \
++ } \
++ } \
++ ___ret; \
++ })
++
+ #define get_random_once(buf, nbytes) \
+ DO_ONCE(get_random_bytes, (buf), (nbytes))
+ #define get_random_once_wait(buf, nbytes) \
+ DO_ONCE(get_random_bytes_wait, (buf), (nbytes)) \
+
++#define get_random_slow_once(buf, nbytes) \
++ DO_ONCE_SLOW(get_random_bytes, (buf), (nbytes))
++
+ #endif /* _LINUX_ONCE_H */
+diff --git a/lib/once.c b/lib/once.c
+index 59149bf3bfb4..351f66aad310 100644
+--- a/lib/once.c
++++ b/lib/once.c
+@@ -66,3 +66,33 @@ void __do_once_done(bool *done, struct static_key_true *once_key,
+ once_disable_jump(once_key, mod);
+ }
+ EXPORT_SYMBOL(__do_once_done);
++
++static DEFINE_MUTEX(once_mutex);
++
++bool __do_once_slow_start(bool *done)
++ __acquires(once_mutex)
++{
++ mutex_lock(&once_mutex);
++ if (*done) {
++ mutex_unlock(&once_mutex);
++ /* Keep sparse happy by restoring an even lock count on
++ * this mutex. In case we return here, we don't call into
++ * __do_once_done but return early in the DO_ONCE_SLOW() macro.
++ */
++ __acquire(once_mutex);
++ return false;
++ }
++
++ return true;
++}
++EXPORT_SYMBOL(__do_once_slow_start);
++
++void __do_once_slow_done(bool *done, struct static_key_true *once_key,
++ struct module *mod)
++ __releases(once_mutex)
++{
++ *done = true;
++ mutex_unlock(&once_mutex);
++ once_disable_jump(once_key, mod);
++}
++EXPORT_SYMBOL(__do_once_slow_done);
+diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c
+index 26c4dd4ec459..ce6a3873f89e 100644
+--- a/net/ipv4/inet_hashtables.c
++++ b/net/ipv4/inet_hashtables.c
+@@ -771,8 +771,8 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row,
+ if (likely(remaining > 1))
+ remaining &= ~1U;
+
+- net_get_random_once(table_perturb,
+- INET_TABLE_PERTURB_SIZE * sizeof(*table_perturb));
++ get_random_slow_once(table_perturb,
++ INET_TABLE_PERTURB_SIZE * sizeof(*table_perturb));
+ index = port_offset & (INET_TABLE_PERTURB_SIZE - 1);
+
+ offset = READ_ONCE(table_perturb[index]) + (port_offset >> 32);
+--
+2.35.1
+
--- /dev/null
+From cd0a591e51fbac6cf0381cb56478f7aabf64b84c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Aug 2022 11:06:34 -0400
+Subject: openvswitch: Fix double reporting of drops in dropwatch
+
+From: Mike Pattrick <mkp@redhat.com>
+
+[ Upstream commit 1100248a5c5ccd57059eb8d02ec077e839a23826 ]
+
+Frames sent to userspace can be reported as dropped in
+ovs_dp_process_packet, however, if they are dropped in the netlink code
+then netlink_attachskb will report the same frame as dropped.
+
+This patch checks for error codes which indicate that the frame has
+already been freed.
+
+Signed-off-by: Mike Pattrick <mkp@redhat.com>
+Link: https://bugzilla.redhat.com/show_bug.cgi?id=2109946
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/openvswitch/datapath.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c
+index 5e2c83cb7b12..f4b088d418fb 100644
+--- a/net/openvswitch/datapath.c
++++ b/net/openvswitch/datapath.c
+@@ -251,10 +251,17 @@ void ovs_dp_process_packet(struct sk_buff *skb, struct sw_flow_key *key)
+
+ upcall.mru = OVS_CB(skb)->mru;
+ error = ovs_dp_upcall(dp, skb, key, &upcall, 0);
+- if (unlikely(error))
+- kfree_skb(skb);
+- else
++ switch (error) {
++ case 0:
++ case -EAGAIN:
++ case -ERESTARTSYS:
++ case -EINTR:
+ consume_skb(skb);
++ break;
++ default:
++ kfree_skb(skb);
++ break;
++ }
+ stats_counter = &stats->n_missed;
+ goto out;
+ }
+--
+2.35.1
+
--- /dev/null
+From 2ee04245541aada4c9260842401fdf509e8e1246 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Aug 2022 11:06:35 -0400
+Subject: openvswitch: Fix overreporting of drops in dropwatch
+
+From: Mike Pattrick <mkp@redhat.com>
+
+[ Upstream commit c21ab2afa2c64896a7f0e3cbc6845ec63dcfad2e ]
+
+Currently queue_userspace_packet will call kfree_skb for all frames,
+whether or not an error occurred. This can result in a single dropped
+frame being reported as multiple drops in dropwatch. This functions
+caller may also call kfree_skb in case of an error. This patch will
+consume the skbs instead and allow caller's to use kfree_skb.
+
+Signed-off-by: Mike Pattrick <mkp@redhat.com>
+Link: https://bugzilla.redhat.com/show_bug.cgi?id=2109957
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/openvswitch/datapath.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c
+index f4b088d418fb..46ef1525b2e5 100644
+--- a/net/openvswitch/datapath.c
++++ b/net/openvswitch/datapath.c
+@@ -557,8 +557,9 @@ static int queue_userspace_packet(struct datapath *dp, struct sk_buff *skb,
+ out:
+ if (err)
+ skb_tx_error(skb);
+- kfree_skb(user_skb);
+- kfree_skb(nskb);
++ consume_skb(user_skb);
++ consume_skb(nskb);
++
+ return err;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From e8bf62d2b3ba0d3ce638ec7c62e9aa8961052730 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 15 Sep 2022 17:35:06 +0800
+Subject: phy: amlogic: phy-meson-axg-mipi-pcie-analog: Hold reference returned
+ by of_get_parent()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit c4c349be07aeec5f397a349046dc5fc0f2657691 ]
+
+As the of_get_parent() will increase the refcount of the node->parent
+and the reference will be discarded, so we should hold the reference
+with which we can decrease the refcount when done.
+
+Fixes: 8eff8b4e22d9 ("phy: amlogic: phy-meson-axg-mipi-pcie-analog: add support for MIPI DSI analog")
+Signed-off-by: Liang He <windhl@126.com>
+
+Link: https://lore.kernel.org/r/20220915093506.4009456-1-windhl@126.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
+index 1027ece6ca12..a3e1108b736d 100644
+--- a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
++++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
+@@ -197,7 +197,7 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
+ struct phy_provider *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_axg_mipi_pcie_analog_priv *priv;
+- struct device_node *np = dev->of_node;
++ struct device_node *np = dev->of_node, *parent_np;
+ struct regmap *map;
+ int ret;
+
+@@ -206,7 +206,9 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
+ return -ENOMEM;
+
+ /* Get the hhi system controller node */
+- map = syscon_node_to_regmap(of_get_parent(dev->of_node));
++ parent_np = of_get_parent(dev->of_node);
++ map = syscon_node_to_regmap(parent_np);
++ of_node_put(parent_np);
+ if (IS_ERR(map)) {
+ dev_err(dev,
+ "failed to get HHI regmap\n");
+--
+2.35.1
+
--- /dev/null
+From f35f1096263df8ad5f3c6ab3f763954b7133b58e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 14:07:46 +0800
+Subject: phy: phy-mtk-tphy: fix the phy type setting issue
+
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+[ Upstream commit 931c05a8cb1be029ef2fbc1e4af313d4cb297c47 ]
+
+The PHY type is not set if the index is non zero, prepare type
+value according to the index, like as mask value.
+
+Fixes: 39099a443358 ("phy: phy-mtk-tphy: support type switch by pericfg")
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20220914060746.10004-7-chunfeng.yun@mediatek.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
+index db39b0c4649a..0649c08fe310 100644
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -1039,7 +1039,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance,
+ static int phy_type_set(struct mtk_phy_instance *instance)
+ {
+ int type;
+- u32 mask;
++ u32 offset;
+
+ if (!instance->type_sw)
+ return 0;
+@@ -1062,8 +1062,9 @@ static int phy_type_set(struct mtk_phy_instance *instance)
+ return 0;
+ }
+
+- mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);
+- regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);
++ offset = instance->type_sw_index * BITS_PER_BYTE;
++ regmap_update_bits(instance->type_sw, instance->type_sw_reg,
++ RG_PHY_SW_TYPE << offset, type << offset);
+
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From f3aca84b69977d7c024d9fbf52163de4b852df22 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 13:07:13 +0200
+Subject: phy: qcom-qmp-combo: disable runtime PM on unbind
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 4382d518d1887e62234560ea08a0203d11d28cc1 ]
+
+Make sure to disable runtime PM also on driver unbind.
+
+Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM").
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220907110728.19092-2-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+index c7309e981bfb..dcf8a8764e17 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ return -ENOMEM;
+
+ pm_runtime_set_active(dev);
+- pm_runtime_enable(dev);
++ ret = devm_pm_runtime_enable(dev);
++ if (ret)
++ return ret;
+ /*
+ * Prevent runtime pm from being ON by default. Users can enable
+ * it using power/control in sysfs.
+@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (!IS_ERR(phy_provider))
+ dev_info(dev, "Registered Qcom-QMP phy\n");
+- else
+- pm_runtime_disable(dev);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+
+ err_node_put:
+- pm_runtime_disable(dev);
+ of_node_put(child);
+ return ret;
+ }
+--
+2.35.1
+
--- /dev/null
+From 69765e7de0ba351b70966b2521e979d8f21312c8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:33 +0200
+Subject: phy: qcom-qmp-combo: fix memleak on probe deferral
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 2de8a325b1084330ae500380cc27edc39f488c30 ]
+
+Switch to using the device-managed of_iomap helper to avoid leaking
+memory on probe deferral and driver unbind.
+
+Note that this helper checks for already reserved regions and may fail
+if there are multiple devices claiming the same memory.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-5-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 32 ++++++++++++-----------
+ 1 file changed, 17 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+index dcf8a8764e17..5606b25ea229 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -5919,17 +5919,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
+ * For single lane PHYs: pcs_misc (optional) -> 3.
+ */
+- qphy->tx = of_iomap(np, 0);
+- if (!qphy->tx)
+- return -ENOMEM;
++ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
++ if (IS_ERR(qphy->tx))
++ return PTR_ERR(qphy->tx);
+
+- qphy->rx = of_iomap(np, 1);
+- if (!qphy->rx)
+- return -ENOMEM;
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (IS_ERR(qphy->rx))
++ return PTR_ERR(qphy->rx);
+
+- qphy->pcs = of_iomap(np, 2);
+- if (!qphy->pcs)
+- return -ENOMEM;
++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
++ if (IS_ERR(qphy->pcs))
++ return PTR_ERR(qphy->pcs);
+
+ /*
+ * If this is a dual-lane PHY, then there should be registers for the
+@@ -5938,9 +5938,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * offset from the first lane.
+ */
+ if (cfg->is_dual_lane_phy) {
+- qphy->tx2 = of_iomap(np, 3);
+- qphy->rx2 = of_iomap(np, 4);
+- if (!qphy->tx2 || !qphy->rx2) {
++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) {
+ dev_warn(dev,
+ "Underspecified device tree, falling back to legacy register regions\n");
+
+@@ -5950,15 +5950,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 5);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
+ }
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 3);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
+ }
+
+- if (!qphy->pcs_misc)
++ if (IS_ERR(qphy->pcs_misc)) {
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++ qphy->pcs_misc = NULL;
++ }
+
+ /*
+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
+--
+2.35.1
+
--- /dev/null
+From edca98098cfb0438ee6b6b44d1ec1aa82e966554 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:35:32 +0300
+Subject: phy: qcom-qmp: create copies of QMP PHY driver
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
+
+In order to split and cleanup the single monstrous QMP PHY driver,
+create blind copies of the current file. They will be used for:
+- PCIe (and a separate msm8996 PCIe PHY driver)
+- UFS
+- USB
+- Combo DP + USB
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 4382d518d188 ("phy: qcom-qmp-combo: disable runtime PM on unbind")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6350 +++++++++++++++++
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6350 +++++++++++++++++
+ 5 files changed, 31750 insertions(+)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+new file mode 100644
+index 000000000000..c7309e981bfb
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN BIT(0)
++#define REFCLK_DRV_DSBL BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START BIT(0)
++#define PCS_START BIT(1)
++#define PLL_READY_GATE_EN BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS BIT(6)
++#define PHYSTATUS_4_20 BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE BIT(0) /* enables USB3 mode */
++#define DP_MODE BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN BIT(0)
++#define ALFPS_DTCT_EN BIT(1)
++#define ARCVR_DTCT_EVENT_SEL BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT 10000
++#define POWER_DOWN_DELAY_US_MIN 10
++#define POWER_DOWN_DELAY_US_MAX 11
++
++#define MAX_PROP_NAME 32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
++
++struct qmp_phy_init_tbl {
++ unsigned int offset;
++ unsigned int val;
++ /*
++ * register part of layout ?
++ * if yes, then offset gives index in the reg-layout
++ */
++ bool in_layout;
++ /*
++ * mask of lanes for which this register is written
++ * for cases when second lane needs different values
++ */
++ u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_L(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .in_layout = true, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = l, \
++ }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++ /* Common block control registers */
++ QPHY_COM_SW_RESET,
++ QPHY_COM_POWER_DOWN_CONTROL,
++ QPHY_COM_START_CONTROL,
++ QPHY_COM_PCS_READY_STATUS,
++ /* PCS registers */
++ QPHY_PLL_LOCK_CHK_DLY_TIME,
++ QPHY_FLL_CNTRL1,
++ QPHY_FLL_CNTRL2,
++ QPHY_FLL_CNT_VAL_L,
++ QPHY_FLL_CNT_VAL_H_TOL,
++ QPHY_FLL_MAN_CODE,
++ QPHY_SW_RESET,
++ QPHY_START_CTRL,
++ QPHY_PCS_READY_STATUS,
++ QPHY_PCS_STATUS,
++ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++ QPHY_PCS_POWER_DOWN_CONTROL,
++ /* PCS_MISC registers */
++ QPHY_PCS_MISC_TYPEC_CTRL,
++ /* Keep last to ensure regs_layout arrays are properly initialized */
++ QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_COM_SW_RESET] = 0x400,
++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
++ [QPHY_COM_START_CONTROL] = 0x408,
++ [QPHY_COM_PCS_READY_STATUS] = 0x448,
++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
++ [QPHY_FLL_CNTRL1] = 0xc4,
++ [QPHY_FLL_CNTRL2] = 0xc8,
++ [QPHY_FLL_CNT_VAL_L] = 0xcc,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
++ [QPHY_FLL_MAN_CODE] = 0xd4,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_FLL_CNTRL1] = 0xc0,
++ [QPHY_FLL_CNTRL2] = 0xc4,
++ [QPHY_FLL_CNT_VAL_L] = 0xc8,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
++ [QPHY_FLL_MAN_CODE] = 0xd0,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x17c,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
++
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
++
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
++
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
++
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
++
++ /* array of registers with different offsets */
++ const unsigned int *regs;
++
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
++
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
++
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
++
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
++
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
++
++ struct qmp_phy **phys;
++
++ struct mutex phy_mutex;
++ int init_count;
++
++ struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++ "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++ "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++ "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++ "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++ "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++ "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++ "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++ "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++ "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++ "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++ "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
++
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_ufs_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++ .tx_tbl = msm8996_ufs_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++ .rx_tbl = msm8996_ufs_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++ .clk_list = msm8996_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++
++ .regs = msm8996_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = msm8996_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++ .pcs_tbl = msm8996_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++ "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++ "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++ .tx_tbl = ipq8074_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++ .rx_tbl = ipq8074_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++ .pcs_tbl = ipq8074_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq6018_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++ .tx_tbl = ipq6018_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++ .rx_tbl = ipq6018_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++ .pcs_tbl = ipq6018_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = ipq_pciephy_gen3_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qmp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qhp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++ .tx_tbl = qmp_v3_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++ .usb_cfg = &sc7180_usb3phy_cfg,
++ .dp_cfg = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++ .tx_tbl = sdm845_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++ .rx_tbl = sdm845_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++ .tx_tbl = sm6115_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++ .rx_tbl = sm6115_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm6115_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++
++ .is_dual_lane_phy = false,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++ .tx_tbl = msm8998_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++ .rx_tbl = msm8998_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++ .pcs_tbl = msm8998_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++ .tx_tbl = msm8998_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++ .rx_tbl = msm8998_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++ .pcs_tbl = msm8998_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++ .tx_tbl = sm8150_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++ .rx_tbl = sm8150_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8150_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++ .rx_tbl = sm8150_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++ .pcs_tbl = sm8150_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++ .usb_cfg = &sm8150_usb3phy_cfg,
++ .dp_cfg = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8250_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++ .rx_tbl = sm8250_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++ .pcs_tbl = sm8250_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++ .usb_cfg = &sm8250_usb3phy_cfg,
++ .dp_cfg = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8350_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++ .rx_tbl = sm8350_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++ .pcs_tbl = sm8350_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sm8450_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qcm2290_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++ .tx_tbl = qcm2290_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++ .rx_tbl = qcm2290_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++ .pcs_tbl = qcm2290_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++ .clk_list = qcm2290_usb3phy_clk_l,
++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++ .reset_list = qcm2290_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qcm2290_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num,
++ u8 lane_mask)
++{
++ int i;
++ const struct qmp_phy_init_tbl *t = tbl;
++
++ if (!t)
++ return;
++
++ for (i = 0; i < num; i++, t++) {
++ if (!(t->lane_mask & lane_mask))
++ continue;
++
++ if (t->in_layout)
++ writel(t->val, base + regs[t->offset]);
++ else
++ writel(t->val, base + t->offset);
++ }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num)
++{
++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++ int serdes_tbl_num = cfg->serdes_tbl_num;
++ int ret;
++
++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ if (cfg->serdes_tbl_sec)
++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ cfg->serdes_tbl_num_sec);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ switch (dp_opts->link_rate) {
++ case 1620:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_rbr,
++ cfg->serdes_tbl_rbr_num);
++ break;
++ case 2700:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr,
++ cfg->serdes_tbl_hbr_num);
++ break;
++ case 5400:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr2,
++ cfg->serdes_tbl_hbr2_num);
++ break;
++ case 8100:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr3,
++ cfg->serdes_tbl_hbr3_num);
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ }
++
++
++ if (cfg->has_phy_com_ctrl) {
++ void __iomem *status;
++ unsigned int mask, val;
++
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
++
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++ DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(QSERDES_V3_COM_BIAS_EN |
++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++ { 0x00, 0x0c, 0x15, 0x1a },
++ { 0x02, 0x0e, 0x16, 0xff },
++ { 0x02, 0x11, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++ { 0x02, 0x12, 0x16, 0x1a },
++ { 0x09, 0x19, 0x1f, 0xff },
++ { 0x10, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++ { 0x00, 0x0c, 0x14, 0x19 },
++ { 0x00, 0x0b, 0x12, 0xff },
++ { 0x00, 0x0b, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++ { 0x08, 0x0f, 0x16, 0x1f },
++ { 0x11, 0x1e, 0x1f, 0xff },
++ { 0x19, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ unsigned int v_level = 0, p_level = 0;
++ u8 voltage_swing_cfg, pre_emphasis_cfg;
++ int i;
++
++ for (i = 0; i < dp_opts->lanes; i++) {
++ v_level = max(v_level, dp_opts->voltage[i]);
++ p_level = max(p_level, dp_opts->pre[i]);
++ }
++
++ if (dp_opts->link_rate <= 2700) {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++ } else {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++ }
++
++ /* TODO: Move check to config check */
++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++ return -EINVAL;
++
++ /* Enable MUX to use Cursor values from these registers */
++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 bias_en, drvr_en;
++
++ if (qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V3_TX_TX_DRV_LVL,
++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++ return;
++
++ if (dp_opts->lanes == 1) {
++ bias_en = 0x3e;
++ drvr_en = 0x13;
++ } else {
++ bias_en = 0x3f;
++ drvr_en = 0x10;
++ }
++
++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++ u32 val;
++ bool reverse = false;
++
++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++ /*
++ * TODO: Assume orientation is CC1 for now and two lanes, need to
++ * use type-c connector to understand orientation and lanes.
++ *
++ * Otherwise val changes to be like below if this code understood
++ * the orientation of the type-c cable.
++ *
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ * if (orientation == ORIENTATION_CC2)
++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++ */
++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++ return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++
++ qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ /* Program default values before writing proper values */
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V4_TX_TX_DRV_LVL,
++ QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++ bool reverse;
++
++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ /*
++ * At least for 7nm DP PHY this has to be done after enabling link
++ * clock.
++ */
++
++ if (dp_opts->lanes == 1) {
++ bias0_en = reverse ? 0x3e : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3e;
++ drvr0_en = reverse ? 0x13 : 0x10;
++ drvr1_en = reverse ? 0x10 : 0x13;
++ } else if (dp_opts->lanes == 2) {
++ bias0_en = reverse ? 0x3f : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ } else {
++ bias0_en = 0x3f;
++ bias1_en = 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ }
++
++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++ if (qphy->dp_opts.set_voltages) {
++ cfg->configure_dp_tx(qphy);
++ qphy->dp_opts.set_voltages = 0;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->calibrate_dp_phy)
++ return cfg->calibrate_dp_phy(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *dp_com = qmp->dp_com;
++ int ret, i;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (qmp->init_count++) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ /* turn on regulator supplies */
++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++ if (ret) {
++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++ goto err_unlock;
++ }
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ ret = reset_control_assert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset assert failed\n",
++ cfg->reset_list[i]);
++ goto err_disable_regulators;
++ }
++ }
++
++ for (i = cfg->num_resets - 1; i >= 0; i--) {
++ ret = reset_control_deassert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset deassert failed\n",
++ qphy->cfg->reset_list[i]);
++ goto err_assert_reset;
++ }
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ goto err_assert_reset;
++
++ if (cfg->has_phy_dp_com_ctrl) {
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++ SW_PWRDN);
++ /* override hardware control for reset of qmp phy */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ /* Default type-c orientation, i.e CC1 */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++ USB3_MODE | DP_MODE);
++
++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++ }
++
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ } else {
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++
++err_assert_reset:
++ while (++i < cfg->num_resets)
++ reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++ mutex_unlock(&qmp->phy_mutex);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ int i = cfg->num_resets;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (--qmp->init_count) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ reset_control_assert(qmp->ufs_reset);
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ }
++
++ while (--i >= 0)
++ reset_control_assert(qmp->resets[i]);
++
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret;
++ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++ if (cfg->no_pcs_sw_reset) {
++ /*
++ * Get UFS reset, which is delayed until now to avoid a
++ * circular dependency where UFS needs its PHY, but the PHY
++ * needs this UFS reset.
++ */
++ if (!qmp->ufs_reset) {
++ qmp->ufs_reset =
++ devm_reset_control_get_exclusive(qmp->dev,
++ "ufsphy");
++
++ if (IS_ERR(qmp->ufs_reset)) {
++ ret = PTR_ERR(qmp->ufs_reset);
++ dev_err(qmp->dev,
++ "failed to get UFS reset: %d\n",
++ ret);
++
++ qmp->ufs_reset = NULL;
++ return ret;
++ }
++ }
++
++ ret = reset_control_assert(qmp->ufs_reset);
++ if (ret)
++ return ret;
++ }
++
++ ret = qcom_qmp_phy_com_init(qphy);
++ if (ret)
++ return ret;
++
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->dp_aux_init(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *tx = qphy->tx;
++ void __iomem *rx = qphy->rx;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ void __iomem *status;
++ unsigned int mask, val, ready;
++ int ret;
++
++ qcom_qmp_phy_serdes_init(qphy);
++
++ if (cfg->has_lane_rst) {
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
++ }
++ }
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++ goto err_reset_lane;
++ }
++
++ /* Tx, Rx, and PCS configurations */
++ qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 1);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 1);
++
++ /* Configuration for other LANE for USB-DP combo PHY */
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 2);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 2);
++ }
++
++ /* Configure special DP tx tunings */
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->configure_dp_tx(qphy);
++
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 1);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 2);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl_sec,
++ cfg->rx_tbl_num_sec, 2);
++ }
++
++ /* Configure link rate, swing, etc. */
++ if (cfg->type == PHY_TYPE_DP) {
++ cfg->configure_dp_phy(qphy);
++ } else {
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
++ }
++
++ ret = reset_control_deassert(qmp->ufs_reset);
++ if (ret)
++ goto err_disable_pipe_clk;
++
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ cfg->pcs_misc_tbl_num);
++ if (cfg->pcs_misc_tbl_sec)
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ cfg->pcs_misc_tbl_num_sec);
++
++ /*
++ * Pull out PHY from POWER DOWN state.
++ * This is active low enable signal to power-down PHY.
++ */
++ if(cfg->type == PHY_TYPE_PCIE)
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++ if (cfg->has_pwrdn_delay)
++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++ if (cfg->type != PHY_TYPE_DP) {
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ if (cfg->type == PHY_TYPE_UFS) {
++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++ mask = PCS_READY;
++ ready = PCS_READY;
++ } else {
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++ }
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
++ }
++ }
++ return 0;
++
++err_disable_pipe_clk:
++ clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ clk_disable_unprepare(qphy->pipe_clk);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ /* Assert DP PHY power down */
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++ } else {
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ qcom_qmp_phy_com_exit(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_init(phy);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_power_on(phy);
++ if (ret)
++ qcom_qmp_phy_exit(phy);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_power_off(phy);
++ if (ret)
++ return ret;
++ return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++ enum phy_mode mode, int submode)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++ qphy->mode = mode;
++
++ return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ u32 intr_mask;
++
++ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++ qphy->mode == PHY_MODE_USB_DEVICE_SS)
++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++ else
++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++ /* Clear any pending interrupts status */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++ /* Enable required PHY autonomous mode interrupts */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++ /* Enable i/o clamp_n for autonomous mode */
++ if (pcs_misc)
++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++
++ /* Disable i/o clamp_n on resume for normal mode */
++ if (pcs_misc)
++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++ clk_disable_unprepare(qphy->pipe_clk);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret = 0;
++
++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++ return ret;
++ }
++
++ qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_vregs;
++ int i;
++
++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++ if (!qmp->vregs)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->vregs[i].supply = cfg->vreg_list[i];
++
++ return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int i;
++
++ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++ sizeof(*qmp->resets), GFP_KERNEL);
++ if (!qmp->resets)
++ return -ENOMEM;
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ struct reset_control *rst;
++ const char *name = cfg->reset_list[i];
++
++ rst = devm_reset_control_get_exclusive(dev, name);
++ if (IS_ERR(rst)) {
++ dev_err(dev, "failed to get %s reset\n", name);
++ return PTR_ERR(rst);
++ }
++ qmp->resets[i] = rst;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_clks;
++ int i;
++
++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++ if (!qmp->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->clks[i].id = cfg->clk_list[i];
++
++ return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++ of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ * +---------------+
++ * | PHY block |<<---------------------------------------+
++ * | | |
++ * | +-------+ | +-----+ |
++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ * clk | +-------+ | +-----+
++ * +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++ struct clk_fixed_rate *fixed;
++ struct clk_init_data init = { };
++ int ret;
++
++ ret = of_property_read_string(np, "clock-output-names", &init.name);
++ if (ret) {
++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++ return ret;
++ }
++
++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++ if (!fixed)
++ return -ENOMEM;
++
++ init.ops = &clk_fixed_rate_ops;
++
++ /* controllers using QMP phys use 125MHz pipe clock interface */
++ fixed->fixed_rate = 125000000;
++ fixed->hw.init = &init;
++
++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ * +------------------------------+
++ * | DP_VCO_CLK |
++ * | |
++ * | +-------------------+ |
++ * | | (DP PLL/VCO) | |
++ * | +---------+---------+ |
++ * | v |
++ * | +----------+-----------+ |
++ * | | hsclk_divsel_clk_src | |
++ * | +----------+-----------+ |
++ * +------------------------------+
++ * |
++ * +---------<---------v------------>----------+
++ * | |
++ * +--------v----------------+ |
++ * | dp_phy_pll_link_clk | |
++ * | link_clk | |
++ * +--------+----------------+ |
++ * | |
++ * | |
++ * v v
++ * Input to DISPCC block |
++ * for link clk, crypto clk |
++ * and interface clock |
++ * |
++ * |
++ * +--------<------------+-----------------+---<---+
++ * | | |
++ * +----v---------+ +--------v-----+ +--------v------+
++ * | vco_divided | | vco_divided | | vco_divided |
++ * | _clk_src | | _clk_src | | _clk_src |
++ * | | | | | |
++ * |divsel_six | | divsel_two | | divsel_four |
++ * +-------+------+ +-----+--------+ +--------+------+
++ * | | |
++ * v---->----------v-------------<------v
++ * |
++ * +----------+-----------------+
++ * | dp_phy_pll_vco_div_clk |
++ * +---------+------------------+
++ * |
++ * v
++ * Input to DISPCC block
++ * for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 1620000000UL / 2:
++ case 2700000000UL / 2:
++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ return 1620000000UL / 2;
++ case 2700:
++ return 2700000000UL / 2;
++ case 5400:
++ return 5400000000UL / 4;
++ case 8100:
++ return 8100000000UL / 6;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 162000000:
++ case 270000000:
++ case 540000000:
++ case 810000000:
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ return dp_opts->link_rate * 100000;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct qmp_phy_dp_clks *dp_clks = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx >= 2) {
++ pr_err("%s: invalid index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (idx == 0)
++ return &dp_clks->dp_link_hw;
++
++ return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++ struct device_node *np)
++{
++ struct clk_init_data init = { };
++ struct qmp_phy_dp_clks *dp_clks;
++ char name[64];
++ int ret;
++
++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++ if (!dp_clks)
++ return -ENOMEM;
++
++ dp_clks->qphy = qphy;
++ qphy->dp_clks = dp_clks;
++
++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_link_clk_ops;
++ init.name = name;
++ dp_clks->dp_link_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++ if (ret)
++ return ret;
++
++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_pixel_clk_ops;
++ init.name = name;
++ dp_clks->dp_pixel_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++ .init = qcom_qmp_phy_enable,
++ .exit = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++ .init = qcom_qmp_phy_init,
++ .configure = qcom_qmp_dp_phy_configure,
++ .power_on = qcom_qmp_phy_power_on,
++ .calibrate = qcom_qmp_dp_phy_calibrate,
++ .power_off = qcom_qmp_phy_power_off,
++ .exit = qcom_qmp_phy_exit,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++ .power_on = qcom_qmp_phy_enable,
++ .power_off = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++ reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct phy *generic_phy;
++ struct qmp_phy *qphy;
++ const struct phy_ops *ops;
++ char prop_name[MAX_PROP_NAME];
++ int ret;
++
++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++ if (!qphy)
++ return -ENOMEM;
++
++ qphy->cfg = cfg;
++ qphy->serdes = serdes;
++ /*
++ * Get memory resources for each phy lane:
++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++ * For single lane PHYs: pcs_misc (optional) -> 3.
++ */
++ qphy->tx = of_iomap(np, 0);
++ if (!qphy->tx)
++ return -ENOMEM;
++
++ qphy->rx = of_iomap(np, 1);
++ if (!qphy->rx)
++ return -ENOMEM;
++
++ qphy->pcs = of_iomap(np, 2);
++ if (!qphy->pcs)
++ return -ENOMEM;
++
++ /*
++ * If this is a dual-lane PHY, then there should be registers for the
++ * second lane. Some old device trees did not specify this, so fall
++ * back to old legacy behavior of assuming they can be reached at an
++ * offset from the first lane.
++ */
++ if (cfg->is_dual_lane_phy) {
++ qphy->tx2 = of_iomap(np, 3);
++ qphy->rx2 = of_iomap(np, 4);
++ if (!qphy->tx2 || !qphy->rx2) {
++ dev_warn(dev,
++ "Underspecified device tree, falling back to legacy register regions\n");
++
++ /* In the old version, pcs_misc is at index 3. */
++ qphy->pcs_misc = qphy->tx2;
++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 5);
++ }
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 3);
++ }
++
++ if (!qphy->pcs_misc)
++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++ /*
++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++ * based phys, so they essentially have pipe clock. So,
++ * we return error in case phy is USB3 or PIPE type.
++ * Otherwise, we initialize pipe clock to NULL for
++ * all phys that don't need this.
++ */
++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ if (IS_ERR(qphy->pipe_clk)) {
++ if (cfg->type == PHY_TYPE_PCIE ||
++ cfg->type == PHY_TYPE_USB3) {
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
++ }
++ qphy->pipe_clk = NULL;
++ }
++
++ /* Get lane reset, if any */
++ if (cfg->has_lane_rst) {
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
++ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
++ }
++
++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++ ops = &qcom_qmp_pcie_ufs_ops;
++ else if (cfg->type == PHY_TYPE_DP)
++ ops = &qcom_qmp_phy_dp_ops;
++ else
++ ops = &qcom_qmp_phy_gen_ops;
++
++ generic_phy = devm_phy_create(dev, np, ops);
++ if (IS_ERR(generic_phy)) {
++ ret = PTR_ERR(generic_phy);
++ dev_err(dev, "failed to create qphy %d\n", ret);
++ return ret;
++ }
++
++ qphy->phy = generic_phy;
++ qphy->index = id;
++ qphy->qmp = qmp;
++ qmp->phys[id] = qphy;
++ phy_set_drvdata(generic_phy, qphy);
++
++ return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,ipq8074-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-pcie-phy",
++ .data = &msm8996_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-ufs-phy",
++ .data = &msm8996_ufs_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-usb3-phy",
++ .data = &msm8996_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-pcie-phy",
++ .data = &msm8998_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,ipq8074-qmp-pcie-phy",
++ .data = &ipq8074_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-pcie-phy",
++ .data = &ipq6018_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-phy",
++ .data = &sc7180_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sc8180x-qmp-pcie-phy",
++ .data = &sc8180x_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sdm845-qhp-pcie-phy",
++ .data = &sdm845_qhp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-pcie-phy",
++ .data = &sdm845_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-phy",
++ .data = &qmp_v3_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++ .data = &qmp_v3_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-usb3-phy",
++ .data = &msm8998_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm6115-qmp-ufs-phy",
++ .data = &sm6115_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm6350-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++ .data = &sm8150_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-phy",
++ .data = &sm8250_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++ .data = &sm8250_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-pcie-phy",
++ .data = &sdx55_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++ .data = &sdx55_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++ .data = &sdx65_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++ .data = &sm8350_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-ufs-phy",
++ .data = &sm8450_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,qcm2290-qmp-usb3-phy",
++ .data = &qcm2290_usb3phy_cfg,
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ .data = &sc7180_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ .data = &sm8250_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ .data = &sc8180x_usb3dpphy_cfg,
++ },
++ { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++ qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++ struct qcom_qmp *qmp;
++ struct device *dev = &pdev->dev;
++ struct device_node *child;
++ struct phy_provider *phy_provider;
++ void __iomem *serdes;
++ void __iomem *usb_serdes;
++ void __iomem *dp_serdes = NULL;
++ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++ const struct qmp_phy_cfg *cfg = NULL;
++ const struct qmp_phy_cfg *usb_cfg = NULL;
++ const struct qmp_phy_cfg *dp_cfg = NULL;
++ int num, id, expected_phys;
++ int ret;
++
++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++ if (!qmp)
++ return -ENOMEM;
++
++ qmp->dev = dev;
++ dev_set_drvdata(dev, qmp);
++
++ /* Get the specific init parameters of QMP phy */
++ cfg = of_device_get_match_data(dev);
++ if (!cfg) {
++ const struct of_device_id *match;
++
++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++ if (!match)
++ return -EINVAL;
++
++ combo_cfg = match->data;
++ if (!combo_cfg)
++ return -EINVAL;
++
++ usb_cfg = combo_cfg->usb_cfg;
++ cfg = usb_cfg; /* Setup clks and regulators */
++ }
++
++ /* per PHY serdes; usually located at base address */
++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(serdes))
++ return PTR_ERR(serdes);
++
++ /* per PHY dp_com; if PHY has dp_com control block */
++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(qmp->dp_com))
++ return PTR_ERR(qmp->dp_com);
++ }
++
++ if (combo_cfg) {
++ /* Only two serdes for combo PHY */
++ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++ if (IS_ERR(dp_serdes))
++ return PTR_ERR(dp_serdes);
++
++ dp_cfg = combo_cfg->dp_cfg;
++ expected_phys = 2;
++ } else {
++ expected_phys = cfg->nlanes;
++ }
++
++ mutex_init(&qmp->phy_mutex);
++
++ ret = qcom_qmp_phy_clk_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_reset_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ if (ret) {
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "failed to get regulator supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ num = of_get_available_child_count(dev->of_node);
++ /* do we have a rogue child node ? */
++ if (num > expected_phys)
++ return -EINVAL;
++
++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++ if (!qmp->phys)
++ return -ENOMEM;
++
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ /*
++ * Prevent runtime pm from being ON by default. Users can enable
++ * it using power/control in sysfs.
++ */
++ pm_runtime_forbid(dev);
++
++ id = 0;
++ for_each_available_child_of_node(dev->of_node, child) {
++ if (of_node_name_eq(child, "dp-phy")) {
++ cfg = dp_cfg;
++ serdes = dp_serdes;
++ } else if (of_node_name_eq(child, "usb3-phy")) {
++ cfg = usb_cfg;
++ serdes = usb_serdes;
++ }
++
++ /* Create per-lane phy */
++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ if (ret) {
++ dev_err(dev, "failed to create lane%d phy, %d\n",
++ id, ret);
++ goto err_node_put;
++ }
++
++ /*
++ * Register the pipe clock provided by phy.
++ * See function description to see details of this pipe clock.
++ */
++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
++ }
++ } else if (cfg->type == PHY_TYPE_DP) {
++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register DP clock source\n");
++ goto err_node_put;
++ }
++ }
++ id++;
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ if (!IS_ERR(phy_provider))
++ dev_info(dev, "Registered Qcom-QMP phy\n");
++ else
++ pm_runtime_disable(dev);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++ pm_runtime_disable(dev);
++ of_node_put(child);
++ return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++ .probe = qcom_qmp_phy_probe,
++ .driver = {
++ .name = "qcom-qmp-phy",
++ .pm = &qcom_qmp_phy_pm_ops,
++ .of_match_table = qcom_qmp_phy_of_match_table,
++ },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+new file mode 100644
+index 000000000000..c7309e981bfb
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN BIT(0)
++#define REFCLK_DRV_DSBL BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START BIT(0)
++#define PCS_START BIT(1)
++#define PLL_READY_GATE_EN BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS BIT(6)
++#define PHYSTATUS_4_20 BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE BIT(0) /* enables USB3 mode */
++#define DP_MODE BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN BIT(0)
++#define ALFPS_DTCT_EN BIT(1)
++#define ARCVR_DTCT_EVENT_SEL BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT 10000
++#define POWER_DOWN_DELAY_US_MIN 10
++#define POWER_DOWN_DELAY_US_MAX 11
++
++#define MAX_PROP_NAME 32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
++
++struct qmp_phy_init_tbl {
++ unsigned int offset;
++ unsigned int val;
++ /*
++ * register part of layout ?
++ * if yes, then offset gives index in the reg-layout
++ */
++ bool in_layout;
++ /*
++ * mask of lanes for which this register is written
++ * for cases when second lane needs different values
++ */
++ u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_L(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .in_layout = true, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = l, \
++ }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++ /* Common block control registers */
++ QPHY_COM_SW_RESET,
++ QPHY_COM_POWER_DOWN_CONTROL,
++ QPHY_COM_START_CONTROL,
++ QPHY_COM_PCS_READY_STATUS,
++ /* PCS registers */
++ QPHY_PLL_LOCK_CHK_DLY_TIME,
++ QPHY_FLL_CNTRL1,
++ QPHY_FLL_CNTRL2,
++ QPHY_FLL_CNT_VAL_L,
++ QPHY_FLL_CNT_VAL_H_TOL,
++ QPHY_FLL_MAN_CODE,
++ QPHY_SW_RESET,
++ QPHY_START_CTRL,
++ QPHY_PCS_READY_STATUS,
++ QPHY_PCS_STATUS,
++ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++ QPHY_PCS_POWER_DOWN_CONTROL,
++ /* PCS_MISC registers */
++ QPHY_PCS_MISC_TYPEC_CTRL,
++ /* Keep last to ensure regs_layout arrays are properly initialized */
++ QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_COM_SW_RESET] = 0x400,
++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
++ [QPHY_COM_START_CONTROL] = 0x408,
++ [QPHY_COM_PCS_READY_STATUS] = 0x448,
++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
++ [QPHY_FLL_CNTRL1] = 0xc4,
++ [QPHY_FLL_CNTRL2] = 0xc8,
++ [QPHY_FLL_CNT_VAL_L] = 0xcc,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
++ [QPHY_FLL_MAN_CODE] = 0xd4,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_FLL_CNTRL1] = 0xc0,
++ [QPHY_FLL_CNTRL2] = 0xc4,
++ [QPHY_FLL_CNT_VAL_L] = 0xc8,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
++ [QPHY_FLL_MAN_CODE] = 0xd0,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x17c,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
++
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
++
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
++
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
++
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
++
++ /* array of registers with different offsets */
++ const unsigned int *regs;
++
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
++
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
++
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
++
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
++
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
++
++ struct qmp_phy **phys;
++
++ struct mutex phy_mutex;
++ int init_count;
++
++ struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++ "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++ "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++ "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++ "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++ "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++ "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++ "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++ "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++ "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++ "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++ "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
++
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_ufs_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++ .tx_tbl = msm8996_ufs_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++ .rx_tbl = msm8996_ufs_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++ .clk_list = msm8996_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++
++ .regs = msm8996_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = msm8996_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++ .pcs_tbl = msm8996_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++ "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++ "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++ .tx_tbl = ipq8074_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++ .rx_tbl = ipq8074_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++ .pcs_tbl = ipq8074_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq6018_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++ .tx_tbl = ipq6018_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++ .rx_tbl = ipq6018_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++ .pcs_tbl = ipq6018_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = ipq_pciephy_gen3_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qmp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qhp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++ .tx_tbl = qmp_v3_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++ .usb_cfg = &sc7180_usb3phy_cfg,
++ .dp_cfg = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++ .tx_tbl = sdm845_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++ .rx_tbl = sdm845_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++ .tx_tbl = sm6115_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++ .rx_tbl = sm6115_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm6115_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++
++ .is_dual_lane_phy = false,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++ .tx_tbl = msm8998_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++ .rx_tbl = msm8998_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++ .pcs_tbl = msm8998_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++ .tx_tbl = msm8998_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++ .rx_tbl = msm8998_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++ .pcs_tbl = msm8998_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++ .tx_tbl = sm8150_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++ .rx_tbl = sm8150_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8150_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++ .rx_tbl = sm8150_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++ .pcs_tbl = sm8150_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++ .usb_cfg = &sm8150_usb3phy_cfg,
++ .dp_cfg = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8250_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++ .rx_tbl = sm8250_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++ .pcs_tbl = sm8250_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++ .usb_cfg = &sm8250_usb3phy_cfg,
++ .dp_cfg = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8350_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++ .rx_tbl = sm8350_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++ .pcs_tbl = sm8350_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sm8450_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qcm2290_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++ .tx_tbl = qcm2290_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++ .rx_tbl = qcm2290_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++ .pcs_tbl = qcm2290_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++ .clk_list = qcm2290_usb3phy_clk_l,
++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++ .reset_list = qcm2290_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qcm2290_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num,
++ u8 lane_mask)
++{
++ int i;
++ const struct qmp_phy_init_tbl *t = tbl;
++
++ if (!t)
++ return;
++
++ for (i = 0; i < num; i++, t++) {
++ if (!(t->lane_mask & lane_mask))
++ continue;
++
++ if (t->in_layout)
++ writel(t->val, base + regs[t->offset]);
++ else
++ writel(t->val, base + t->offset);
++ }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num)
++{
++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++ int serdes_tbl_num = cfg->serdes_tbl_num;
++ int ret;
++
++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ if (cfg->serdes_tbl_sec)
++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ cfg->serdes_tbl_num_sec);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ switch (dp_opts->link_rate) {
++ case 1620:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_rbr,
++ cfg->serdes_tbl_rbr_num);
++ break;
++ case 2700:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr,
++ cfg->serdes_tbl_hbr_num);
++ break;
++ case 5400:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr2,
++ cfg->serdes_tbl_hbr2_num);
++ break;
++ case 8100:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr3,
++ cfg->serdes_tbl_hbr3_num);
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ }
++
++
++ if (cfg->has_phy_com_ctrl) {
++ void __iomem *status;
++ unsigned int mask, val;
++
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
++
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++ DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(QSERDES_V3_COM_BIAS_EN |
++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++ { 0x00, 0x0c, 0x15, 0x1a },
++ { 0x02, 0x0e, 0x16, 0xff },
++ { 0x02, 0x11, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++ { 0x02, 0x12, 0x16, 0x1a },
++ { 0x09, 0x19, 0x1f, 0xff },
++ { 0x10, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++ { 0x00, 0x0c, 0x14, 0x19 },
++ { 0x00, 0x0b, 0x12, 0xff },
++ { 0x00, 0x0b, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++ { 0x08, 0x0f, 0x16, 0x1f },
++ { 0x11, 0x1e, 0x1f, 0xff },
++ { 0x19, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ unsigned int v_level = 0, p_level = 0;
++ u8 voltage_swing_cfg, pre_emphasis_cfg;
++ int i;
++
++ for (i = 0; i < dp_opts->lanes; i++) {
++ v_level = max(v_level, dp_opts->voltage[i]);
++ p_level = max(p_level, dp_opts->pre[i]);
++ }
++
++ if (dp_opts->link_rate <= 2700) {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++ } else {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++ }
++
++ /* TODO: Move check to config check */
++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++ return -EINVAL;
++
++ /* Enable MUX to use Cursor values from these registers */
++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 bias_en, drvr_en;
++
++ if (qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V3_TX_TX_DRV_LVL,
++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++ return;
++
++ if (dp_opts->lanes == 1) {
++ bias_en = 0x3e;
++ drvr_en = 0x13;
++ } else {
++ bias_en = 0x3f;
++ drvr_en = 0x10;
++ }
++
++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++ u32 val;
++ bool reverse = false;
++
++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++ /*
++ * TODO: Assume orientation is CC1 for now and two lanes, need to
++ * use type-c connector to understand orientation and lanes.
++ *
++ * Otherwise val changes to be like below if this code understood
++ * the orientation of the type-c cable.
++ *
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ * if (orientation == ORIENTATION_CC2)
++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++ */
++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++ return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++
++ qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ /* Program default values before writing proper values */
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V4_TX_TX_DRV_LVL,
++ QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++ bool reverse;
++
++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ /*
++ * At least for 7nm DP PHY this has to be done after enabling link
++ * clock.
++ */
++
++ if (dp_opts->lanes == 1) {
++ bias0_en = reverse ? 0x3e : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3e;
++ drvr0_en = reverse ? 0x13 : 0x10;
++ drvr1_en = reverse ? 0x10 : 0x13;
++ } else if (dp_opts->lanes == 2) {
++ bias0_en = reverse ? 0x3f : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ } else {
++ bias0_en = 0x3f;
++ bias1_en = 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ }
++
++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++ if (qphy->dp_opts.set_voltages) {
++ cfg->configure_dp_tx(qphy);
++ qphy->dp_opts.set_voltages = 0;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->calibrate_dp_phy)
++ return cfg->calibrate_dp_phy(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *dp_com = qmp->dp_com;
++ int ret, i;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (qmp->init_count++) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ /* turn on regulator supplies */
++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++ if (ret) {
++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++ goto err_unlock;
++ }
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ ret = reset_control_assert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset assert failed\n",
++ cfg->reset_list[i]);
++ goto err_disable_regulators;
++ }
++ }
++
++ for (i = cfg->num_resets - 1; i >= 0; i--) {
++ ret = reset_control_deassert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset deassert failed\n",
++ qphy->cfg->reset_list[i]);
++ goto err_assert_reset;
++ }
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ goto err_assert_reset;
++
++ if (cfg->has_phy_dp_com_ctrl) {
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++ SW_PWRDN);
++ /* override hardware control for reset of qmp phy */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ /* Default type-c orientation, i.e CC1 */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++ USB3_MODE | DP_MODE);
++
++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++ }
++
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ } else {
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++
++err_assert_reset:
++ while (++i < cfg->num_resets)
++ reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++ mutex_unlock(&qmp->phy_mutex);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ int i = cfg->num_resets;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (--qmp->init_count) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ reset_control_assert(qmp->ufs_reset);
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ }
++
++ while (--i >= 0)
++ reset_control_assert(qmp->resets[i]);
++
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret;
++ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++ if (cfg->no_pcs_sw_reset) {
++ /*
++ * Get UFS reset, which is delayed until now to avoid a
++ * circular dependency where UFS needs its PHY, but the PHY
++ * needs this UFS reset.
++ */
++ if (!qmp->ufs_reset) {
++ qmp->ufs_reset =
++ devm_reset_control_get_exclusive(qmp->dev,
++ "ufsphy");
++
++ if (IS_ERR(qmp->ufs_reset)) {
++ ret = PTR_ERR(qmp->ufs_reset);
++ dev_err(qmp->dev,
++ "failed to get UFS reset: %d\n",
++ ret);
++
++ qmp->ufs_reset = NULL;
++ return ret;
++ }
++ }
++
++ ret = reset_control_assert(qmp->ufs_reset);
++ if (ret)
++ return ret;
++ }
++
++ ret = qcom_qmp_phy_com_init(qphy);
++ if (ret)
++ return ret;
++
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->dp_aux_init(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *tx = qphy->tx;
++ void __iomem *rx = qphy->rx;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ void __iomem *status;
++ unsigned int mask, val, ready;
++ int ret;
++
++ qcom_qmp_phy_serdes_init(qphy);
++
++ if (cfg->has_lane_rst) {
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
++ }
++ }
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++ goto err_reset_lane;
++ }
++
++ /* Tx, Rx, and PCS configurations */
++ qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 1);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 1);
++
++ /* Configuration for other LANE for USB-DP combo PHY */
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 2);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 2);
++ }
++
++ /* Configure special DP tx tunings */
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->configure_dp_tx(qphy);
++
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 1);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 2);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl_sec,
++ cfg->rx_tbl_num_sec, 2);
++ }
++
++ /* Configure link rate, swing, etc. */
++ if (cfg->type == PHY_TYPE_DP) {
++ cfg->configure_dp_phy(qphy);
++ } else {
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
++ }
++
++ ret = reset_control_deassert(qmp->ufs_reset);
++ if (ret)
++ goto err_disable_pipe_clk;
++
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ cfg->pcs_misc_tbl_num);
++ if (cfg->pcs_misc_tbl_sec)
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ cfg->pcs_misc_tbl_num_sec);
++
++ /*
++ * Pull out PHY from POWER DOWN state.
++ * This is active low enable signal to power-down PHY.
++ */
++ if(cfg->type == PHY_TYPE_PCIE)
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++ if (cfg->has_pwrdn_delay)
++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++ if (cfg->type != PHY_TYPE_DP) {
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ if (cfg->type == PHY_TYPE_UFS) {
++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++ mask = PCS_READY;
++ ready = PCS_READY;
++ } else {
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++ }
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
++ }
++ }
++ return 0;
++
++err_disable_pipe_clk:
++ clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ clk_disable_unprepare(qphy->pipe_clk);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ /* Assert DP PHY power down */
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++ } else {
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ qcom_qmp_phy_com_exit(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_init(phy);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_power_on(phy);
++ if (ret)
++ qcom_qmp_phy_exit(phy);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_power_off(phy);
++ if (ret)
++ return ret;
++ return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++ enum phy_mode mode, int submode)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++ qphy->mode = mode;
++
++ return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ u32 intr_mask;
++
++ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++ qphy->mode == PHY_MODE_USB_DEVICE_SS)
++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++ else
++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++ /* Clear any pending interrupts status */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++ /* Enable required PHY autonomous mode interrupts */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++ /* Enable i/o clamp_n for autonomous mode */
++ if (pcs_misc)
++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++
++ /* Disable i/o clamp_n on resume for normal mode */
++ if (pcs_misc)
++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++ clk_disable_unprepare(qphy->pipe_clk);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret = 0;
++
++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++ return ret;
++ }
++
++ qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_vregs;
++ int i;
++
++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++ if (!qmp->vregs)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->vregs[i].supply = cfg->vreg_list[i];
++
++ return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int i;
++
++ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++ sizeof(*qmp->resets), GFP_KERNEL);
++ if (!qmp->resets)
++ return -ENOMEM;
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ struct reset_control *rst;
++ const char *name = cfg->reset_list[i];
++
++ rst = devm_reset_control_get_exclusive(dev, name);
++ if (IS_ERR(rst)) {
++ dev_err(dev, "failed to get %s reset\n", name);
++ return PTR_ERR(rst);
++ }
++ qmp->resets[i] = rst;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_clks;
++ int i;
++
++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++ if (!qmp->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->clks[i].id = cfg->clk_list[i];
++
++ return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++ of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ * +---------------+
++ * | PHY block |<<---------------------------------------+
++ * | | |
++ * | +-------+ | +-----+ |
++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ * clk | +-------+ | +-----+
++ * +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++ struct clk_fixed_rate *fixed;
++ struct clk_init_data init = { };
++ int ret;
++
++ ret = of_property_read_string(np, "clock-output-names", &init.name);
++ if (ret) {
++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++ return ret;
++ }
++
++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++ if (!fixed)
++ return -ENOMEM;
++
++ init.ops = &clk_fixed_rate_ops;
++
++ /* controllers using QMP phys use 125MHz pipe clock interface */
++ fixed->fixed_rate = 125000000;
++ fixed->hw.init = &init;
++
++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ * +------------------------------+
++ * | DP_VCO_CLK |
++ * | |
++ * | +-------------------+ |
++ * | | (DP PLL/VCO) | |
++ * | +---------+---------+ |
++ * | v |
++ * | +----------+-----------+ |
++ * | | hsclk_divsel_clk_src | |
++ * | +----------+-----------+ |
++ * +------------------------------+
++ * |
++ * +---------<---------v------------>----------+
++ * | |
++ * +--------v----------------+ |
++ * | dp_phy_pll_link_clk | |
++ * | link_clk | |
++ * +--------+----------------+ |
++ * | |
++ * | |
++ * v v
++ * Input to DISPCC block |
++ * for link clk, crypto clk |
++ * and interface clock |
++ * |
++ * |
++ * +--------<------------+-----------------+---<---+
++ * | | |
++ * +----v---------+ +--------v-----+ +--------v------+
++ * | vco_divided | | vco_divided | | vco_divided |
++ * | _clk_src | | _clk_src | | _clk_src |
++ * | | | | | |
++ * |divsel_six | | divsel_two | | divsel_four |
++ * +-------+------+ +-----+--------+ +--------+------+
++ * | | |
++ * v---->----------v-------------<------v
++ * |
++ * +----------+-----------------+
++ * | dp_phy_pll_vco_div_clk |
++ * +---------+------------------+
++ * |
++ * v
++ * Input to DISPCC block
++ * for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 1620000000UL / 2:
++ case 2700000000UL / 2:
++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ return 1620000000UL / 2;
++ case 2700:
++ return 2700000000UL / 2;
++ case 5400:
++ return 5400000000UL / 4;
++ case 8100:
++ return 8100000000UL / 6;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 162000000:
++ case 270000000:
++ case 540000000:
++ case 810000000:
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ return dp_opts->link_rate * 100000;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct qmp_phy_dp_clks *dp_clks = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx >= 2) {
++ pr_err("%s: invalid index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (idx == 0)
++ return &dp_clks->dp_link_hw;
++
++ return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++ struct device_node *np)
++{
++ struct clk_init_data init = { };
++ struct qmp_phy_dp_clks *dp_clks;
++ char name[64];
++ int ret;
++
++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++ if (!dp_clks)
++ return -ENOMEM;
++
++ dp_clks->qphy = qphy;
++ qphy->dp_clks = dp_clks;
++
++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_link_clk_ops;
++ init.name = name;
++ dp_clks->dp_link_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++ if (ret)
++ return ret;
++
++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_pixel_clk_ops;
++ init.name = name;
++ dp_clks->dp_pixel_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++ .init = qcom_qmp_phy_enable,
++ .exit = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++ .init = qcom_qmp_phy_init,
++ .configure = qcom_qmp_dp_phy_configure,
++ .power_on = qcom_qmp_phy_power_on,
++ .calibrate = qcom_qmp_dp_phy_calibrate,
++ .power_off = qcom_qmp_phy_power_off,
++ .exit = qcom_qmp_phy_exit,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++ .power_on = qcom_qmp_phy_enable,
++ .power_off = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++ reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct phy *generic_phy;
++ struct qmp_phy *qphy;
++ const struct phy_ops *ops;
++ char prop_name[MAX_PROP_NAME];
++ int ret;
++
++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++ if (!qphy)
++ return -ENOMEM;
++
++ qphy->cfg = cfg;
++ qphy->serdes = serdes;
++ /*
++ * Get memory resources for each phy lane:
++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++ * For single lane PHYs: pcs_misc (optional) -> 3.
++ */
++ qphy->tx = of_iomap(np, 0);
++ if (!qphy->tx)
++ return -ENOMEM;
++
++ qphy->rx = of_iomap(np, 1);
++ if (!qphy->rx)
++ return -ENOMEM;
++
++ qphy->pcs = of_iomap(np, 2);
++ if (!qphy->pcs)
++ return -ENOMEM;
++
++ /*
++ * If this is a dual-lane PHY, then there should be registers for the
++ * second lane. Some old device trees did not specify this, so fall
++ * back to old legacy behavior of assuming they can be reached at an
++ * offset from the first lane.
++ */
++ if (cfg->is_dual_lane_phy) {
++ qphy->tx2 = of_iomap(np, 3);
++ qphy->rx2 = of_iomap(np, 4);
++ if (!qphy->tx2 || !qphy->rx2) {
++ dev_warn(dev,
++ "Underspecified device tree, falling back to legacy register regions\n");
++
++ /* In the old version, pcs_misc is at index 3. */
++ qphy->pcs_misc = qphy->tx2;
++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 5);
++ }
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 3);
++ }
++
++ if (!qphy->pcs_misc)
++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++ /*
++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++ * based phys, so they essentially have pipe clock. So,
++ * we return error in case phy is USB3 or PIPE type.
++ * Otherwise, we initialize pipe clock to NULL for
++ * all phys that don't need this.
++ */
++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ if (IS_ERR(qphy->pipe_clk)) {
++ if (cfg->type == PHY_TYPE_PCIE ||
++ cfg->type == PHY_TYPE_USB3) {
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
++ }
++ qphy->pipe_clk = NULL;
++ }
++
++ /* Get lane reset, if any */
++ if (cfg->has_lane_rst) {
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
++ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
++ }
++
++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++ ops = &qcom_qmp_pcie_ufs_ops;
++ else if (cfg->type == PHY_TYPE_DP)
++ ops = &qcom_qmp_phy_dp_ops;
++ else
++ ops = &qcom_qmp_phy_gen_ops;
++
++ generic_phy = devm_phy_create(dev, np, ops);
++ if (IS_ERR(generic_phy)) {
++ ret = PTR_ERR(generic_phy);
++ dev_err(dev, "failed to create qphy %d\n", ret);
++ return ret;
++ }
++
++ qphy->phy = generic_phy;
++ qphy->index = id;
++ qphy->qmp = qmp;
++ qmp->phys[id] = qphy;
++ phy_set_drvdata(generic_phy, qphy);
++
++ return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,ipq8074-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-pcie-phy",
++ .data = &msm8996_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-ufs-phy",
++ .data = &msm8996_ufs_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-usb3-phy",
++ .data = &msm8996_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-pcie-phy",
++ .data = &msm8998_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,ipq8074-qmp-pcie-phy",
++ .data = &ipq8074_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-pcie-phy",
++ .data = &ipq6018_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-phy",
++ .data = &sc7180_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sc8180x-qmp-pcie-phy",
++ .data = &sc8180x_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sdm845-qhp-pcie-phy",
++ .data = &sdm845_qhp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-pcie-phy",
++ .data = &sdm845_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-phy",
++ .data = &qmp_v3_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++ .data = &qmp_v3_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-usb3-phy",
++ .data = &msm8998_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm6115-qmp-ufs-phy",
++ .data = &sm6115_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm6350-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++ .data = &sm8150_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-phy",
++ .data = &sm8250_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++ .data = &sm8250_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-pcie-phy",
++ .data = &sdx55_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++ .data = &sdx55_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++ .data = &sdx65_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++ .data = &sm8350_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-ufs-phy",
++ .data = &sm8450_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,qcm2290-qmp-usb3-phy",
++ .data = &qcm2290_usb3phy_cfg,
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ .data = &sc7180_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ .data = &sm8250_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ .data = &sc8180x_usb3dpphy_cfg,
++ },
++ { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++ qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++ struct qcom_qmp *qmp;
++ struct device *dev = &pdev->dev;
++ struct device_node *child;
++ struct phy_provider *phy_provider;
++ void __iomem *serdes;
++ void __iomem *usb_serdes;
++ void __iomem *dp_serdes = NULL;
++ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++ const struct qmp_phy_cfg *cfg = NULL;
++ const struct qmp_phy_cfg *usb_cfg = NULL;
++ const struct qmp_phy_cfg *dp_cfg = NULL;
++ int num, id, expected_phys;
++ int ret;
++
++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++ if (!qmp)
++ return -ENOMEM;
++
++ qmp->dev = dev;
++ dev_set_drvdata(dev, qmp);
++
++ /* Get the specific init parameters of QMP phy */
++ cfg = of_device_get_match_data(dev);
++ if (!cfg) {
++ const struct of_device_id *match;
++
++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++ if (!match)
++ return -EINVAL;
++
++ combo_cfg = match->data;
++ if (!combo_cfg)
++ return -EINVAL;
++
++ usb_cfg = combo_cfg->usb_cfg;
++ cfg = usb_cfg; /* Setup clks and regulators */
++ }
++
++ /* per PHY serdes; usually located at base address */
++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(serdes))
++ return PTR_ERR(serdes);
++
++ /* per PHY dp_com; if PHY has dp_com control block */
++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(qmp->dp_com))
++ return PTR_ERR(qmp->dp_com);
++ }
++
++ if (combo_cfg) {
++ /* Only two serdes for combo PHY */
++ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++ if (IS_ERR(dp_serdes))
++ return PTR_ERR(dp_serdes);
++
++ dp_cfg = combo_cfg->dp_cfg;
++ expected_phys = 2;
++ } else {
++ expected_phys = cfg->nlanes;
++ }
++
++ mutex_init(&qmp->phy_mutex);
++
++ ret = qcom_qmp_phy_clk_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_reset_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ if (ret) {
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "failed to get regulator supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ num = of_get_available_child_count(dev->of_node);
++ /* do we have a rogue child node ? */
++ if (num > expected_phys)
++ return -EINVAL;
++
++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++ if (!qmp->phys)
++ return -ENOMEM;
++
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ /*
++ * Prevent runtime pm from being ON by default. Users can enable
++ * it using power/control in sysfs.
++ */
++ pm_runtime_forbid(dev);
++
++ id = 0;
++ for_each_available_child_of_node(dev->of_node, child) {
++ if (of_node_name_eq(child, "dp-phy")) {
++ cfg = dp_cfg;
++ serdes = dp_serdes;
++ } else if (of_node_name_eq(child, "usb3-phy")) {
++ cfg = usb_cfg;
++ serdes = usb_serdes;
++ }
++
++ /* Create per-lane phy */
++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ if (ret) {
++ dev_err(dev, "failed to create lane%d phy, %d\n",
++ id, ret);
++ goto err_node_put;
++ }
++
++ /*
++ * Register the pipe clock provided by phy.
++ * See function description to see details of this pipe clock.
++ */
++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
++ }
++ } else if (cfg->type == PHY_TYPE_DP) {
++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register DP clock source\n");
++ goto err_node_put;
++ }
++ }
++ id++;
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ if (!IS_ERR(phy_provider))
++ dev_info(dev, "Registered Qcom-QMP phy\n");
++ else
++ pm_runtime_disable(dev);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++ pm_runtime_disable(dev);
++ of_node_put(child);
++ return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++ .probe = qcom_qmp_phy_probe,
++ .driver = {
++ .name = "qcom-qmp-phy",
++ .pm = &qcom_qmp_phy_pm_ops,
++ .of_match_table = qcom_qmp_phy_of_match_table,
++ },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+new file mode 100644
+index 000000000000..c7309e981bfb
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN BIT(0)
++#define REFCLK_DRV_DSBL BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START BIT(0)
++#define PCS_START BIT(1)
++#define PLL_READY_GATE_EN BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS BIT(6)
++#define PHYSTATUS_4_20 BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE BIT(0) /* enables USB3 mode */
++#define DP_MODE BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN BIT(0)
++#define ALFPS_DTCT_EN BIT(1)
++#define ARCVR_DTCT_EVENT_SEL BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT 10000
++#define POWER_DOWN_DELAY_US_MIN 10
++#define POWER_DOWN_DELAY_US_MAX 11
++
++#define MAX_PROP_NAME 32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
++
++struct qmp_phy_init_tbl {
++ unsigned int offset;
++ unsigned int val;
++ /*
++ * register part of layout ?
++ * if yes, then offset gives index in the reg-layout
++ */
++ bool in_layout;
++ /*
++ * mask of lanes for which this register is written
++ * for cases when second lane needs different values
++ */
++ u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_L(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .in_layout = true, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = l, \
++ }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++ /* Common block control registers */
++ QPHY_COM_SW_RESET,
++ QPHY_COM_POWER_DOWN_CONTROL,
++ QPHY_COM_START_CONTROL,
++ QPHY_COM_PCS_READY_STATUS,
++ /* PCS registers */
++ QPHY_PLL_LOCK_CHK_DLY_TIME,
++ QPHY_FLL_CNTRL1,
++ QPHY_FLL_CNTRL2,
++ QPHY_FLL_CNT_VAL_L,
++ QPHY_FLL_CNT_VAL_H_TOL,
++ QPHY_FLL_MAN_CODE,
++ QPHY_SW_RESET,
++ QPHY_START_CTRL,
++ QPHY_PCS_READY_STATUS,
++ QPHY_PCS_STATUS,
++ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++ QPHY_PCS_POWER_DOWN_CONTROL,
++ /* PCS_MISC registers */
++ QPHY_PCS_MISC_TYPEC_CTRL,
++ /* Keep last to ensure regs_layout arrays are properly initialized */
++ QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_COM_SW_RESET] = 0x400,
++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
++ [QPHY_COM_START_CONTROL] = 0x408,
++ [QPHY_COM_PCS_READY_STATUS] = 0x448,
++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
++ [QPHY_FLL_CNTRL1] = 0xc4,
++ [QPHY_FLL_CNTRL2] = 0xc8,
++ [QPHY_FLL_CNT_VAL_L] = 0xcc,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
++ [QPHY_FLL_MAN_CODE] = 0xd4,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_FLL_CNTRL1] = 0xc0,
++ [QPHY_FLL_CNTRL2] = 0xc4,
++ [QPHY_FLL_CNT_VAL_L] = 0xc8,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
++ [QPHY_FLL_MAN_CODE] = 0xd0,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x17c,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
++
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
++
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
++
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
++
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
++
++ /* array of registers with different offsets */
++ const unsigned int *regs;
++
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
++
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
++
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
++
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
++
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
++
++ struct qmp_phy **phys;
++
++ struct mutex phy_mutex;
++ int init_count;
++
++ struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++ "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++ "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++ "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++ "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++ "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++ "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++ "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++ "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++ "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++ "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++ "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
++
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_ufs_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++ .tx_tbl = msm8996_ufs_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++ .rx_tbl = msm8996_ufs_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++ .clk_list = msm8996_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++
++ .regs = msm8996_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = msm8996_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++ .pcs_tbl = msm8996_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++ "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++ "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++ .tx_tbl = ipq8074_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++ .rx_tbl = ipq8074_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++ .pcs_tbl = ipq8074_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq6018_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++ .tx_tbl = ipq6018_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++ .rx_tbl = ipq6018_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++ .pcs_tbl = ipq6018_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = ipq_pciephy_gen3_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qmp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qhp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++ .tx_tbl = qmp_v3_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++ .usb_cfg = &sc7180_usb3phy_cfg,
++ .dp_cfg = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++ .tx_tbl = sdm845_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++ .rx_tbl = sdm845_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++ .tx_tbl = sm6115_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++ .rx_tbl = sm6115_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm6115_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++
++ .is_dual_lane_phy = false,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++ .tx_tbl = msm8998_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++ .rx_tbl = msm8998_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++ .pcs_tbl = msm8998_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++ .tx_tbl = msm8998_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++ .rx_tbl = msm8998_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++ .pcs_tbl = msm8998_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++ .tx_tbl = sm8150_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++ .rx_tbl = sm8150_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8150_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++ .rx_tbl = sm8150_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++ .pcs_tbl = sm8150_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++ .usb_cfg = &sm8150_usb3phy_cfg,
++ .dp_cfg = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8250_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++ .rx_tbl = sm8250_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++ .pcs_tbl = sm8250_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++ .usb_cfg = &sm8250_usb3phy_cfg,
++ .dp_cfg = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8350_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++ .rx_tbl = sm8350_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++ .pcs_tbl = sm8350_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sm8450_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qcm2290_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++ .tx_tbl = qcm2290_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++ .rx_tbl = qcm2290_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++ .pcs_tbl = qcm2290_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++ .clk_list = qcm2290_usb3phy_clk_l,
++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++ .reset_list = qcm2290_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qcm2290_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num,
++ u8 lane_mask)
++{
++ int i;
++ const struct qmp_phy_init_tbl *t = tbl;
++
++ if (!t)
++ return;
++
++ for (i = 0; i < num; i++, t++) {
++ if (!(t->lane_mask & lane_mask))
++ continue;
++
++ if (t->in_layout)
++ writel(t->val, base + regs[t->offset]);
++ else
++ writel(t->val, base + t->offset);
++ }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num)
++{
++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++ int serdes_tbl_num = cfg->serdes_tbl_num;
++ int ret;
++
++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ if (cfg->serdes_tbl_sec)
++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ cfg->serdes_tbl_num_sec);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ switch (dp_opts->link_rate) {
++ case 1620:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_rbr,
++ cfg->serdes_tbl_rbr_num);
++ break;
++ case 2700:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr,
++ cfg->serdes_tbl_hbr_num);
++ break;
++ case 5400:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr2,
++ cfg->serdes_tbl_hbr2_num);
++ break;
++ case 8100:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr3,
++ cfg->serdes_tbl_hbr3_num);
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ }
++
++
++ if (cfg->has_phy_com_ctrl) {
++ void __iomem *status;
++ unsigned int mask, val;
++
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
++
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++ DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(QSERDES_V3_COM_BIAS_EN |
++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++ { 0x00, 0x0c, 0x15, 0x1a },
++ { 0x02, 0x0e, 0x16, 0xff },
++ { 0x02, 0x11, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++ { 0x02, 0x12, 0x16, 0x1a },
++ { 0x09, 0x19, 0x1f, 0xff },
++ { 0x10, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++ { 0x00, 0x0c, 0x14, 0x19 },
++ { 0x00, 0x0b, 0x12, 0xff },
++ { 0x00, 0x0b, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++ { 0x08, 0x0f, 0x16, 0x1f },
++ { 0x11, 0x1e, 0x1f, 0xff },
++ { 0x19, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ unsigned int v_level = 0, p_level = 0;
++ u8 voltage_swing_cfg, pre_emphasis_cfg;
++ int i;
++
++ for (i = 0; i < dp_opts->lanes; i++) {
++ v_level = max(v_level, dp_opts->voltage[i]);
++ p_level = max(p_level, dp_opts->pre[i]);
++ }
++
++ if (dp_opts->link_rate <= 2700) {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++ } else {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++ }
++
++ /* TODO: Move check to config check */
++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++ return -EINVAL;
++
++ /* Enable MUX to use Cursor values from these registers */
++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 bias_en, drvr_en;
++
++ if (qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V3_TX_TX_DRV_LVL,
++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++ return;
++
++ if (dp_opts->lanes == 1) {
++ bias_en = 0x3e;
++ drvr_en = 0x13;
++ } else {
++ bias_en = 0x3f;
++ drvr_en = 0x10;
++ }
++
++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++ u32 val;
++ bool reverse = false;
++
++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++ /*
++ * TODO: Assume orientation is CC1 for now and two lanes, need to
++ * use type-c connector to understand orientation and lanes.
++ *
++ * Otherwise val changes to be like below if this code understood
++ * the orientation of the type-c cable.
++ *
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ * if (orientation == ORIENTATION_CC2)
++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++ */
++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++ return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++
++ qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ /* Program default values before writing proper values */
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V4_TX_TX_DRV_LVL,
++ QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++ bool reverse;
++
++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ /*
++ * At least for 7nm DP PHY this has to be done after enabling link
++ * clock.
++ */
++
++ if (dp_opts->lanes == 1) {
++ bias0_en = reverse ? 0x3e : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3e;
++ drvr0_en = reverse ? 0x13 : 0x10;
++ drvr1_en = reverse ? 0x10 : 0x13;
++ } else if (dp_opts->lanes == 2) {
++ bias0_en = reverse ? 0x3f : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ } else {
++ bias0_en = 0x3f;
++ bias1_en = 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ }
++
++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++ if (qphy->dp_opts.set_voltages) {
++ cfg->configure_dp_tx(qphy);
++ qphy->dp_opts.set_voltages = 0;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->calibrate_dp_phy)
++ return cfg->calibrate_dp_phy(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *dp_com = qmp->dp_com;
++ int ret, i;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (qmp->init_count++) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ /* turn on regulator supplies */
++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++ if (ret) {
++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++ goto err_unlock;
++ }
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ ret = reset_control_assert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset assert failed\n",
++ cfg->reset_list[i]);
++ goto err_disable_regulators;
++ }
++ }
++
++ for (i = cfg->num_resets - 1; i >= 0; i--) {
++ ret = reset_control_deassert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset deassert failed\n",
++ qphy->cfg->reset_list[i]);
++ goto err_assert_reset;
++ }
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ goto err_assert_reset;
++
++ if (cfg->has_phy_dp_com_ctrl) {
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++ SW_PWRDN);
++ /* override hardware control for reset of qmp phy */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ /* Default type-c orientation, i.e CC1 */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++ USB3_MODE | DP_MODE);
++
++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++ }
++
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ } else {
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++
++err_assert_reset:
++ while (++i < cfg->num_resets)
++ reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++ mutex_unlock(&qmp->phy_mutex);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ int i = cfg->num_resets;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (--qmp->init_count) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ reset_control_assert(qmp->ufs_reset);
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ }
++
++ while (--i >= 0)
++ reset_control_assert(qmp->resets[i]);
++
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret;
++ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++ if (cfg->no_pcs_sw_reset) {
++ /*
++ * Get UFS reset, which is delayed until now to avoid a
++ * circular dependency where UFS needs its PHY, but the PHY
++ * needs this UFS reset.
++ */
++ if (!qmp->ufs_reset) {
++ qmp->ufs_reset =
++ devm_reset_control_get_exclusive(qmp->dev,
++ "ufsphy");
++
++ if (IS_ERR(qmp->ufs_reset)) {
++ ret = PTR_ERR(qmp->ufs_reset);
++ dev_err(qmp->dev,
++ "failed to get UFS reset: %d\n",
++ ret);
++
++ qmp->ufs_reset = NULL;
++ return ret;
++ }
++ }
++
++ ret = reset_control_assert(qmp->ufs_reset);
++ if (ret)
++ return ret;
++ }
++
++ ret = qcom_qmp_phy_com_init(qphy);
++ if (ret)
++ return ret;
++
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->dp_aux_init(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *tx = qphy->tx;
++ void __iomem *rx = qphy->rx;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ void __iomem *status;
++ unsigned int mask, val, ready;
++ int ret;
++
++ qcom_qmp_phy_serdes_init(qphy);
++
++ if (cfg->has_lane_rst) {
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
++ }
++ }
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++ goto err_reset_lane;
++ }
++
++ /* Tx, Rx, and PCS configurations */
++ qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 1);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 1);
++
++ /* Configuration for other LANE for USB-DP combo PHY */
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 2);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 2);
++ }
++
++ /* Configure special DP tx tunings */
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->configure_dp_tx(qphy);
++
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 1);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 2);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl_sec,
++ cfg->rx_tbl_num_sec, 2);
++ }
++
++ /* Configure link rate, swing, etc. */
++ if (cfg->type == PHY_TYPE_DP) {
++ cfg->configure_dp_phy(qphy);
++ } else {
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
++ }
++
++ ret = reset_control_deassert(qmp->ufs_reset);
++ if (ret)
++ goto err_disable_pipe_clk;
++
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ cfg->pcs_misc_tbl_num);
++ if (cfg->pcs_misc_tbl_sec)
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ cfg->pcs_misc_tbl_num_sec);
++
++ /*
++ * Pull out PHY from POWER DOWN state.
++ * This is active low enable signal to power-down PHY.
++ */
++ if(cfg->type == PHY_TYPE_PCIE)
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++ if (cfg->has_pwrdn_delay)
++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++ if (cfg->type != PHY_TYPE_DP) {
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ if (cfg->type == PHY_TYPE_UFS) {
++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++ mask = PCS_READY;
++ ready = PCS_READY;
++ } else {
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++ }
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
++ }
++ }
++ return 0;
++
++err_disable_pipe_clk:
++ clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ clk_disable_unprepare(qphy->pipe_clk);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ /* Assert DP PHY power down */
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++ } else {
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ qcom_qmp_phy_com_exit(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_init(phy);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_power_on(phy);
++ if (ret)
++ qcom_qmp_phy_exit(phy);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_power_off(phy);
++ if (ret)
++ return ret;
++ return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++ enum phy_mode mode, int submode)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++ qphy->mode = mode;
++
++ return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ u32 intr_mask;
++
++ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++ qphy->mode == PHY_MODE_USB_DEVICE_SS)
++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++ else
++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++ /* Clear any pending interrupts status */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++ /* Enable required PHY autonomous mode interrupts */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++ /* Enable i/o clamp_n for autonomous mode */
++ if (pcs_misc)
++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++
++ /* Disable i/o clamp_n on resume for normal mode */
++ if (pcs_misc)
++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++ clk_disable_unprepare(qphy->pipe_clk);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret = 0;
++
++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++ return ret;
++ }
++
++ qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_vregs;
++ int i;
++
++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++ if (!qmp->vregs)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->vregs[i].supply = cfg->vreg_list[i];
++
++ return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int i;
++
++ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++ sizeof(*qmp->resets), GFP_KERNEL);
++ if (!qmp->resets)
++ return -ENOMEM;
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ struct reset_control *rst;
++ const char *name = cfg->reset_list[i];
++
++ rst = devm_reset_control_get_exclusive(dev, name);
++ if (IS_ERR(rst)) {
++ dev_err(dev, "failed to get %s reset\n", name);
++ return PTR_ERR(rst);
++ }
++ qmp->resets[i] = rst;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_clks;
++ int i;
++
++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++ if (!qmp->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->clks[i].id = cfg->clk_list[i];
++
++ return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++ of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ * +---------------+
++ * | PHY block |<<---------------------------------------+
++ * | | |
++ * | +-------+ | +-----+ |
++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ * clk | +-------+ | +-----+
++ * +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++ struct clk_fixed_rate *fixed;
++ struct clk_init_data init = { };
++ int ret;
++
++ ret = of_property_read_string(np, "clock-output-names", &init.name);
++ if (ret) {
++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++ return ret;
++ }
++
++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++ if (!fixed)
++ return -ENOMEM;
++
++ init.ops = &clk_fixed_rate_ops;
++
++ /* controllers using QMP phys use 125MHz pipe clock interface */
++ fixed->fixed_rate = 125000000;
++ fixed->hw.init = &init;
++
++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ * +------------------------------+
++ * | DP_VCO_CLK |
++ * | |
++ * | +-------------------+ |
++ * | | (DP PLL/VCO) | |
++ * | +---------+---------+ |
++ * | v |
++ * | +----------+-----------+ |
++ * | | hsclk_divsel_clk_src | |
++ * | +----------+-----------+ |
++ * +------------------------------+
++ * |
++ * +---------<---------v------------>----------+
++ * | |
++ * +--------v----------------+ |
++ * | dp_phy_pll_link_clk | |
++ * | link_clk | |
++ * +--------+----------------+ |
++ * | |
++ * | |
++ * v v
++ * Input to DISPCC block |
++ * for link clk, crypto clk |
++ * and interface clock |
++ * |
++ * |
++ * +--------<------------+-----------------+---<---+
++ * | | |
++ * +----v---------+ +--------v-----+ +--------v------+
++ * | vco_divided | | vco_divided | | vco_divided |
++ * | _clk_src | | _clk_src | | _clk_src |
++ * | | | | | |
++ * |divsel_six | | divsel_two | | divsel_four |
++ * +-------+------+ +-----+--------+ +--------+------+
++ * | | |
++ * v---->----------v-------------<------v
++ * |
++ * +----------+-----------------+
++ * | dp_phy_pll_vco_div_clk |
++ * +---------+------------------+
++ * |
++ * v
++ * Input to DISPCC block
++ * for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 1620000000UL / 2:
++ case 2700000000UL / 2:
++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ return 1620000000UL / 2;
++ case 2700:
++ return 2700000000UL / 2;
++ case 5400:
++ return 5400000000UL / 4;
++ case 8100:
++ return 8100000000UL / 6;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 162000000:
++ case 270000000:
++ case 540000000:
++ case 810000000:
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ return dp_opts->link_rate * 100000;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct qmp_phy_dp_clks *dp_clks = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx >= 2) {
++ pr_err("%s: invalid index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (idx == 0)
++ return &dp_clks->dp_link_hw;
++
++ return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++ struct device_node *np)
++{
++ struct clk_init_data init = { };
++ struct qmp_phy_dp_clks *dp_clks;
++ char name[64];
++ int ret;
++
++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++ if (!dp_clks)
++ return -ENOMEM;
++
++ dp_clks->qphy = qphy;
++ qphy->dp_clks = dp_clks;
++
++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_link_clk_ops;
++ init.name = name;
++ dp_clks->dp_link_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++ if (ret)
++ return ret;
++
++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_pixel_clk_ops;
++ init.name = name;
++ dp_clks->dp_pixel_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++ .init = qcom_qmp_phy_enable,
++ .exit = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++ .init = qcom_qmp_phy_init,
++ .configure = qcom_qmp_dp_phy_configure,
++ .power_on = qcom_qmp_phy_power_on,
++ .calibrate = qcom_qmp_dp_phy_calibrate,
++ .power_off = qcom_qmp_phy_power_off,
++ .exit = qcom_qmp_phy_exit,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++ .power_on = qcom_qmp_phy_enable,
++ .power_off = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++ reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct phy *generic_phy;
++ struct qmp_phy *qphy;
++ const struct phy_ops *ops;
++ char prop_name[MAX_PROP_NAME];
++ int ret;
++
++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++ if (!qphy)
++ return -ENOMEM;
++
++ qphy->cfg = cfg;
++ qphy->serdes = serdes;
++ /*
++ * Get memory resources for each phy lane:
++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++ * For single lane PHYs: pcs_misc (optional) -> 3.
++ */
++ qphy->tx = of_iomap(np, 0);
++ if (!qphy->tx)
++ return -ENOMEM;
++
++ qphy->rx = of_iomap(np, 1);
++ if (!qphy->rx)
++ return -ENOMEM;
++
++ qphy->pcs = of_iomap(np, 2);
++ if (!qphy->pcs)
++ return -ENOMEM;
++
++ /*
++ * If this is a dual-lane PHY, then there should be registers for the
++ * second lane. Some old device trees did not specify this, so fall
++ * back to old legacy behavior of assuming they can be reached at an
++ * offset from the first lane.
++ */
++ if (cfg->is_dual_lane_phy) {
++ qphy->tx2 = of_iomap(np, 3);
++ qphy->rx2 = of_iomap(np, 4);
++ if (!qphy->tx2 || !qphy->rx2) {
++ dev_warn(dev,
++ "Underspecified device tree, falling back to legacy register regions\n");
++
++ /* In the old version, pcs_misc is at index 3. */
++ qphy->pcs_misc = qphy->tx2;
++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 5);
++ }
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 3);
++ }
++
++ if (!qphy->pcs_misc)
++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++ /*
++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++ * based phys, so they essentially have pipe clock. So,
++ * we return error in case phy is USB3 or PIPE type.
++ * Otherwise, we initialize pipe clock to NULL for
++ * all phys that don't need this.
++ */
++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ if (IS_ERR(qphy->pipe_clk)) {
++ if (cfg->type == PHY_TYPE_PCIE ||
++ cfg->type == PHY_TYPE_USB3) {
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
++ }
++ qphy->pipe_clk = NULL;
++ }
++
++ /* Get lane reset, if any */
++ if (cfg->has_lane_rst) {
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
++ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
++ }
++
++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++ ops = &qcom_qmp_pcie_ufs_ops;
++ else if (cfg->type == PHY_TYPE_DP)
++ ops = &qcom_qmp_phy_dp_ops;
++ else
++ ops = &qcom_qmp_phy_gen_ops;
++
++ generic_phy = devm_phy_create(dev, np, ops);
++ if (IS_ERR(generic_phy)) {
++ ret = PTR_ERR(generic_phy);
++ dev_err(dev, "failed to create qphy %d\n", ret);
++ return ret;
++ }
++
++ qphy->phy = generic_phy;
++ qphy->index = id;
++ qphy->qmp = qmp;
++ qmp->phys[id] = qphy;
++ phy_set_drvdata(generic_phy, qphy);
++
++ return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,ipq8074-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-pcie-phy",
++ .data = &msm8996_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-ufs-phy",
++ .data = &msm8996_ufs_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-usb3-phy",
++ .data = &msm8996_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-pcie-phy",
++ .data = &msm8998_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,ipq8074-qmp-pcie-phy",
++ .data = &ipq8074_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-pcie-phy",
++ .data = &ipq6018_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-phy",
++ .data = &sc7180_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sc8180x-qmp-pcie-phy",
++ .data = &sc8180x_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sdm845-qhp-pcie-phy",
++ .data = &sdm845_qhp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-pcie-phy",
++ .data = &sdm845_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-phy",
++ .data = &qmp_v3_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++ .data = &qmp_v3_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-usb3-phy",
++ .data = &msm8998_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm6115-qmp-ufs-phy",
++ .data = &sm6115_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm6350-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++ .data = &sm8150_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-phy",
++ .data = &sm8250_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++ .data = &sm8250_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-pcie-phy",
++ .data = &sdx55_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++ .data = &sdx55_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++ .data = &sdx65_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++ .data = &sm8350_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-ufs-phy",
++ .data = &sm8450_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,qcm2290-qmp-usb3-phy",
++ .data = &qcm2290_usb3phy_cfg,
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ .data = &sc7180_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ .data = &sm8250_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ .data = &sc8180x_usb3dpphy_cfg,
++ },
++ { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++ qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++ struct qcom_qmp *qmp;
++ struct device *dev = &pdev->dev;
++ struct device_node *child;
++ struct phy_provider *phy_provider;
++ void __iomem *serdes;
++ void __iomem *usb_serdes;
++ void __iomem *dp_serdes = NULL;
++ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++ const struct qmp_phy_cfg *cfg = NULL;
++ const struct qmp_phy_cfg *usb_cfg = NULL;
++ const struct qmp_phy_cfg *dp_cfg = NULL;
++ int num, id, expected_phys;
++ int ret;
++
++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++ if (!qmp)
++ return -ENOMEM;
++
++ qmp->dev = dev;
++ dev_set_drvdata(dev, qmp);
++
++ /* Get the specific init parameters of QMP phy */
++ cfg = of_device_get_match_data(dev);
++ if (!cfg) {
++ const struct of_device_id *match;
++
++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++ if (!match)
++ return -EINVAL;
++
++ combo_cfg = match->data;
++ if (!combo_cfg)
++ return -EINVAL;
++
++ usb_cfg = combo_cfg->usb_cfg;
++ cfg = usb_cfg; /* Setup clks and regulators */
++ }
++
++ /* per PHY serdes; usually located at base address */
++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(serdes))
++ return PTR_ERR(serdes);
++
++ /* per PHY dp_com; if PHY has dp_com control block */
++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(qmp->dp_com))
++ return PTR_ERR(qmp->dp_com);
++ }
++
++ if (combo_cfg) {
++ /* Only two serdes for combo PHY */
++ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++ if (IS_ERR(dp_serdes))
++ return PTR_ERR(dp_serdes);
++
++ dp_cfg = combo_cfg->dp_cfg;
++ expected_phys = 2;
++ } else {
++ expected_phys = cfg->nlanes;
++ }
++
++ mutex_init(&qmp->phy_mutex);
++
++ ret = qcom_qmp_phy_clk_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_reset_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ if (ret) {
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "failed to get regulator supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ num = of_get_available_child_count(dev->of_node);
++ /* do we have a rogue child node ? */
++ if (num > expected_phys)
++ return -EINVAL;
++
++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++ if (!qmp->phys)
++ return -ENOMEM;
++
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ /*
++ * Prevent runtime pm from being ON by default. Users can enable
++ * it using power/control in sysfs.
++ */
++ pm_runtime_forbid(dev);
++
++ id = 0;
++ for_each_available_child_of_node(dev->of_node, child) {
++ if (of_node_name_eq(child, "dp-phy")) {
++ cfg = dp_cfg;
++ serdes = dp_serdes;
++ } else if (of_node_name_eq(child, "usb3-phy")) {
++ cfg = usb_cfg;
++ serdes = usb_serdes;
++ }
++
++ /* Create per-lane phy */
++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ if (ret) {
++ dev_err(dev, "failed to create lane%d phy, %d\n",
++ id, ret);
++ goto err_node_put;
++ }
++
++ /*
++ * Register the pipe clock provided by phy.
++ * See function description to see details of this pipe clock.
++ */
++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
++ }
++ } else if (cfg->type == PHY_TYPE_DP) {
++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register DP clock source\n");
++ goto err_node_put;
++ }
++ }
++ id++;
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ if (!IS_ERR(phy_provider))
++ dev_info(dev, "Registered Qcom-QMP phy\n");
++ else
++ pm_runtime_disable(dev);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++ pm_runtime_disable(dev);
++ of_node_put(child);
++ return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++ .probe = qcom_qmp_phy_probe,
++ .driver = {
++ .name = "qcom-qmp-phy",
++ .pm = &qcom_qmp_phy_pm_ops,
++ .of_match_table = qcom_qmp_phy_of_match_table,
++ },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+new file mode 100644
+index 000000000000..c7309e981bfb
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN BIT(0)
++#define REFCLK_DRV_DSBL BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START BIT(0)
++#define PCS_START BIT(1)
++#define PLL_READY_GATE_EN BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS BIT(6)
++#define PHYSTATUS_4_20 BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE BIT(0) /* enables USB3 mode */
++#define DP_MODE BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN BIT(0)
++#define ALFPS_DTCT_EN BIT(1)
++#define ARCVR_DTCT_EVENT_SEL BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT 10000
++#define POWER_DOWN_DELAY_US_MIN 10
++#define POWER_DOWN_DELAY_US_MAX 11
++
++#define MAX_PROP_NAME 32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
++
++struct qmp_phy_init_tbl {
++ unsigned int offset;
++ unsigned int val;
++ /*
++ * register part of layout ?
++ * if yes, then offset gives index in the reg-layout
++ */
++ bool in_layout;
++ /*
++ * mask of lanes for which this register is written
++ * for cases when second lane needs different values
++ */
++ u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_L(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .in_layout = true, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = l, \
++ }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++ /* Common block control registers */
++ QPHY_COM_SW_RESET,
++ QPHY_COM_POWER_DOWN_CONTROL,
++ QPHY_COM_START_CONTROL,
++ QPHY_COM_PCS_READY_STATUS,
++ /* PCS registers */
++ QPHY_PLL_LOCK_CHK_DLY_TIME,
++ QPHY_FLL_CNTRL1,
++ QPHY_FLL_CNTRL2,
++ QPHY_FLL_CNT_VAL_L,
++ QPHY_FLL_CNT_VAL_H_TOL,
++ QPHY_FLL_MAN_CODE,
++ QPHY_SW_RESET,
++ QPHY_START_CTRL,
++ QPHY_PCS_READY_STATUS,
++ QPHY_PCS_STATUS,
++ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++ QPHY_PCS_POWER_DOWN_CONTROL,
++ /* PCS_MISC registers */
++ QPHY_PCS_MISC_TYPEC_CTRL,
++ /* Keep last to ensure regs_layout arrays are properly initialized */
++ QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_COM_SW_RESET] = 0x400,
++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
++ [QPHY_COM_START_CONTROL] = 0x408,
++ [QPHY_COM_PCS_READY_STATUS] = 0x448,
++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
++ [QPHY_FLL_CNTRL1] = 0xc4,
++ [QPHY_FLL_CNTRL2] = 0xc8,
++ [QPHY_FLL_CNT_VAL_L] = 0xcc,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
++ [QPHY_FLL_MAN_CODE] = 0xd4,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_FLL_CNTRL1] = 0xc0,
++ [QPHY_FLL_CNTRL2] = 0xc4,
++ [QPHY_FLL_CNT_VAL_L] = 0xc8,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
++ [QPHY_FLL_MAN_CODE] = 0xd0,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x17c,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
++
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
++
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
++
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
++
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
++
++ /* array of registers with different offsets */
++ const unsigned int *regs;
++
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
++
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
++
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
++
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
++
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
++
++ struct qmp_phy **phys;
++
++ struct mutex phy_mutex;
++ int init_count;
++
++ struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++ "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++ "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++ "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++ "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++ "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++ "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++ "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++ "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++ "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++ "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++ "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
++
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_ufs_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++ .tx_tbl = msm8996_ufs_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++ .rx_tbl = msm8996_ufs_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++ .clk_list = msm8996_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++
++ .regs = msm8996_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = msm8996_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++ .pcs_tbl = msm8996_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++ "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++ "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++ .tx_tbl = ipq8074_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++ .rx_tbl = ipq8074_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++ .pcs_tbl = ipq8074_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq6018_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++ .tx_tbl = ipq6018_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++ .rx_tbl = ipq6018_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++ .pcs_tbl = ipq6018_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = ipq_pciephy_gen3_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qmp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qhp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++ .tx_tbl = qmp_v3_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++ .usb_cfg = &sc7180_usb3phy_cfg,
++ .dp_cfg = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++ .tx_tbl = sdm845_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++ .rx_tbl = sdm845_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++ .tx_tbl = sm6115_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++ .rx_tbl = sm6115_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm6115_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++
++ .is_dual_lane_phy = false,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++ .tx_tbl = msm8998_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++ .rx_tbl = msm8998_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++ .pcs_tbl = msm8998_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++ .tx_tbl = msm8998_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++ .rx_tbl = msm8998_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++ .pcs_tbl = msm8998_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++ .tx_tbl = sm8150_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++ .rx_tbl = sm8150_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8150_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++ .rx_tbl = sm8150_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++ .pcs_tbl = sm8150_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++ .usb_cfg = &sm8150_usb3phy_cfg,
++ .dp_cfg = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8250_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++ .rx_tbl = sm8250_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++ .pcs_tbl = sm8250_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++ .usb_cfg = &sm8250_usb3phy_cfg,
++ .dp_cfg = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8350_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++ .rx_tbl = sm8350_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++ .pcs_tbl = sm8350_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sm8450_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qcm2290_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++ .tx_tbl = qcm2290_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++ .rx_tbl = qcm2290_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++ .pcs_tbl = qcm2290_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++ .clk_list = qcm2290_usb3phy_clk_l,
++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++ .reset_list = qcm2290_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qcm2290_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num,
++ u8 lane_mask)
++{
++ int i;
++ const struct qmp_phy_init_tbl *t = tbl;
++
++ if (!t)
++ return;
++
++ for (i = 0; i < num; i++, t++) {
++ if (!(t->lane_mask & lane_mask))
++ continue;
++
++ if (t->in_layout)
++ writel(t->val, base + regs[t->offset]);
++ else
++ writel(t->val, base + t->offset);
++ }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num)
++{
++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++ int serdes_tbl_num = cfg->serdes_tbl_num;
++ int ret;
++
++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ if (cfg->serdes_tbl_sec)
++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ cfg->serdes_tbl_num_sec);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ switch (dp_opts->link_rate) {
++ case 1620:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_rbr,
++ cfg->serdes_tbl_rbr_num);
++ break;
++ case 2700:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr,
++ cfg->serdes_tbl_hbr_num);
++ break;
++ case 5400:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr2,
++ cfg->serdes_tbl_hbr2_num);
++ break;
++ case 8100:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr3,
++ cfg->serdes_tbl_hbr3_num);
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ }
++
++
++ if (cfg->has_phy_com_ctrl) {
++ void __iomem *status;
++ unsigned int mask, val;
++
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
++
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++ DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(QSERDES_V3_COM_BIAS_EN |
++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++ { 0x00, 0x0c, 0x15, 0x1a },
++ { 0x02, 0x0e, 0x16, 0xff },
++ { 0x02, 0x11, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++ { 0x02, 0x12, 0x16, 0x1a },
++ { 0x09, 0x19, 0x1f, 0xff },
++ { 0x10, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++ { 0x00, 0x0c, 0x14, 0x19 },
++ { 0x00, 0x0b, 0x12, 0xff },
++ { 0x00, 0x0b, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++ { 0x08, 0x0f, 0x16, 0x1f },
++ { 0x11, 0x1e, 0x1f, 0xff },
++ { 0x19, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ unsigned int v_level = 0, p_level = 0;
++ u8 voltage_swing_cfg, pre_emphasis_cfg;
++ int i;
++
++ for (i = 0; i < dp_opts->lanes; i++) {
++ v_level = max(v_level, dp_opts->voltage[i]);
++ p_level = max(p_level, dp_opts->pre[i]);
++ }
++
++ if (dp_opts->link_rate <= 2700) {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++ } else {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++ }
++
++ /* TODO: Move check to config check */
++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++ return -EINVAL;
++
++ /* Enable MUX to use Cursor values from these registers */
++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 bias_en, drvr_en;
++
++ if (qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V3_TX_TX_DRV_LVL,
++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++ return;
++
++ if (dp_opts->lanes == 1) {
++ bias_en = 0x3e;
++ drvr_en = 0x13;
++ } else {
++ bias_en = 0x3f;
++ drvr_en = 0x10;
++ }
++
++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++ u32 val;
++ bool reverse = false;
++
++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++ /*
++ * TODO: Assume orientation is CC1 for now and two lanes, need to
++ * use type-c connector to understand orientation and lanes.
++ *
++ * Otherwise val changes to be like below if this code understood
++ * the orientation of the type-c cable.
++ *
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ * if (orientation == ORIENTATION_CC2)
++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++ */
++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++ return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++
++ qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ /* Program default values before writing proper values */
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V4_TX_TX_DRV_LVL,
++ QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++ bool reverse;
++
++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ /*
++ * At least for 7nm DP PHY this has to be done after enabling link
++ * clock.
++ */
++
++ if (dp_opts->lanes == 1) {
++ bias0_en = reverse ? 0x3e : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3e;
++ drvr0_en = reverse ? 0x13 : 0x10;
++ drvr1_en = reverse ? 0x10 : 0x13;
++ } else if (dp_opts->lanes == 2) {
++ bias0_en = reverse ? 0x3f : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ } else {
++ bias0_en = 0x3f;
++ bias1_en = 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ }
++
++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++ if (qphy->dp_opts.set_voltages) {
++ cfg->configure_dp_tx(qphy);
++ qphy->dp_opts.set_voltages = 0;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->calibrate_dp_phy)
++ return cfg->calibrate_dp_phy(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *dp_com = qmp->dp_com;
++ int ret, i;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (qmp->init_count++) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ /* turn on regulator supplies */
++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++ if (ret) {
++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++ goto err_unlock;
++ }
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ ret = reset_control_assert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset assert failed\n",
++ cfg->reset_list[i]);
++ goto err_disable_regulators;
++ }
++ }
++
++ for (i = cfg->num_resets - 1; i >= 0; i--) {
++ ret = reset_control_deassert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset deassert failed\n",
++ qphy->cfg->reset_list[i]);
++ goto err_assert_reset;
++ }
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ goto err_assert_reset;
++
++ if (cfg->has_phy_dp_com_ctrl) {
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++ SW_PWRDN);
++ /* override hardware control for reset of qmp phy */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ /* Default type-c orientation, i.e CC1 */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++ USB3_MODE | DP_MODE);
++
++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++ }
++
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ } else {
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++
++err_assert_reset:
++ while (++i < cfg->num_resets)
++ reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++ mutex_unlock(&qmp->phy_mutex);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ int i = cfg->num_resets;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (--qmp->init_count) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ reset_control_assert(qmp->ufs_reset);
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ }
++
++ while (--i >= 0)
++ reset_control_assert(qmp->resets[i]);
++
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret;
++ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++ if (cfg->no_pcs_sw_reset) {
++ /*
++ * Get UFS reset, which is delayed until now to avoid a
++ * circular dependency where UFS needs its PHY, but the PHY
++ * needs this UFS reset.
++ */
++ if (!qmp->ufs_reset) {
++ qmp->ufs_reset =
++ devm_reset_control_get_exclusive(qmp->dev,
++ "ufsphy");
++
++ if (IS_ERR(qmp->ufs_reset)) {
++ ret = PTR_ERR(qmp->ufs_reset);
++ dev_err(qmp->dev,
++ "failed to get UFS reset: %d\n",
++ ret);
++
++ qmp->ufs_reset = NULL;
++ return ret;
++ }
++ }
++
++ ret = reset_control_assert(qmp->ufs_reset);
++ if (ret)
++ return ret;
++ }
++
++ ret = qcom_qmp_phy_com_init(qphy);
++ if (ret)
++ return ret;
++
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->dp_aux_init(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *tx = qphy->tx;
++ void __iomem *rx = qphy->rx;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ void __iomem *status;
++ unsigned int mask, val, ready;
++ int ret;
++
++ qcom_qmp_phy_serdes_init(qphy);
++
++ if (cfg->has_lane_rst) {
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
++ }
++ }
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++ goto err_reset_lane;
++ }
++
++ /* Tx, Rx, and PCS configurations */
++ qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 1);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 1);
++
++ /* Configuration for other LANE for USB-DP combo PHY */
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 2);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 2);
++ }
++
++ /* Configure special DP tx tunings */
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->configure_dp_tx(qphy);
++
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 1);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 2);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl_sec,
++ cfg->rx_tbl_num_sec, 2);
++ }
++
++ /* Configure link rate, swing, etc. */
++ if (cfg->type == PHY_TYPE_DP) {
++ cfg->configure_dp_phy(qphy);
++ } else {
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
++ }
++
++ ret = reset_control_deassert(qmp->ufs_reset);
++ if (ret)
++ goto err_disable_pipe_clk;
++
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ cfg->pcs_misc_tbl_num);
++ if (cfg->pcs_misc_tbl_sec)
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ cfg->pcs_misc_tbl_num_sec);
++
++ /*
++ * Pull out PHY from POWER DOWN state.
++ * This is active low enable signal to power-down PHY.
++ */
++ if(cfg->type == PHY_TYPE_PCIE)
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++ if (cfg->has_pwrdn_delay)
++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++ if (cfg->type != PHY_TYPE_DP) {
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ if (cfg->type == PHY_TYPE_UFS) {
++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++ mask = PCS_READY;
++ ready = PCS_READY;
++ } else {
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++ }
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
++ }
++ }
++ return 0;
++
++err_disable_pipe_clk:
++ clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ clk_disable_unprepare(qphy->pipe_clk);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ /* Assert DP PHY power down */
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++ } else {
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ qcom_qmp_phy_com_exit(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_init(phy);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_power_on(phy);
++ if (ret)
++ qcom_qmp_phy_exit(phy);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_power_off(phy);
++ if (ret)
++ return ret;
++ return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++ enum phy_mode mode, int submode)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++ qphy->mode = mode;
++
++ return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ u32 intr_mask;
++
++ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++ qphy->mode == PHY_MODE_USB_DEVICE_SS)
++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++ else
++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++ /* Clear any pending interrupts status */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++ /* Enable required PHY autonomous mode interrupts */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++ /* Enable i/o clamp_n for autonomous mode */
++ if (pcs_misc)
++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++
++ /* Disable i/o clamp_n on resume for normal mode */
++ if (pcs_misc)
++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++ clk_disable_unprepare(qphy->pipe_clk);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret = 0;
++
++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++ return ret;
++ }
++
++ qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_vregs;
++ int i;
++
++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++ if (!qmp->vregs)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->vregs[i].supply = cfg->vreg_list[i];
++
++ return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int i;
++
++ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++ sizeof(*qmp->resets), GFP_KERNEL);
++ if (!qmp->resets)
++ return -ENOMEM;
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ struct reset_control *rst;
++ const char *name = cfg->reset_list[i];
++
++ rst = devm_reset_control_get_exclusive(dev, name);
++ if (IS_ERR(rst)) {
++ dev_err(dev, "failed to get %s reset\n", name);
++ return PTR_ERR(rst);
++ }
++ qmp->resets[i] = rst;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_clks;
++ int i;
++
++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++ if (!qmp->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->clks[i].id = cfg->clk_list[i];
++
++ return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++ of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ * +---------------+
++ * | PHY block |<<---------------------------------------+
++ * | | |
++ * | +-------+ | +-----+ |
++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ * clk | +-------+ | +-----+
++ * +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++ struct clk_fixed_rate *fixed;
++ struct clk_init_data init = { };
++ int ret;
++
++ ret = of_property_read_string(np, "clock-output-names", &init.name);
++ if (ret) {
++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++ return ret;
++ }
++
++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++ if (!fixed)
++ return -ENOMEM;
++
++ init.ops = &clk_fixed_rate_ops;
++
++ /* controllers using QMP phys use 125MHz pipe clock interface */
++ fixed->fixed_rate = 125000000;
++ fixed->hw.init = &init;
++
++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ * +------------------------------+
++ * | DP_VCO_CLK |
++ * | |
++ * | +-------------------+ |
++ * | | (DP PLL/VCO) | |
++ * | +---------+---------+ |
++ * | v |
++ * | +----------+-----------+ |
++ * | | hsclk_divsel_clk_src | |
++ * | +----------+-----------+ |
++ * +------------------------------+
++ * |
++ * +---------<---------v------------>----------+
++ * | |
++ * +--------v----------------+ |
++ * | dp_phy_pll_link_clk | |
++ * | link_clk | |
++ * +--------+----------------+ |
++ * | |
++ * | |
++ * v v
++ * Input to DISPCC block |
++ * for link clk, crypto clk |
++ * and interface clock |
++ * |
++ * |
++ * +--------<------------+-----------------+---<---+
++ * | | |
++ * +----v---------+ +--------v-----+ +--------v------+
++ * | vco_divided | | vco_divided | | vco_divided |
++ * | _clk_src | | _clk_src | | _clk_src |
++ * | | | | | |
++ * |divsel_six | | divsel_two | | divsel_four |
++ * +-------+------+ +-----+--------+ +--------+------+
++ * | | |
++ * v---->----------v-------------<------v
++ * |
++ * +----------+-----------------+
++ * | dp_phy_pll_vco_div_clk |
++ * +---------+------------------+
++ * |
++ * v
++ * Input to DISPCC block
++ * for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 1620000000UL / 2:
++ case 2700000000UL / 2:
++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ return 1620000000UL / 2;
++ case 2700:
++ return 2700000000UL / 2;
++ case 5400:
++ return 5400000000UL / 4;
++ case 8100:
++ return 8100000000UL / 6;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 162000000:
++ case 270000000:
++ case 540000000:
++ case 810000000:
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ return dp_opts->link_rate * 100000;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct qmp_phy_dp_clks *dp_clks = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx >= 2) {
++ pr_err("%s: invalid index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (idx == 0)
++ return &dp_clks->dp_link_hw;
++
++ return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++ struct device_node *np)
++{
++ struct clk_init_data init = { };
++ struct qmp_phy_dp_clks *dp_clks;
++ char name[64];
++ int ret;
++
++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++ if (!dp_clks)
++ return -ENOMEM;
++
++ dp_clks->qphy = qphy;
++ qphy->dp_clks = dp_clks;
++
++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_link_clk_ops;
++ init.name = name;
++ dp_clks->dp_link_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++ if (ret)
++ return ret;
++
++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_pixel_clk_ops;
++ init.name = name;
++ dp_clks->dp_pixel_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++ .init = qcom_qmp_phy_enable,
++ .exit = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++ .init = qcom_qmp_phy_init,
++ .configure = qcom_qmp_dp_phy_configure,
++ .power_on = qcom_qmp_phy_power_on,
++ .calibrate = qcom_qmp_dp_phy_calibrate,
++ .power_off = qcom_qmp_phy_power_off,
++ .exit = qcom_qmp_phy_exit,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++ .power_on = qcom_qmp_phy_enable,
++ .power_off = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++ reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct phy *generic_phy;
++ struct qmp_phy *qphy;
++ const struct phy_ops *ops;
++ char prop_name[MAX_PROP_NAME];
++ int ret;
++
++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++ if (!qphy)
++ return -ENOMEM;
++
++ qphy->cfg = cfg;
++ qphy->serdes = serdes;
++ /*
++ * Get memory resources for each phy lane:
++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++ * For single lane PHYs: pcs_misc (optional) -> 3.
++ */
++ qphy->tx = of_iomap(np, 0);
++ if (!qphy->tx)
++ return -ENOMEM;
++
++ qphy->rx = of_iomap(np, 1);
++ if (!qphy->rx)
++ return -ENOMEM;
++
++ qphy->pcs = of_iomap(np, 2);
++ if (!qphy->pcs)
++ return -ENOMEM;
++
++ /*
++ * If this is a dual-lane PHY, then there should be registers for the
++ * second lane. Some old device trees did not specify this, so fall
++ * back to old legacy behavior of assuming they can be reached at an
++ * offset from the first lane.
++ */
++ if (cfg->is_dual_lane_phy) {
++ qphy->tx2 = of_iomap(np, 3);
++ qphy->rx2 = of_iomap(np, 4);
++ if (!qphy->tx2 || !qphy->rx2) {
++ dev_warn(dev,
++ "Underspecified device tree, falling back to legacy register regions\n");
++
++ /* In the old version, pcs_misc is at index 3. */
++ qphy->pcs_misc = qphy->tx2;
++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 5);
++ }
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 3);
++ }
++
++ if (!qphy->pcs_misc)
++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++ /*
++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++ * based phys, so they essentially have pipe clock. So,
++ * we return error in case phy is USB3 or PIPE type.
++ * Otherwise, we initialize pipe clock to NULL for
++ * all phys that don't need this.
++ */
++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ if (IS_ERR(qphy->pipe_clk)) {
++ if (cfg->type == PHY_TYPE_PCIE ||
++ cfg->type == PHY_TYPE_USB3) {
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
++ }
++ qphy->pipe_clk = NULL;
++ }
++
++ /* Get lane reset, if any */
++ if (cfg->has_lane_rst) {
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
++ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
++ }
++
++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++ ops = &qcom_qmp_pcie_ufs_ops;
++ else if (cfg->type == PHY_TYPE_DP)
++ ops = &qcom_qmp_phy_dp_ops;
++ else
++ ops = &qcom_qmp_phy_gen_ops;
++
++ generic_phy = devm_phy_create(dev, np, ops);
++ if (IS_ERR(generic_phy)) {
++ ret = PTR_ERR(generic_phy);
++ dev_err(dev, "failed to create qphy %d\n", ret);
++ return ret;
++ }
++
++ qphy->phy = generic_phy;
++ qphy->index = id;
++ qphy->qmp = qmp;
++ qmp->phys[id] = qphy;
++ phy_set_drvdata(generic_phy, qphy);
++
++ return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,ipq8074-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-pcie-phy",
++ .data = &msm8996_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-ufs-phy",
++ .data = &msm8996_ufs_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-usb3-phy",
++ .data = &msm8996_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-pcie-phy",
++ .data = &msm8998_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,ipq8074-qmp-pcie-phy",
++ .data = &ipq8074_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-pcie-phy",
++ .data = &ipq6018_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-phy",
++ .data = &sc7180_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sc8180x-qmp-pcie-phy",
++ .data = &sc8180x_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sdm845-qhp-pcie-phy",
++ .data = &sdm845_qhp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-pcie-phy",
++ .data = &sdm845_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-phy",
++ .data = &qmp_v3_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++ .data = &qmp_v3_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-usb3-phy",
++ .data = &msm8998_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm6115-qmp-ufs-phy",
++ .data = &sm6115_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm6350-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++ .data = &sm8150_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-phy",
++ .data = &sm8250_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++ .data = &sm8250_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-pcie-phy",
++ .data = &sdx55_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++ .data = &sdx55_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++ .data = &sdx65_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++ .data = &sm8350_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-ufs-phy",
++ .data = &sm8450_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,qcm2290-qmp-usb3-phy",
++ .data = &qcm2290_usb3phy_cfg,
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ .data = &sc7180_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ .data = &sm8250_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ .data = &sc8180x_usb3dpphy_cfg,
++ },
++ { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++ qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++ struct qcom_qmp *qmp;
++ struct device *dev = &pdev->dev;
++ struct device_node *child;
++ struct phy_provider *phy_provider;
++ void __iomem *serdes;
++ void __iomem *usb_serdes;
++ void __iomem *dp_serdes = NULL;
++ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++ const struct qmp_phy_cfg *cfg = NULL;
++ const struct qmp_phy_cfg *usb_cfg = NULL;
++ const struct qmp_phy_cfg *dp_cfg = NULL;
++ int num, id, expected_phys;
++ int ret;
++
++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++ if (!qmp)
++ return -ENOMEM;
++
++ qmp->dev = dev;
++ dev_set_drvdata(dev, qmp);
++
++ /* Get the specific init parameters of QMP phy */
++ cfg = of_device_get_match_data(dev);
++ if (!cfg) {
++ const struct of_device_id *match;
++
++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++ if (!match)
++ return -EINVAL;
++
++ combo_cfg = match->data;
++ if (!combo_cfg)
++ return -EINVAL;
++
++ usb_cfg = combo_cfg->usb_cfg;
++ cfg = usb_cfg; /* Setup clks and regulators */
++ }
++
++ /* per PHY serdes; usually located at base address */
++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(serdes))
++ return PTR_ERR(serdes);
++
++ /* per PHY dp_com; if PHY has dp_com control block */
++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(qmp->dp_com))
++ return PTR_ERR(qmp->dp_com);
++ }
++
++ if (combo_cfg) {
++ /* Only two serdes for combo PHY */
++ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++ if (IS_ERR(dp_serdes))
++ return PTR_ERR(dp_serdes);
++
++ dp_cfg = combo_cfg->dp_cfg;
++ expected_phys = 2;
++ } else {
++ expected_phys = cfg->nlanes;
++ }
++
++ mutex_init(&qmp->phy_mutex);
++
++ ret = qcom_qmp_phy_clk_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_reset_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ if (ret) {
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "failed to get regulator supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ num = of_get_available_child_count(dev->of_node);
++ /* do we have a rogue child node ? */
++ if (num > expected_phys)
++ return -EINVAL;
++
++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++ if (!qmp->phys)
++ return -ENOMEM;
++
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ /*
++ * Prevent runtime pm from being ON by default. Users can enable
++ * it using power/control in sysfs.
++ */
++ pm_runtime_forbid(dev);
++
++ id = 0;
++ for_each_available_child_of_node(dev->of_node, child) {
++ if (of_node_name_eq(child, "dp-phy")) {
++ cfg = dp_cfg;
++ serdes = dp_serdes;
++ } else if (of_node_name_eq(child, "usb3-phy")) {
++ cfg = usb_cfg;
++ serdes = usb_serdes;
++ }
++
++ /* Create per-lane phy */
++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ if (ret) {
++ dev_err(dev, "failed to create lane%d phy, %d\n",
++ id, ret);
++ goto err_node_put;
++ }
++
++ /*
++ * Register the pipe clock provided by phy.
++ * See function description to see details of this pipe clock.
++ */
++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
++ }
++ } else if (cfg->type == PHY_TYPE_DP) {
++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register DP clock source\n");
++ goto err_node_put;
++ }
++ }
++ id++;
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ if (!IS_ERR(phy_provider))
++ dev_info(dev, "Registered Qcom-QMP phy\n");
++ else
++ pm_runtime_disable(dev);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++ pm_runtime_disable(dev);
++ of_node_put(child);
++ return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++ .probe = qcom_qmp_phy_probe,
++ .driver = {
++ .name = "qcom-qmp-phy",
++ .pm = &qcom_qmp_phy_pm_ops,
++ .of_match_table = qcom_qmp_phy_of_match_table,
++ },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+new file mode 100644
+index 000000000000..c7309e981bfb
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN BIT(0)
++#define REFCLK_DRV_DSBL BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START BIT(0)
++#define PCS_START BIT(1)
++#define PLL_READY_GATE_EN BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS BIT(6)
++#define PHYSTATUS_4_20 BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE BIT(0) /* enables USB3 mode */
++#define DP_MODE BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN BIT(0)
++#define ALFPS_DTCT_EN BIT(1)
++#define ARCVR_DTCT_EVENT_SEL BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT 10000
++#define POWER_DOWN_DELAY_US_MIN 10
++#define POWER_DOWN_DELAY_US_MAX 11
++
++#define MAX_PROP_NAME 32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
++
++struct qmp_phy_init_tbl {
++ unsigned int offset;
++ unsigned int val;
++ /*
++ * register part of layout ?
++ * if yes, then offset gives index in the reg-layout
++ */
++ bool in_layout;
++ /*
++ * mask of lanes for which this register is written
++ * for cases when second lane needs different values
++ */
++ u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_L(o, v) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .in_layout = true, \
++ .lane_mask = 0xff, \
++ }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
++ { \
++ .offset = o, \
++ .val = v, \
++ .lane_mask = l, \
++ }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++ /* Common block control registers */
++ QPHY_COM_SW_RESET,
++ QPHY_COM_POWER_DOWN_CONTROL,
++ QPHY_COM_START_CONTROL,
++ QPHY_COM_PCS_READY_STATUS,
++ /* PCS registers */
++ QPHY_PLL_LOCK_CHK_DLY_TIME,
++ QPHY_FLL_CNTRL1,
++ QPHY_FLL_CNTRL2,
++ QPHY_FLL_CNT_VAL_L,
++ QPHY_FLL_CNT_VAL_H_TOL,
++ QPHY_FLL_MAN_CODE,
++ QPHY_SW_RESET,
++ QPHY_START_CTRL,
++ QPHY_PCS_READY_STATUS,
++ QPHY_PCS_STATUS,
++ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++ QPHY_PCS_POWER_DOWN_CONTROL,
++ /* PCS_MISC registers */
++ QPHY_PCS_MISC_TYPEC_CTRL,
++ /* Keep last to ensure regs_layout arrays are properly initialized */
++ QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_COM_SW_RESET] = 0x400,
++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
++ [QPHY_COM_START_CONTROL] = 0x408,
++ [QPHY_COM_PCS_READY_STATUS] = 0x448,
++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
++ [QPHY_FLL_CNTRL1] = 0xc4,
++ [QPHY_FLL_CNTRL2] = 0xc8,
++ [QPHY_FLL_CNT_VAL_L] = 0xcc,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
++ [QPHY_FLL_MAN_CODE] = 0xd4,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_FLL_CNTRL1] = 0xc0,
++ [QPHY_FLL_CNTRL2] = 0xc4,
++ [QPHY_FLL_CNT_VAL_L] = 0xc8,
++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
++ [QPHY_FLL_MAN_CODE] = 0xd0,
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x17c,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_STATUS] = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
++ [QPHY_START_CTRL] = 0x08,
++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++ [QPHY_PCS_STATUS] = 0x174,
++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = 0x00,
++ [QPHY_PCS_READY_STATUS] = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_SW_RESET] = 0x00,
++ [QPHY_START_CTRL] = 0x44,
++ [QPHY_PCS_STATUS] = 0x14,
++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++ /* FLL settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++ /* Lock Det settings */
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++ /* Rate B */
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
++
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
++
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
++
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
++
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
++
++ /* array of registers with different offsets */
++ const unsigned int *regs;
++
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
++
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
++
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
++
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
++
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
++
++ struct qmp_phy **phys;
++
++ struct mutex phy_mutex;
++ int init_count;
++
++ struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
++
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
++
++ /* ensure that above write is through */
++ readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++ "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++ "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++ "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++ "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++ "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++ "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++ "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++ "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++ "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++ "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++ "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++ "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
++
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_ufs_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++ .tx_tbl = msm8996_ufs_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++ .rx_tbl = msm8996_ufs_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++ .clk_list = msm8996_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++
++ .regs = msm8996_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8996_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = msm8996_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++ .pcs_tbl = msm8996_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++ "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++ "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq8074_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++ .tx_tbl = ipq8074_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++ .rx_tbl = ipq8074_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++ .pcs_tbl = ipq8074_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = ipq6018_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++ .tx_tbl = ipq6018_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++ .rx_tbl = ipq6018_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++ .pcs_tbl = ipq6018_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .clk_list = ipq8074_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = NULL,
++ .num_vregs = 0,
++ .regs = ipq_pciephy_gen3_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_phy_com_ctrl = false,
++ .has_lane_rst = false,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qmp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_qhp_pciephy_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++ .tx_tbl = qmp_v3_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++ .usb_cfg = &sc7180_usb3phy_cfg,
++ .dp_cfg = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++ .tx_tbl = sdm845_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++ .rx_tbl = sdm845_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sdm845_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 1,
++
++ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++ .tx_tbl = sm6115_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++ .rx_tbl = sm6115_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm6115_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++
++ .is_dual_lane_phy = false,
++ .no_pcs_sw_reset = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++ .tx_tbl = msm8998_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++ .rx_tbl = msm8998_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++ .pcs_tbl = msm8998_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = ipq8074_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = pciephy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = msm8998_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++ .tx_tbl = msm8998_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++ .rx_tbl = msm8998_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++ .pcs_tbl = msm8998_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++ .tx_tbl = sm8150_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++ .rx_tbl = sm8150_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8150_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++ .rx_tbl = sm8150_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++ .pcs_tbl = sm8150_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v3_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
++ .reset_list = sc7180_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++ .usb_cfg = &sm8150_usb3phy_cfg,
++ .dp_cfg = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8250_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++ .rx_tbl = sm8250_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++ .pcs_tbl = sm8250_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++ .type = PHY_TYPE_DP,
++ .nlanes = 1,
++
++ .serdes_tbl = qmp_v4_dp_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++ .tx_tbl = qmp_v4_dp_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++
++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++ .usb_cfg = &sm8250_usb3phy_cfg,
++ .dp_cfg = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = PCS_START | SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sdm845_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++ .tx_tbl = sm8350_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++ .rx_tbl = sm8350_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++ .pcs_tbl = sm8350_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v4_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++
++ .has_phy_dp_com_ctrl = true,
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++ .clk_list = qmp_v4_phy_clk_l,
++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8350_usb3_uniphy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++ .type = PHY_TYPE_UFS,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++ .tx_tbl = sm8350_ufsphy_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++ .rx_tbl = sm8350_ufsphy_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++ .clk_list = sm8450_ufs_phy_clk_l,
++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8150_ufsphy_regs_layout,
++
++ .start_ctrl = SERDES_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 1,
++
++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS,
++
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 2,
++
++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++ .clk_list = sdm845_pciephy_clk_l,
++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
++ .reset_list = sdm845_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = sm8250_pcie_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .phy_status = PHYSTATUS_4_20,
++
++ .is_dual_lane_phy = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = 995, /* us */
++ .pwrdn_delay_max = 1005, /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++ .type = PHY_TYPE_USB3,
++ .nlanes = 1,
++
++ .serdes_tbl = qcm2290_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++ .tx_tbl = qcm2290_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++ .rx_tbl = qcm2290_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++ .pcs_tbl = qcm2290_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++ .clk_list = qcm2290_usb3phy_clk_l,
++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++ .reset_list = qcm2290_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qcm2290_usb3phy_regs_layout,
++
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
++ .phy_status = PHYSTATUS,
++
++ .is_dual_lane_phy = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num,
++ u8 lane_mask)
++{
++ int i;
++ const struct qmp_phy_init_tbl *t = tbl;
++
++ if (!t)
++ return;
++
++ for (i = 0; i < num; i++, t++) {
++ if (!(t->lane_mask & lane_mask))
++ continue;
++
++ if (t->in_layout)
++ writel(t->val, base + regs[t->offset]);
++ else
++ writel(t->val, base + t->offset);
++ }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++ const unsigned int *regs,
++ const struct qmp_phy_init_tbl tbl[],
++ int num)
++{
++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++ int serdes_tbl_num = cfg->serdes_tbl_num;
++ int ret;
++
++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ if (cfg->serdes_tbl_sec)
++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ cfg->serdes_tbl_num_sec);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ switch (dp_opts->link_rate) {
++ case 1620:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_rbr,
++ cfg->serdes_tbl_rbr_num);
++ break;
++ case 2700:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr,
++ cfg->serdes_tbl_hbr_num);
++ break;
++ case 5400:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr2,
++ cfg->serdes_tbl_hbr2_num);
++ break;
++ case 8100:
++ qcom_qmp_phy_configure(serdes, cfg->regs,
++ cfg->serdes_tbl_hbr3,
++ cfg->serdes_tbl_hbr3_num);
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ }
++
++
++ if (cfg->has_phy_com_ctrl) {
++ void __iomem *status;
++ unsigned int mask, val;
++
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
++
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++ DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(QSERDES_V3_COM_BIAS_EN |
++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++ { 0x00, 0x0c, 0x15, 0x1a },
++ { 0x02, 0x0e, 0x16, 0xff },
++ { 0x02, 0x11, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++ { 0x02, 0x12, 0x16, 0x1a },
++ { 0x09, 0x19, 0x1f, 0xff },
++ { 0x10, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++ { 0x00, 0x0c, 0x14, 0x19 },
++ { 0x00, 0x0b, 0x12, 0xff },
++ { 0x00, 0x0b, 0xff, 0xff },
++ { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++ { 0x08, 0x0f, 0x16, 0x1f },
++ { 0x11, 0x1e, 0x1f, 0xff },
++ { 0x19, 0x1f, 0xff, 0xff },
++ { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ unsigned int v_level = 0, p_level = 0;
++ u8 voltage_swing_cfg, pre_emphasis_cfg;
++ int i;
++
++ for (i = 0; i < dp_opts->lanes; i++) {
++ v_level = max(v_level, dp_opts->voltage[i]);
++ p_level = max(p_level, dp_opts->pre[i]);
++ }
++
++ if (dp_opts->link_rate <= 2700) {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++ } else {
++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++ }
++
++ /* TODO: Move check to config check */
++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++ return -EINVAL;
++
++ /* Enable MUX to use Cursor values from these registers */
++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++ return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 bias_en, drvr_en;
++
++ if (qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V3_TX_TX_DRV_LVL,
++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++ return;
++
++ if (dp_opts->lanes == 1) {
++ bias_en = 0x3e;
++ drvr_en = 0x13;
++ } else {
++ bias_en = 0x3f;
++ drvr_en = 0x10;
++ }
++
++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++ u32 val;
++ bool reverse = false;
++
++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++ /*
++ * TODO: Assume orientation is CC1 for now and two lanes, need to
++ * use type-c connector to understand orientation and lanes.
++ *
++ * Otherwise val changes to be like below if this code understood
++ * the orientation of the type-c cable.
++ *
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ * if (orientation == ORIENTATION_CC2)
++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++ */
++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++ return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++
++ qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++ /* Turn on BIAS current for PHY/PLL */
++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++ qphy->dp_aux_cfg = 0;
++
++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++ PHY_AUX_REQ_ERR_MASK,
++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++ /* Program default values before writing proper values */
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ qcom_qmp_phy_configure_dp_swing(qphy,
++ QSERDES_V4_TX_TX_DRV_LVL,
++ QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++ u32 phy_vco_div, status;
++ unsigned long pixel_freq;
++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++ bool reverse;
++
++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ phy_vco_div = 0x1;
++ pixel_freq = 1620000000UL / 2;
++ break;
++ case 2700:
++ phy_vco_div = 0x1;
++ pixel_freq = 2700000000UL / 2;
++ break;
++ case 5400:
++ phy_vco_div = 0x2;
++ pixel_freq = 5400000000UL / 4;
++ break;
++ case 8100:
++ phy_vco_div = 0x0;
++ pixel_freq = 8100000000UL / 6;
++ break;
++ default:
++ /* Other link rates aren't supported */
++ return -EINVAL;
++ }
++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(0)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ /*
++ * At least for 7nm DP PHY this has to be done after enabling link
++ * clock.
++ */
++
++ if (dp_opts->lanes == 1) {
++ bias0_en = reverse ? 0x3e : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3e;
++ drvr0_en = reverse ? 0x13 : 0x10;
++ drvr1_en = reverse ? 0x10 : 0x13;
++ } else if (dp_opts->lanes == 2) {
++ bias0_en = reverse ? 0x3f : 0x15;
++ bias1_en = reverse ? 0x15 : 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ } else {
++ bias0_en = 0x3f;
++ bias1_en = 0x3f;
++ drvr0_en = 0x10;
++ drvr1_en = 0x10;
++ }
++
++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++ udelay(2000);
++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++ status,
++ ((status & BIT(1)) > 0),
++ 500,
++ 10000))
++ return -ETIMEDOUT;
++
++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++ return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++ u8 val;
++
++ qphy->dp_aux_cfg++;
++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++ val = cfg1_settings[qphy->dp_aux_cfg];
++
++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++ if (qphy->dp_opts.set_voltages) {
++ cfg->configure_dp_tx(qphy);
++ qphy->dp_opts.set_voltages = 0;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->calibrate_dp_phy)
++ return cfg->calibrate_dp_phy(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *dp_com = qmp->dp_com;
++ int ret, i;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (qmp->init_count++) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ /* turn on regulator supplies */
++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++ if (ret) {
++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++ goto err_unlock;
++ }
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ ret = reset_control_assert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset assert failed\n",
++ cfg->reset_list[i]);
++ goto err_disable_regulators;
++ }
++ }
++
++ for (i = cfg->num_resets - 1; i >= 0; i--) {
++ ret = reset_control_deassert(qmp->resets[i]);
++ if (ret) {
++ dev_err(qmp->dev, "%s reset deassert failed\n",
++ qphy->cfg->reset_list[i]);
++ goto err_assert_reset;
++ }
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ goto err_assert_reset;
++
++ if (cfg->has_phy_dp_com_ctrl) {
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++ SW_PWRDN);
++ /* override hardware control for reset of qmp phy */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ /* Default type-c orientation, i.e CC1 */
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++ USB3_MODE | DP_MODE);
++
++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++ }
++
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ } else {
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++
++err_assert_reset:
++ while (++i < cfg->num_resets)
++ reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++ mutex_unlock(&qmp->phy_mutex);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *serdes = qphy->serdes;
++ int i = cfg->num_resets;
++
++ mutex_lock(&qmp->phy_mutex);
++ if (--qmp->init_count) {
++ mutex_unlock(&qmp->phy_mutex);
++ return 0;
++ }
++
++ reset_control_assert(qmp->ufs_reset);
++ if (cfg->has_phy_com_ctrl) {
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
++ }
++
++ while (--i >= 0)
++ reset_control_assert(qmp->resets[i]);
++
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++ mutex_unlock(&qmp->phy_mutex);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret;
++ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++ if (cfg->no_pcs_sw_reset) {
++ /*
++ * Get UFS reset, which is delayed until now to avoid a
++ * circular dependency where UFS needs its PHY, but the PHY
++ * needs this UFS reset.
++ */
++ if (!qmp->ufs_reset) {
++ qmp->ufs_reset =
++ devm_reset_control_get_exclusive(qmp->dev,
++ "ufsphy");
++
++ if (IS_ERR(qmp->ufs_reset)) {
++ ret = PTR_ERR(qmp->ufs_reset);
++ dev_err(qmp->dev,
++ "failed to get UFS reset: %d\n",
++ ret);
++
++ qmp->ufs_reset = NULL;
++ return ret;
++ }
++ }
++
++ ret = reset_control_assert(qmp->ufs_reset);
++ if (ret)
++ return ret;
++ }
++
++ ret = qcom_qmp_phy_com_init(qphy);
++ if (ret)
++ return ret;
++
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->dp_aux_init(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ struct qcom_qmp *qmp = qphy->qmp;
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *tx = qphy->tx;
++ void __iomem *rx = qphy->rx;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ void __iomem *status;
++ unsigned int mask, val, ready;
++ int ret;
++
++ qcom_qmp_phy_serdes_init(qphy);
++
++ if (cfg->has_lane_rst) {
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
++ }
++ }
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++ goto err_reset_lane;
++ }
++
++ /* Tx, Rx, and PCS configurations */
++ qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 1);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 1);
++
++ /* Configuration for other LANE for USB-DP combo PHY */
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl, cfg->tx_tbl_num, 2);
++ if (cfg->tx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ cfg->tx_tbl_sec,
++ cfg->tx_tbl_num_sec, 2);
++ }
++
++ /* Configure special DP tx tunings */
++ if (cfg->type == PHY_TYPE_DP)
++ cfg->configure_dp_tx(qphy);
++
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 1);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++ if (cfg->is_dual_lane_phy) {
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl, cfg->rx_tbl_num, 2);
++ if (cfg->rx_tbl_sec)
++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ cfg->rx_tbl_sec,
++ cfg->rx_tbl_num_sec, 2);
++ }
++
++ /* Configure link rate, swing, etc. */
++ if (cfg->type == PHY_TYPE_DP) {
++ cfg->configure_dp_phy(qphy);
++ } else {
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
++ }
++
++ ret = reset_control_deassert(qmp->ufs_reset);
++ if (ret)
++ goto err_disable_pipe_clk;
++
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ cfg->pcs_misc_tbl_num);
++ if (cfg->pcs_misc_tbl_sec)
++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ cfg->pcs_misc_tbl_num_sec);
++
++ /*
++ * Pull out PHY from POWER DOWN state.
++ * This is active low enable signal to power-down PHY.
++ */
++ if(cfg->type == PHY_TYPE_PCIE)
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++ if (cfg->has_pwrdn_delay)
++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++ if (cfg->type != PHY_TYPE_DP) {
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ if (cfg->type == PHY_TYPE_UFS) {
++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++ mask = PCS_READY;
++ ready = PCS_READY;
++ } else {
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++ }
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
++ }
++ }
++ return 0;
++
++err_disable_pipe_clk:
++ clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ clk_disable_unprepare(qphy->pipe_clk);
++
++ if (cfg->type == PHY_TYPE_DP) {
++ /* Assert DP PHY power down */
++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++ } else {
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
++ }
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ if (cfg->has_lane_rst)
++ reset_control_assert(qphy->lane_rst);
++
++ qcom_qmp_phy_com_exit(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_init(phy);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_power_on(phy);
++ if (ret)
++ qcom_qmp_phy_exit(phy);
++
++ return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++ int ret;
++
++ ret = qcom_qmp_phy_power_off(phy);
++ if (ret)
++ return ret;
++ return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++ enum phy_mode mode, int submode)
++{
++ struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++ qphy->mode = mode;
++
++ return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++ u32 intr_mask;
++
++ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++ qphy->mode == PHY_MODE_USB_DEVICE_SS)
++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++ else
++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++ /* Clear any pending interrupts status */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++ /* Enable required PHY autonomous mode interrupts */
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++ /* Enable i/o clamp_n for autonomous mode */
++ if (pcs_misc)
++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ void __iomem *pcs = qphy->pcs;
++ void __iomem *pcs_misc = qphy->pcs_misc;
++
++ /* Disable i/o clamp_n on resume for normal mode */
++ if (pcs_misc)
++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++ /* Writing 1 followed by 0 clears the interrupt */
++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++ clk_disable_unprepare(qphy->pipe_clk);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++ return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct qmp_phy *qphy = qmp->phys[0];
++ const struct qmp_phy_cfg *cfg = qphy->cfg;
++ int ret = 0;
++
++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++ if (cfg->type != PHY_TYPE_USB3)
++ return 0;
++
++ if (!qmp->init_count) {
++ dev_vdbg(dev, "PHY not initialized, bailing out\n");
++ return 0;
++ }
++
++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(qphy->pipe_clk);
++ if (ret) {
++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++ return ret;
++ }
++
++ qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++ return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_vregs;
++ int i;
++
++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++ if (!qmp->vregs)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->vregs[i].supply = cfg->vreg_list[i];
++
++ return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int i;
++
++ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++ sizeof(*qmp->resets), GFP_KERNEL);
++ if (!qmp->resets)
++ return -ENOMEM;
++
++ for (i = 0; i < cfg->num_resets; i++) {
++ struct reset_control *rst;
++ const char *name = cfg->reset_list[i];
++
++ rst = devm_reset_control_get_exclusive(dev, name);
++ if (IS_ERR(rst)) {
++ dev_err(dev, "failed to get %s reset\n", name);
++ return PTR_ERR(rst);
++ }
++ qmp->resets[i] = rst;
++ }
++
++ return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ int num = cfg->num_clks;
++ int i;
++
++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++ if (!qmp->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++)
++ qmp->clks[i].id = cfg->clk_list[i];
++
++ return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++ of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ * +---------------+
++ * | PHY block |<<---------------------------------------+
++ * | | |
++ * | +-------+ | +-----+ |
++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ * clk | +-------+ | +-----+
++ * +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++ struct clk_fixed_rate *fixed;
++ struct clk_init_data init = { };
++ int ret;
++
++ ret = of_property_read_string(np, "clock-output-names", &init.name);
++ if (ret) {
++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++ return ret;
++ }
++
++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++ if (!fixed)
++ return -ENOMEM;
++
++ init.ops = &clk_fixed_rate_ops;
++
++ /* controllers using QMP phys use 125MHz pipe clock interface */
++ fixed->fixed_rate = 125000000;
++ fixed->hw.init = &init;
++
++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ * +------------------------------+
++ * | DP_VCO_CLK |
++ * | |
++ * | +-------------------+ |
++ * | | (DP PLL/VCO) | |
++ * | +---------+---------+ |
++ * | v |
++ * | +----------+-----------+ |
++ * | | hsclk_divsel_clk_src | |
++ * | +----------+-----------+ |
++ * +------------------------------+
++ * |
++ * +---------<---------v------------>----------+
++ * | |
++ * +--------v----------------+ |
++ * | dp_phy_pll_link_clk | |
++ * | link_clk | |
++ * +--------+----------------+ |
++ * | |
++ * | |
++ * v v
++ * Input to DISPCC block |
++ * for link clk, crypto clk |
++ * and interface clock |
++ * |
++ * |
++ * +--------<------------+-----------------+---<---+
++ * | | |
++ * +----v---------+ +--------v-----+ +--------v------+
++ * | vco_divided | | vco_divided | | vco_divided |
++ * | _clk_src | | _clk_src | | _clk_src |
++ * | | | | | |
++ * |divsel_six | | divsel_two | | divsel_four |
++ * +-------+------+ +-----+--------+ +--------+------+
++ * | | |
++ * v---->----------v-------------<------v
++ * |
++ * +----------+-----------------+
++ * | dp_phy_pll_vco_div_clk |
++ * +---------+------------------+
++ * |
++ * v
++ * Input to DISPCC block
++ * for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 1620000000UL / 2:
++ case 2700000000UL / 2:
++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ return 1620000000UL / 2;
++ case 2700:
++ return 2700000000UL / 2;
++ case 5400:
++ return 5400000000UL / 4;
++ case 8100:
++ return 8100000000UL / 6;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ switch (req->rate) {
++ case 162000000:
++ case 270000000:
++ case 540000000:
++ case 810000000:
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++ const struct qmp_phy_dp_clks *dp_clks;
++ const struct qmp_phy *qphy;
++ const struct phy_configure_opts_dp *dp_opts;
++
++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++ qphy = dp_clks->qphy;
++ dp_opts = &qphy->dp_opts;
++
++ switch (dp_opts->link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ return dp_opts->link_rate * 100000;
++ default:
++ return 0;
++ }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct qmp_phy_dp_clks *dp_clks = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx >= 2) {
++ pr_err("%s: invalid index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (idx == 0)
++ return &dp_clks->dp_link_hw;
++
++ return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++ struct device_node *np)
++{
++ struct clk_init_data init = { };
++ struct qmp_phy_dp_clks *dp_clks;
++ char name[64];
++ int ret;
++
++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++ if (!dp_clks)
++ return -ENOMEM;
++
++ dp_clks->qphy = qphy;
++ qphy->dp_clks = dp_clks;
++
++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_link_clk_ops;
++ init.name = name;
++ dp_clks->dp_link_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++ if (ret)
++ return ret;
++
++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++ init.ops = &qcom_qmp_dp_pixel_clk_ops;
++ init.name = name;
++ dp_clks->dp_pixel_hw.init = &init;
++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++ if (ret)
++ return ret;
++
++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++ if (ret)
++ return ret;
++
++ /*
++ * Roll a devm action because the clock provider is the child node, but
++ * the child node is not actually a device.
++ */
++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++ .init = qcom_qmp_phy_enable,
++ .exit = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++ .init = qcom_qmp_phy_init,
++ .configure = qcom_qmp_dp_phy_configure,
++ .power_on = qcom_qmp_phy_power_on,
++ .calibrate = qcom_qmp_dp_phy_calibrate,
++ .power_off = qcom_qmp_phy_power_off,
++ .exit = qcom_qmp_phy_exit,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++ .power_on = qcom_qmp_phy_enable,
++ .power_off = qcom_qmp_phy_disable,
++ .set_mode = qcom_qmp_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++ reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++ struct qcom_qmp *qmp = dev_get_drvdata(dev);
++ struct phy *generic_phy;
++ struct qmp_phy *qphy;
++ const struct phy_ops *ops;
++ char prop_name[MAX_PROP_NAME];
++ int ret;
++
++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++ if (!qphy)
++ return -ENOMEM;
++
++ qphy->cfg = cfg;
++ qphy->serdes = serdes;
++ /*
++ * Get memory resources for each phy lane:
++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++ * For single lane PHYs: pcs_misc (optional) -> 3.
++ */
++ qphy->tx = of_iomap(np, 0);
++ if (!qphy->tx)
++ return -ENOMEM;
++
++ qphy->rx = of_iomap(np, 1);
++ if (!qphy->rx)
++ return -ENOMEM;
++
++ qphy->pcs = of_iomap(np, 2);
++ if (!qphy->pcs)
++ return -ENOMEM;
++
++ /*
++ * If this is a dual-lane PHY, then there should be registers for the
++ * second lane. Some old device trees did not specify this, so fall
++ * back to old legacy behavior of assuming they can be reached at an
++ * offset from the first lane.
++ */
++ if (cfg->is_dual_lane_phy) {
++ qphy->tx2 = of_iomap(np, 3);
++ qphy->rx2 = of_iomap(np, 4);
++ if (!qphy->tx2 || !qphy->rx2) {
++ dev_warn(dev,
++ "Underspecified device tree, falling back to legacy register regions\n");
++
++ /* In the old version, pcs_misc is at index 3. */
++ qphy->pcs_misc = qphy->tx2;
++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 5);
++ }
++
++ } else {
++ qphy->pcs_misc = of_iomap(np, 3);
++ }
++
++ if (!qphy->pcs_misc)
++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++ /*
++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++ * based phys, so they essentially have pipe clock. So,
++ * we return error in case phy is USB3 or PIPE type.
++ * Otherwise, we initialize pipe clock to NULL for
++ * all phys that don't need this.
++ */
++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ if (IS_ERR(qphy->pipe_clk)) {
++ if (cfg->type == PHY_TYPE_PCIE ||
++ cfg->type == PHY_TYPE_USB3) {
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
++ }
++ qphy->pipe_clk = NULL;
++ }
++
++ /* Get lane reset, if any */
++ if (cfg->has_lane_rst) {
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
++ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
++ }
++
++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++ ops = &qcom_qmp_pcie_ufs_ops;
++ else if (cfg->type == PHY_TYPE_DP)
++ ops = &qcom_qmp_phy_dp_ops;
++ else
++ ops = &qcom_qmp_phy_gen_ops;
++
++ generic_phy = devm_phy_create(dev, np, ops);
++ if (IS_ERR(generic_phy)) {
++ ret = PTR_ERR(generic_phy);
++ dev_err(dev, "failed to create qphy %d\n", ret);
++ return ret;
++ }
++
++ qphy->phy = generic_phy;
++ qphy->index = id;
++ qphy->qmp = qmp;
++ qmp->phys[id] = qphy;
++ phy_set_drvdata(generic_phy, qphy);
++
++ return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,ipq8074-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-pcie-phy",
++ .data = &msm8996_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-ufs-phy",
++ .data = &msm8996_ufs_cfg,
++ }, {
++ .compatible = "qcom,msm8996-qmp-usb3-phy",
++ .data = &msm8996_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-pcie-phy",
++ .data = &msm8998_pciephy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,ipq8074-qmp-pcie-phy",
++ .data = &ipq8074_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-pcie-phy",
++ .data = &ipq6018_pciephy_cfg,
++ }, {
++ .compatible = "qcom,ipq6018-qmp-usb3-phy",
++ .data = &ipq8074_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-phy",
++ .data = &sc7180_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sc8180x-qmp-pcie-phy",
++ .data = &sc8180x_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sdm845-qhp-pcie-phy",
++ .data = &sdm845_qhp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-pcie-phy",
++ .data = &sdm845_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-phy",
++ .data = &qmp_v3_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++ .data = &qmp_v3_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdm845-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,msm8998-qmp-usb3-phy",
++ .data = &msm8998_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm6115-qmp-ufs-phy",
++ .data = &sm6115_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm6350-qmp-ufs-phy",
++ .data = &sdm845_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-ufs-phy",
++ .data = &sm8150_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-phy",
++ .data = &sm8150_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++ .data = &sm8150_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-phy",
++ .data = &sm8250_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ /* It's a combo phy */
++ }, {
++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++ .data = &sm8250_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-ufs-phy",
++ .data = &sm8350_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-pcie-phy",
++ .data = &sdx55_qmp_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++ .data = &sdx55_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++ .data = &sdx65_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++ .data = &sm8350_usb3_uniphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-ufs-phy",
++ .data = &sm8450_ufsphy_cfg,
++ }, {
++ .compatible = "qcom,sm8450-qmp-usb3-phy",
++ .data = &sm8350_usb3phy_cfg,
++ }, {
++ .compatible = "qcom,qcm2290-qmp-usb3-phy",
++ .data = &qcm2290_usb3phy_cfg,
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++ {
++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++ .data = &sc7180_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++ .data = &sm8250_usb3dpphy_cfg,
++ },
++ {
++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++ .data = &sc8180x_usb3dpphy_cfg,
++ },
++ { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++ qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++ struct qcom_qmp *qmp;
++ struct device *dev = &pdev->dev;
++ struct device_node *child;
++ struct phy_provider *phy_provider;
++ void __iomem *serdes;
++ void __iomem *usb_serdes;
++ void __iomem *dp_serdes = NULL;
++ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++ const struct qmp_phy_cfg *cfg = NULL;
++ const struct qmp_phy_cfg *usb_cfg = NULL;
++ const struct qmp_phy_cfg *dp_cfg = NULL;
++ int num, id, expected_phys;
++ int ret;
++
++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++ if (!qmp)
++ return -ENOMEM;
++
++ qmp->dev = dev;
++ dev_set_drvdata(dev, qmp);
++
++ /* Get the specific init parameters of QMP phy */
++ cfg = of_device_get_match_data(dev);
++ if (!cfg) {
++ const struct of_device_id *match;
++
++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++ if (!match)
++ return -EINVAL;
++
++ combo_cfg = match->data;
++ if (!combo_cfg)
++ return -EINVAL;
++
++ usb_cfg = combo_cfg->usb_cfg;
++ cfg = usb_cfg; /* Setup clks and regulators */
++ }
++
++ /* per PHY serdes; usually located at base address */
++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(serdes))
++ return PTR_ERR(serdes);
++
++ /* per PHY dp_com; if PHY has dp_com control block */
++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(qmp->dp_com))
++ return PTR_ERR(qmp->dp_com);
++ }
++
++ if (combo_cfg) {
++ /* Only two serdes for combo PHY */
++ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++ if (IS_ERR(dp_serdes))
++ return PTR_ERR(dp_serdes);
++
++ dp_cfg = combo_cfg->dp_cfg;
++ expected_phys = 2;
++ } else {
++ expected_phys = cfg->nlanes;
++ }
++
++ mutex_init(&qmp->phy_mutex);
++
++ ret = qcom_qmp_phy_clk_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_reset_init(dev, cfg);
++ if (ret)
++ return ret;
++
++ ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ if (ret) {
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "failed to get regulator supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ num = of_get_available_child_count(dev->of_node);
++ /* do we have a rogue child node ? */
++ if (num > expected_phys)
++ return -EINVAL;
++
++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++ if (!qmp->phys)
++ return -ENOMEM;
++
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ /*
++ * Prevent runtime pm from being ON by default. Users can enable
++ * it using power/control in sysfs.
++ */
++ pm_runtime_forbid(dev);
++
++ id = 0;
++ for_each_available_child_of_node(dev->of_node, child) {
++ if (of_node_name_eq(child, "dp-phy")) {
++ cfg = dp_cfg;
++ serdes = dp_serdes;
++ } else if (of_node_name_eq(child, "usb3-phy")) {
++ cfg = usb_cfg;
++ serdes = usb_serdes;
++ }
++
++ /* Create per-lane phy */
++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ if (ret) {
++ dev_err(dev, "failed to create lane%d phy, %d\n",
++ id, ret);
++ goto err_node_put;
++ }
++
++ /*
++ * Register the pipe clock provided by phy.
++ * See function description to see details of this pipe clock.
++ */
++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
++ }
++ } else if (cfg->type == PHY_TYPE_DP) {
++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register DP clock source\n");
++ goto err_node_put;
++ }
++ }
++ id++;
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ if (!IS_ERR(phy_provider))
++ dev_info(dev, "Registered Qcom-QMP phy\n");
++ else
++ pm_runtime_disable(dev);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++ pm_runtime_disable(dev);
++ of_node_put(child);
++ return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++ .probe = qcom_qmp_phy_probe,
++ .driver = {
++ .name = "qcom-qmp-phy",
++ .pm = &qcom_qmp_phy_pm_ops,
++ .of_match_table = qcom_qmp_phy_of_match_table,
++ },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+--
+2.35.1
+
--- /dev/null
+From 8ead6de2dc7ebb10a2361ecc4891135ed1dc6d4c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:30 +0200
+Subject: phy: qcom-qmp-pcie: add pcs_misc sanity check
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit ecd5507e72ea03659dc2cc3e4393fbf8f4e2e02a ]
+
+Make sure that the (otherwise) optional pcs_misc IO region has been
+provided in case the configuration specifies a corresponding
+initialisation table to avoid crashing with malformed device trees.
+
+Note that the related debug message is now superfluous as the region is
+only used when the configuration has a pcs_misc table.
+
+Fixes: 421c9a0e9731 ("phy: qcom: qmp: Add SDM845 PCIe QMP PHY support")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-2-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+index 38fd0c5c3797..77f861bad8da 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -5966,8 +5966,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
+ qphy->pcs_misc = qphy->pcs + 0x400;
+
+- if (!qphy->pcs_misc)
+- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++ if (!qphy->pcs_misc) {
++ if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec)
++ return -EINVAL;
++ }
+
+ /*
+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
+--
+2.35.1
+
--- /dev/null
+From 439ba35ff86af2152e588957e923ac3c29e45c92 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:42 +0300
+Subject: phy: qcom-qmp-pcie: change symbol prefix to qcom_qmp_phy_pcie_msm8996
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 2abf0c8e61a900a77f2262f54596973db572cabb ]
+
+Change all symbol names to start with qcom_qmp_phy_pcie_msm8996_ rather
+than old qcom_qmp_phy_.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-10-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 158 +++++++++---------
+ 1 file changed, 79 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index 260e534b5607..1741a5675f9a 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -474,7 +474,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static void qcom_qmp_phy_configure_lane(void __iomem *base,
++static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base,
+ const unsigned int *regs,
+ const struct qmp_phy_init_tbl tbl[],
+ int num,
+@@ -497,15 +497,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
+ }
+ }
+
+-static void qcom_qmp_phy_configure(void __iomem *base,
++static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base,
+ const unsigned int *regs,
+ const struct qmp_phy_init_tbl tbl[],
+ int num)
+ {
+- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++ qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff);
+ }
+
+-static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -515,30 +515,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
+ int serdes_tbl_num = cfg->serdes_tbl_num;
+ int ret;
+
+- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+ if (cfg->serdes_tbl_sec)
+- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+ cfg->serdes_tbl_num_sec);
+
+ if (cfg->type == PHY_TYPE_DP) {
+ switch (dp_opts->link_rate) {
+ case 1620:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_rbr,
+ cfg->serdes_tbl_rbr_num);
+ break;
+ case 2700:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr,
+ cfg->serdes_tbl_hbr_num);
+ break;
+ case 5400:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr2,
+ cfg->serdes_tbl_hbr2_num);
+ break;
+ case 8100:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr3,
+ cfg->serdes_tbl_hbr3_num);
+ break;
+@@ -602,7 +602,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -697,7 +697,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+ return ret;
+ }
+
+-static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -732,7 +732,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_init(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -767,7 +767,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
+ return ret;
+ }
+
+- ret = qcom_qmp_phy_com_init(qphy);
++ ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
+ if (ret)
+ return ret;
+
+@@ -777,7 +777,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_power_on(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -790,7 +790,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ unsigned int mask, val, ready;
+ int ret;
+
+- qcom_qmp_phy_serdes_init(qphy);
++ qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
+
+ if (cfg->has_lane_rst) {
+ ret = reset_control_deassert(qphy->lane_rst);
+@@ -808,18 +808,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ }
+
+ /* Tx, Rx, and PCS configurations */
+- qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
+ if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
+ cfg->tx_tbl_num_sec, 1);
+
+ /* Configuration for other LANE for USB-DP combo PHY */
+ if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
+ if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
+ cfg->tx_tbl_sec,
+ cfg->tx_tbl_num_sec, 2);
+ }
+@@ -828,17 +828,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (cfg->type == PHY_TYPE_DP)
+ cfg->configure_dp_tx(qphy);
+
+- qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+ if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
+
+ if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
+ if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
+ cfg->rx_tbl_sec,
+ cfg->rx_tbl_num_sec, 2);
+ }
+@@ -847,9 +847,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (cfg->type == PHY_TYPE_DP) {
+ cfg->configure_dp_phy(qphy);
+ } else {
+- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ if (cfg->pcs_tbl_sec)
+- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+ cfg->pcs_tbl_num_sec);
+ }
+
+@@ -857,10 +857,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (ret)
+ goto err_disable_pipe_clk;
+
+- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
+ cfg->pcs_misc_tbl_num);
+ if (cfg->pcs_misc_tbl_sec)
+- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
+ cfg->pcs_misc_tbl_num_sec);
+
+ /*
+@@ -908,7 +908,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ return ret;
+ }
+
+-static int qcom_qmp_phy_power_off(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -939,7 +939,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_exit(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -947,37 +947,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
+ if (cfg->has_lane_rst)
+ reset_control_assert(qphy->lane_rst);
+
+- qcom_qmp_phy_com_exit(qphy);
++ qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
+
+ return 0;
+ }
+
+-static int qcom_qmp_phy_enable(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy)
+ {
+ int ret;
+
+- ret = qcom_qmp_phy_init(phy);
++ ret = qcom_qmp_phy_pcie_msm8996_init(phy);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_power_on(phy);
++ ret = qcom_qmp_phy_pcie_msm8996_power_on(phy);
+ if (ret)
+- qcom_qmp_phy_exit(phy);
++ qcom_qmp_phy_pcie_msm8996_exit(phy);
+
+ return ret;
+ }
+
+-static int qcom_qmp_phy_disable(struct phy *phy)
++static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy)
+ {
+ int ret;
+
+- ret = qcom_qmp_phy_power_off(phy);
++ ret = qcom_qmp_phy_pcie_msm8996_power_off(phy);
+ if (ret)
+ return ret;
+- return qcom_qmp_phy_exit(phy);
++ return qcom_qmp_phy_pcie_msm8996_exit(phy);
+ }
+
+-static int qcom_qmp_phy_set_mode(struct phy *phy,
++static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+@@ -987,7 +987,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
+ return 0;
+ }
+
+-static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
+ {
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+@@ -1016,7 +1016,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+ }
+
+-static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
+ {
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+@@ -1034,7 +1034,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ }
+
+-static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct qmp_phy *qphy = qmp->phys[0];
+@@ -1051,7 +1051,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
+ return 0;
+ }
+
+- qcom_qmp_phy_enable_autonomous_mode(qphy);
++ qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
+
+ clk_disable_unprepare(qphy->pipe_clk);
+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
+@@ -1059,7 +1059,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
+ return 0;
+ }
+
+-static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct qmp_phy *qphy = qmp->phys[0];
+@@ -1088,12 +1088,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
+ return ret;
+ }
+
+- qcom_qmp_phy_disable_autonomous_mode(qphy);
++ qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
+
+ return 0;
+ }
+
+-static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int num = cfg->num_vregs;
+@@ -1109,7 +1109,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
+ }
+
+-static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int i;
+@@ -1134,7 +1134,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
+ return 0;
+ }
+
+-static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int num = cfg->num_clks;
+@@ -1402,28 +1402,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+ }
+
+-static const struct phy_ops qcom_qmp_phy_gen_ops = {
+- .init = qcom_qmp_phy_enable,
+- .exit = qcom_qmp_phy_disable,
+- .set_mode = qcom_qmp_phy_set_mode,
++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
++ .init = qcom_qmp_phy_pcie_msm8996_enable,
++ .exit = qcom_qmp_phy_pcie_msm8996_disable,
++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+-static const struct phy_ops qcom_qmp_phy_dp_ops = {
+- .init = qcom_qmp_phy_init,
++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
++ .init = qcom_qmp_phy_pcie_msm8996_init,
+ .configure = qcom_qmp_dp_phy_configure,
+- .power_on = qcom_qmp_phy_power_on,
++ .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
+ .calibrate = qcom_qmp_dp_phy_calibrate,
+- .power_off = qcom_qmp_phy_power_off,
+- .exit = qcom_qmp_phy_exit,
+- .set_mode = qcom_qmp_phy_set_mode,
++ .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
++ .exit = qcom_qmp_phy_pcie_msm8996_exit,
++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+ static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
+- .power_on = qcom_qmp_phy_enable,
+- .power_off = qcom_qmp_phy_disable,
+- .set_mode = qcom_qmp_phy_set_mode,
++ .power_on = qcom_qmp_phy_pcie_msm8996_enable,
++ .power_off = qcom_qmp_phy_pcie_msm8996_disable,
++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+@@ -1433,7 +1433,7 @@ static void qcom_qmp_reset_control_put(void *data)
+ }
+
+ static
+-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id,
+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+@@ -1535,9 +1535,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
+ ops = &qcom_qmp_pcie_ufs_ops;
+ else if (cfg->type == PHY_TYPE_DP)
+- ops = &qcom_qmp_phy_dp_ops;
++ ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
+ else
+- ops = &qcom_qmp_phy_gen_ops;
++ ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
+
+ generic_phy = devm_phy_create(dev, np, ops);
+ if (IS_ERR(generic_phy)) {
+@@ -1555,21 +1555,21 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ return 0;
+ }
+
+-static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
+ {
+ .compatible = "qcom,msm8996-qmp-pcie-phy",
+ .data = &msm8996_pciephy_cfg,
+ },
+ { },
+ };
+-MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
+
+-static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
+- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
+- qcom_qmp_phy_runtime_resume, NULL)
++static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
++ qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
+ };
+
+-static int qcom_qmp_phy_probe(struct platform_device *pdev)
++static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ {
+ struct qcom_qmp *qmp;
+ struct device *dev = &pdev->dev;
+@@ -1623,15 +1623,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+
+ mutex_init(&qmp->phy_mutex);
+
+- ret = qcom_qmp_phy_clk_init(dev, cfg);
++ ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_reset_init(dev, cfg);
++ ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get regulator supplies: %d\n",
+@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ }
+
+ /* Create per-lane phy */
+- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
+ if (ret) {
+ dev_err(dev, "failed to create lane%d phy, %d\n",
+ id, ret);
+@@ -1710,16 +1710,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ return ret;
+ }
+
+-static struct platform_driver qcom_qmp_phy_driver = {
+- .probe = qcom_qmp_phy_probe,
++static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
++ .probe = qcom_qmp_phy_pcie_msm8996_probe,
+ .driver = {
+ .name = "qcom-qmp-msm8996-pcie-phy",
+- .pm = &qcom_qmp_phy_pm_ops,
+- .of_match_table = qcom_qmp_phy_of_match_table,
++ .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
++ .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
+ },
+ };
+
+-module_platform_driver(qcom_qmp_phy_driver);
++module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver);
+
+ MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
+ MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
+--
+2.35.1
+
--- /dev/null
+From 7a0854f6126f463e1c40c592ac067d18c997737d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:31 +0200
+Subject: phy: qcom-qmp-pcie: fix memleak on probe deferral
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 4be26f695ffa458b065b7942dbff9393bf0836ea ]
+
+Switch to using the device-managed of_iomap helper to avoid leaking
+memory on probe deferral and driver unbind.
+
+Note that this helper checks for already reserved regions and may fail
+if there are multiple devices claiming the same memory.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-3-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 34 ++++++++++++------------
+ 1 file changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+index 77f861bad8da..7073af57345b 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -5924,17 +5924,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
+ * For single lane PHYs: pcs_misc (optional) -> 3.
+ */
+- qphy->tx = of_iomap(np, 0);
+- if (!qphy->tx)
+- return -ENOMEM;
++ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
++ if (IS_ERR(qphy->tx))
++ return PTR_ERR(qphy->tx);
+
+- qphy->rx = of_iomap(np, 1);
+- if (!qphy->rx)
+- return -ENOMEM;
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (IS_ERR(qphy->rx))
++ return PTR_ERR(qphy->rx);
+
+- qphy->pcs = of_iomap(np, 2);
+- if (!qphy->pcs)
+- return -ENOMEM;
++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
++ if (IS_ERR(qphy->pcs))
++ return PTR_ERR(qphy->pcs);
+
+ /*
+ * If this is a dual-lane PHY, then there should be registers for the
+@@ -5943,9 +5943,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * offset from the first lane.
+ */
+ if (cfg->is_dual_lane_phy) {
+- qphy->tx2 = of_iomap(np, 3);
+- qphy->rx2 = of_iomap(np, 4);
+- if (!qphy->tx2 || !qphy->rx2) {
++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) {
+ dev_warn(dev,
+ "Underspecified device tree, falling back to legacy register regions\n");
+
+@@ -5955,20 +5955,20 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 5);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
+ }
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 3);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
+ }
+
+- if (!qphy->pcs_misc &&
++ if (IS_ERR(qphy->pcs_misc) &&
+ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
+ qphy->pcs_misc = qphy->pcs + 0x400;
+
+- if (!qphy->pcs_misc) {
++ if (IS_ERR(qphy->pcs_misc)) {
+ if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec)
+- return -EINVAL;
++ return PTR_ERR(qphy->pcs_misc);
+ }
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From ce93f20bba25f5c859d04491050b8a4f70968ad6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Sep 2022 20:25:14 +0300
+Subject: phy: qcom-qmp-pcie: fix resource mapping for SDM845 QHP PHY
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 0a40891b83f257b25a2b983758f72f6813f361cb ]
+
+On SDM845 one of PCIe PHYs (the QHP one) has the same region for TX and
+RX registers. Since the commit 4be26f695ffa ("phy: qcom-qmp-pcie: fix
+memleak on probe deferral") added checking that resources are not
+allocated beforehand, this PHY can not be probed anymore. Fix this by
+skipping the map of ->rx resource on the QHP PHY and assign it manually.
+
+Fixes: 4be26f695ffa ("phy: qcom-qmp-pcie: fix memleak on probe deferral")
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220926172514.880776-1-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+index 7073af57345b..154712af5410 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -5928,7 +5928,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ if (IS_ERR(qphy->tx))
+ return PTR_ERR(qphy->tx);
+
+- qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
++ qphy->rx = qphy->tx;
++ else
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
+ if (IS_ERR(qphy->rx))
+ return PTR_ERR(qphy->rx);
+
+--
+2.35.1
+
--- /dev/null
+From 2279b83eab0c0afe89c96f1609ddcfa54d5295e2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:54 +0300
+Subject: phy: qcom-qmp-pcie-msm8996: cleanup the driver
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 4856865b0dec88570edfbdf3e9c3b551923c0768 ]
+
+Remove the conditionals and options that are not used by the MSM8996
+PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is
+the case for this PHY.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-22-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 268 +++---------------
+ 1 file changed, 41 insertions(+), 227 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index 02e5ae7fa213..51da3a3a199e 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -266,22 +266,6 @@ struct qmp_phy_cfg {
+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
+ int pcs_misc_tbl_num_sec;
+
+- /* Init sequence for DP PHY block link rates */
+- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
+- int serdes_tbl_rbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
+- int serdes_tbl_hbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
+- int serdes_tbl_hbr2_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
+- int serdes_tbl_hbr3_num;
+-
+- /* DP PHY callbacks */
+- int (*configure_dp_phy)(struct qmp_phy *qphy);
+- void (*configure_dp_tx)(struct qmp_phy *qphy);
+- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
+- void (*dp_aux_init)(struct qmp_phy *qphy);
+-
+ /* clock ids to be requested */
+ const char * const *clk_list;
+ int num_clks;
+@@ -301,28 +285,11 @@ struct qmp_phy_cfg {
+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
+ unsigned int phy_status;
+
+- /* true, if PHY has a separate PHY_COM control block */
+- bool has_phy_com_ctrl;
+- /* true, if PHY has a reset for individual lanes */
+- bool has_lane_rst;
+ /* true, if PHY needs delay after POWER_DOWN */
+ bool has_pwrdn_delay;
+ /* power_down delay in usec */
+ int pwrdn_delay_min;
+ int pwrdn_delay_max;
+-
+- /* true, if PHY has a separate DP_COM control block */
+- bool has_phy_dp_com_ctrl;
+- /* true, if PHY has secondary tx/rx lanes to be configured */
+- bool is_dual_lane_phy;
+-
+- /* true, if PCS block has no separate SW_RESET register */
+- bool no_pcs_sw_reset;
+-};
+-
+-struct qmp_phy_combo_cfg {
+- const struct qmp_phy_cfg *usb_cfg;
+- const struct qmp_phy_cfg *dp_cfg;
+ };
+
+ /**
+@@ -334,17 +301,12 @@ struct qmp_phy_combo_cfg {
+ * @tx: iomapped memory space for lane's tx
+ * @rx: iomapped memory space for lane's rx
+ * @pcs: iomapped memory space for lane's pcs
+- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
+- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
+ * @pcs_misc: iomapped memory space for lane's pcs_misc
+ * @pipe_clk: pipe clock
+ * @index: lane index
+ * @qmp: QMP phy to which this lane belongs
+ * @lane_rst: lane's reset controller
+ * @mode: current PHY mode
+- * @dp_aux_cfg: Display port aux config
+- * @dp_opts: Display port optional config
+- * @dp_clks: Display port clocks
+ */
+ struct qmp_phy {
+ struct phy *phy;
+@@ -353,30 +315,18 @@ struct qmp_phy {
+ void __iomem *tx;
+ void __iomem *rx;
+ void __iomem *pcs;
+- void __iomem *tx2;
+- void __iomem *rx2;
+ void __iomem *pcs_misc;
+ struct clk *pipe_clk;
+ unsigned int index;
+ struct qcom_qmp *qmp;
+ struct reset_control *lane_rst;
+ enum phy_mode mode;
+- unsigned int dp_aux_cfg;
+- struct phy_configure_opts_dp dp_opts;
+- struct qmp_phy_dp_clks *dp_clks;
+-};
+-
+-struct qmp_phy_dp_clks {
+- struct qmp_phy *qphy;
+- struct clk_hw dp_link_hw;
+- struct clk_hw dp_pixel_hw;
+ };
+
+ /**
+ * struct qcom_qmp - structure holding QMP phy block attributes
+ *
+ * @dev: device
+- * @dp_com: iomapped memory space for phy's dp_com control block
+ *
+ * @clks: array of clocks required by phy
+ * @resets: array of resets required by phy
+@@ -385,11 +335,9 @@ struct qmp_phy_dp_clks {
+ * @phys: array of per-lane phy descriptors
+ * @phy_mutex: mutex lock for PHY common block initialization
+ * @init_count: phy common block initialization count
+- * @ufs_reset: optional UFS PHY reset handle
+ */
+ struct qcom_qmp {
+ struct device *dev;
+- void __iomem *dp_com;
+
+ struct clk_bulk_data *clks;
+ struct reset_control **resets;
+@@ -399,8 +347,6 @@ struct qcom_qmp {
+
+ struct mutex phy_mutex;
+ int init_count;
+-
+- struct reset_control *ufs_reset;
+ };
+
+ static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
+@@ -467,8 +413,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
+ .mask_com_pcs_ready = PCS_READY,
+ .phy_status = PHYSTATUS,
+
+- .has_phy_com_ctrl = true,
+- .has_lane_rst = true,
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+@@ -512,6 +456,8 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ void __iomem *serdes = qphy->serdes;
+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
+ int serdes_tbl_num = cfg->serdes_tbl_num;
++ void __iomem *status;
++ unsigned int mask, val;
+ int ret;
+
+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+@@ -519,24 +465,20 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+ cfg->serdes_tbl_num_sec);
+
+- if (cfg->has_phy_com_ctrl) {
+- void __iomem *status;
+- unsigned int mask, val;
+
+- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
+- SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
+
+- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
+- mask = cfg->mask_com_pcs_ready;
++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++ mask = cfg->mask_com_pcs_ready;
+
+- ret = readl_poll_timeout(status, val, (val & mask), 10,
+- PHY_INIT_COMPLETE_TIMEOUT);
+- if (ret) {
+- dev_err(qmp->dev,
+- "phy common block init timed-out\n");
+- return ret;
+- }
++ ret = readl_poll_timeout(status, val, (val & mask), 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev,
++ "phy common block init timed-out\n");
++ return ret;
+ }
+
+ return 0;
+@@ -547,8 +489,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
+- void __iomem *pcs = qphy->pcs;
+- void __iomem *dp_com = qmp->dp_com;
+ int ret, i;
+
+ mutex_lock(&qmp->phy_mutex);
+@@ -586,41 +526,8 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
+ if (ret)
+ goto err_assert_reset;
+
+- if (cfg->has_phy_dp_com_ctrl) {
+- qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
+- SW_PWRDN);
+- /* override hardware control for reset of qmp phy */
+- qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
+- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
+- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
+-
+- /* Default type-c orientation, i.e CC1 */
+- qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
+-
+- qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
+- USB3_MODE | DP_MODE);
+-
+- /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
+- qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
+- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
+- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
+-
+- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
+- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
+- }
+-
+- if (cfg->has_phy_com_ctrl) {
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
+- SW_PWRDN);
+- } else {
+- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
+- qphy_setbits(pcs,
+- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+- cfg->pwrdn_ctrl);
+- else
+- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+- cfg->pwrdn_ctrl);
+- }
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
+
+ mutex_unlock(&qmp->phy_mutex);
+
+@@ -650,15 +557,12 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
+ return 0;
+ }
+
+- reset_control_assert(qmp->ufs_reset);
+- if (cfg->has_phy_com_ctrl) {
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
+- SERDES_START | PCS_START);
+- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
+- SW_RESET);
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
+- SW_PWRDN);
+- }
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++ SERDES_START | PCS_START);
++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++ SW_RESET);
++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++ SW_PWRDN);
+
+ while (--i >= 0)
+ reset_control_assert(qmp->resets[i]);
+@@ -676,37 +580,9 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+ int ret;
+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
+
+- if (cfg->no_pcs_sw_reset) {
+- /*
+- * Get UFS reset, which is delayed until now to avoid a
+- * circular dependency where UFS needs its PHY, but the PHY
+- * needs this UFS reset.
+- */
+- if (!qmp->ufs_reset) {
+- qmp->ufs_reset =
+- devm_reset_control_get_exclusive(qmp->dev,
+- "ufsphy");
+-
+- if (IS_ERR(qmp->ufs_reset)) {
+- ret = PTR_ERR(qmp->ufs_reset);
+- dev_err(qmp->dev,
+- "failed to get UFS reset: %d\n",
+- ret);
+-
+- qmp->ufs_reset = NULL;
+- return ret;
+- }
+- }
+-
+- ret = reset_control_assert(qmp->ufs_reset);
+- if (ret)
+- return ret;
+- }
+-
+ ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
+ if (ret)
+ return ret;
+@@ -729,13 +605,11 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+
+ qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
+
+- if (cfg->has_lane_rst) {
+- ret = reset_control_deassert(qphy->lane_rst);
+- if (ret) {
+- dev_err(qmp->dev, "lane%d reset deassert failed\n",
+- qphy->index);
+- return ret;
+- }
++ ret = reset_control_deassert(qphy->lane_rst);
++ if (ret) {
++ dev_err(qmp->dev, "lane%d reset deassert failed\n",
++ qphy->index);
++ return ret;
+ }
+
+ ret = clk_prepare_enable(qphy->pipe_clk);
+@@ -751,40 +625,17 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
+ cfg->tx_tbl_num_sec, 1);
+
+- /* Configuration for other LANE for USB-DP combo PHY */
+- if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
+- cfg->tx_tbl, cfg->tx_tbl_num, 2);
+- if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
+- cfg->tx_tbl_sec,
+- cfg->tx_tbl_num_sec, 2);
+- }
+-
+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+ if (cfg->rx_tbl_sec)
+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
+
+- if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
+- cfg->rx_tbl, cfg->rx_tbl_num, 2);
+- if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
+- cfg->rx_tbl_sec,
+- cfg->rx_tbl_num_sec, 2);
+- }
+-
+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ if (cfg->pcs_tbl_sec)
+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+ cfg->pcs_tbl_num_sec);
+
+- ret = reset_control_deassert(qmp->ufs_reset);
+- if (ret)
+- goto err_disable_pipe_clk;
+-
+ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
+ cfg->pcs_misc_tbl_num);
+ if (cfg->pcs_misc_tbl_sec)
+@@ -801,8 +652,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
+
+ /* Pull PHY out of reset state */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
+ /* start SerDes and Phy-Coding-Sublayer */
+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+@@ -822,8 +673,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ err_disable_pipe_clk:
+ clk_disable_unprepare(qphy->pipe_clk);
+ err_reset_lane:
+- if (cfg->has_lane_rst)
+- reset_control_assert(qphy->lane_rst);
++ reset_control_assert(qphy->lane_rst);
+
+ return ret;
+ }
+@@ -836,8 +686,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
+ clk_disable_unprepare(qphy->pipe_clk);
+
+ /* PHY reset */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
+ /* stop SerDes and Phy-Coding-Sublayer */
+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+@@ -857,10 +706,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
+ static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+
+- if (cfg->has_lane_rst)
+- reset_control_assert(qphy->lane_rst);
++ reset_control_assert(qphy->lane_rst);
+
+ qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
+
+@@ -1065,31 +912,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
+ if (!qphy->pcs)
+ return -ENOMEM;
+
+- /*
+- * If this is a dual-lane PHY, then there should be registers for the
+- * second lane. Some old device trees did not specify this, so fall
+- * back to old legacy behavior of assuming they can be reached at an
+- * offset from the first lane.
+- */
+- if (cfg->is_dual_lane_phy) {
+- qphy->tx2 = of_iomap(np, 3);
+- qphy->rx2 = of_iomap(np, 4);
+- if (!qphy->tx2 || !qphy->rx2) {
+- dev_warn(dev,
+- "Underspecified device tree, falling back to legacy register regions\n");
+-
+- /* In the old version, pcs_misc is at index 3. */
+- qphy->pcs_misc = qphy->tx2;
+- qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
+- qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
+-
+- } else {
+- qphy->pcs_misc = of_iomap(np, 5);
+- }
+-
+- } else {
+- qphy->pcs_misc = of_iomap(np, 3);
+- }
++ qphy->pcs_misc = of_iomap(np, 3);
+
+ if (!qphy->pcs_misc)
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+@@ -1117,18 +940,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
+ }
+
+ /* Get lane reset, if any */
+- if (cfg->has_lane_rst) {
+- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
+- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
+- if (IS_ERR(qphy->lane_rst)) {
+- dev_err(dev, "failed to get lane%d reset\n", id);
+- return PTR_ERR(qphy->lane_rst);
+- }
+- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
+- qphy->lane_rst);
+- if (ret)
+- return ret;
++ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++ if (IS_ERR(qphy->lane_rst)) {
++ dev_err(dev, "failed to get lane%d reset\n", id);
++ return PTR_ERR(qphy->lane_rst);
+ }
++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++ qphy->lane_rst);
++ if (ret)
++ return ret;
+
+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
+ if (IS_ERR(generic_phy)) {
+@@ -1183,13 +1004,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ if (IS_ERR(serdes))
+ return PTR_ERR(serdes);
+
+- /* per PHY dp_com; if PHY has dp_com control block */
+- if (cfg->has_phy_dp_com_ctrl) {
+- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
+- if (IS_ERR(qmp->dp_com))
+- return PTR_ERR(qmp->dp_com);
+- }
+-
+ expected_phys = cfg->nlanes;
+
+ mutex_init(&qmp->phy_mutex);
+--
+2.35.1
+
--- /dev/null
+From 98d520bf8babb35032781cb6a3b1096c53ea857f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:36 +0300
+Subject: phy: qcom-qmp-pcie-msm8996: drop all compatibles except
+ msm8996-pcie-phy
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 9fc8fa59ef1038714a9b86259f515373a7380169 ]
+
+Drop support for all compatibles from the new qmp-pcie driver except the
+qcom,msm8996-qmp-pcie-phy. This PHY differs from the rest of PCIe PHYs,
+so it warrants a separate device driver.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-4-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5024 +----------------
+ 1 file changed, 200 insertions(+), 4824 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index c7309e981bfb..260e534b5607 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -141,18 +141,6 @@ enum qphy_reg_layout {
+ QPHY_LAYOUT_SIZE
+ };
+
+-static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x168,
+-};
+-
+-static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+-};
+-
+ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_COM_SW_RESET] = 0x400,
+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
+@@ -169,176 +157,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_PCS_STATUS] = 0x174,
+ };
+
+-static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_FLL_CNTRL1] = 0xc0,
+- [QPHY_FLL_CNTRL2] = 0xc4,
+- [QPHY_FLL_CNT_VAL_L] = 0xc8,
+- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
+- [QPHY_FLL_MAN_CODE] = 0xd0,
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x17c,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
+-};
+-
+-static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x174,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
+-};
+-
+-static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x174,
+-};
+-
+-static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x2ac,
+-};
+-
+-static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
+-};
+-
+-static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
+-};
+-
+-static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
+-};
+-
+-static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
+- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
+- [QPHY_PCS_STATUS] = 0x174,
+- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
+-};
+-
+-static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x160,
+-};
+-
+-static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x168,
+-};
+-
+-static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+-};
+-
+-static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
+- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
+- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+- /* PLL and Loop filter settings */
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- /* SSC settings */
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+-};
+-
+ static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+@@ -417,4078 +235,243 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
+ };
+
+-static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
+- /* PLL and Loop filter settings */
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- /* SSC settings */
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
+- /* FLL settings */
+- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
+- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
+- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
+- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
+-
+- /* Lock Det settings */
+- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
+- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
+- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
+- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
+- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
+- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
+- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++struct qmp_phy;
+
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++ /* phy-type - PCIE/UFS/USB */
++ unsigned int type;
++ /* number of lanes provided by phy */
++ int nlanes;
+
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
+-};
++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++ const struct qmp_phy_init_tbl *serdes_tbl;
++ int serdes_tbl_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_sec;
++ int serdes_tbl_num_sec;
++ const struct qmp_phy_init_tbl *tx_tbl;
++ int tx_tbl_num;
++ const struct qmp_phy_init_tbl *tx_tbl_sec;
++ int tx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *rx_tbl;
++ int rx_tbl_num;
++ const struct qmp_phy_init_tbl *rx_tbl_sec;
++ int rx_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_tbl;
++ int pcs_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_tbl_sec;
++ int pcs_tbl_num_sec;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl;
++ int pcs_misc_tbl_num;
++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++ int pcs_misc_tbl_num_sec;
+
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+-};
++ /* Init sequence for DP PHY block link rates */
++ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++ int serdes_tbl_rbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++ int serdes_tbl_hbr_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++ int serdes_tbl_hbr2_num;
++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++ int serdes_tbl_hbr3_num;
+
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
+-};
++ /* DP PHY callbacks */
++ int (*configure_dp_phy)(struct qmp_phy *qphy);
++ void (*configure_dp_tx)(struct qmp_phy *qphy);
++ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++ void (*dp_aux_init)(struct qmp_phy *qphy);
+
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
+-};
++ /* clock ids to be requested */
++ const char * const *clk_list;
++ int num_clks;
++ /* resets to be requested */
++ const char * const *reset_list;
++ int num_resets;
++ /* regulators to be requested */
++ const char * const *vreg_list;
++ int num_vregs;
+
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
+-};
++ /* array of registers with different offsets */
++ const unsigned int *regs;
+
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
+-};
++ unsigned int start_ctrl;
++ unsigned int pwrdn_ctrl;
++ unsigned int mask_com_pcs_ready;
++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++ unsigned int phy_status;
+
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
+-};
++ /* true, if PHY has a separate PHY_COM control block */
++ bool has_phy_com_ctrl;
++ /* true, if PHY has a reset for individual lanes */
++ bool has_lane_rst;
++ /* true, if PHY needs delay after POWER_DOWN */
++ bool has_pwrdn_delay;
++ /* power_down delay in usec */
++ int pwrdn_delay_min;
++ int pwrdn_delay_max;
+
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+-};
++ /* true, if PHY has a separate DP_COM control block */
++ bool has_phy_dp_com_ctrl;
++ /* true, if PHY has secondary tx/rx lanes to be configured */
++ bool is_dual_lane_phy;
+
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++ /* true, if PCS block has no separate SW_RESET register */
++ bool no_pcs_sw_reset;
+ };
+
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++struct qmp_phy_combo_cfg {
++ const struct qmp_phy_cfg *usb_cfg;
++ const struct qmp_phy_cfg *dp_cfg;
+ };
+
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
+- /* FLL settings */
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+-
+- /* Lock Det settings */
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
+- /* FLL settings */
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+-
+- /* Lock Det settings */
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
+- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
+- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+-
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
+- /* Lock Det settings */
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+-
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
+- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+-};
+-
+-static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
+-};
+-
+-static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
+-};
+-
+-/* Register names should be validated, they might be different for this PHY */
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
+-};
+-
+-struct qmp_phy;
+-
+-/* struct qmp_phy_cfg - per-PHY initialization config */
+-struct qmp_phy_cfg {
+- /* phy-type - PCIE/UFS/USB */
+- unsigned int type;
+- /* number of lanes provided by phy */
+- int nlanes;
+-
+- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
+- const struct qmp_phy_init_tbl *serdes_tbl;
+- int serdes_tbl_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_sec;
+- int serdes_tbl_num_sec;
+- const struct qmp_phy_init_tbl *tx_tbl;
+- int tx_tbl_num;
+- const struct qmp_phy_init_tbl *tx_tbl_sec;
+- int tx_tbl_num_sec;
+- const struct qmp_phy_init_tbl *rx_tbl;
+- int rx_tbl_num;
+- const struct qmp_phy_init_tbl *rx_tbl_sec;
+- int rx_tbl_num_sec;
+- const struct qmp_phy_init_tbl *pcs_tbl;
+- int pcs_tbl_num;
+- const struct qmp_phy_init_tbl *pcs_tbl_sec;
+- int pcs_tbl_num_sec;
+- const struct qmp_phy_init_tbl *pcs_misc_tbl;
+- int pcs_misc_tbl_num;
+- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
+- int pcs_misc_tbl_num_sec;
+-
+- /* Init sequence for DP PHY block link rates */
+- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
+- int serdes_tbl_rbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
+- int serdes_tbl_hbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
+- int serdes_tbl_hbr2_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
+- int serdes_tbl_hbr3_num;
+-
+- /* DP PHY callbacks */
+- int (*configure_dp_phy)(struct qmp_phy *qphy);
+- void (*configure_dp_tx)(struct qmp_phy *qphy);
+- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
+- void (*dp_aux_init)(struct qmp_phy *qphy);
+-
+- /* clock ids to be requested */
+- const char * const *clk_list;
+- int num_clks;
+- /* resets to be requested */
+- const char * const *reset_list;
+- int num_resets;
+- /* regulators to be requested */
+- const char * const *vreg_list;
+- int num_vregs;
+-
+- /* array of registers with different offsets */
+- const unsigned int *regs;
+-
+- unsigned int start_ctrl;
+- unsigned int pwrdn_ctrl;
+- unsigned int mask_com_pcs_ready;
+- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
+- unsigned int phy_status;
+-
+- /* true, if PHY has a separate PHY_COM control block */
+- bool has_phy_com_ctrl;
+- /* true, if PHY has a reset for individual lanes */
+- bool has_lane_rst;
+- /* true, if PHY needs delay after POWER_DOWN */
+- bool has_pwrdn_delay;
+- /* power_down delay in usec */
+- int pwrdn_delay_min;
+- int pwrdn_delay_max;
+-
+- /* true, if PHY has a separate DP_COM control block */
+- bool has_phy_dp_com_ctrl;
+- /* true, if PHY has secondary tx/rx lanes to be configured */
+- bool is_dual_lane_phy;
+-
+- /* true, if PCS block has no separate SW_RESET register */
+- bool no_pcs_sw_reset;
+-};
+-
+-struct qmp_phy_combo_cfg {
+- const struct qmp_phy_cfg *usb_cfg;
+- const struct qmp_phy_cfg *dp_cfg;
+-};
+-
+-/**
+- * struct qmp_phy - per-lane phy descriptor
+- *
+- * @phy: generic phy
+- * @cfg: phy specific configuration
+- * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
+- * @tx: iomapped memory space for lane's tx
+- * @rx: iomapped memory space for lane's rx
+- * @pcs: iomapped memory space for lane's pcs
+- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
+- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
+- * @pcs_misc: iomapped memory space for lane's pcs_misc
+- * @pipe_clk: pipe clock
+- * @index: lane index
+- * @qmp: QMP phy to which this lane belongs
+- * @lane_rst: lane's reset controller
+- * @mode: current PHY mode
+- * @dp_aux_cfg: Display port aux config
+- * @dp_opts: Display port optional config
+- * @dp_clks: Display port clocks
+- */
+-struct qmp_phy {
+- struct phy *phy;
+- const struct qmp_phy_cfg *cfg;
+- void __iomem *serdes;
+- void __iomem *tx;
+- void __iomem *rx;
+- void __iomem *pcs;
+- void __iomem *tx2;
+- void __iomem *rx2;
+- void __iomem *pcs_misc;
+- struct clk *pipe_clk;
+- unsigned int index;
+- struct qcom_qmp *qmp;
+- struct reset_control *lane_rst;
+- enum phy_mode mode;
+- unsigned int dp_aux_cfg;
+- struct phy_configure_opts_dp dp_opts;
+- struct qmp_phy_dp_clks *dp_clks;
+-};
+-
+-struct qmp_phy_dp_clks {
+- struct qmp_phy *qphy;
+- struct clk_hw dp_link_hw;
+- struct clk_hw dp_pixel_hw;
+-};
+-
+-/**
+- * struct qcom_qmp - structure holding QMP phy block attributes
+- *
+- * @dev: device
+- * @dp_com: iomapped memory space for phy's dp_com control block
+- *
+- * @clks: array of clocks required by phy
+- * @resets: array of resets required by phy
+- * @vregs: regulator supplies bulk data
+- *
+- * @phys: array of per-lane phy descriptors
+- * @phy_mutex: mutex lock for PHY common block initialization
+- * @init_count: phy common block initialization count
+- * @ufs_reset: optional UFS PHY reset handle
+- */
+-struct qcom_qmp {
+- struct device *dev;
+- void __iomem *dp_com;
+-
+- struct clk_bulk_data *clks;
+- struct reset_control **resets;
+- struct regulator_bulk_data *vregs;
+-
+- struct qmp_phy **phys;
+-
+- struct mutex phy_mutex;
+- int init_count;
+-
+- struct reset_control *ufs_reset;
+-};
+-
+-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
+-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
+-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
+-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
+-
+-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
+-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
+-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
+-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
+-
+-static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
+-{
+- u32 reg;
+-
+- reg = readl(base + offset);
+- reg |= val;
+- writel(reg, base + offset);
+-
+- /* ensure that above write is through */
+- readl(base + offset);
+-}
+-
+-static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
+-{
+- u32 reg;
+-
+- reg = readl(base + offset);
+- reg &= ~val;
+- writel(reg, base + offset);
+-
+- /* ensure that above write is through */
+- readl(base + offset);
+-}
+-
+-/* list of clocks required by phy */
+-static const char * const msm8996_phy_clk_l[] = {
+- "aux", "cfg_ahb", "ref",
+-};
+-
+-static const char * const msm8996_ufs_phy_clk_l[] = {
+- "ref",
+-};
+-
+-static const char * const qmp_v3_phy_clk_l[] = {
+- "aux", "cfg_ahb", "ref", "com_aux",
+-};
+-
+-static const char * const sdm845_pciephy_clk_l[] = {
+- "aux", "cfg_ahb", "ref", "refgen",
+-};
+-
+-static const char * const qmp_v4_phy_clk_l[] = {
+- "aux", "ref_clk_src", "ref", "com_aux",
+-};
+-
+-/* the primary usb3 phy on sm8250 doesn't have a ref clock */
+-static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
+- "aux", "ref_clk_src", "com_aux"
+-};
+-
+-static const char * const sm8450_ufs_phy_clk_l[] = {
+- "qref", "ref", "ref_aux",
+-};
+-
+-static const char * const sdm845_ufs_phy_clk_l[] = {
+- "ref", "ref_aux",
+-};
+-
+-/* usb3 phy on sdx55 doesn't have com_aux clock */
+-static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
+- "aux", "cfg_ahb", "ref"
+-};
+-
+-static const char * const qcm2290_usb3phy_clk_l[] = {
+- "cfg_ahb", "ref", "com_aux",
+-};
+-
+-/* list of resets */
+-static const char * const msm8996_pciephy_reset_l[] = {
+- "phy", "common", "cfg",
+-};
+-
+-static const char * const msm8996_usb3phy_reset_l[] = {
+- "phy", "common",
+-};
+-
+-static const char * const sc7180_usb3phy_reset_l[] = {
+- "phy",
+-};
+-
+-static const char * const qcm2290_usb3phy_reset_l[] = {
+- "phy_phy", "phy",
+-};
+-
+-static const char * const sdm845_pciephy_reset_l[] = {
+- "phy",
+-};
+-
+-/* list of regulators */
+-static const char * const qmp_phy_vreg_l[] = {
+- "vdda-phy", "vdda-pll",
+-};
+-
+-static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = ipq8074_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
+- .tx_tbl = msm8996_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
+- .rx_tbl = ipq8074_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
+- .pcs_tbl = ipq8074_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-};
+-
+-static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 3,
+-
+- .serdes_tbl = msm8996_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
+- .tx_tbl = msm8996_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
+- .rx_tbl = msm8996_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
+- .pcs_tbl = msm8996_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = msm8996_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .mask_com_pcs_ready = PCS_READY,
+- .phy_status = PHYSTATUS,
+-
+- .has_phy_com_ctrl = true,
+- .has_lane_rst = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg msm8996_ufs_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8996_ufs_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
+- .tx_tbl = msm8996_ufs_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
+- .rx_tbl = msm8996_ufs_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
+-
+- .clk_list = msm8996_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
+-
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+-
+- .regs = msm8996_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .no_pcs_sw_reset = true,
+-};
+-
+-static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8996_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
+- .tx_tbl = msm8996_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
+- .rx_tbl = msm8996_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
+- .pcs_tbl = msm8996_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-};
+-
+-static const char * const ipq8074_pciephy_clk_l[] = {
+- "aux", "cfg_ahb",
+-};
+-/* list of resets */
+-static const char * const ipq8074_pciephy_reset_l[] = {
+- "phy", "common",
+-};
+-
+-static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = ipq8074_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
+- .tx_tbl = ipq8074_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
+- .rx_tbl = ipq8074_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
+- .pcs_tbl = ipq8074_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
+- .clk_list = ipq8074_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = NULL,
+- .num_vregs = 0,
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_phy_com_ctrl = false,
+- .has_lane_rst = false,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = ipq6018_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
+- .tx_tbl = ipq6018_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
+- .rx_tbl = ipq6018_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
+- .pcs_tbl = ipq6018_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+- .clk_list = ipq8074_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = NULL,
+- .num_vregs = 0,
+- .regs = ipq_pciephy_gen3_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+-
+- .has_phy_com_ctrl = false,
+- .has_lane_rst = false,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
+- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
+- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
+- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_qmp_pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
+- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
+- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
+- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_qhp_pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
+- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
+- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
+- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
+- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
+- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
+- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
+- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
+- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
+- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
+- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+- .tx_tbl = qmp_v3_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+- .rx_tbl = qmp_v3_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
+- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+- .tx_tbl = qmp_v3_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+- .rx_tbl = qmp_v3_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
+- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = sc7180_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v3_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
+- .tx_tbl = qmp_v3_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = sc7180_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
+- .usb_cfg = &sc7180_usb3phy_cfg,
+- .dp_cfg = &sc7180_dpphy_cfg,
+-};
+-
+-static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
+- .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
+- .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
+- .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
+- .tx_tbl = sdm845_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
+- .rx_tbl = sdm845_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
+- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+- .no_pcs_sw_reset = true,
+-};
+-
+-static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
+- .tx_tbl = sm6115_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
+- .rx_tbl = sm6115_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
+- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm6115_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+-
+- .is_dual_lane_phy = false,
+- .no_pcs_sw_reset = true,
+-};
+-
+-static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8998_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
+- .tx_tbl = msm8998_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
+- .rx_tbl = msm8998_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
+- .pcs_tbl = msm8998_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-};
+-
+-static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8998_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
+- .tx_tbl = msm8998_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
+- .rx_tbl = msm8998_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
+- .pcs_tbl = msm8998_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
+- .tx_tbl = sm8150_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
+- .rx_tbl = sm8150_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
+- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
+- .tx_tbl = sm8150_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
+- .rx_tbl = sm8150_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
+- .pcs_tbl = sm8150_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
+- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
+- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
+- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v4_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
+- .tx_tbl = qmp_v4_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = sc7180_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
+- .usb_cfg = &sm8150_usb3phy_cfg,
+- .dp_cfg = &sc8180x_dpphy_cfg,
+-};
+-
+-static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+- .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
+- .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
+- .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3_uniphy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
+- .tx_tbl = sm8250_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
+- .rx_tbl = sm8250_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
+- .pcs_tbl = sm8250_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
+- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+- .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
+- .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
+- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3_uniphy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v4_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
+- .tx_tbl = qmp_v4_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
+- .usb_cfg = &sm8250_usb3phy_cfg,
+- .dp_cfg = &sm8250_dpphy_cfg,
+-};
+-
+-static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+- .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
+- .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
+- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3_uniphy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
+- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
+- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
+- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS_4_20,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++ struct phy *phy;
++ const struct qmp_phy_cfg *cfg;
++ void __iomem *serdes;
++ void __iomem *tx;
++ void __iomem *rx;
++ void __iomem *pcs;
++ void __iomem *tx2;
++ void __iomem *rx2;
++ void __iomem *pcs_misc;
++ struct clk *pipe_clk;
++ unsigned int index;
++ struct qcom_qmp *qmp;
++ struct reset_control *lane_rst;
++ enum phy_mode mode;
++ unsigned int dp_aux_cfg;
++ struct phy_configure_opts_dp dp_opts;
++ struct qmp_phy_dp_clks *dp_clks;
+ };
+
+-static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+- .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
+- .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
+- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8350_usb3_uniphy_regs_layout,
++struct qmp_phy_dp_clks {
++ struct qmp_phy *qphy;
++ struct clk_hw dp_link_hw;
++ struct clk_hw dp_pixel_hw;
++};
+
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++ struct device *dev;
++ void __iomem *dp_com;
+
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
++ struct clk_bulk_data *clks;
++ struct reset_control **resets;
++ struct regulator_bulk_data *vregs;
+
+-static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+- .tx_tbl = sm8350_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+- .rx_tbl = sm8350_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
++ struct qmp_phy **phys;
+
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
++ struct mutex phy_mutex;
++ int init_count;
+
+- .is_dual_lane_phy = true,
++ struct reset_control *ufs_reset;
+ };
+
+-static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
+- .tx_tbl = sm8350_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
+- .rx_tbl = sm8350_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
+- .pcs_tbl = sm8350_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
+- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3phy_regs_layout,
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
+
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
++ reg = readl(base + offset);
++ reg |= val;
++ writel(reg, base + offset);
+
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++ /* ensure that above write is through */
++ readl(base + offset);
++}
+
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-};
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++ u32 reg;
+
+-static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+- .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
+- .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
+- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8350_usb3_uniphy_regs_layout,
++ reg = readl(base + offset);
++ reg &= ~val;
++ writel(reg, base + offset);
+
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
++ /* ensure that above write is through */
++ readl(base + offset);
++}
+
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++ "aux", "cfg_ahb", "ref",
+ };
+
+-static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+- .tx_tbl = sm8350_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+- .rx_tbl = sm8350_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+- .clk_list = sm8450_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++ "phy", "common", "cfg",
+ };
+
+-static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
+- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
+- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
+- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++ "vdda-phy", "vdda-pll",
+ };
+
+-static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
+- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
+- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
+- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS_4_20,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++ .type = PHY_TYPE_PCIE,
++ .nlanes = 3,
+
+-static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
+- .type = PHY_TYPE_USB3,
+- .nlanes = 1,
+-
+- .serdes_tbl = qcm2290_usb3_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
+- .tx_tbl = qcm2290_usb3_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
+- .rx_tbl = qcm2290_usb3_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
+- .pcs_tbl = qcm2290_usb3_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
+- .clk_list = qcm2290_usb3phy_clk_l,
+- .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
+- .reset_list = qcm2290_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++ .serdes_tbl = msm8996_pcie_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++ .tx_tbl = msm8996_pcie_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++ .rx_tbl = msm8996_pcie_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++ .pcs_tbl = msm8996_pcie_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_pciephy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qcm2290_usb3phy_regs_layout,
++ .regs = pciephy_regs_layout,
+
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
++ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
++ .mask_com_pcs_ready = PCS_READY,
+ .phy_status = PHYSTATUS,
+
+- .is_dual_lane_phy = true,
++ .has_phy_com_ctrl = true,
++ .has_lane_rst = true,
++ .has_pwrdn_delay = true,
++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+ static void qcom_qmp_phy_configure_lane(void __iomem *base,
+@@ -4589,457 +572,10 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
+-{
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- /* Turn on BIAS current for PHY/PLL */
+- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
+- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
+- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
+- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
+- DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(QSERDES_V3_COM_BIAS_EN |
+- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
+- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
+- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
+- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
+- qphy->dp_aux_cfg = 0;
+-
+- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
+- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
+- PHY_AUX_REQ_ERR_MASK,
+- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
+-}
+-
+-static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
+- { 0x00, 0x0c, 0x15, 0x1a },
+- { 0x02, 0x0e, 0x16, 0xff },
+- { 0x02, 0x11, 0xff, 0xff },
+- { 0x04, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
+- { 0x02, 0x12, 0x16, 0x1a },
+- { 0x09, 0x19, 0x1f, 0xff },
+- { 0x10, 0x1f, 0xff, 0xff },
+- { 0x1f, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
+- { 0x00, 0x0c, 0x14, 0x19 },
+- { 0x00, 0x0b, 0x12, 0xff },
+- { 0x00, 0x0b, 0xff, 0xff },
+- { 0x04, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
+- { 0x08, 0x0f, 0x16, 0x1f },
+- { 0x11, 0x1e, 0x1f, 0xff },
+- { 0x19, 0x1f, 0xff, 0xff },
+- { 0x1f, 0xff, 0xff, 0xff }
+-};
+-
+-static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
+- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- unsigned int v_level = 0, p_level = 0;
+- u8 voltage_swing_cfg, pre_emphasis_cfg;
+- int i;
+-
+- for (i = 0; i < dp_opts->lanes; i++) {
+- v_level = max(v_level, dp_opts->voltage[i]);
+- p_level = max(p_level, dp_opts->pre[i]);
+- }
+-
+- if (dp_opts->link_rate <= 2700) {
+- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
+- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
+- } else {
+- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
+- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
+- }
+-
+- /* TODO: Move check to config check */
+- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
+- return -EINVAL;
+-
+- /* Enable MUX to use Cursor values from these registers */
+- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
+- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
+-
+- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
+- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
+- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
+- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
+-
+- return 0;
+-}
+-
+-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 bias_en, drvr_en;
+-
+- if (qcom_qmp_phy_configure_dp_swing(qphy,
+- QSERDES_V3_TX_TX_DRV_LVL,
+- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
+- return;
+-
+- if (dp_opts->lanes == 1) {
+- bias_en = 0x3e;
+- drvr_en = 0x13;
+- } else {
+- bias_en = 0x3f;
+- drvr_en = 0x10;
+- }
+-
+- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+-}
+-
+-static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
+-{
+- u32 val;
+- bool reverse = false;
+-
+- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
+-
+- /*
+- * TODO: Assume orientation is CC1 for now and two lanes, need to
+- * use type-c connector to understand orientation and lanes.
+- *
+- * Otherwise val changes to be like below if this code understood
+- * the orientation of the type-c cable.
+- *
+- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
+- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
+- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
+- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+- * if (orientation == ORIENTATION_CC2)
+- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+- */
+- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
+-
+- return reverse;
+-}
+-
+-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 phy_vco_div, status;
+- unsigned long pixel_freq;
+-
+- qcom_qmp_phy_configure_dp_mode(qphy);
+-
+- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
+- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- phy_vco_div = 0x1;
+- pixel_freq = 1620000000UL / 2;
+- break;
+- case 2700:
+- phy_vco_div = 0x1;
+- pixel_freq = 2700000000UL / 2;
+- break;
+- case 5400:
+- phy_vco_div = 0x2;
+- pixel_freq = 5400000000UL / 4;
+- break;
+- case 8100:
+- phy_vco_div = 0x0;
+- pixel_freq = 8100000000UL / 6;
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
+-
+- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
+- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
+-
+- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
+- udelay(2000);
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000);
+-}
+-
+-/*
+- * We need to calibrate the aux setting here as many times
+- * as the caller tries
+- */
+-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
+-{
+- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
+- u8 val;
+-
+- qphy->dp_aux_cfg++;
+- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
+- val = cfg1_settings[qphy->dp_aux_cfg];
+-
+- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+-
+- return 0;
+-}
+-
+-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
+-{
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- /* Turn on BIAS current for PHY/PLL */
+- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
+- qphy->dp_aux_cfg = 0;
+-
+- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
+- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
+- PHY_AUX_REQ_ERR_MASK,
+- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
+-}
+-
+-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
+-{
+- /* Program default values before writing proper values */
+- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
+- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
+-
+- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-
+- qcom_qmp_phy_configure_dp_swing(qphy,
+- QSERDES_V4_TX_TX_DRV_LVL,
+- QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-}
+-
+-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 phy_vco_div, status;
+- unsigned long pixel_freq;
+- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
+- bool reverse;
+-
+- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
+-
+- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
+-
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+-
+- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
+- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- phy_vco_div = 0x1;
+- pixel_freq = 1620000000UL / 2;
+- break;
+- case 2700:
+- phy_vco_div = 0x1;
+- pixel_freq = 2700000000UL / 2;
+- break;
+- case 5400:
+- phy_vco_div = 0x2;
+- pixel_freq = 5400000000UL / 4;
+- break;
+- case 8100:
+- phy_vco_div = 0x0;
+- pixel_freq = 8100000000UL / 6;
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
+-
+- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
+- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
+-
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- /*
+- * At least for 7nm DP PHY this has to be done after enabling link
+- * clock.
+- */
+-
+- if (dp_opts->lanes == 1) {
+- bias0_en = reverse ? 0x3e : 0x15;
+- bias1_en = reverse ? 0x15 : 0x3e;
+- drvr0_en = reverse ? 0x13 : 0x10;
+- drvr1_en = reverse ? 0x10 : 0x13;
+- } else if (dp_opts->lanes == 2) {
+- bias0_en = reverse ? 0x3f : 0x15;
+- bias1_en = reverse ? 0x15 : 0x3f;
+- drvr0_en = 0x10;
+- drvr1_en = 0x10;
+- } else {
+- bias0_en = 0x3f;
+- bias1_en = 0x3f;
+- drvr0_en = 0x10;
+- drvr1_en = 0x10;
+- }
+-
+- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
+- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
+- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+-
+- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
+- udelay(2000);
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
+- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
+-
+- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
+- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
+-
+- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-
+- return 0;
+-}
+-
+ /*
+ * We need to calibrate the aux setting here as many times
+ * as the caller tries
+ */
+-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
+-{
+- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
+- u8 val;
+-
+- qphy->dp_aux_cfg++;
+- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
+- val = cfg1_settings[qphy->dp_aux_cfg];
+-
+- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+-
+- return 0;
+-}
+-
+ static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
+ {
+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
+@@ -6021,161 +1557,13 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+
+ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ {
+- .compatible = "qcom,ipq8074-qmp-usb3-phy",
+- .data = &ipq8074_usb3phy_cfg,
+- }, {
+ .compatible = "qcom,msm8996-qmp-pcie-phy",
+ .data = &msm8996_pciephy_cfg,
+- }, {
+- .compatible = "qcom,msm8996-qmp-ufs-phy",
+- .data = &msm8996_ufs_cfg,
+- }, {
+- .compatible = "qcom,msm8996-qmp-usb3-phy",
+- .data = &msm8996_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,msm8998-qmp-pcie-phy",
+- .data = &msm8998_pciephy_cfg,
+- }, {
+- .compatible = "qcom,msm8998-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,ipq8074-qmp-pcie-phy",
+- .data = &ipq8074_pciephy_cfg,
+- }, {
+- .compatible = "qcom,ipq6018-qmp-pcie-phy",
+- .data = &ipq6018_pciephy_cfg,
+- }, {
+- .compatible = "qcom,ipq6018-qmp-usb3-phy",
+- .data = &ipq8074_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sc7180-qmp-usb3-phy",
+- .data = &sc7180_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+- }, {
+- .compatible = "qcom,sc8180x-qmp-pcie-phy",
+- .data = &sc8180x_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sc8180x-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
+- .data = &sm8350_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sc8180x-qmp-usb3-phy",
+- .data = &sm8150_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+- }, {
+- .compatible = "qcom,sdm845-qhp-pcie-phy",
+- .data = &sdm845_qhp_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-pcie-phy",
+- .data = &sdm845_qmp_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-usb3-phy",
+- .data = &qmp_v3_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
+- .data = &qmp_v3_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,msm8998-qmp-usb3-phy",
+- .data = &msm8998_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm6115-qmp-ufs-phy",
+- .data = &sm6115_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm6350-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8150-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8150-qmp-usb3-phy",
+- .data = &sm8150_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
+- .data = &sm8150_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-usb3-phy",
+- .data = &sm8250_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+- }, {
+- .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
+- .data = &sm8250_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
+- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
+- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8350-qmp-ufs-phy",
+- .data = &sm8350_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
+- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdx55-qmp-pcie-phy",
+- .data = &sdx55_qmp_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
+- .data = &sdx55_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
+- .data = &sdx65_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8350-qmp-usb3-phy",
+- .data = &sm8350_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
+- .data = &sm8350_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
+- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
+- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-ufs-phy",
+- .data = &sm8450_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-usb3-phy",
+- .data = &sm8350_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,qcm2290-qmp-usb3-phy",
+- .data = &qcm2290_usb3phy_cfg,
+ },
+ { },
+ };
+ MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
+
+-static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
+- {
+- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+- .data = &sc7180_usb3dpphy_cfg,
+- },
+- {
+- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
+- .data = &sm8250_usb3dpphy_cfg,
+- },
+- {
+- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
+- .data = &sc8180x_usb3dpphy_cfg,
+- },
+- { }
+-};
+-
+ static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
+ qcom_qmp_phy_runtime_resume, NULL)
+@@ -6206,20 +1594,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+
+ /* Get the specific init parameters of QMP phy */
+ cfg = of_device_get_match_data(dev);
+- if (!cfg) {
+- const struct of_device_id *match;
+-
+- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
+- if (!match)
+- return -EINVAL;
+-
+- combo_cfg = match->data;
+- if (!combo_cfg)
+- return -EINVAL;
+-
+- usb_cfg = combo_cfg->usb_cfg;
+- cfg = usb_cfg; /* Setup clks and regulators */
+- }
++ if (!cfg)
++ return -EINVAL;
+
+ /* per PHY serdes; usually located at base address */
+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
+@@ -6337,7 +1713,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ static struct platform_driver qcom_qmp_phy_driver = {
+ .probe = qcom_qmp_phy_probe,
+ .driver = {
+- .name = "qcom-qmp-phy",
++ .name = "qcom-qmp-msm8996-pcie-phy",
+ .pm = &qcom_qmp_phy_pm_ops,
+ .of_match_table = qcom_qmp_phy_of_match_table,
+ },
+@@ -6346,5 +1722,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
+ module_platform_driver(qcom_qmp_phy_driver);
+
+ MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
+-MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
+ MODULE_LICENSE("GPL v2");
+--
+2.35.1
+
--- /dev/null
+From 92b851087d73968358ef5624044c5747b5e01730 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:49 +0300
+Subject: phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit f575ac2d64e7cedb2d70acd5baa359da216cf718 ]
+
+Drop remaining support for PHY types other than PCIe.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-17-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 532 ++----------------
+ 1 file changed, 43 insertions(+), 489 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index 1741a5675f9a..02e5ae7fa213 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -510,7 +510,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
+ int serdes_tbl_num = cfg->serdes_tbl_num;
+ int ret;
+@@ -520,35 +519,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+ cfg->serdes_tbl_num_sec);
+
+- if (cfg->type == PHY_TYPE_DP) {
+- switch (dp_opts->link_rate) {
+- case 1620:
+- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_rbr,
+- cfg->serdes_tbl_rbr_num);
+- break;
+- case 2700:
+- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr,
+- cfg->serdes_tbl_hbr_num);
+- break;
+- case 5400:
+- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr2,
+- cfg->serdes_tbl_hbr2_num);
+- break;
+- case 8100:
+- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr3,
+- cfg->serdes_tbl_hbr3_num);
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- }
+-
+-
+ if (cfg->has_phy_com_ctrl) {
+ void __iomem *status;
+ unsigned int mask, val;
+@@ -572,36 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-/*
+- * We need to calibrate the aux setting here as many times
+- * as the caller tries
+- */
+-static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
+- struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
+- if (qphy->dp_opts.set_voltages) {
+- cfg->configure_dp_tx(qphy);
+- qphy->dp_opts.set_voltages = 0;
+- }
+-
+- return 0;
+-}
+-
+-static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
+-{
+- struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- if (cfg->calibrate_dp_phy)
+- return cfg->calibrate_dp_phy(qphy);
+-
+- return 0;
+-}
+-
+ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -771,9 +711,6 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
+ if (ret)
+ return ret;
+
+- if (cfg->type == PHY_TYPE_DP)
+- cfg->dp_aux_init(qphy);
+-
+ return 0;
+ }
+
+@@ -824,10 +761,6 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ cfg->tx_tbl_num_sec, 2);
+ }
+
+- /* Configure special DP tx tunings */
+- if (cfg->type == PHY_TYPE_DP)
+- cfg->configure_dp_tx(qphy);
+-
+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+ if (cfg->rx_tbl_sec)
+@@ -843,15 +776,10 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ cfg->rx_tbl_num_sec, 2);
+ }
+
+- /* Configure link rate, swing, etc. */
+- if (cfg->type == PHY_TYPE_DP) {
+- cfg->configure_dp_phy(qphy);
+- } else {
+- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+- if (cfg->pcs_tbl_sec)
+- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+- cfg->pcs_tbl_num_sec);
+- }
++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
+
+ ret = reset_control_deassert(qmp->ufs_reset);
+ if (ret)
+@@ -867,36 +795,28 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
+ * Pull out PHY from POWER DOWN state.
+ * This is active low enable signal to power-down PHY.
+ */
+- if(cfg->type == PHY_TYPE_PCIE)
+- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+
+ if (cfg->has_pwrdn_delay)
+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
+
+- if (cfg->type != PHY_TYPE_DP) {
+- /* Pull PHY out of reset state */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+- /* start SerDes and Phy-Coding-Sublayer */
+- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+-
+- if (cfg->type == PHY_TYPE_UFS) {
+- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
+- mask = PCS_READY;
+- ready = PCS_READY;
+- } else {
+- status = pcs + cfg->regs[QPHY_PCS_STATUS];
+- mask = cfg->phy_status;
+- ready = 0;
+- }
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
+- PHY_INIT_COMPLETE_TIMEOUT);
+- if (ret) {
+- dev_err(qmp->dev, "phy initialization timed-out\n");
+- goto err_disable_pipe_clk;
+- }
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
+ }
++
+ return 0;
+
+ err_disable_pipe_clk:
+@@ -915,25 +835,20 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
+
+ clk_disable_unprepare(qphy->pipe_clk);
+
+- if (cfg->type == PHY_TYPE_DP) {
+- /* Assert DP PHY power down */
+- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+- } else {
+- /* PHY reset */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
+- /* stop SerDes and Phy-Coding-Sublayer */
+- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+- /* Put PHY into POWER DOWN state: active low */
+- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+- cfg->pwrdn_ctrl);
+- } else {
+- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+- cfg->pwrdn_ctrl);
+- }
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
+ }
+
+ return 0;
+@@ -987,112 +902,6 @@ static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
+ return 0;
+ }
+
+-static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+- void __iomem *pcs = qphy->pcs;
+- void __iomem *pcs_misc = qphy->pcs_misc;
+- u32 intr_mask;
+-
+- if (qphy->mode == PHY_MODE_USB_HOST_SS ||
+- qphy->mode == PHY_MODE_USB_DEVICE_SS)
+- intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
+- else
+- intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
+-
+- /* Clear any pending interrupts status */
+- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+- /* Writing 1 followed by 0 clears the interrupt */
+- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+-
+- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+- ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
+-
+- /* Enable required PHY autonomous mode interrupts */
+- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
+-
+- /* Enable i/o clamp_n for autonomous mode */
+- if (pcs_misc)
+- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+-}
+-
+-static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+- void __iomem *pcs = qphy->pcs;
+- void __iomem *pcs_misc = qphy->pcs_misc;
+-
+- /* Disable i/o clamp_n on resume for normal mode */
+- if (pcs_misc)
+- qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+-
+- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+- ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
+-
+- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+- /* Writing 1 followed by 0 clears the interrupt */
+- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+-}
+-
+-static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
+-{
+- struct qcom_qmp *qmp = dev_get_drvdata(dev);
+- struct qmp_phy *qphy = qmp->phys[0];
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
+-
+- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
+- if (cfg->type != PHY_TYPE_USB3)
+- return 0;
+-
+- if (!qmp->init_count) {
+- dev_vdbg(dev, "PHY not initialized, bailing out\n");
+- return 0;
+- }
+-
+- qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
+-
+- clk_disable_unprepare(qphy->pipe_clk);
+- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
+-
+- return 0;
+-}
+-
+-static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
+-{
+- struct qcom_qmp *qmp = dev_get_drvdata(dev);
+- struct qmp_phy *qphy = qmp->phys[0];
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+- int ret = 0;
+-
+- dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
+-
+- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
+- if (cfg->type != PHY_TYPE_USB3)
+- return 0;
+-
+- if (!qmp->init_count) {
+- dev_vdbg(dev, "PHY not initialized, bailing out\n");
+- return 0;
+- }
+-
+- ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
+- if (ret)
+- return ret;
+-
+- ret = clk_prepare_enable(qphy->pipe_clk);
+- if (ret) {
+- dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
+- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
+- return ret;
+- }
+-
+- qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
+-
+- return 0;
+-}
+-
+ static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+@@ -1210,223 +1019,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+ }
+
+-/*
+- * Display Port PLL driver block diagram for branch clocks
+- *
+- * +------------------------------+
+- * | DP_VCO_CLK |
+- * | |
+- * | +-------------------+ |
+- * | | (DP PLL/VCO) | |
+- * | +---------+---------+ |
+- * | v |
+- * | +----------+-----------+ |
+- * | | hsclk_divsel_clk_src | |
+- * | +----------+-----------+ |
+- * +------------------------------+
+- * |
+- * +---------<---------v------------>----------+
+- * | |
+- * +--------v----------------+ |
+- * | dp_phy_pll_link_clk | |
+- * | link_clk | |
+- * +--------+----------------+ |
+- * | |
+- * | |
+- * v v
+- * Input to DISPCC block |
+- * for link clk, crypto clk |
+- * and interface clock |
+- * |
+- * |
+- * +--------<------------+-----------------+---<---+
+- * | | |
+- * +----v---------+ +--------v-----+ +--------v------+
+- * | vco_divided | | vco_divided | | vco_divided |
+- * | _clk_src | | _clk_src | | _clk_src |
+- * | | | | | |
+- * |divsel_six | | divsel_two | | divsel_four |
+- * +-------+------+ +-----+--------+ +--------+------+
+- * | | |
+- * v---->----------v-------------<------v
+- * |
+- * +----------+-----------------+
+- * | dp_phy_pll_vco_div_clk |
+- * +---------+------------------+
+- * |
+- * v
+- * Input to DISPCC block
+- * for DP pixel clock
+- *
+- */
+-static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
+- struct clk_rate_request *req)
+-{
+- switch (req->rate) {
+- case 1620000000UL / 2:
+- case 2700000000UL / 2:
+- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
+- return 0;
+- default:
+- return -EINVAL;
+- }
+-}
+-
+-static unsigned long
+-qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+-{
+- const struct qmp_phy_dp_clks *dp_clks;
+- const struct qmp_phy *qphy;
+- const struct phy_configure_opts_dp *dp_opts;
+-
+- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
+- qphy = dp_clks->qphy;
+- dp_opts = &qphy->dp_opts;
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- return 1620000000UL / 2;
+- case 2700:
+- return 2700000000UL / 2;
+- case 5400:
+- return 5400000000UL / 4;
+- case 8100:
+- return 8100000000UL / 6;
+- default:
+- return 0;
+- }
+-}
+-
+-static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
+- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
+- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
+-};
+-
+-static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
+- struct clk_rate_request *req)
+-{
+- switch (req->rate) {
+- case 162000000:
+- case 270000000:
+- case 540000000:
+- case 810000000:
+- return 0;
+- default:
+- return -EINVAL;
+- }
+-}
+-
+-static unsigned long
+-qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+-{
+- const struct qmp_phy_dp_clks *dp_clks;
+- const struct qmp_phy *qphy;
+- const struct phy_configure_opts_dp *dp_opts;
+-
+- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
+- qphy = dp_clks->qphy;
+- dp_opts = &qphy->dp_opts;
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- case 2700:
+- case 5400:
+- case 8100:
+- return dp_opts->link_rate * 100000;
+- default:
+- return 0;
+- }
+-}
+-
+-static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
+- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
+- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
+-};
+-
+-static struct clk_hw *
+-qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
+-{
+- struct qmp_phy_dp_clks *dp_clks = data;
+- unsigned int idx = clkspec->args[0];
+-
+- if (idx >= 2) {
+- pr_err("%s: invalid index %u\n", __func__, idx);
+- return ERR_PTR(-EINVAL);
+- }
+-
+- if (idx == 0)
+- return &dp_clks->dp_link_hw;
+-
+- return &dp_clks->dp_pixel_hw;
+-}
+-
+-static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
+- struct device_node *np)
+-{
+- struct clk_init_data init = { };
+- struct qmp_phy_dp_clks *dp_clks;
+- char name[64];
+- int ret;
+-
+- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
+- if (!dp_clks)
+- return -ENOMEM;
+-
+- dp_clks->qphy = qphy;
+- qphy->dp_clks = dp_clks;
+-
+- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
+- init.ops = &qcom_qmp_dp_link_clk_ops;
+- init.name = name;
+- dp_clks->dp_link_hw.init = &init;
+- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
+- if (ret)
+- return ret;
+-
+- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
+- init.ops = &qcom_qmp_dp_pixel_clk_ops;
+- init.name = name;
+- dp_clks->dp_pixel_hw.init = &init;
+- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
+- if (ret)
+- return ret;
+-
+- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
+- if (ret)
+- return ret;
+-
+- /*
+- * Roll a devm action because the clock provider is the child node, but
+- * the child node is not actually a device.
+- */
+- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+-}
+-
+-static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
+ .init = qcom_qmp_phy_pcie_msm8996_enable,
+ .exit = qcom_qmp_phy_pcie_msm8996_disable,
+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+-static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
+- .init = qcom_qmp_phy_pcie_msm8996_init,
+- .configure = qcom_qmp_dp_phy_configure,
+- .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
+- .calibrate = qcom_qmp_dp_phy_calibrate,
+- .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
+- .exit = qcom_qmp_phy_pcie_msm8996_exit,
+- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+- .owner = THIS_MODULE,
+-};
+-
+-static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
+- .power_on = qcom_qmp_phy_pcie_msm8996_enable,
+- .power_off = qcom_qmp_phy_pcie_msm8996_disable,
+- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
+- .owner = THIS_MODULE,
+-};
+-
+ static void qcom_qmp_reset_control_put(void *data)
+ {
+ reset_control_put(data);
+@@ -1439,7 +1038,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct phy *generic_phy;
+ struct qmp_phy *qphy;
+- const struct phy_ops *ops;
+ char prop_name[MAX_PROP_NAME];
+ int ret;
+
+@@ -1532,14 +1130,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
+ return ret;
+ }
+
+- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
+- ops = &qcom_qmp_pcie_ufs_ops;
+- else if (cfg->type == PHY_TYPE_DP)
+- ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
+- else
+- ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
+-
+- generic_phy = devm_phy_create(dev, np, ops);
++ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
+ if (IS_ERR(generic_phy)) {
+ ret = PTR_ERR(generic_phy);
+ dev_err(dev, "failed to create qphy %d\n", ret);
+@@ -1564,11 +1155,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
+ };
+ MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
+
+-static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
+- SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
+- qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
+-};
+-
+ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ {
+ struct qcom_qmp *qmp;
+@@ -1576,12 +1162,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ struct device_node *child;
+ struct phy_provider *phy_provider;
+ void __iomem *serdes;
+- void __iomem *usb_serdes;
+- void __iomem *dp_serdes = NULL;
+- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
+ const struct qmp_phy_cfg *cfg = NULL;
+- const struct qmp_phy_cfg *usb_cfg = NULL;
+- const struct qmp_phy_cfg *dp_cfg = NULL;
+ int num, id, expected_phys;
+ int ret;
+
+@@ -1598,28 +1179,18 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ return -EINVAL;
+
+ /* per PHY serdes; usually located at base address */
+- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ serdes = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(serdes))
+ return PTR_ERR(serdes);
+
+ /* per PHY dp_com; if PHY has dp_com control block */
+- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ if (cfg->has_phy_dp_com_ctrl) {
+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(qmp->dp_com))
+ return PTR_ERR(qmp->dp_com);
+ }
+
+- if (combo_cfg) {
+- /* Only two serdes for combo PHY */
+- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
+- if (IS_ERR(dp_serdes))
+- return PTR_ERR(dp_serdes);
+-
+- dp_cfg = combo_cfg->dp_cfg;
+- expected_phys = 2;
+- } else {
+- expected_phys = cfg->nlanes;
+- }
++ expected_phys = cfg->nlanes;
+
+ mutex_init(&qmp->phy_mutex);
+
+@@ -1658,14 +1229,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+
+ id = 0;
+ for_each_available_child_of_node(dev->of_node, child) {
+- if (of_node_name_eq(child, "dp-phy")) {
+- cfg = dp_cfg;
+- serdes = dp_serdes;
+- } else if (of_node_name_eq(child, "usb3-phy")) {
+- cfg = usb_cfg;
+- serdes = usb_serdes;
+- }
+-
+ /* Create per-lane phy */
+ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
+ if (ret) {
+@@ -1678,21 +1241,13 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
+ * Register the pipe clock provided by phy.
+ * See function description to see details of this pipe clock.
+ */
+- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
+- ret = phy_pipe_clk_register(qmp, child);
+- if (ret) {
+- dev_err(qmp->dev,
+- "failed to register pipe clock source\n");
+- goto err_node_put;
+- }
+- } else if (cfg->type == PHY_TYPE_DP) {
+- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
+- if (ret) {
+- dev_err(qmp->dev,
+- "failed to register DP clock source\n");
+- goto err_node_put;
+- }
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
+ }
++
+ id++;
+ }
+
+@@ -1714,7 +1269,6 @@ static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
+ .probe = qcom_qmp_phy_pcie_msm8996_probe,
+ .driver = {
+ .name = "qcom-qmp-msm8996-pcie-phy",
+- .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
+ .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
+ },
+ };
+--
+2.35.1
+
--- /dev/null
+From a00426d474394b1f287cc9a4ca0212c0ba09db35 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:32 +0200
+Subject: phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 1f69ededf8e80c42352e7f1c165a003614de9cc2 ]
+
+Switch to using the device-managed of_iomap helper to avoid leaking
+memory on probe deferral and driver unbind.
+
+Note that this helper checks for already reserved regions and may fail
+if there are multiple devices claiming the same memory.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-4-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 23 +++++++++----------
+ 1 file changed, 11 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index 51da3a3a199e..9caad14aacde 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -900,21 +900,20 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
+ * For single lane PHYs: pcs_misc (optional) -> 3.
+ */
+- qphy->tx = of_iomap(np, 0);
+- if (!qphy->tx)
+- return -ENOMEM;
+-
+- qphy->rx = of_iomap(np, 1);
+- if (!qphy->rx)
+- return -ENOMEM;
++ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
++ if (IS_ERR(qphy->tx))
++ return PTR_ERR(qphy->tx);
+
+- qphy->pcs = of_iomap(np, 2);
+- if (!qphy->pcs)
+- return -ENOMEM;
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (IS_ERR(qphy->rx))
++ return PTR_ERR(qphy->rx);
+
+- qphy->pcs_misc = of_iomap(np, 3);
++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
++ if (IS_ERR(qphy->pcs))
++ return PTR_ERR(qphy->pcs);
+
+- if (!qphy->pcs_misc)
++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
++ if (IS_ERR(qphy->pcs_misc))
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From a521c6e7b712ecf3803d903ccc91dbbc0d26fffa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 12:42:56 +0300
+Subject: phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit af6643242d3ac9c90674c5ba8dbddb01ffc37f29 ]
+
+Follow the example of other PCIe PHYs and use separate pcs_misc region
+to access PCS_PCIE_* resources.
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220705094320.1313312-5-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: ecd5507e72ea ("phy: qcom-qmp-pcie: add pcs_misc sanity check")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++++
+ drivers/phy/qualcomm/phy-qcom-qmp.h | 32 ++++++++++++------------
+ 2 files changed, 25 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+index c7309e981bfb..38fd0c5c3797 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -735,6 +735,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+@@ -3549,6 +3552,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++ .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl,
++ .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
+ .clk_list = ipq8074_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+ .reset_list = ipq8074_pciephy_reset_l,
+@@ -5957,6 +5962,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ qphy->pcs_misc = of_iomap(np, 3);
+ }
+
++ if (!qphy->pcs_misc &&
++ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
++ qphy->pcs_misc = qphy->pcs + 0x400;
++
+ if (!qphy->pcs_misc)
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
+index bebeac2c091c..9f05966cb60d 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
++++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
+@@ -121,22 +121,22 @@
+
+ /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
+
+-#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
+-#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
+-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
+-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
+-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
+-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
+-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
+-#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
+-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
+-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
+-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
+-#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
+-#define PCS_PCIE_EQ_CONFIG1 0x4a0
+-#define PCS_PCIE_EQ_CONFIG2 0x4a4
+-#define PCS_PCIE_PRESET_P10_PRE 0x4bc
+-#define PCS_PCIE_PRESET_P10_POST 0x4e0
++#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
++#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
++#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
++#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
++#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
++#define PCS_PCIE_EQ_CONFIG1 0x0a0
++#define PCS_PCIE_EQ_CONFIG2 0x0a4
++#define PCS_PCIE_PRESET_P10_PRE 0x0bc
++#define PCS_PCIE_PRESET_P10_POST 0x0e0
+
+ /* Only for QMP V2 PHY - QSERDES COM registers */
+ #define QSERDES_COM_BG_TIMER 0x00c
+--
+2.35.1
+
--- /dev/null
+From ae4ac319637206f20dc889c4709c3b9e13aaf18d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:34 +0200
+Subject: phy: qcom-qmp-ufs: fix memleak on probe deferral
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit ef74a97f0df8758efe4476b4645961286aa86f0d ]
+
+Switch to using the device-managed of_iomap helper to avoid leaking
+memory on probe deferral and driver unbind.
+
+Note that this helper checks for already reserved regions and may fail
+if there are multiple devices claiming the same memory.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-6-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 30 ++++++++++++-------------
+ 1 file changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+index c7309e981bfb..66a89fbacb33 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+@@ -5919,17 +5919,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
+ * For single lane PHYs: pcs_misc (optional) -> 3.
+ */
+- qphy->tx = of_iomap(np, 0);
+- if (!qphy->tx)
+- return -ENOMEM;
++ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
++ if (IS_ERR(qphy->tx))
++ return PTR_ERR(qphy->tx);
+
+- qphy->rx = of_iomap(np, 1);
+- if (!qphy->rx)
+- return -ENOMEM;
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (IS_ERR(qphy->rx))
++ return PTR_ERR(qphy->rx);
+
+- qphy->pcs = of_iomap(np, 2);
+- if (!qphy->pcs)
+- return -ENOMEM;
++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
++ if (IS_ERR(qphy->pcs))
++ return PTR_ERR(qphy->pcs);
+
+ /*
+ * If this is a dual-lane PHY, then there should be registers for the
+@@ -5938,9 +5938,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ * offset from the first lane.
+ */
+ if (cfg->is_dual_lane_phy) {
+- qphy->tx2 = of_iomap(np, 3);
+- qphy->rx2 = of_iomap(np, 4);
+- if (!qphy->tx2 || !qphy->rx2) {
++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) {
+ dev_warn(dev,
+ "Underspecified device tree, falling back to legacy register regions\n");
+
+@@ -5950,14 +5950,14 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 5);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
+ }
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 3);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
+ }
+
+- if (!qphy->pcs_misc)
++ if (IS_ERR(qphy->pcs_misc))
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From 99370fdab6d7d8784fa5e4d5eea748204da5e45f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:44 +0300
+Subject: phy: qcom-qmp-usb: change symbol prefix to qcom_qmp_phy_usb
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 09b492a379402395f646c6db2e16cdac1fc2229d ]
+
+Change all symbol names to start with qcom_qmp_phy_usb_ rather than old
+qcom_qmp_phy_
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-12-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 158 ++++++++++++------------
+ 1 file changed, 79 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index e147182afea7..2ae13b4485b6 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -2023,7 +2023,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
+ .is_dual_lane_phy = true,
+ };
+
+-static void qcom_qmp_phy_configure_lane(void __iomem *base,
++static void qcom_qmp_phy_usb_configure_lane(void __iomem *base,
+ const unsigned int *regs,
+ const struct qmp_phy_init_tbl tbl[],
+ int num,
+@@ -2046,15 +2046,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
+ }
+ }
+
+-static void qcom_qmp_phy_configure(void __iomem *base,
++static void qcom_qmp_phy_usb_configure(void __iomem *base,
+ const unsigned int *regs,
+ const struct qmp_phy_init_tbl tbl[],
+ int num)
+ {
+- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++ qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff);
+ }
+
+-static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -2064,30 +2064,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
+ int serdes_tbl_num = cfg->serdes_tbl_num;
+ int ret;
+
+- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+ if (cfg->serdes_tbl_sec)
+- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+ cfg->serdes_tbl_num_sec);
+
+ if (cfg->type == PHY_TYPE_DP) {
+ switch (dp_opts->link_rate) {
+ case 1620:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_rbr,
+ cfg->serdes_tbl_rbr_num);
+ break;
+ case 2700:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr,
+ cfg->serdes_tbl_hbr_num);
+ break;
+ case 5400:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr2,
+ cfg->serdes_tbl_hbr2_num);
+ break;
+ case 8100:
+- qcom_qmp_phy_configure(serdes, cfg->regs,
++ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+ cfg->serdes_tbl_hbr3,
+ cfg->serdes_tbl_hbr3_num);
+ break;
+@@ -2147,7 +2147,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -2242,7 +2242,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+ return ret;
+ }
+
+-static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -2277,7 +2277,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_init(struct phy *phy)
++static int qcom_qmp_phy_usb_init(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -2312,7 +2312,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
+ return ret;
+ }
+
+- ret = qcom_qmp_phy_com_init(qphy);
++ ret = qcom_qmp_phy_usb_com_init(qphy);
+ if (ret)
+ return ret;
+
+@@ -2322,7 +2322,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_power_on(struct phy *phy)
++static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -2335,7 +2335,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ unsigned int mask, val, ready;
+ int ret;
+
+- qcom_qmp_phy_serdes_init(qphy);
++ qcom_qmp_phy_usb_serdes_init(qphy);
+
+ if (cfg->has_lane_rst) {
+ ret = reset_control_deassert(qphy->lane_rst);
+@@ -2353,18 +2353,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ }
+
+ /* Tx, Rx, and PCS configurations */
+- qcom_qmp_phy_configure_lane(tx, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
+ if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
+ cfg->tx_tbl_num_sec, 1);
+
+ /* Configuration for other LANE for USB-DP combo PHY */
+ if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
+ if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
+ cfg->tx_tbl_sec,
+ cfg->tx_tbl_num_sec, 2);
+ }
+@@ -2373,17 +2373,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (cfg->type == PHY_TYPE_DP)
+ cfg->configure_dp_tx(qphy);
+
+- qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+ if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_configure_lane(rx, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
+
+ if (cfg->is_dual_lane_phy) {
+- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
+ if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
+ cfg->rx_tbl_sec,
+ cfg->rx_tbl_num_sec, 2);
+ }
+@@ -2392,9 +2392,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (cfg->type == PHY_TYPE_DP) {
+ cfg->configure_dp_phy(qphy);
+ } else {
+- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ if (cfg->pcs_tbl_sec)
+- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+ cfg->pcs_tbl_num_sec);
+ }
+
+@@ -2402,10 +2402,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ if (ret)
+ goto err_disable_pipe_clk;
+
+- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
+ cfg->pcs_misc_tbl_num);
+ if (cfg->pcs_misc_tbl_sec)
+- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
+ cfg->pcs_misc_tbl_num_sec);
+
+ /*
+@@ -2453,7 +2453,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
+ return ret;
+ }
+
+-static int qcom_qmp_phy_power_off(struct phy *phy)
++static int qcom_qmp_phy_usb_power_off(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -2484,7 +2484,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
+ return 0;
+ }
+
+-static int qcom_qmp_phy_exit(struct phy *phy)
++static int qcom_qmp_phy_usb_exit(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+@@ -2492,37 +2492,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
+ if (cfg->has_lane_rst)
+ reset_control_assert(qphy->lane_rst);
+
+- qcom_qmp_phy_com_exit(qphy);
++ qcom_qmp_phy_usb_com_exit(qphy);
+
+ return 0;
+ }
+
+-static int qcom_qmp_phy_enable(struct phy *phy)
++static int qcom_qmp_phy_usb_enable(struct phy *phy)
+ {
+ int ret;
+
+- ret = qcom_qmp_phy_init(phy);
++ ret = qcom_qmp_phy_usb_init(phy);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_power_on(phy);
++ ret = qcom_qmp_phy_usb_power_on(phy);
+ if (ret)
+- qcom_qmp_phy_exit(phy);
++ qcom_qmp_phy_usb_exit(phy);
+
+ return ret;
+ }
+
+-static int qcom_qmp_phy_disable(struct phy *phy)
++static int qcom_qmp_phy_usb_disable(struct phy *phy)
+ {
+ int ret;
+
+- ret = qcom_qmp_phy_power_off(phy);
++ ret = qcom_qmp_phy_usb_power_off(phy);
+ if (ret)
+ return ret;
+- return qcom_qmp_phy_exit(phy);
++ return qcom_qmp_phy_usb_exit(phy);
+ }
+
+-static int qcom_qmp_phy_set_mode(struct phy *phy,
++static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+@@ -2532,7 +2532,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
+ return 0;
+ }
+
+-static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
+ {
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+@@ -2561,7 +2561,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+ }
+
+-static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
+ {
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+@@ -2579,7 +2579,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ }
+
+-static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct qmp_phy *qphy = qmp->phys[0];
+@@ -2596,7 +2596,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
+ return 0;
+ }
+
+- qcom_qmp_phy_enable_autonomous_mode(qphy);
++ qcom_qmp_phy_usb_enable_autonomous_mode(qphy);
+
+ clk_disable_unprepare(qphy->pipe_clk);
+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
+@@ -2604,7 +2604,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
+ return 0;
+ }
+
+-static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct qmp_phy *qphy = qmp->phys[0];
+@@ -2633,12 +2633,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
+ return ret;
+ }
+
+- qcom_qmp_phy_disable_autonomous_mode(qphy);
++ qcom_qmp_phy_usb_disable_autonomous_mode(qphy);
+
+ return 0;
+ }
+
+-static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int num = cfg->num_vregs;
+@@ -2654,7 +2654,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
+ }
+
+-static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int i;
+@@ -2679,7 +2679,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
+ return 0;
+ }
+
+-static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ int num = cfg->num_clks;
+@@ -2947,28 +2947,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+ }
+
+-static const struct phy_ops qcom_qmp_phy_gen_ops = {
+- .init = qcom_qmp_phy_enable,
+- .exit = qcom_qmp_phy_disable,
+- .set_mode = qcom_qmp_phy_set_mode,
++static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
++ .init = qcom_qmp_phy_usb_enable,
++ .exit = qcom_qmp_phy_usb_disable,
++ .set_mode = qcom_qmp_phy_usb_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+-static const struct phy_ops qcom_qmp_phy_dp_ops = {
+- .init = qcom_qmp_phy_init,
++static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
++ .init = qcom_qmp_phy_usb_init,
+ .configure = qcom_qmp_dp_phy_configure,
+- .power_on = qcom_qmp_phy_power_on,
++ .power_on = qcom_qmp_phy_usb_power_on,
+ .calibrate = qcom_qmp_dp_phy_calibrate,
+- .power_off = qcom_qmp_phy_power_off,
+- .exit = qcom_qmp_phy_exit,
+- .set_mode = qcom_qmp_phy_set_mode,
++ .power_off = qcom_qmp_phy_usb_power_off,
++ .exit = qcom_qmp_phy_usb_exit,
++ .set_mode = qcom_qmp_phy_usb_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+ static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
+- .power_on = qcom_qmp_phy_enable,
+- .power_off = qcom_qmp_phy_disable,
+- .set_mode = qcom_qmp_phy_set_mode,
++ .power_on = qcom_qmp_phy_usb_enable,
++ .power_off = qcom_qmp_phy_usb_disable,
++ .set_mode = qcom_qmp_phy_usb_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+@@ -2978,7 +2978,7 @@ static void qcom_qmp_reset_control_put(void *data)
+ }
+
+ static
+-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
+ {
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+@@ -3080,9 +3080,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
+ ops = &qcom_qmp_pcie_ufs_ops;
+ else if (cfg->type == PHY_TYPE_DP)
+- ops = &qcom_qmp_phy_dp_ops;
++ ops = &qcom_qmp_phy_usb_dp_ops;
+ else
+- ops = &qcom_qmp_phy_gen_ops;
++ ops = &qcom_qmp_phy_usb_gen_ops;
+
+ generic_phy = devm_phy_create(dev, np, ops);
+ if (IS_ERR(generic_phy)) {
+@@ -3100,7 +3100,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ return 0;
+ }
+
+-static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = {
+ {
+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
+ .data = &ipq8074_usb3phy_cfg,
+@@ -3158,14 +3158,14 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ },
+ { },
+ };
+-MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table);
+
+-static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
+- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
+- qcom_qmp_phy_runtime_resume, NULL)
++static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = {
++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend,
++ qcom_qmp_phy_usb_runtime_resume, NULL)
+ };
+
+-static int qcom_qmp_phy_probe(struct platform_device *pdev)
++static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
+ {
+ struct qcom_qmp *qmp;
+ struct device *dev = &pdev->dev;
+@@ -3219,15 +3219,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+
+ mutex_init(&qmp->phy_mutex);
+
+- ret = qcom_qmp_phy_clk_init(dev, cfg);
++ ret = qcom_qmp_phy_usb_clk_init(dev, cfg);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_reset_init(dev, cfg);
++ ret = qcom_qmp_phy_usb_reset_init(dev, cfg);
+ if (ret)
+ return ret;
+
+- ret = qcom_qmp_phy_vreg_init(dev, cfg);
++ ret = qcom_qmp_phy_usb_vreg_init(dev, cfg);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get regulator supplies: %d\n",
+@@ -3265,7 +3265,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ }
+
+ /* Create per-lane phy */
+- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++ ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
+ if (ret) {
+ dev_err(dev, "failed to create lane%d phy, %d\n",
+ id, ret);
+@@ -3305,16 +3305,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ return ret;
+ }
+
+-static struct platform_driver qcom_qmp_phy_driver = {
+- .probe = qcom_qmp_phy_probe,
++static struct platform_driver qcom_qmp_phy_usb_driver = {
++ .probe = qcom_qmp_phy_usb_probe,
+ .driver = {
+ .name = "qcom-qmp-usb-phy",
+- .pm = &qcom_qmp_phy_pm_ops,
+- .of_match_table = qcom_qmp_phy_of_match_table,
++ .pm = &qcom_qmp_phy_usb_pm_ops,
++ .of_match_table = qcom_qmp_phy_usb_of_match_table,
+ },
+ };
+
+-module_platform_driver(qcom_qmp_phy_driver);
++module_platform_driver(qcom_qmp_phy_usb_driver);
+
+ MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
+ MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
+--
+2.35.1
+
--- /dev/null
+From f7e0a5e72ca54215471d23384650e3ce19b4a70d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 23 Jun 2022 13:33:14 +0200
+Subject: phy: qcom-qmp-usb: clean up pipe clock handling
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 5d5b7d509ff85675779caeafcffa8086d7094339 ]
+
+Clean up the pipe clock handling by using dev_err_probe() to handle
+probe deferral and dropping the obsolete comment that claimed that the
+pipe clock was optional for some other PHY types.
+
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220623113314.29761-4-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 15 ++-------------
+ 1 file changed, 2 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index 9e752fce638d..687f1a534837 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -2566,22 +2566,11 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ if (!qphy->pcs_misc)
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+
+- /*
+- * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
+- * based phys, so they essentially have pipe clock. So,
+- * we return error in case phy is USB3 or PIPE type.
+- * Otherwise, we initialize pipe clock to NULL for
+- * all phys that don't need this.
+- */
+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ if (IS_ERR(qphy->pipe_clk)) {
+- ret = PTR_ERR(qphy->pipe_clk);
+- if (ret != -EPROBE_DEFER)
+- dev_err(dev,
+- "failed to get lane%d pipe_clk, %d\n",
+- id, ret);
+- return ret;
++ return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
++ "failed to get lane%d pipe clock\n", id);
+ }
+
+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
+--
+2.35.1
+
--- /dev/null
+From 00b19fe255215980b0b97d8d64bde9c4b82e870f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:56 +0300
+Subject: phy: qcom-qmp-usb: cleanup the driver
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit faf83af5d59498509eb84015453073fd5e85231e ]
+
+Remove the conditionals and options that are not used by any of USB PHY
+devices.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-24-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 214 ++----------------------
+ 1 file changed, 11 insertions(+), 203 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index 55785dcd47e0..9e752fce638d 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -1359,40 +1359,12 @@ struct qmp_phy_cfg {
+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_init_tbl *serdes_tbl;
+ int serdes_tbl_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_sec;
+- int serdes_tbl_num_sec;
+ const struct qmp_phy_init_tbl *tx_tbl;
+ int tx_tbl_num;
+- const struct qmp_phy_init_tbl *tx_tbl_sec;
+- int tx_tbl_num_sec;
+ const struct qmp_phy_init_tbl *rx_tbl;
+ int rx_tbl_num;
+- const struct qmp_phy_init_tbl *rx_tbl_sec;
+- int rx_tbl_num_sec;
+ const struct qmp_phy_init_tbl *pcs_tbl;
+ int pcs_tbl_num;
+- const struct qmp_phy_init_tbl *pcs_tbl_sec;
+- int pcs_tbl_num_sec;
+- const struct qmp_phy_init_tbl *pcs_misc_tbl;
+- int pcs_misc_tbl_num;
+- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
+- int pcs_misc_tbl_num_sec;
+-
+- /* Init sequence for DP PHY block link rates */
+- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
+- int serdes_tbl_rbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
+- int serdes_tbl_hbr_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
+- int serdes_tbl_hbr2_num;
+- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
+- int serdes_tbl_hbr3_num;
+-
+- /* DP PHY callbacks */
+- int (*configure_dp_phy)(struct qmp_phy *qphy);
+- void (*configure_dp_tx)(struct qmp_phy *qphy);
+- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
+- void (*dp_aux_init)(struct qmp_phy *qphy);
+
+ /* clock ids to be requested */
+ const char * const *clk_list;
+@@ -1409,14 +1381,9 @@ struct qmp_phy_cfg {
+
+ unsigned int start_ctrl;
+ unsigned int pwrdn_ctrl;
+- unsigned int mask_com_pcs_ready;
+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
+ unsigned int phy_status;
+
+- /* true, if PHY has a separate PHY_COM control block */
+- bool has_phy_com_ctrl;
+- /* true, if PHY has a reset for individual lanes */
+- bool has_lane_rst;
+ /* true, if PHY needs delay after POWER_DOWN */
+ bool has_pwrdn_delay;
+ /* power_down delay in usec */
+@@ -1427,14 +1394,6 @@ struct qmp_phy_cfg {
+ bool has_phy_dp_com_ctrl;
+ /* true, if PHY has secondary tx/rx lanes to be configured */
+ bool is_dual_lane_phy;
+-
+- /* true, if PCS block has no separate SW_RESET register */
+- bool no_pcs_sw_reset;
+-};
+-
+-struct qmp_phy_combo_cfg {
+- const struct qmp_phy_cfg *usb_cfg;
+- const struct qmp_phy_cfg *dp_cfg;
+ };
+
+ /**
+@@ -1452,11 +1411,7 @@ struct qmp_phy_combo_cfg {
+ * @pipe_clk: pipe clock
+ * @index: lane index
+ * @qmp: QMP phy to which this lane belongs
+- * @lane_rst: lane's reset controller
+ * @mode: current PHY mode
+- * @dp_aux_cfg: Display port aux config
+- * @dp_opts: Display port optional config
+- * @dp_clks: Display port clocks
+ */
+ struct qmp_phy {
+ struct phy *phy;
+@@ -1471,17 +1426,7 @@ struct qmp_phy {
+ struct clk *pipe_clk;
+ unsigned int index;
+ struct qcom_qmp *qmp;
+- struct reset_control *lane_rst;
+ enum phy_mode mode;
+- unsigned int dp_aux_cfg;
+- struct phy_configure_opts_dp dp_opts;
+- struct qmp_phy_dp_clks *dp_clks;
+-};
+-
+-struct qmp_phy_dp_clks {
+- struct qmp_phy *qphy;
+- struct clk_hw dp_link_hw;
+- struct clk_hw dp_pixel_hw;
+ };
+
+ /**
+@@ -1497,7 +1442,6 @@ struct qmp_phy_dp_clks {
+ * @phys: array of per-lane phy descriptors
+ * @phy_mutex: mutex lock for PHY common block initialization
+ * @init_count: phy common block initialization count
+- * @ufs_reset: optional UFS PHY reset handle
+ */
+ struct qcom_qmp {
+ struct device *dev;
+@@ -1511,8 +1455,6 @@ struct qcom_qmp {
+
+ struct mutex phy_mutex;
+ int init_count;
+-
+- struct reset_control *ufs_reset;
+ };
+
+ static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
+@@ -2056,37 +1998,12 @@ static void qcom_qmp_phy_usb_configure(void __iomem *base,
+
+ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
+ {
+- struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
+ int serdes_tbl_num = cfg->serdes_tbl_num;
+- int ret;
+
+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+- if (cfg->serdes_tbl_sec)
+- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+- cfg->serdes_tbl_num_sec);
+-
+- if (cfg->has_phy_com_ctrl) {
+- void __iomem *status;
+- unsigned int mask, val;
+-
+- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
+- SERDES_START | PCS_START);
+-
+- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
+- mask = cfg->mask_com_pcs_ready;
+-
+- ret = readl_poll_timeout(status, val, (val & mask), 10,
+- PHY_INIT_COMPLETE_TIMEOUT);
+- if (ret) {
+- dev_err(qmp->dev,
+- "phy common block init timed-out\n");
+- return ret;
+- }
+- }
+
+ return 0;
+ }
+@@ -2095,7 +2012,6 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+- void __iomem *serdes = qphy->serdes;
+ void __iomem *pcs = qphy->pcs;
+ void __iomem *dp_com = qmp->dp_com;
+ int ret, i;
+@@ -2158,18 +2074,13 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
+ }
+
+- if (cfg->has_phy_com_ctrl) {
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
+- SW_PWRDN);
+- } else {
+- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
+- qphy_setbits(pcs,
+- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+- cfg->pwrdn_ctrl);
+- else
+- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+- cfg->pwrdn_ctrl);
+- }
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++ qphy_setbits(pcs,
++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ else
++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
+
+ mutex_unlock(&qmp->phy_mutex);
+
+@@ -2190,7 +2101,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+- void __iomem *serdes = qphy->serdes;
+ int i = cfg->num_resets;
+
+ mutex_lock(&qmp->phy_mutex);
+@@ -2199,16 +2109,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
+ return 0;
+ }
+
+- reset_control_assert(qmp->ufs_reset);
+- if (cfg->has_phy_com_ctrl) {
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
+- SERDES_START | PCS_START);
+- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
+- SW_RESET);
+- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
+- SW_PWRDN);
+- }
+-
+ while (--i >= 0)
+ reset_control_assert(qmp->resets[i]);
+
+@@ -2225,37 +2125,9 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+ int ret;
+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
+
+- if (cfg->no_pcs_sw_reset) {
+- /*
+- * Get UFS reset, which is delayed until now to avoid a
+- * circular dependency where UFS needs its PHY, but the PHY
+- * needs this UFS reset.
+- */
+- if (!qmp->ufs_reset) {
+- qmp->ufs_reset =
+- devm_reset_control_get_exclusive(qmp->dev,
+- "ufsphy");
+-
+- if (IS_ERR(qmp->ufs_reset)) {
+- ret = PTR_ERR(qmp->ufs_reset);
+- dev_err(qmp->dev,
+- "failed to get UFS reset: %d\n",
+- ret);
+-
+- qmp->ufs_reset = NULL;
+- return ret;
+- }
+- }
+-
+- ret = reset_control_assert(qmp->ufs_reset);
+- if (ret)
+- return ret;
+- }
+-
+ ret = qcom_qmp_phy_usb_com_init(qphy);
+ if (ret)
+ return ret;
+@@ -2271,82 +2143,45 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+ void __iomem *tx = qphy->tx;
+ void __iomem *rx = qphy->rx;
+ void __iomem *pcs = qphy->pcs;
+- void __iomem *pcs_misc = qphy->pcs_misc;
+ void __iomem *status;
+ unsigned int mask, val, ready;
+ int ret;
+
+ qcom_qmp_phy_usb_serdes_init(qphy);
+
+- if (cfg->has_lane_rst) {
+- ret = reset_control_deassert(qphy->lane_rst);
+- if (ret) {
+- dev_err(qmp->dev, "lane%d reset deassert failed\n",
+- qphy->index);
+- return ret;
+- }
+- }
+-
+ ret = clk_prepare_enable(qphy->pipe_clk);
+ if (ret) {
+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
+- goto err_reset_lane;
++ return ret;
+ }
+
+ /* Tx, Rx, and PCS configurations */
+ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
+- if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
+- cfg->tx_tbl_num_sec, 1);
+
+ /* Configuration for other LANE for USB-DP combo PHY */
+ if (cfg->is_dual_lane_phy) {
+ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
+- if (cfg->tx_tbl_sec)
+- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
+- cfg->tx_tbl_sec,
+- cfg->tx_tbl_num_sec, 2);
+ }
+
+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+- if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
+- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
+
+ if (cfg->is_dual_lane_phy) {
+ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
+- if (cfg->rx_tbl_sec)
+- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
+- cfg->rx_tbl_sec,
+- cfg->rx_tbl_num_sec, 2);
+ }
+
+ /* Configure link rate, swing, etc. */
+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+- if (cfg->pcs_tbl_sec)
+- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+- cfg->pcs_tbl_num_sec);
+-
+- ret = reset_control_deassert(qmp->ufs_reset);
+- if (ret)
+- goto err_disable_pipe_clk;
+-
+- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
+- cfg->pcs_misc_tbl_num);
+- if (cfg->pcs_misc_tbl_sec)
+- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
+- cfg->pcs_misc_tbl_num_sec);
+
+ if (cfg->has_pwrdn_delay)
+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
+
+ /* Pull PHY out of reset state */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
+ /* start SerDes and Phy-Coding-Sublayer */
+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+@@ -2365,9 +2200,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+
+ err_disable_pipe_clk:
+ clk_disable_unprepare(qphy->pipe_clk);
+-err_reset_lane:
+- if (cfg->has_lane_rst)
+- reset_control_assert(qphy->lane_rst);
+
+ return ret;
+ }
+@@ -2380,8 +2212,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
+ clk_disable_unprepare(qphy->pipe_clk);
+
+ /* PHY reset */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
+ /* stop SerDes and Phy-Coding-Sublayer */
+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+@@ -2401,10 +2232,6 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
+ static int qcom_qmp_phy_usb_exit(struct phy *phy)
+ {
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- if (cfg->has_lane_rst)
+- reset_control_assert(qphy->lane_rst);
+
+ qcom_qmp_phy_usb_com_exit(qphy);
+
+@@ -2676,11 +2503,6 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = {
+ .owner = THIS_MODULE,
+ };
+
+-static void qcom_qmp_reset_control_put(void *data)
+-{
+- reset_control_put(data);
+-}
+-
+ static
+ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
+@@ -2762,20 +2584,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ return ret;
+ }
+
+- /* Get lane reset, if any */
+- if (cfg->has_lane_rst) {
+- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
+- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
+- if (IS_ERR(qphy->lane_rst)) {
+- dev_err(dev, "failed to get lane%d reset\n", id);
+- return PTR_ERR(qphy->lane_rst);
+- }
+- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
+- qphy->lane_rst);
+- if (ret)
+- return ret;
+- }
+-
+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
+ if (IS_ERR(generic_phy)) {
+ ret = PTR_ERR(generic_phy);
+--
+2.35.1
+
--- /dev/null
+From 7b9b153c67dfed5063ad8ba797b28c742aa05aca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 13:07:21 +0200
+Subject: phy: qcom-qmp-usb: disable runtime PM on unbind
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit e57655e66806750785f9121c98a962404d02395b ]
+
+Make sure to disable runtime PM also on driver unbind.
+
+Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM").
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220907110728.19092-10-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index c7309e981bfb..dcf8a8764e17 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ return -ENOMEM;
+
+ pm_runtime_set_active(dev);
+- pm_runtime_enable(dev);
++ ret = devm_pm_runtime_enable(dev);
++ if (ret)
++ return ret;
+ /*
+ * Prevent runtime pm from being ON by default. Users can enable
+ * it using power/control in sysfs.
+@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (!IS_ERR(phy_provider))
+ dev_info(dev, "Registered Qcom-QMP phy\n");
+- else
+- pm_runtime_disable(dev);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+
+ err_node_put:
+- pm_runtime_disable(dev);
+ of_node_put(child);
+ return ret;
+ }
+--
+2.35.1
+
--- /dev/null
+From fc6a1be1ee217d1ec1f986400c741ce00bcd87d3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:38 +0300
+Subject: phy: qcom-qmp-usb: drop all non-USB compatibles support
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 8c924330ebe3e5c6f41bad0e5118875848843864 ]
+
+Drop support for all non-USB compatibles from the new qmp-usb driver.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-6-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3108 +----------------------
+ 1 file changed, 40 insertions(+), 3068 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index dcf8a8764e17..e147182afea7 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -141,34 +141,6 @@ enum qphy_reg_layout {
+ QPHY_LAYOUT_SIZE
+ };
+
+-static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x168,
+-};
+-
+-static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+-};
+-
+-static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_COM_SW_RESET] = 0x400,
+- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
+- [QPHY_COM_START_CONTROL] = 0x408,
+- [QPHY_COM_PCS_READY_STATUS] = 0x448,
+- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
+- [QPHY_FLL_CNTRL1] = 0xc4,
+- [QPHY_FLL_CNTRL2] = 0xc8,
+- [QPHY_FLL_CNT_VAL_L] = 0xcc,
+- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
+- [QPHY_FLL_MAN_CODE] = 0xd4,
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x174,
+-};
+-
+ static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_FLL_CNTRL1] = 0xc0,
+ [QPHY_FLL_CNTRL2] = 0xc4,
+@@ -192,18 +164,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
+ };
+
+-static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x174,
+-};
+-
+-static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x08,
+- [QPHY_PCS_STATUS] = 0x2ac,
+-};
+-
+ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = 0x00,
+ [QPHY_START_CTRL] = 0x44,
+@@ -241,29 +201,6 @@ static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
+ };
+
+-static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x160,
+-};
+-
+-static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = 0x00,
+- [QPHY_PCS_READY_STATUS] = 0x168,
+-};
+-
+-static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_SW_RESET] = 0x00,
+- [QPHY_START_CTRL] = 0x44,
+- [QPHY_PCS_STATUS] = 0x14,
+- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
+-};
+-
+-static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
+- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
+- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
+-};
+-
+ static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+@@ -339,235 +276,6 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+ };
+
+-static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
+- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+-
+- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
+-
+- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
+- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
+- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
+-};
+-
+ static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+@@ -639,414 +347,6 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+ };
+
+-static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
+- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
+- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
+- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
+- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
+- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
+-};
+-
+-static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
+- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
+- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
+- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+-
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
+- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
+-};
+-
+ static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
+@@ -1094,88 +394,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+ };
+
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+-};
+-
+ static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+@@ -1346,175 +564,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
+ };
+
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
+- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
+-};
+-
+-static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
+- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
+- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
+- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+-};
+-
+-static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
+- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+ static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+@@ -1624,93 +673,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ };
+
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+-
+-};
+-
+-static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+ static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+@@ -2023,374 +985,44 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
+-};
+-
+-static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
+-};
+-
+-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+ };
+
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
+ };
+
+ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
+@@ -2440,101 +1072,6 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+ };
+
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
+-};
+-
+-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
+-};
+-
+ static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
+@@ -2579,106 +1116,6 @@ static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
+ };
+
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+-
+- /* Rate B */
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+-};
+-
+ static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
+@@ -2910,215 +1347,6 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ };
+
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
+- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
+- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
+-
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
+- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
+-};
+-
+-/* Register names should be validated, they might be different for this PHY */
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
+- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
+-};
+-
+-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
+- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
+-};
+-
+ struct qmp_phy;
+
+ /* struct qmp_phy_cfg - per-PHY initialization config */
+@@ -3287,16 +1515,6 @@ struct qcom_qmp {
+ struct reset_control *ufs_reset;
+ };
+
+-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
+-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
+-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
+-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
+-
+-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
+-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
+-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
+-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
+-
+ static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
+ {
+ u32 reg;
+@@ -3326,18 +1544,10 @@ static const char * const msm8996_phy_clk_l[] = {
+ "aux", "cfg_ahb", "ref",
+ };
+
+-static const char * const msm8996_ufs_phy_clk_l[] = {
+- "ref",
+-};
+-
+ static const char * const qmp_v3_phy_clk_l[] = {
+ "aux", "cfg_ahb", "ref", "com_aux",
+ };
+
+-static const char * const sdm845_pciephy_clk_l[] = {
+- "aux", "cfg_ahb", "ref", "refgen",
+-};
+-
+ static const char * const qmp_v4_phy_clk_l[] = {
+ "aux", "ref_clk_src", "ref", "com_aux",
+ };
+@@ -3347,14 +1557,6 @@ static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
+ "aux", "ref_clk_src", "com_aux"
+ };
+
+-static const char * const sm8450_ufs_phy_clk_l[] = {
+- "qref", "ref", "ref_aux",
+-};
+-
+-static const char * const sdm845_ufs_phy_clk_l[] = {
+- "ref", "ref_aux",
+-};
+-
+ /* usb3 phy on sdx55 doesn't have com_aux clock */
+ static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
+ "aux", "cfg_ahb", "ref"
+@@ -3365,10 +1567,6 @@ static const char * const qcm2290_usb3phy_clk_l[] = {
+ };
+
+ /* list of resets */
+-static const char * const msm8996_pciephy_reset_l[] = {
+- "phy", "common", "cfg",
+-};
+-
+ static const char * const msm8996_usb3phy_reset_l[] = {
+ "phy", "common",
+ };
+@@ -3381,10 +1579,6 @@ static const char * const qcm2290_usb3phy_reset_l[] = {
+ "phy_phy", "phy",
+ };
+
+-static const char * const sdm845_pciephy_reset_l[] = {
+- "phy",
+-};
+-
+ /* list of regulators */
+ static const char * const qmp_phy_vreg_l[] = {
+ "vdda-phy", "vdda-pll",
+@@ -3415,64 +1609,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
+ .phy_status = PHYSTATUS,
+ };
+
+-static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 3,
+-
+- .serdes_tbl = msm8996_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
+- .tx_tbl = msm8996_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
+- .rx_tbl = msm8996_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
+- .pcs_tbl = msm8996_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = msm8996_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .mask_com_pcs_ready = PCS_READY,
+- .phy_status = PHYSTATUS,
+-
+- .has_phy_com_ctrl = true,
+- .has_lane_rst = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+-};
+-
+-static const struct qmp_phy_cfg msm8996_ufs_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8996_ufs_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
+- .tx_tbl = msm8996_ufs_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
+- .rx_tbl = msm8996_ufs_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
+-
+- .clk_list = msm8996_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
+-
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+-
+- .regs = msm8996_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .no_pcs_sw_reset = true,
+-};
+-
+ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -3498,214 +1634,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
+ .phy_status = PHYSTATUS,
+ };
+
+-static const char * const ipq8074_pciephy_clk_l[] = {
+- "aux", "cfg_ahb",
+-};
+-/* list of resets */
+-static const char * const ipq8074_pciephy_reset_l[] = {
+- "phy", "common",
+-};
+-
+-static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = ipq8074_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
+- .tx_tbl = ipq8074_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
+- .rx_tbl = ipq8074_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
+- .pcs_tbl = ipq8074_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
+- .clk_list = ipq8074_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = NULL,
+- .num_vregs = 0,
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_phy_com_ctrl = false,
+- .has_lane_rst = false,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = ipq6018_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
+- .tx_tbl = ipq6018_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
+- .rx_tbl = ipq6018_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
+- .pcs_tbl = ipq6018_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+- .clk_list = ipq8074_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = NULL,
+- .num_vregs = 0,
+- .regs = ipq_pciephy_gen3_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+-
+- .has_phy_com_ctrl = false,
+- .has_lane_rst = false,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
+- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
+- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
+- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_qmp_pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
+- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
+- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
+- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_qhp_pciephy_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
+- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
+- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
+- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
+- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
+- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
+- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
+- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
+- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
+- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
+- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -3770,46 +1698,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
+ .is_dual_lane_phy = true,
+ };
+
+-static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v3_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
+- .tx_tbl = qmp_v3_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = sc7180_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
+- .usb_cfg = &sc7180_usb3phy_cfg,
+- .dp_cfg = &sc7180_dpphy_cfg,
+-};
+-
+ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -3839,82 +1727,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
+- .tx_tbl = sdm845_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
+- .rx_tbl = sdm845_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
+- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sdm845_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+- .no_pcs_sw_reset = true,
+-};
+-
+-static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
+- .tx_tbl = sm6115_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
+- .rx_tbl = sm6115_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
+- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm6115_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+-
+- .is_dual_lane_phy = false,
+- .no_pcs_sw_reset = true,
+-};
+-
+-static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = msm8998_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
+- .tx_tbl = msm8998_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
+- .rx_tbl = msm8998_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
+- .pcs_tbl = msm8998_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
+- .clk_list = msm8996_phy_clk_l,
+- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+- .reset_list = ipq8074_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = pciephy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-};
+-
+ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -3933,38 +1745,13 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
+- .tx_tbl = sm8150_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
+- .rx_tbl = sm8150_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
+- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
++ .regs = qmp_v3_usb3phy_regs_layout,
+
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
++ .start_ctrl = SERDES_START | PCS_START,
++ .pwrdn_ctrl = SW_PWRDN,
+ .phy_status = PHYSTATUS,
+
+- .is_dual_lane_phy = true,
++ .is_dual_lane_phy = true,
+ };
+
+ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
+@@ -4000,76 +1787,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
+ .is_dual_lane_phy = true,
+ };
+
+-static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
+- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
+- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
+- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v4_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
+- .tx_tbl = qmp_v4_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v3_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+- .reset_list = sc7180_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v3_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
+- .usb_cfg = &sm8150_usb3phy_cfg,
+- .dp_cfg = &sc8180x_dpphy_cfg,
+-};
+-
+ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -4160,46 +1877,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
+- .type = PHY_TYPE_DP,
+- .nlanes = 1,
+-
+- .serdes_tbl = qmp_v4_dp_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
+- .tx_tbl = qmp_v4_dp_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
+-
+- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
+- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
+- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
+- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
+- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
+- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
+- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
+- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
+-
+- .clk_list = qmp_v4_phy_clk_l,
+- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+- .reset_list = msm8996_usb3phy_reset_l,
+- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = qmp_v4_usb3phy_regs_layout,
+-
+- .has_phy_dp_com_ctrl = true,
+- .is_dual_lane_phy = true,
+-
+- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
+- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
+- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
+- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
+-};
+-
+-static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
+- .usb_cfg = &sm8250_usb3phy_cfg,
+- .dp_cfg = &sm8250_dpphy_cfg,
+-};
+-
+ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -4229,38 +1906,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
+- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
+- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
+- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
+- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = PCS_START | SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS_4_20,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -4290,31 +1935,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+- .tx_tbl = sm8350_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+- .rx_tbl = sm8350_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+- .clk_list = sdm845_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+-};
+-
+ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -4376,94 +1996,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+ };
+
+-static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
+- .type = PHY_TYPE_UFS,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+- .tx_tbl = sm8350_ufsphy_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+- .rx_tbl = sm8350_ufsphy_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+- .clk_list = sm8450_ufs_phy_clk_l,
+- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8150_ufsphy_regs_layout,
+-
+- .start_ctrl = SERDES_START,
+- .pwrdn_ctrl = SW_PWRDN,
+- .phy_status = PHYSTATUS,
+-
+- .is_dual_lane_phy = true,
+-};
+-
+-static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 1,
+-
+- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
+- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
+- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
+- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS,
+-
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+-static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
+- .type = PHY_TYPE_PCIE,
+- .nlanes = 2,
+-
+- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
+- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
+- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
+- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
+- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
+- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
+- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
+- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
+- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
+- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
+- .clk_list = sdm845_pciephy_clk_l,
+- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+- .reset_list = sdm845_pciephy_reset_l,
+- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+- .vreg_list = qmp_phy_vreg_l,
+- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+- .regs = sm8250_pcie_regs_layout,
+-
+- .start_ctrl = SERDES_START | PCS_START,
+- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+- .phy_status = PHYSTATUS_4_20,
+-
+- .is_dual_lane_phy = true,
+- .has_pwrdn_delay = true,
+- .pwrdn_delay_min = 995, /* us */
+- .pwrdn_delay_max = 1005, /* us */
+-};
+-
+ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+@@ -4589,457 +2121,6 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
+-{
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- /* Turn on BIAS current for PHY/PLL */
+- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
+- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
+- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
+- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
+- DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(QSERDES_V3_COM_BIAS_EN |
+- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
+- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
+- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
+- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
+- qphy->dp_aux_cfg = 0;
+-
+- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
+- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
+- PHY_AUX_REQ_ERR_MASK,
+- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
+-}
+-
+-static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
+- { 0x00, 0x0c, 0x15, 0x1a },
+- { 0x02, 0x0e, 0x16, 0xff },
+- { 0x02, 0x11, 0xff, 0xff },
+- { 0x04, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
+- { 0x02, 0x12, 0x16, 0x1a },
+- { 0x09, 0x19, 0x1f, 0xff },
+- { 0x10, 0x1f, 0xff, 0xff },
+- { 0x1f, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
+- { 0x00, 0x0c, 0x14, 0x19 },
+- { 0x00, 0x0b, 0x12, 0xff },
+- { 0x00, 0x0b, 0xff, 0xff },
+- { 0x04, 0xff, 0xff, 0xff }
+-};
+-
+-static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
+- { 0x08, 0x0f, 0x16, 0x1f },
+- { 0x11, 0x1e, 0x1f, 0xff },
+- { 0x19, 0x1f, 0xff, 0xff },
+- { 0x1f, 0xff, 0xff, 0xff }
+-};
+-
+-static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
+- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- unsigned int v_level = 0, p_level = 0;
+- u8 voltage_swing_cfg, pre_emphasis_cfg;
+- int i;
+-
+- for (i = 0; i < dp_opts->lanes; i++) {
+- v_level = max(v_level, dp_opts->voltage[i]);
+- p_level = max(p_level, dp_opts->pre[i]);
+- }
+-
+- if (dp_opts->link_rate <= 2700) {
+- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
+- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
+- } else {
+- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
+- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
+- }
+-
+- /* TODO: Move check to config check */
+- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
+- return -EINVAL;
+-
+- /* Enable MUX to use Cursor values from these registers */
+- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
+- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
+-
+- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
+- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
+- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
+- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
+-
+- return 0;
+-}
+-
+-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 bias_en, drvr_en;
+-
+- if (qcom_qmp_phy_configure_dp_swing(qphy,
+- QSERDES_V3_TX_TX_DRV_LVL,
+- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
+- return;
+-
+- if (dp_opts->lanes == 1) {
+- bias_en = 0x3e;
+- drvr_en = 0x13;
+- } else {
+- bias_en = 0x3f;
+- drvr_en = 0x10;
+- }
+-
+- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+-}
+-
+-static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
+-{
+- u32 val;
+- bool reverse = false;
+-
+- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
+-
+- /*
+- * TODO: Assume orientation is CC1 for now and two lanes, need to
+- * use type-c connector to understand orientation and lanes.
+- *
+- * Otherwise val changes to be like below if this code understood
+- * the orientation of the type-c cable.
+- *
+- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
+- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
+- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
+- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+- * if (orientation == ORIENTATION_CC2)
+- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+- */
+- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
+-
+- return reverse;
+-}
+-
+-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 phy_vco_div, status;
+- unsigned long pixel_freq;
+-
+- qcom_qmp_phy_configure_dp_mode(qphy);
+-
+- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
+- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- phy_vco_div = 0x1;
+- pixel_freq = 1620000000UL / 2;
+- break;
+- case 2700:
+- phy_vco_div = 0x1;
+- pixel_freq = 2700000000UL / 2;
+- break;
+- case 5400:
+- phy_vco_div = 0x2;
+- pixel_freq = 5400000000UL / 4;
+- break;
+- case 8100:
+- phy_vco_div = 0x0;
+- pixel_freq = 8100000000UL / 6;
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
+-
+- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
+- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
+-
+- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
+- udelay(2000);
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000);
+-}
+-
+-/*
+- * We need to calibrate the aux setting here as many times
+- * as the caller tries
+- */
+-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
+-{
+- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
+- u8 val;
+-
+- qphy->dp_aux_cfg++;
+- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
+- val = cfg1_settings[qphy->dp_aux_cfg];
+-
+- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+-
+- return 0;
+-}
+-
+-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
+-{
+- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+-
+- /* Turn on BIAS current for PHY/PLL */
+- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
+-
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
+- qphy->dp_aux_cfg = 0;
+-
+- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
+- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
+- PHY_AUX_REQ_ERR_MASK,
+- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
+-}
+-
+-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
+-{
+- /* Program default values before writing proper values */
+- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
+- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
+-
+- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-
+- qcom_qmp_phy_configure_dp_swing(qphy,
+- QSERDES_V4_TX_TX_DRV_LVL,
+- QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-}
+-
+-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
+-{
+- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+- u32 phy_vco_div, status;
+- unsigned long pixel_freq;
+- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
+- bool reverse;
+-
+- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
+-
+- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
+-
+- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+-
+- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
+- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- phy_vco_div = 0x1;
+- pixel_freq = 1620000000UL / 2;
+- break;
+- case 2700:
+- phy_vco_div = 0x1;
+- pixel_freq = 2700000000UL / 2;
+- break;
+- case 5400:
+- phy_vco_div = 0x2;
+- pixel_freq = 5400000000UL / 4;
+- break;
+- case 8100:
+- phy_vco_div = 0x0;
+- pixel_freq = 8100000000UL / 6;
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
+-
+- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
+- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
+-
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(0)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- /*
+- * At least for 7nm DP PHY this has to be done after enabling link
+- * clock.
+- */
+-
+- if (dp_opts->lanes == 1) {
+- bias0_en = reverse ? 0x3e : 0x15;
+- bias1_en = reverse ? 0x15 : 0x3e;
+- drvr0_en = reverse ? 0x13 : 0x10;
+- drvr1_en = reverse ? 0x10 : 0x13;
+- } else if (dp_opts->lanes == 2) {
+- bias0_en = reverse ? 0x3f : 0x15;
+- bias1_en = reverse ? 0x15 : 0x3f;
+- drvr0_en = 0x10;
+- drvr1_en = 0x10;
+- } else {
+- bias0_en = 0x3f;
+- bias1_en = 0x3f;
+- drvr0_en = 0x10;
+- drvr1_en = 0x10;
+- }
+-
+- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
+- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
+- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+-
+- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
+- udelay(2000);
+- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
+-
+- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
+- status,
+- ((status & BIT(1)) > 0),
+- 500,
+- 10000))
+- return -ETIMEDOUT;
+-
+- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
+- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
+-
+- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
+- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
+-
+- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
+-
+- return 0;
+-}
+-
+-/*
+- * We need to calibrate the aux setting here as many times
+- * as the caller tries
+- */
+-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
+-{
+- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
+- u8 val;
+-
+- qphy->dp_aux_cfg++;
+- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
+- val = cfg1_settings[qphy->dp_aux_cfg];
+-
+- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+-
+- return 0;
+-}
+-
+ static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
+ {
+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
+@@ -6023,81 +3104,27 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ {
+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
+ .data = &ipq8074_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,msm8996-qmp-pcie-phy",
+- .data = &msm8996_pciephy_cfg,
+- }, {
+- .compatible = "qcom,msm8996-qmp-ufs-phy",
+- .data = &msm8996_ufs_cfg,
+ }, {
+ .compatible = "qcom,msm8996-qmp-usb3-phy",
+ .data = &msm8996_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,msm8998-qmp-pcie-phy",
+- .data = &msm8998_pciephy_cfg,
+- }, {
+- .compatible = "qcom,msm8998-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,ipq8074-qmp-pcie-phy",
+- .data = &ipq8074_pciephy_cfg,
+- }, {
+- .compatible = "qcom,ipq6018-qmp-pcie-phy",
+- .data = &ipq6018_pciephy_cfg,
+ }, {
+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
+ .data = &ipq8074_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,sc7180-qmp-usb3-phy",
+ .data = &sc7180_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+- }, {
+- .compatible = "qcom,sc8180x-qmp-pcie-phy",
+- .data = &sc8180x_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sc8180x-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
+- .data = &sm8350_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
+ .data = &sm8150_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+- }, {
+- .compatible = "qcom,sdm845-qhp-pcie-phy",
+- .data = &sdm845_qhp_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-pcie-phy",
+- .data = &sdm845_qmp_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sdm845-qmp-usb3-phy",
+ .data = &qmp_v3_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
+ .data = &qmp_v3_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sdm845-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,msm8998-qmp-usb3-phy",
+ .data = &msm8998_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm6115-qmp-ufs-phy",
+- .data = &sm6115_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm6350-qmp-ufs-phy",
+- .data = &sdm845_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8150-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-ufs-phy",
+- .data = &sm8150_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm8150-qmp-usb3-phy",
+ .data = &sm8150_usb3phy_cfg,
+@@ -6107,27 +3134,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ }, {
+ .compatible = "qcom,sm8250-qmp-usb3-phy",
+ .data = &sm8250_usb3phy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
+- /* It's a combo phy */
+ }, {
+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
+ .data = &sm8250_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
+- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
+- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8350-qmp-ufs-phy",
+- .data = &sm8350_ufsphy_cfg,
+- }, {
+- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
+- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sdx55-qmp-pcie-phy",
+- .data = &sdx55_qmp_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
+ .data = &sdx55_usb3_uniphy_cfg,
+@@ -6140,15 +3149,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ }, {
+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
+ .data = &sm8350_usb3_uniphy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
+- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
+- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
+- }, {
+- .compatible = "qcom,sm8450-qmp-ufs-phy",
+- .data = &sm8450_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm8450-qmp-usb3-phy",
+ .data = &sm8350_usb3phy_cfg,
+@@ -6160,22 +3160,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ };
+ MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
+
+-static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
+- {
+- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+- .data = &sc7180_usb3dpphy_cfg,
+- },
+- {
+- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
+- .data = &sm8250_usb3dpphy_cfg,
+- },
+- {
+- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
+- .data = &sc8180x_usb3dpphy_cfg,
+- },
+- { }
+-};
+-
+ static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
+ qcom_qmp_phy_runtime_resume, NULL)
+@@ -6206,20 +3190,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+
+ /* Get the specific init parameters of QMP phy */
+ cfg = of_device_get_match_data(dev);
+- if (!cfg) {
+- const struct of_device_id *match;
+-
+- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
+- if (!match)
+- return -EINVAL;
+-
+- combo_cfg = match->data;
+- if (!combo_cfg)
+- return -EINVAL;
+-
+- usb_cfg = combo_cfg->usb_cfg;
+- cfg = usb_cfg; /* Setup clks and regulators */
+- }
++ if (!cfg)
++ return -EINVAL;
+
+ /* per PHY serdes; usually located at base address */
+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
+@@ -6336,7 +3308,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
+ static struct platform_driver qcom_qmp_phy_driver = {
+ .probe = qcom_qmp_phy_probe,
+ .driver = {
+- .name = "qcom-qmp-phy",
++ .name = "qcom-qmp-usb-phy",
+ .pm = &qcom_qmp_phy_pm_ops,
+ .of_match_table = qcom_qmp_phy_of_match_table,
+ },
+@@ -6345,5 +3317,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
+ module_platform_driver(qcom_qmp_phy_driver);
+
+ MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
+-MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
+ MODULE_LICENSE("GPL v2");
+--
+2.35.1
+
--- /dev/null
+From 3805907d92cd0199edf405eb7a3d16e023f481fb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 13:29:23 +0200
+Subject: phy: qcom-qmp-usb: drop pipe clock lane suffix
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit c8c5d5e89ac52a462f48264863a7a32f0c76fa1d ]
+
+The pipe clock is defined in the "lane" node so there's no need to keep
+adding a redundant lane-number suffix to the clock name.
+
+Update driver to support the new binding where the pipe clock name has
+been deprecated by instead requesting the clock by index.
+
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220830112923.3725-31-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index 687f1a534837..116f60ef0649 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -2510,7 +2510,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct phy *generic_phy;
+ struct qmp_phy *qphy;
+- char prop_name[MAX_PROP_NAME];
+ int ret;
+
+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
+@@ -2566,8 +2565,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ if (!qphy->pcs_misc)
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
+
+- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
+- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
+ if (IS_ERR(qphy->pipe_clk)) {
+ return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
+ "failed to get lane%d pipe clock\n", id);
+--
+2.35.1
+
--- /dev/null
+From a27bf0d085843b2d538221bdbd250c82aa7eeb1f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:31:51 +0300
+Subject: phy: qcom-qmp-usb: drop support for non-USB PHY types
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 86f5ddddcd9c4755e3d1d1ca4be01df5a4ed5d96 ]
+
+Drop remaining support for PHY types other than USB.
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-19-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 435 +++---------------------
+ 1 file changed, 48 insertions(+), 387 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index 2ae13b4485b6..55785dcd47e0 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -2059,7 +2059,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
+- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
+ int serdes_tbl_num = cfg->serdes_tbl_num;
+ int ret;
+@@ -2069,35 +2068,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
+ cfg->serdes_tbl_num_sec);
+
+- if (cfg->type == PHY_TYPE_DP) {
+- switch (dp_opts->link_rate) {
+- case 1620:
+- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_rbr,
+- cfg->serdes_tbl_rbr_num);
+- break;
+- case 2700:
+- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr,
+- cfg->serdes_tbl_hbr_num);
+- break;
+- case 5400:
+- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr2,
+- cfg->serdes_tbl_hbr2_num);
+- break;
+- case 8100:
+- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
+- cfg->serdes_tbl_hbr3,
+- cfg->serdes_tbl_hbr3_num);
+- break;
+- default:
+- /* Other link rates aren't supported */
+- return -EINVAL;
+- }
+- }
+-
+-
+ if (cfg->has_phy_com_ctrl) {
+ void __iomem *status;
+ unsigned int mask, val;
+@@ -2121,32 +2091,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
+ return 0;
+ }
+
+-static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
+-{
+- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
+- struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
+- if (qphy->dp_opts.set_voltages) {
+- cfg->configure_dp_tx(qphy);
+- qphy->dp_opts.set_voltages = 0;
+- }
+-
+- return 0;
+-}
+-
+-static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
+-{
+- struct qmp_phy *qphy = phy_get_drvdata(phy);
+- const struct qmp_phy_cfg *cfg = qphy->cfg;
+-
+- if (cfg->calibrate_dp_phy)
+- return cfg->calibrate_dp_phy(qphy);
+-
+- return 0;
+-}
+-
+ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
+ {
+ struct qcom_qmp *qmp = qphy->qmp;
+@@ -2316,9 +2260,6 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
+ if (ret)
+ return ret;
+
+- if (cfg->type == PHY_TYPE_DP)
+- cfg->dp_aux_init(qphy);
+-
+ return 0;
+ }
+
+@@ -2369,10 +2310,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+ cfg->tx_tbl_num_sec, 2);
+ }
+
+- /* Configure special DP tx tunings */
+- if (cfg->type == PHY_TYPE_DP)
+- cfg->configure_dp_tx(qphy);
+-
+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
+ if (cfg->rx_tbl_sec)
+@@ -2389,14 +2326,10 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+ }
+
+ /* Configure link rate, swing, etc. */
+- if (cfg->type == PHY_TYPE_DP) {
+- cfg->configure_dp_phy(qphy);
+- } else {
+- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+- if (cfg->pcs_tbl_sec)
+- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
+- cfg->pcs_tbl_num_sec);
+- }
++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++ if (cfg->pcs_tbl_sec)
++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++ cfg->pcs_tbl_num_sec);
+
+ ret = reset_control_deassert(qmp->ufs_reset);
+ if (ret)
+@@ -2408,40 +2341,26 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
+ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
+ cfg->pcs_misc_tbl_num_sec);
+
+- /*
+- * Pull out PHY from POWER DOWN state.
+- * This is active low enable signal to power-down PHY.
+- */
+- if(cfg->type == PHY_TYPE_PCIE)
+- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+-
+ if (cfg->has_pwrdn_delay)
+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
+
+- if (cfg->type != PHY_TYPE_DP) {
+- /* Pull PHY out of reset state */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+- /* start SerDes and Phy-Coding-Sublayer */
+- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+-
+- if (cfg->type == PHY_TYPE_UFS) {
+- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
+- mask = PCS_READY;
+- ready = PCS_READY;
+- } else {
+- status = pcs + cfg->regs[QPHY_PCS_STATUS];
+- mask = cfg->phy_status;
+- ready = 0;
+- }
++ /* Pull PHY out of reset state */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* start SerDes and Phy-Coding-Sublayer */
++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
+- PHY_INIT_COMPLETE_TIMEOUT);
+- if (ret) {
+- dev_err(qmp->dev, "phy initialization timed-out\n");
+- goto err_disable_pipe_clk;
+- }
++ status = pcs + cfg->regs[QPHY_PCS_STATUS];
++ mask = cfg->phy_status;
++ ready = 0;
++
++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++ PHY_INIT_COMPLETE_TIMEOUT);
++ if (ret) {
++ dev_err(qmp->dev, "phy initialization timed-out\n");
++ goto err_disable_pipe_clk;
+ }
++
+ return 0;
+
+ err_disable_pipe_clk:
+@@ -2460,25 +2379,20 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
+
+ clk_disable_unprepare(qphy->pipe_clk);
+
+- if (cfg->type == PHY_TYPE_DP) {
+- /* Assert DP PHY power down */
+- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
+- } else {
+- /* PHY reset */
+- if (!cfg->no_pcs_sw_reset)
+- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++ /* PHY reset */
++ if (!cfg->no_pcs_sw_reset)
++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
+- /* stop SerDes and Phy-Coding-Sublayer */
+- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++ /* stop SerDes and Phy-Coding-Sublayer */
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+- /* Put PHY into POWER DOWN state: active low */
+- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+- cfg->pwrdn_ctrl);
+- } else {
+- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+- cfg->pwrdn_ctrl);
+- }
++ /* Put PHY into POWER DOWN state: active low */
++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++ cfg->pwrdn_ctrl);
++ } else {
++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++ cfg->pwrdn_ctrl);
+ }
+
+ return 0;
+@@ -2755,223 +2669,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+ }
+
+-/*
+- * Display Port PLL driver block diagram for branch clocks
+- *
+- * +------------------------------+
+- * | DP_VCO_CLK |
+- * | |
+- * | +-------------------+ |
+- * | | (DP PLL/VCO) | |
+- * | +---------+---------+ |
+- * | v |
+- * | +----------+-----------+ |
+- * | | hsclk_divsel_clk_src | |
+- * | +----------+-----------+ |
+- * +------------------------------+
+- * |
+- * +---------<---------v------------>----------+
+- * | |
+- * +--------v----------------+ |
+- * | dp_phy_pll_link_clk | |
+- * | link_clk | |
+- * +--------+----------------+ |
+- * | |
+- * | |
+- * v v
+- * Input to DISPCC block |
+- * for link clk, crypto clk |
+- * and interface clock |
+- * |
+- * |
+- * +--------<------------+-----------------+---<---+
+- * | | |
+- * +----v---------+ +--------v-----+ +--------v------+
+- * | vco_divided | | vco_divided | | vco_divided |
+- * | _clk_src | | _clk_src | | _clk_src |
+- * | | | | | |
+- * |divsel_six | | divsel_two | | divsel_four |
+- * +-------+------+ +-----+--------+ +--------+------+
+- * | | |
+- * v---->----------v-------------<------v
+- * |
+- * +----------+-----------------+
+- * | dp_phy_pll_vco_div_clk |
+- * +---------+------------------+
+- * |
+- * v
+- * Input to DISPCC block
+- * for DP pixel clock
+- *
+- */
+-static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
+- struct clk_rate_request *req)
+-{
+- switch (req->rate) {
+- case 1620000000UL / 2:
+- case 2700000000UL / 2:
+- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
+- return 0;
+- default:
+- return -EINVAL;
+- }
+-}
+-
+-static unsigned long
+-qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+-{
+- const struct qmp_phy_dp_clks *dp_clks;
+- const struct qmp_phy *qphy;
+- const struct phy_configure_opts_dp *dp_opts;
+-
+- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
+- qphy = dp_clks->qphy;
+- dp_opts = &qphy->dp_opts;
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- return 1620000000UL / 2;
+- case 2700:
+- return 2700000000UL / 2;
+- case 5400:
+- return 5400000000UL / 4;
+- case 8100:
+- return 8100000000UL / 6;
+- default:
+- return 0;
+- }
+-}
+-
+-static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
+- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
+- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
+-};
+-
+-static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
+- struct clk_rate_request *req)
+-{
+- switch (req->rate) {
+- case 162000000:
+- case 270000000:
+- case 540000000:
+- case 810000000:
+- return 0;
+- default:
+- return -EINVAL;
+- }
+-}
+-
+-static unsigned long
+-qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+-{
+- const struct qmp_phy_dp_clks *dp_clks;
+- const struct qmp_phy *qphy;
+- const struct phy_configure_opts_dp *dp_opts;
+-
+- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
+- qphy = dp_clks->qphy;
+- dp_opts = &qphy->dp_opts;
+-
+- switch (dp_opts->link_rate) {
+- case 1620:
+- case 2700:
+- case 5400:
+- case 8100:
+- return dp_opts->link_rate * 100000;
+- default:
+- return 0;
+- }
+-}
+-
+-static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
+- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
+- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
+-};
+-
+-static struct clk_hw *
+-qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
+-{
+- struct qmp_phy_dp_clks *dp_clks = data;
+- unsigned int idx = clkspec->args[0];
+-
+- if (idx >= 2) {
+- pr_err("%s: invalid index %u\n", __func__, idx);
+- return ERR_PTR(-EINVAL);
+- }
+-
+- if (idx == 0)
+- return &dp_clks->dp_link_hw;
+-
+- return &dp_clks->dp_pixel_hw;
+-}
+-
+-static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
+- struct device_node *np)
+-{
+- struct clk_init_data init = { };
+- struct qmp_phy_dp_clks *dp_clks;
+- char name[64];
+- int ret;
+-
+- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
+- if (!dp_clks)
+- return -ENOMEM;
+-
+- dp_clks->qphy = qphy;
+- qphy->dp_clks = dp_clks;
+-
+- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
+- init.ops = &qcom_qmp_dp_link_clk_ops;
+- init.name = name;
+- dp_clks->dp_link_hw.init = &init;
+- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
+- if (ret)
+- return ret;
+-
+- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
+- init.ops = &qcom_qmp_dp_pixel_clk_ops;
+- init.name = name;
+- dp_clks->dp_pixel_hw.init = &init;
+- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
+- if (ret)
+- return ret;
+-
+- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
+- if (ret)
+- return ret;
+-
+- /*
+- * Roll a devm action because the clock provider is the child node, but
+- * the child node is not actually a device.
+- */
+- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+-}
+-
+-static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
++static const struct phy_ops qcom_qmp_phy_usb_ops = {
+ .init = qcom_qmp_phy_usb_enable,
+ .exit = qcom_qmp_phy_usb_disable,
+ .set_mode = qcom_qmp_phy_usb_set_mode,
+ .owner = THIS_MODULE,
+ };
+
+-static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
+- .init = qcom_qmp_phy_usb_init,
+- .configure = qcom_qmp_dp_phy_configure,
+- .power_on = qcom_qmp_phy_usb_power_on,
+- .calibrate = qcom_qmp_dp_phy_calibrate,
+- .power_off = qcom_qmp_phy_usb_power_off,
+- .exit = qcom_qmp_phy_usb_exit,
+- .set_mode = qcom_qmp_phy_usb_set_mode,
+- .owner = THIS_MODULE,
+-};
+-
+-static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
+- .power_on = qcom_qmp_phy_usb_enable,
+- .power_off = qcom_qmp_phy_usb_disable,
+- .set_mode = qcom_qmp_phy_usb_set_mode,
+- .owner = THIS_MODULE,
+-};
+-
+ static void qcom_qmp_reset_control_put(void *data)
+ {
+ reset_control_put(data);
+@@ -2984,7 +2688,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct phy *generic_phy;
+ struct qmp_phy *qphy;
+- const struct phy_ops *ops;
+ char prop_name[MAX_PROP_NAME];
+ int ret;
+
+@@ -3051,16 +2754,12 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ if (IS_ERR(qphy->pipe_clk)) {
+- if (cfg->type == PHY_TYPE_PCIE ||
+- cfg->type == PHY_TYPE_USB3) {
+- ret = PTR_ERR(qphy->pipe_clk);
+- if (ret != -EPROBE_DEFER)
+- dev_err(dev,
+- "failed to get lane%d pipe_clk, %d\n",
+- id, ret);
+- return ret;
+- }
+- qphy->pipe_clk = NULL;
++ ret = PTR_ERR(qphy->pipe_clk);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev,
++ "failed to get lane%d pipe_clk, %d\n",
++ id, ret);
++ return ret;
+ }
+
+ /* Get lane reset, if any */
+@@ -3077,14 +2776,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ return ret;
+ }
+
+- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
+- ops = &qcom_qmp_pcie_ufs_ops;
+- else if (cfg->type == PHY_TYPE_DP)
+- ops = &qcom_qmp_phy_usb_dp_ops;
+- else
+- ops = &qcom_qmp_phy_usb_gen_ops;
+-
+- generic_phy = devm_phy_create(dev, np, ops);
++ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
+ if (IS_ERR(generic_phy)) {
+ ret = PTR_ERR(generic_phy);
+ dev_err(dev, "failed to create qphy %d\n", ret);
+@@ -3172,12 +2864,7 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
+ struct device_node *child;
+ struct phy_provider *phy_provider;
+ void __iomem *serdes;
+- void __iomem *usb_serdes;
+- void __iomem *dp_serdes = NULL;
+- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
+ const struct qmp_phy_cfg *cfg = NULL;
+- const struct qmp_phy_cfg *usb_cfg = NULL;
+- const struct qmp_phy_cfg *dp_cfg = NULL;
+ int num, id, expected_phys;
+ int ret;
+
+@@ -3194,28 +2881,18 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
+ return -EINVAL;
+
+ /* per PHY serdes; usually located at base address */
+- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++ serdes = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(serdes))
+ return PTR_ERR(serdes);
+
+ /* per PHY dp_com; if PHY has dp_com control block */
+- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++ if (cfg->has_phy_dp_com_ctrl) {
+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(qmp->dp_com))
+ return PTR_ERR(qmp->dp_com);
+ }
+
+- if (combo_cfg) {
+- /* Only two serdes for combo PHY */
+- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
+- if (IS_ERR(dp_serdes))
+- return PTR_ERR(dp_serdes);
+-
+- dp_cfg = combo_cfg->dp_cfg;
+- expected_phys = 2;
+- } else {
+- expected_phys = cfg->nlanes;
+- }
++ expected_phys = cfg->nlanes;
+
+ mutex_init(&qmp->phy_mutex);
+
+@@ -3256,14 +2933,6 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
+
+ id = 0;
+ for_each_available_child_of_node(dev->of_node, child) {
+- if (of_node_name_eq(child, "dp-phy")) {
+- cfg = dp_cfg;
+- serdes = dp_serdes;
+- } else if (of_node_name_eq(child, "usb3-phy")) {
+- cfg = usb_cfg;
+- serdes = usb_serdes;
+- }
+-
+ /* Create per-lane phy */
+ ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
+ if (ret) {
+@@ -3276,21 +2945,13 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
+ * Register the pipe clock provided by phy.
+ * See function description to see details of this pipe clock.
+ */
+- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
+- ret = phy_pipe_clk_register(qmp, child);
+- if (ret) {
+- dev_err(qmp->dev,
+- "failed to register pipe clock source\n");
+- goto err_node_put;
+- }
+- } else if (cfg->type == PHY_TYPE_DP) {
+- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
+- if (ret) {
+- dev_err(qmp->dev,
+- "failed to register DP clock source\n");
+- goto err_node_put;
+- }
++ ret = phy_pipe_clk_register(qmp, child);
++ if (ret) {
++ dev_err(qmp->dev,
++ "failed to register pipe clock source\n");
++ goto err_node_put;
+ }
++
+ id++;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From e28891255ecb303288fc26a5982f9a3601ef1e35 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 12:23:35 +0200
+Subject: phy: qcom-qmp-usb: fix memleak on probe deferral
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit a5d6b1ac56cbd6b5850a3a54e35f1cb71e8e8cdd ]
+
+Switch to using the device-managed of_iomap helper to avoid leaking
+memory on probe deferral and driver unbind.
+
+Note that this helper checks for already reserved regions and may fail
+if there are multiple devices claiming the same memory.
+
+Two bindings currently rely on overlapping mappings for the PCS region
+so fallback to non-exclusive mappings for those for now.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20220916102340.11520-7-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 57 ++++++++++++++++++-------
+ 1 file changed, 42 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+index 116f60ef0649..b727dcf4f906 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -2503,6 +2503,21 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = {
+ .owner = THIS_MODULE,
+ };
+
++static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
++ int index, bool exclusive)
++{
++ struct resource res;
++
++ if (!exclusive) {
++ if (of_address_to_resource(np, index, &res))
++ return IOMEM_ERR_PTR(-EINVAL);
++
++ return devm_ioremap(dev, res.start, resource_size(&res));
++ }
++
++ return devm_of_iomap(dev, np, index, NULL);
++}
++
+ static
+ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
+@@ -2510,8 +2525,18 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
+ struct phy *generic_phy;
+ struct qmp_phy *qphy;
++ bool exclusive = true;
+ int ret;
+
++ /*
++ * FIXME: These bindings should be fixed to not rely on overlapping
++ * mappings for PCS.
++ */
++ if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
++ exclusive = false;
++ if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
++ exclusive = false;
++
+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
+ if (!qphy)
+ return -ENOMEM;
+@@ -2524,17 +2549,17 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
+ * For single lane PHYs: pcs_misc (optional) -> 3.
+ */
+- qphy->tx = of_iomap(np, 0);
+- if (!qphy->tx)
+- return -ENOMEM;
++ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
++ if (IS_ERR(qphy->tx))
++ return PTR_ERR(qphy->tx);
+
+- qphy->rx = of_iomap(np, 1);
+- if (!qphy->rx)
+- return -ENOMEM;
++ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
++ if (IS_ERR(qphy->rx))
++ return PTR_ERR(qphy->rx);
+
+- qphy->pcs = of_iomap(np, 2);
+- if (!qphy->pcs)
+- return -ENOMEM;
++ qphy->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
++ if (IS_ERR(qphy->pcs))
++ return PTR_ERR(qphy->pcs);
+
+ /*
+ * If this is a dual-lane PHY, then there should be registers for the
+@@ -2543,9 +2568,9 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ * offset from the first lane.
+ */
+ if (cfg->is_dual_lane_phy) {
+- qphy->tx2 = of_iomap(np, 3);
+- qphy->rx2 = of_iomap(np, 4);
+- if (!qphy->tx2 || !qphy->rx2) {
++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) {
+ dev_warn(dev,
+ "Underspecified device tree, falling back to legacy register regions\n");
+
+@@ -2555,15 +2580,17 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 5);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
+ }
+
+ } else {
+- qphy->pcs_misc = of_iomap(np, 3);
++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
+ }
+
+- if (!qphy->pcs_misc)
++ if (IS_ERR(qphy->pcs_misc)) {
+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++ qphy->pcs_misc = NULL;
++ }
+
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
+ if (IS_ERR(qphy->pipe_clk)) {
+--
+2.35.1
+
--- /dev/null
+From 8fd28585b01fdd1243751a5aad3ce32e9d134542 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 Sep 2022 13:13:33 +0800
+Subject: phy: qualcomm: call clk_disable_unprepare in the error handling
+
+From: Dongliang Mu <mudongliangabcd@gmail.com>
+
+[ Upstream commit c3966ced8eb8dc53b6c8d7f97d32cc8a2107d83e ]
+
+Smatch reports the following error:
+
+drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
+warn: 'uphy->cal_clk' from clk_prepare_enable() not released on lines:
+58.
+drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
+warn: 'uphy->cal_sleep_clk' from clk_prepare_enable() not released on
+lines: 58.
+drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
+warn: 'uphy->phy_clk' from clk_prepare_enable() not released on lines:
+58.
+
+Fix this by calling proper clk_disable_unprepare calls.
+
+Fixes: 0b56e9a7e835 ("phy: Group vendor specific phy drivers")
+Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20220914051334.69282-1-dzm91@hust.edu.cn
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
+index 04d18d52f700..d4741c2dbbb5 100644
+--- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
++++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
+@@ -54,8 +54,10 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy)
+
+ /* Configure pins for HSIC functionality */
+ pins_default = pinctrl_lookup_state(uphy->pctl, PINCTRL_STATE_DEFAULT);
+- if (IS_ERR(pins_default))
+- return PTR_ERR(pins_default);
++ if (IS_ERR(pins_default)) {
++ ret = PTR_ERR(pins_default);
++ goto err_ulpi;
++ }
+
+ ret = pinctrl_select_state(uphy->pctl, pins_default);
+ if (ret)
+--
+2.35.1
+
--- /dev/null
+From cda8f32a3c5c75fa4f074f74dc77918721aab3ab Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 20:49:54 +0000
+Subject: platform/chrome: cros_ec: Notify the PM of wake events during resume
+
+From: Jameson Thies <jthies@google.com>
+
+[ Upstream commit 8edd2752b0aa498b3a61f3caee8f79f7e0567fad ]
+
+cros_ec_handle_event in the cros_ec driver can notify the PM of wake
+events. When a device is suspended, cros_ec_handle_event will not check
+MKBP events. Instead, received MKBP events are checked during resume by
+cros_ec_report_events_during_suspend. But
+cros_ec_report_events_during_suspend cannot notify the PM if received
+events are wake events, causing wake events to not be reported if
+received while the device is suspended.
+
+Update cros_ec_report_events_during_suspend to notify the PM of wake
+events during resume by calling pm_wakeup_event.
+
+Signed-off-by: Jameson Thies <jthies@google.com>
+Reviewed-by: Prashant Malani <pmalani@chromium.org>
+Reviewed-by: Benson Leung <bleung@chromium.org>
+Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
+Link: https://lore.kernel.org/r/20220913204954.2931042-1-jthies@google.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/chrome/cros_ec.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cros_ec.c
+index 4f0390b10cd3..9664e13ded59 100644
+--- a/drivers/platform/chrome/cros_ec.c
++++ b/drivers/platform/chrome/cros_ec.c
+@@ -353,10 +353,16 @@ EXPORT_SYMBOL(cros_ec_suspend);
+
+ static void cros_ec_report_events_during_suspend(struct cros_ec_device *ec_dev)
+ {
++ bool wake_event;
++
+ while (ec_dev->mkbp_event_supported &&
+- cros_ec_get_next_event(ec_dev, NULL, NULL) > 0)
++ cros_ec_get_next_event(ec_dev, &wake_event, NULL) > 0) {
+ blocking_notifier_call_chain(&ec_dev->event_notifier,
+ 1, ec_dev);
++
++ if (wake_event && device_may_wakeup(ec_dev->dev))
++ pm_wakeup_event(ec_dev->dev, 0);
++ }
+ }
+
+ /**
+--
+2.35.1
+
--- /dev/null
+From 5d6f6ab554920d597d470b2bf310a9aa54174601 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 19:08:03 +0000
+Subject: platform/chrome: cros_ec_typec: Correct alt mode index
+
+From: Prashant Malani <pmalani@chromium.org>
+
+[ Upstream commit 4e477663e396f48c5cfc5f2d75d4b514f409516a ]
+
+Alt mode indices used by USB PD (Power Delivery) start with 1, not 0.
+
+Update the alt mdoe registration code to factor this in to the alt mode
+descriptor.
+
+Fixes: de0f49487db3 ("platform/chrome: cros_ec_typec: Register partner altmodes")
+Signed-off-by: Prashant Malani <pmalani@chromium.org>
+Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
+Link: https://lore.kernel.org/r/20220819190807.1275937-3-pmalani@chromium.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/chrome/cros_ec_typec.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
+index 4027c3ef90d7..aadb8d237aef 100644
+--- a/drivers/platform/chrome/cros_ec_typec.c
++++ b/drivers/platform/chrome/cros_ec_typec.c
+@@ -691,7 +691,7 @@ static int cros_typec_register_altmodes(struct cros_typec_data *typec, int port_
+ for (j = 0; j < sop_disc->svids[i].mode_count; j++) {
+ memset(&desc, 0, sizeof(desc));
+ desc.svid = sop_disc->svids[i].svid;
+- desc.mode = j;
++ desc.mode = j + 1;
+ desc.vdo = sop_disc->svids[i].mode_vdo[j];
+
+ if (is_partner)
+--
+2.35.1
+
--- /dev/null
+From fe7411d1e3320ebf1187135e53dc68db62eb15e4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 14 Aug 2022 01:08:43 +0300
+Subject: platform/chrome: fix double-free in chromeos_laptop_prepare()
+
+From: Rustam Subkhankulov <subkhankulov@ispras.ru>
+
+[ Upstream commit 6ad4194d6a1e1d11b285989cd648ef695b4a93c0 ]
+
+If chromeos_laptop_prepare_i2c_peripherals() fails after allocating memory
+for 'cros_laptop->i2c_peripherals', this memory is freed at 'err_out' label
+and nonzero value is returned. Then chromeos_laptop_destroy() is called,
+resulting in double-free error.
+
+Found by Linux Verification Center (linuxtesting.org) with SVACE.
+
+Signed-off-by: Rustam Subkhankulov <subkhankulov@ispras.ru>
+Fixes: 5020cd29d8bf ("platform/chrome: chromeos_laptop - supply properties for ACPI devices")
+Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
+Link: https://lore.kernel.org/r/20220813220843.2373004-1-subkhankulov@ispras.ru
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/chrome/chromeos_laptop.c | 24 ++++++++++++-----------
+ 1 file changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/platform/chrome/chromeos_laptop.c b/drivers/platform/chrome/chromeos_laptop.c
+index 4e14b4d6635d..a2cdbfbaeae6 100644
+--- a/drivers/platform/chrome/chromeos_laptop.c
++++ b/drivers/platform/chrome/chromeos_laptop.c
+@@ -740,6 +740,7 @@ static int __init
+ chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop,
+ const struct chromeos_laptop *src)
+ {
++ struct i2c_peripheral *i2c_peripherals;
+ struct i2c_peripheral *i2c_dev;
+ struct i2c_board_info *info;
+ int i;
+@@ -748,17 +749,15 @@ chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop,
+ if (!src->num_i2c_peripherals)
+ return 0;
+
+- cros_laptop->i2c_peripherals = kmemdup(src->i2c_peripherals,
+- src->num_i2c_peripherals *
+- sizeof(*src->i2c_peripherals),
+- GFP_KERNEL);
+- if (!cros_laptop->i2c_peripherals)
++ i2c_peripherals = kmemdup(src->i2c_peripherals,
++ src->num_i2c_peripherals *
++ sizeof(*src->i2c_peripherals),
++ GFP_KERNEL);
++ if (!i2c_peripherals)
+ return -ENOMEM;
+
+- cros_laptop->num_i2c_peripherals = src->num_i2c_peripherals;
+-
+- for (i = 0; i < cros_laptop->num_i2c_peripherals; i++) {
+- i2c_dev = &cros_laptop->i2c_peripherals[i];
++ for (i = 0; i < src->num_i2c_peripherals; i++) {
++ i2c_dev = &i2c_peripherals[i];
+ info = &i2c_dev->board_info;
+
+ error = chromeos_laptop_setup_irq(i2c_dev);
+@@ -775,16 +774,19 @@ chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop,
+ }
+ }
+
++ cros_laptop->i2c_peripherals = i2c_peripherals;
++ cros_laptop->num_i2c_peripherals = src->num_i2c_peripherals;
++
+ return 0;
+
+ err_out:
+ while (--i >= 0) {
+- i2c_dev = &cros_laptop->i2c_peripherals[i];
++ i2c_dev = &i2c_peripherals[i];
+ info = &i2c_dev->board_info;
+ if (!IS_ERR_OR_NULL(info->fwnode))
+ fwnode_remove_software_node(info->fwnode);
+ }
+- kfree(cros_laptop->i2c_peripherals);
++ kfree(i2c_peripherals);
+ return error;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 3ff39f9d68fce8c9a099672191f7ff778a5a524d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 08:20:36 +0300
+Subject: platform/chrome: fix memory corruption in ioctl
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 8a07b45fd3c2dda24fad43639be5335a4595196a ]
+
+If "s_mem.bytes" is larger than the buffer size it leads to memory
+corruption.
+
+Fixes: eda2e30c6684 ("mfd / platform: cros_ec: Miscellaneous character device to talk with the EC")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Guenter Roeck <groeck@chromium.org>
+Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
+Link: https://lore.kernel.org/r/Yv8dpCFZJdbUT5ye@kili
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/chrome/cros_ec_chardev.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/platform/chrome/cros_ec_chardev.c b/drivers/platform/chrome/cros_ec_chardev.c
+index fd33de546aee..0de7c255254e 100644
+--- a/drivers/platform/chrome/cros_ec_chardev.c
++++ b/drivers/platform/chrome/cros_ec_chardev.c
+@@ -327,6 +327,9 @@ static long cros_ec_chardev_ioctl_readmem(struct cros_ec_dev *ec,
+ if (copy_from_user(&s_mem, arg, sizeof(s_mem)))
+ return -EFAULT;
+
++ if (s_mem.bytes > sizeof(s_mem.buffer))
++ return -EINVAL;
++
+ num = ec_dev->cmd_readmem(ec_dev, s_mem.offset, s_mem.bytes,
+ s_mem.buffer);
+ if (num <= 0)
+--
+2.35.1
+
--- /dev/null
+From 832bddebc1df5c79d94ecf6d25b26ea5a804b0a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 23:04:07 +0200
+Subject: platform/x86: msi-laptop: Change DMI match / alias strings to fix
+ module autoloading
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit 2a2565272a3628e45d61625e36ef17af7af4e3de ]
+
+On a MSI S270 with Fedora 37 x86_64 / systemd-251.4 the module does not
+properly autoload.
+
+This is likely caused by issues with how systemd-udevd handles the single
+quote char (') which is part of the sys_vendor / chassis_vendor strings
+on this laptop. As a workaround remove the single quote char + everything
+behind it from the sys_vendor + chassis_vendor matches. This fixes
+the module not autoloading.
+
+Link: https://github.com/systemd/systemd/issues/24715
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://lore.kernel.org/r/20220917210407.647432-1-hdegoede@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/x86/msi-laptop.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c
+index 3e935303b143..0e804b6c2d24 100644
+--- a/drivers/platform/x86/msi-laptop.c
++++ b/drivers/platform/x86/msi-laptop.c
+@@ -596,11 +596,10 @@ static const struct dmi_system_id msi_dmi_table[] __initconst = {
+ {
+ .ident = "MSI S270",
+ .matches = {
+- DMI_MATCH(DMI_SYS_VENDOR, "MICRO-STAR INT'L CO.,LTD"),
++ DMI_MATCH(DMI_SYS_VENDOR, "MICRO-STAR INT"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "MS-1013"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "0131"),
+- DMI_MATCH(DMI_CHASSIS_VENDOR,
+- "MICRO-STAR INT'L CO.,LTD")
++ DMI_MATCH(DMI_CHASSIS_VENDOR, "MICRO-STAR INT")
+ },
+ .driver_data = &quirk_old_ec_model,
+ .callback = dmi_check_cb
+@@ -633,8 +632,7 @@ static const struct dmi_system_id msi_dmi_table[] __initconst = {
+ DMI_MATCH(DMI_SYS_VENDOR, "NOTEBOOK"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "SAM2000"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "0131"),
+- DMI_MATCH(DMI_CHASSIS_VENDOR,
+- "MICRO-STAR INT'L CO.,LTD")
++ DMI_MATCH(DMI_CHASSIS_VENDOR, "MICRO-STAR INT")
+ },
+ .driver_data = &quirk_old_ec_model,
+ .callback = dmi_check_cb
+--
+2.35.1
+
--- /dev/null
+From 56b0f8113ea3dd6b971f95ea3d3acb13a3483cd3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 16:13:34 +0200
+Subject: platform/x86: msi-laptop: Fix old-ec check for backlight registering
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit 83ac7a1c2ed5f17caa07cbbc84bad3c05dc3bf22 ]
+
+Commit 2cc6c717799f ("msi-laptop: Port to new backlight interface
+selection API") replaced this check:
+
+ if (!quirks->old_ec_model || acpi_video_backlight_support())
+ pr_info("Brightness ignored, ...");
+ else
+ do_register();
+
+With:
+
+ if (quirks->old_ec_model ||
+ acpi_video_get_backlight_type() == acpi_backlight_vendor)
+ do_register();
+
+But since the do_register() part was part of the else branch, the entire
+condition should be inverted. So not only the 2 statements on either
+side of the || should be inverted, but the || itself should be replaced
+with a &&.
+
+In practice this has likely not been an issue because the new-ec models
+(old_ec_model==false) likely all support ACPI video backlight control,
+making acpi_video_get_backlight_type() return acpi_backlight_video
+turning the second part of the || also false when old_ec_model == false.
+
+Fixes: 2cc6c717799f ("msi-laptop: Port to new backlight interface selection API")
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://lore.kernel.org/r/20220825141336.208597-1-hdegoede@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/x86/msi-laptop.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c
+index 24ffc8e2d2d1..0960205ee49f 100644
+--- a/drivers/platform/x86/msi-laptop.c
++++ b/drivers/platform/x86/msi-laptop.c
+@@ -1048,8 +1048,7 @@ static int __init msi_init(void)
+ return -EINVAL;
+
+ /* Register backlight stuff */
+-
+- if (quirks->old_ec_model ||
++ if (quirks->old_ec_model &&
+ acpi_video_get_backlight_type() == acpi_backlight_vendor) {
+ struct backlight_properties props;
+ memset(&props, 0, sizeof(struct backlight_properties));
+--
+2.35.1
+
--- /dev/null
+From 7a077af13a367a7301bbcc0ed30b6d0ccd0f845a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 16:13:36 +0200
+Subject: platform/x86: msi-laptop: Fix resource cleanup
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit 5523632aa10f906dfe2eb714ee748590dc7fc6b1 ]
+
+Fix the input-device not getting free-ed on probe-errors and
+fix the msi_touchpad_dwork not getting cancelled on neither
+probe-errors nor on remove.
+
+Fixes: 143a4c0284dc ("msi-laptop: send out touchpad on/off key")
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://lore.kernel.org/r/20220825141336.208597-3-hdegoede@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/platform/x86/msi-laptop.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c
+index 0960205ee49f..3e935303b143 100644
+--- a/drivers/platform/x86/msi-laptop.c
++++ b/drivers/platform/x86/msi-laptop.c
+@@ -1116,6 +1116,8 @@ static int __init msi_init(void)
+ fail_create_group:
+ if (quirks->load_scm_model) {
+ i8042_remove_filter(msi_laptop_i8042_filter);
++ cancel_delayed_work_sync(&msi_touchpad_dwork);
++ input_unregister_device(msi_laptop_input_dev);
+ cancel_delayed_work_sync(&msi_rfkill_dwork);
+ cancel_work_sync(&msi_rfkill_work);
+ rfkill_cleanup();
+@@ -1136,6 +1138,7 @@ static void __exit msi_cleanup(void)
+ {
+ if (quirks->load_scm_model) {
+ i8042_remove_filter(msi_laptop_i8042_filter);
++ cancel_delayed_work_sync(&msi_touchpad_dwork);
+ input_unregister_device(msi_laptop_input_dev);
+ cancel_delayed_work_sync(&msi_rfkill_dwork);
+ cancel_work_sync(&msi_rfkill_work);
+--
+2.35.1
+
--- /dev/null
+From e64677cfc03dffa85a4ce5d419d6103e9dc7f292 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 27 Aug 2022 07:32:23 +0000
+Subject: power: supply: adp5061: fix out-of-bounds read in
+ adp5061_get_chg_type()
+
+From: Wei Yongjun <weiyongjun1@huawei.com>
+
+[ Upstream commit 9d47e01b9d807808224347935562f7043a358054 ]
+
+ADP5061_CHG_STATUS_1_CHG_STATUS is masked with 0x07, which means a length
+of 8, but adp5061_chg_type array size is 4, may end up reading 4 elements
+beyond the end of the adp5061_chg_type[] array.
+
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Acked-by: Michael Hennerich <michael.hennerich@analog.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/power/supply/adp5061.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/power/supply/adp5061.c b/drivers/power/supply/adp5061.c
+index 003557043ab3..daee1161c305 100644
+--- a/drivers/power/supply/adp5061.c
++++ b/drivers/power/supply/adp5061.c
+@@ -427,11 +427,11 @@ static int adp5061_get_chg_type(struct adp5061_state *st,
+ if (ret < 0)
+ return ret;
+
+- chg_type = adp5061_chg_type[ADP5061_CHG_STATUS_1_CHG_STATUS(status1)];
+- if (chg_type > ADP5061_CHG_FAST_CV)
++ chg_type = ADP5061_CHG_STATUS_1_CHG_STATUS(status1);
++ if (chg_type >= ARRAY_SIZE(adp5061_chg_type))
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+ else
+- val->intval = chg_type;
++ val->intval = adp5061_chg_type[chg_type];
+
+ return ret;
+ }
+--
+2.35.1
+
--- /dev/null
+From 6460d3ed455caa19e40cb2b34e1f2dfa03f338a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 14:08:26 +0800
+Subject: powercap: intel_rapl: fix UBSAN shift-out-of-bounds issue
+
+From: Chao Qin <chao.qin@intel.com>
+
+[ Upstream commit 2d93540014387d1c73b9ccc4d7895320df66d01b ]
+
+When value < time_unit, the parameter of ilog2() will be zero and
+the return value is -1. u64(-1) is too large for shift exponent
+and then will trigger shift-out-of-bounds:
+
+shift exponent 18446744073709551615 is too large for 32-bit type 'int'
+Call Trace:
+ rapl_compute_time_window_core
+ rapl_write_data_raw
+ set_time_window
+ store_constraint_time_window_us
+
+Signed-off-by: Chao Qin <chao.qin@intel.com>
+Acked-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/powercap/intel_rapl_common.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
+index c87d4687aa67..9dfc053878fd 100644
+--- a/drivers/powercap/intel_rapl_common.c
++++ b/drivers/powercap/intel_rapl_common.c
+@@ -938,6 +938,9 @@ static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
+ y = value & 0x1f;
+ value = (1 << y) * (4 + f) * rp->time_unit / 4;
+ } else {
++ if (value < rp->time_unit)
++ return 0;
++
+ do_div(value, rp->time_unit);
+ y = ilog2(value);
+ f = div64_u64(4 * (value - (1 << y)), 1 << y);
+--
+2.35.1
+
--- /dev/null
+From 15a4becff3cc9c7a55ad178a2c4d8b0d90bbf10d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 11:41:02 +1000
+Subject: powerpc/64s: Fix GENERIC_CPU build flags for PPC970 / G5
+
+From: Nicholas Piggin <npiggin@gmail.com>
+
+[ Upstream commit 58ec7f06b74e0d6e76c4110afce367c8b5f0837d ]
+
+Big-endian GENERIC_CPU supports 970, but builds with -mcpu=power5.
+POWER5 is ISA v2.02 whereas 970 is v2.01 plus Altivec. 2.02 added
+the popcntb instruction which a compiler might use.
+
+Use -mcpu=power4.
+
+Fixes: 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")
+Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
+Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220921014103.587954-1-npiggin@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
+index 2bb0fe9b2058..7859ae56fcdc 100644
+--- a/arch/powerpc/Makefile
++++ b/arch/powerpc/Makefile
+@@ -154,7 +154,7 @@ CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power8
+ CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power9,-mtune=power8)
+ else
+ CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,$(call cc-option,-mtune=power5))
+-CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mcpu=power5,-mcpu=power4)
++CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power4
+ endif
+ else ifdef CONFIG_PPC_BOOK3E_64
+ CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64
+--
+2.35.1
+
--- /dev/null
+From 71668749307426002b7d4f29baffb913e387824a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 11:42:53 +1000
+Subject: powerpc/configs: Properly enable PAPR_SCM in pseries_defconfig
+
+From: Michael Ellerman <mpe@ellerman.id.au>
+
+[ Upstream commit aa398d88aea4ec863bd7aea35d5035a37096dc59 ]
+
+My commit to add PAPR_SCM to pseries_defconfig failed to add the
+required dependencies, meaning the driver doesn't get built.
+
+Add the required LIBNVDIMM=m.
+
+Fixes: d6481a7195df ("powerpc/configs: Add PAPR_SCM to pseries_defconfig")
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220901014253.252927-1-mpe@ellerman.id.au
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/configs/pseries_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
+index d0494fbb4961..6011977d43c9 100644
+--- a/arch/powerpc/configs/pseries_defconfig
++++ b/arch/powerpc/configs/pseries_defconfig
+@@ -41,6 +41,7 @@ CONFIG_DTL=y
+ CONFIG_SCANLOG=m
+ CONFIG_PPC_SMLPAR=y
+ CONFIG_IBMEBUS=y
++CONFIG_LIBNVDIMM=m
+ CONFIG_PAPR_SCM=m
+ CONFIG_PPC_SVM=y
+ # CONFIG_PPC_PMAC is not set
+--
+2.35.1
+
--- /dev/null
+From e0b0c16228f5840b02d684f6e522c89926421e26 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 16:55:48 +1000
+Subject: powerpc: Fix fallocate and fadvise64_64 compat parameter combination
+
+From: Rohan McLure <rmclure@linux.ibm.com>
+
+[ Upstream commit 016ff72bd2090903715c0f9422a44afbb966f4ee ]
+
+As reported[1] by Arnd, the arch-specific fadvise64_64 and fallocate
+compatibility handlers assume parameters are passed with 32-bit
+big-endian ABI. This affects the assignment of odd-even parameter pairs
+to the high or low words of a 64-bit syscall parameter.
+
+Fix fadvise64_64 fallocate compat handlers to correctly swap upper/lower
+32 bits conditioned on endianness.
+
+A future patch will replace the arch-specific compat fallocate with an
+asm-generic implementation. This patch is intended for ease of
+back-port.
+
+[1]: https://lore.kernel.org/all/be29926f-226e-48dc-871a-e29a54e80583@www.fastmail.com/
+
+Fixes: 57f48b4b74e7 ("powerpc/compat_sys: swap hi/lo parts of 64-bit syscall args in LE mode")
+Reported-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Rohan McLure <rmclure@linux.ibm.com>
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220921065605.1051927-9-rmclure@linux.ibm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/include/asm/syscalls.h | 12 ++++++++++++
+ arch/powerpc/kernel/sys_ppc32.c | 14 +-------------
+ arch/powerpc/kernel/syscalls.c | 4 ++--
+ 3 files changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/arch/powerpc/include/asm/syscalls.h b/arch/powerpc/include/asm/syscalls.h
+index 7ee66ae5444d..0e85d7aa395d 100644
+--- a/arch/powerpc/include/asm/syscalls.h
++++ b/arch/powerpc/include/asm/syscalls.h
+@@ -8,6 +8,18 @@
+ #include <linux/types.h>
+ #include <linux/compat.h>
+
++/*
++ * long long munging:
++ * The 32 bit ABI passes long longs in an odd even register pair.
++ * High and low parts are swapped depending on endian mode,
++ * so define a macro (similar to mips linux32) to handle that.
++ */
++#ifdef __LITTLE_ENDIAN__
++#define merge_64(low, high) (((u64)high << 32) | low)
++#else
++#define merge_64(high, low) (((u64)high << 32) | low)
++#endif
++
+ struct rtas_args;
+
+ asmlinkage long sys_mmap(unsigned long addr, size_t len,
+diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
+index 16ff0399a257..719bfc6d1e3f 100644
+--- a/arch/powerpc/kernel/sys_ppc32.c
++++ b/arch/powerpc/kernel/sys_ppc32.c
+@@ -56,18 +56,6 @@ unsigned long compat_sys_mmap2(unsigned long addr, size_t len,
+ return sys_mmap(addr, len, prot, flags, fd, pgoff << 12);
+ }
+
+-/*
+- * long long munging:
+- * The 32 bit ABI passes long longs in an odd even register pair.
+- * High and low parts are swapped depending on endian mode,
+- * so define a macro (similar to mips linux32) to handle that.
+- */
+-#ifdef __LITTLE_ENDIAN__
+-#define merge_64(low, high) ((u64)high << 32) | low
+-#else
+-#define merge_64(high, low) ((u64)high << 32) | low
+-#endif
+-
+ compat_ssize_t compat_sys_pread64(unsigned int fd, char __user *ubuf, compat_size_t count,
+ u32 reg6, u32 pos1, u32 pos2)
+ {
+@@ -94,7 +82,7 @@ asmlinkage int compat_sys_truncate64(const char __user * path, u32 reg4,
+ asmlinkage long compat_sys_fallocate(int fd, int mode, u32 offset1, u32 offset2,
+ u32 len1, u32 len2)
+ {
+- return ksys_fallocate(fd, mode, ((loff_t)offset1 << 32) | offset2,
++ return ksys_fallocate(fd, mode, merge_64(offset1, offset2),
+ merge_64(len1, len2));
+ }
+
+diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
+index 825931e400df..e3edcf8f7cae 100644
+--- a/arch/powerpc/kernel/syscalls.c
++++ b/arch/powerpc/kernel/syscalls.c
+@@ -99,8 +99,8 @@ long ppc64_personality(unsigned long personality)
+ long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low,
+ u32 len_high, u32 len_low)
+ {
+- return ksys_fadvise64_64(fd, (u64)offset_high << 32 | offset_low,
+- (u64)len_high << 32 | len_low, advice);
++ return ksys_fadvise64_64(fd, merge_64(offset_high, offset_low),
++ merge_64(len_high, len_low), advice);
+ }
+
+ SYSCALL_DEFINE0(switch_endian)
+--
+2.35.1
+
--- /dev/null
+From 0cef6572b45e8c73b9ecd990031f00a79a1cb608 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 23:21:02 +0200
+Subject: powerpc: Fix SPE Power ISA properties for e500v1 platforms
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Pali Rohár <pali@kernel.org>
+
+[ Upstream commit 37b9345ce7f4ab17538ea62def6f6d430f091355 ]
+
+Commit 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply
+with ePAPR 1.1") introduced new include file e500v2_power_isa.dtsi and
+should have used it for all e500v2 platforms. But apparently it was used
+also for e500v1 platforms mpc8540, mpc8541, mpc8555 and mpc8560.
+
+e500v1 cores compared to e500v2 do not support double precision floating
+point SPE instructions. Hence power-isa-sp.fd should not be set on e500v1
+platforms, which is in e500v2_power_isa.dtsi include file.
+
+Fix this issue by introducing a new e500v1_power_isa.dtsi include file and
+use it in all e500v1 device tree files.
+
+Fixes: 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1")
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220902212103.22534-1-pali@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../boot/dts/fsl/e500v1_power_isa.dtsi | 51 +++++++++++++++++++
+ arch/powerpc/boot/dts/fsl/mpc8540ads.dts | 2 +-
+ arch/powerpc/boot/dts/fsl/mpc8541cds.dts | 2 +-
+ arch/powerpc/boot/dts/fsl/mpc8555cds.dts | 2 +-
+ arch/powerpc/boot/dts/fsl/mpc8560ads.dts | 2 +-
+ 5 files changed, 55 insertions(+), 4 deletions(-)
+ create mode 100644 arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi
+
+diff --git a/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi
+new file mode 100644
+index 000000000000..7e2a90cde72e
+--- /dev/null
++++ b/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi
+@@ -0,0 +1,51 @@
++/*
++ * e500v1 Power ISA Device Tree Source (include)
++ *
++ * Copyright 2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Freescale Semiconductor nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/ {
++ cpus {
++ power-isa-version = "2.03";
++ power-isa-b; // Base
++ power-isa-e; // Embedded
++ power-isa-atb; // Alternate Time Base
++ power-isa-cs; // Cache Specification
++ power-isa-e.le; // Embedded.Little-Endian
++ power-isa-e.pm; // Embedded.Performance Monitor
++ power-isa-ecl; // Embedded Cache Locking
++ power-isa-mmc; // Memory Coherence
++ power-isa-sp; // Signal Processing Engine
++ power-isa-sp.fs; // SPE.Embedded Float Scalar Single
++ power-isa-sp.fv; // SPE.Embedded Float Vector
++ mmu-type = "power-embedded";
++ };
++};
+diff --git a/arch/powerpc/boot/dts/fsl/mpc8540ads.dts b/arch/powerpc/boot/dts/fsl/mpc8540ads.dts
+index 18a885130538..e03ae130162b 100644
+--- a/arch/powerpc/boot/dts/fsl/mpc8540ads.dts
++++ b/arch/powerpc/boot/dts/fsl/mpc8540ads.dts
+@@ -7,7 +7,7 @@
+
+ /dts-v1/;
+
+-/include/ "e500v2_power_isa.dtsi"
++/include/ "e500v1_power_isa.dtsi"
+
+ / {
+ model = "MPC8540ADS";
+diff --git a/arch/powerpc/boot/dts/fsl/mpc8541cds.dts b/arch/powerpc/boot/dts/fsl/mpc8541cds.dts
+index ac381e7b1c60..a2a6c5cf852e 100644
+--- a/arch/powerpc/boot/dts/fsl/mpc8541cds.dts
++++ b/arch/powerpc/boot/dts/fsl/mpc8541cds.dts
+@@ -7,7 +7,7 @@
+
+ /dts-v1/;
+
+-/include/ "e500v2_power_isa.dtsi"
++/include/ "e500v1_power_isa.dtsi"
+
+ / {
+ model = "MPC8541CDS";
+diff --git a/arch/powerpc/boot/dts/fsl/mpc8555cds.dts b/arch/powerpc/boot/dts/fsl/mpc8555cds.dts
+index 9f58db2a7e66..901b6ff06dfb 100644
+--- a/arch/powerpc/boot/dts/fsl/mpc8555cds.dts
++++ b/arch/powerpc/boot/dts/fsl/mpc8555cds.dts
+@@ -7,7 +7,7 @@
+
+ /dts-v1/;
+
+-/include/ "e500v2_power_isa.dtsi"
++/include/ "e500v1_power_isa.dtsi"
+
+ / {
+ model = "MPC8555CDS";
+diff --git a/arch/powerpc/boot/dts/fsl/mpc8560ads.dts b/arch/powerpc/boot/dts/fsl/mpc8560ads.dts
+index a24722ccaebf..c2f9aea78b29 100644
+--- a/arch/powerpc/boot/dts/fsl/mpc8560ads.dts
++++ b/arch/powerpc/boot/dts/fsl/mpc8560ads.dts
+@@ -7,7 +7,7 @@
+
+ /dts-v1/;
+
+-/include/ "e500v2_power_isa.dtsi"
++/include/ "e500v1_power_isa.dtsi"
+
+ / {
+ model = "MPC8560ADS";
+--
+2.35.1
+
--- /dev/null
+From 4a2b2cbb41285b2434273ffa455e6dc1c9eab44a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Sep 2022 17:32:53 +0800
+Subject: powerpc/kprobes: Fix null pointer reference in arch_prepare_kprobe()
+
+From: Li Huafei <lihuafei1@huawei.com>
+
+[ Upstream commit 97f88a3d723162781d6cbfdc7b9617eefab55b19 ]
+
+I found a null pointer reference in arch_prepare_kprobe():
+
+ # echo 'p cmdline_proc_show' > kprobe_events
+ # echo 'p cmdline_proc_show+16' >> kprobe_events
+ Kernel attempted to read user page (0) - exploit attempt? (uid: 0)
+ BUG: Kernel NULL pointer dereference on read at 0x00000000
+ Faulting instruction address: 0xc000000000050bfc
+ Oops: Kernel access of bad area, sig: 11 [#1]
+ LE PAGE_SIZE=64K MMU=Radix SMP NR_CPUS=2048 NUMA PowerNV
+ Modules linked in:
+ CPU: 0 PID: 122 Comm: sh Not tainted 6.0.0-rc3-00007-gdcf8e5633e2e #10
+ NIP: c000000000050bfc LR: c000000000050bec CTR: 0000000000005bdc
+ REGS: c0000000348475b0 TRAP: 0300 Not tainted (6.0.0-rc3-00007-gdcf8e5633e2e)
+ MSR: 9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE> CR: 88002444 XER: 20040006
+ CFAR: c00000000022d100 DAR: 0000000000000000 DSISR: 40000000 IRQMASK: 0
+ ...
+ NIP arch_prepare_kprobe+0x10c/0x2d0
+ LR arch_prepare_kprobe+0xfc/0x2d0
+ Call Trace:
+ 0xc0000000012f77a0 (unreliable)
+ register_kprobe+0x3c0/0x7a0
+ __register_trace_kprobe+0x140/0x1a0
+ __trace_kprobe_create+0x794/0x1040
+ trace_probe_create+0xc4/0xe0
+ create_or_delete_trace_kprobe+0x2c/0x80
+ trace_parse_run_command+0xf0/0x210
+ probes_write+0x20/0x40
+ vfs_write+0xfc/0x450
+ ksys_write+0x84/0x140
+ system_call_exception+0x17c/0x3a0
+ system_call_vectored_common+0xe8/0x278
+ --- interrupt: 3000 at 0x7fffa5682de0
+ NIP: 00007fffa5682de0 LR: 0000000000000000 CTR: 0000000000000000
+ REGS: c000000034847e80 TRAP: 3000 Not tainted (6.0.0-rc3-00007-gdcf8e5633e2e)
+ MSR: 900000000280f033 <SF,HV,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE> CR: 44002408 XER: 00000000
+
+The address being probed has some special:
+
+ cmdline_proc_show: Probe based on ftrace
+ cmdline_proc_show+16: Probe for the next instruction at the ftrace location
+
+The ftrace-based kprobe does not generate kprobe::ainsn::insn, it gets
+set to NULL. In arch_prepare_kprobe() it will check for:
+
+ ...
+ prev = get_kprobe(p->addr - 1);
+ preempt_enable_no_resched();
+ if (prev && ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) {
+ ...
+
+If prev is based on ftrace, 'ppc_inst_read(prev->ainsn.insn)' will occur
+with a null pointer reference. At this point prev->addr will not be a
+prefixed instruction, so the check can be skipped.
+
+Check if prev is ftrace-based kprobe before reading 'prev->ainsn.insn'
+to fix this problem.
+
+Fixes: b4657f7650ba ("powerpc/kprobes: Don't allow breakpoints on suffixes")
+Signed-off-by: Li Huafei <lihuafei1@huawei.com>
+[mpe: Trim oops]
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220923093253.177298-1-lihuafei1@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/kernel/kprobes.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
+index 7a7cd6bda53e..61552f57db0b 100644
+--- a/arch/powerpc/kernel/kprobes.c
++++ b/arch/powerpc/kernel/kprobes.c
+@@ -140,7 +140,13 @@ int arch_prepare_kprobe(struct kprobe *p)
+ preempt_disable();
+ prev = get_kprobe(p->addr - 1);
+ preempt_enable_no_resched();
+- if (prev && ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) {
++
++ /*
++ * When prev is a ftrace-based kprobe, we don't have an insn, and it
++ * doesn't probe for prefixed instruction.
++ */
++ if (prev && !kprobe_ftrace(prev) &&
++ ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) {
+ printk("Cannot register a kprobe on the second word of prefixed instruction\n");
+ ret = -EINVAL;
+ }
+--
+2.35.1
+
--- /dev/null
+From 39d366683a27f693e726d51c1a21c156e7e29c99 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 18:00:08 +0200
+Subject: powerpc/math_emu/efp: Include module.h
+
+From: Nathan Chancellor <nathan@kernel.org>
+
+[ Upstream commit cfe0d370e0788625ce0df3239aad07a2506c1796 ]
+
+When building with a recent version of clang, there are a couple of
+errors around the call to module_init():
+
+ arch/powerpc/math-emu/math_efp.c:927:1: error: type specifier missing, defaults to 'int'; ISO C99 and later do not support implicit int [-Wimplicit-int]
+ module_init(spe_mathemu_init);
+ ^
+ int
+ arch/powerpc/math-emu/math_efp.c:927:13: error: a parameter list without types is only allowed in a function definition
+ module_init(spe_mathemu_init);
+ ^
+ 2 errors generated.
+
+module_init() is a macro, which is not getting expanded because module.h
+is not included in this file. Add the include so that the macro can
+expand properly, clearing up the build failure.
+
+Fixes: ac6f120369ff ("powerpc/85xx: Workaroudn e500 CPU erratum A005")
+[chleroy: added fixes tag]
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Nathan Chancellor <nathan@kernel.org>
+Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Link: https://lore.kernel.org/r/8403854a4c187459b2f4da3537f51227b70b9223.1662134272.git.christophe.leroy@csgroup.eu
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/math-emu/math_efp.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c
+index 39b84e7452e1..aa3bb8da1cb9 100644
+--- a/arch/powerpc/math-emu/math_efp.c
++++ b/arch/powerpc/math-emu/math_efp.c
+@@ -17,6 +17,7 @@
+
+ #include <linux/types.h>
+ #include <linux/prctl.h>
++#include <linux/module.h>
+
+ #include <linux/uaccess.h>
+ #include <asm/reg.h>
+--
+2.35.1
+
--- /dev/null
+From 55e82bb9b1626a6b206f1207ea356886c1d0f63e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 1 Jul 2022 21:17:50 +0800
+Subject: powerpc/pci_dn: Add missing of_node_put()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 110a1fcb6c4d55144d8179983a475f17a1d6f832 ]
+
+In pci_add_device_node_info(), use of_node_put() to drop the reference
+to 'parent' returned by of_get_parent() to keep refcount balance.
+
+Fixes: cca87d303c85 ("powerpc/pci: Refactor pci_dn")
+Co-authored-by: Miaoqian Lin <linmq006@gmail.com>
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Reviewed-by: Tyrel Datwyler <tyreld@linux.ibm.com>
+Link: https://lore.kernel.org/r/20220701131750.240170-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/kernel/pci_dn.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
+index 61571ae23953..335767cea137 100644
+--- a/arch/powerpc/kernel/pci_dn.c
++++ b/arch/powerpc/kernel/pci_dn.c
+@@ -330,6 +330,7 @@ struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
+ INIT_LIST_HEAD(&pdn->list);
+ parent = of_get_parent(dn);
+ pdn->parent = parent ? PCI_DN(parent) : NULL;
++ of_node_put(parent);
+ if (pdn->parent)
+ list_add_tail(&pdn->list, &pdn->parent->child_list);
+
+--
+2.35.1
+
--- /dev/null
+From 5eb344e9e0f28d1a61833fb1ea173dc0cadd5633 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 14:17:03 +0000
+Subject: powerpc/powernv: add missing of_node_put() in opal_export_attrs()
+
+From: Zheng Yongjun <zhengyongjun3@huawei.com>
+
+[ Upstream commit 71a92e99c47900cc164620948b3863382cec4f1a ]
+
+After using 'np' returned by of_find_node_by_path(), of_node_put()
+need be called to decrease the refcount.
+
+Fixes: 11fe909d2362 ("powerpc/powernv: Add OPAL exports attributes to sysfs")
+Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220906141703.118192-1-zhengyongjun3@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/platforms/powernv/opal.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
+index e9d18519e650..5178ec6f3715 100644
+--- a/arch/powerpc/platforms/powernv/opal.c
++++ b/arch/powerpc/platforms/powernv/opal.c
+@@ -892,6 +892,7 @@ static void opal_export_attrs(void)
+ kobj = kobject_create_and_add("exports", opal_kobj);
+ if (!kobj) {
+ pr_warn("kobject_create_and_add() of exports failed\n");
++ of_node_put(np);
+ return;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From ea24b34d2a24bc9ce4c4fff3859015b078e10e95 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 18:57:33 -0700
+Subject: powerpc/pseries/vas: Pass hw_cpu_id to node associativity HCALL
+
+From: Haren Myneni <haren@linux.ibm.com>
+
+[ Upstream commit f3e5d9e53e74d77e711a2c90a91a8b0836a9e0b3 ]
+
+Generally the hypervisor decides to allocate a window on different
+VAS instances. But if user space wishes to allocate on the current VAS
+instance where the process is executing, the kernel has to pass
+associativity domain IDs to allocate VAS window HCALL.
+
+To determine the associativity domain IDs for the current CPU,
+smp_processor_id() is passed to node associativity HCALL which may
+return H_P2 (-55) error during DLPAR CPU event. This is because Linux
+CPU numbers (smp_processor_id()) are not the same as the hypervisor's
+view of CPU numbers.
+
+Fix the issue by passing hard_smp_processor_id() with
+VPHN_FLAG_VCPU flag (PAPR 14.11.6.1 H_HOME_NODE_ASSOCIATIVITY).
+
+Fixes: b22f2d88e435 ("powerpc/pseries/vas: Integrate API with open/close windows")
+Reviewed-by: Nathan Lynch <nathanl@linux.ibm.com>
+Signed-off-by: Haren Myneni <haren@linux.ibm.com>
+[mpe: Update change log to mention Linux vs HV CPU numbers]
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/55380253ea0c11341824cd4c0fc6bbcfc5752689.camel@linux.ibm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/platforms/pseries/vas.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/powerpc/platforms/pseries/vas.c b/arch/powerpc/platforms/pseries/vas.c
+index b043e3936d21..15046d80f042 100644
+--- a/arch/powerpc/platforms/pseries/vas.c
++++ b/arch/powerpc/platforms/pseries/vas.c
+@@ -324,7 +324,7 @@ static struct vas_window *vas_allocate_window(int vas_id, u64 flags,
+ * So no unpacking needs to be done.
+ */
+ rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, domain,
+- VPHN_FLAG_VCPU, smp_processor_id());
++ VPHN_FLAG_VCPU, hard_smp_processor_id());
+ if (rc != H_SUCCESS) {
+ pr_err("H_HOME_NODE_ASSOCIATIVITY error: %d\n", rc);
+ goto out;
+--
+2.35.1
+
--- /dev/null
+From fd77c8e4dc2c6fbc1639c98355475e751b5fde68 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Jul 2022 22:52:33 +0800
+Subject: powerpc/sysdev/fsl_msi: Add missing of_node_put()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit def435c04ee984a5f9ed2711b2bfe946936c6a21 ]
+
+In fsl_setup_msi_irqs(), use of_node_put() to drop the reference
+returned by of_parse_phandle().
+
+Fixes: 895d603f945ba ("powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes")
+Co-authored-by: Miaoqian Lin <linmq006@gmail.com>
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20220704145233.278539-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/sysdev/fsl_msi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
+index e6b06c3f8197..c55ccec0a169 100644
+--- a/arch/powerpc/sysdev/fsl_msi.c
++++ b/arch/powerpc/sysdev/fsl_msi.c
+@@ -211,8 +211,10 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
+ dev_err(&pdev->dev,
+ "node %pOF has an invalid fsl,msi phandle %u\n",
+ hose->dn, np->phandle);
++ of_node_put(np);
+ return -EINVAL;
+ }
++ of_node_put(np);
+ }
+
+ for_each_pci_msi_entry(entry, pdev) {
+--
+2.35.1
+
--- /dev/null
+From 2665e2c6824ad9df65eac8fa9d51136655e78b3d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 2 Oct 2022 12:41:28 +0900
+Subject: r8152: Rate limit overflow messages
+
+From: Andrew Gaul <gaul@gaul.org>
+
+[ Upstream commit 93e2be344a7db169b7119de21ac1bf253b8c6907 ]
+
+My system shows almost 10 million of these messages over a 24-hour
+period which pollutes my logs.
+
+Signed-off-by: Andrew Gaul <gaul@google.com>
+Link: https://lore.kernel.org/r/20221002034128.2026653-1-gaul@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/usb/r8152.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index 7e821bed91ce..c7169243aa6e 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -1871,7 +1871,9 @@ static void intr_callback(struct urb *urb)
+ "Stop submitting intr, status %d\n", status);
+ return;
+ case -EOVERFLOW:
+- netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
++ if (net_ratelimit())
++ netif_info(tp, intr, tp->netdev,
++ "intr status -EOVERFLOW\n");
+ goto resubmit;
+ /* -EPIPE: should clear the halt */
+ default:
+--
+2.35.1
+
--- /dev/null
+From 6e52e20495bd70094395b240998a71f4a9b9fb7f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Aug 2022 10:26:26 +0800
+Subject: rcu: Avoid triggering strict-GP irq-work when RCU is idle
+
+From: Zqiang <qiang1.zhang@intel.com>
+
+[ Upstream commit 621189a1fe93cb2b34d62c5cdb9e258bca044813 ]
+
+Kernels built with PREEMPT_RCU=y and RCU_STRICT_GRACE_PERIOD=y trigger
+irq-work from rcu_read_unlock(), and the resulting irq-work handler
+invokes rcu_preempt_deferred_qs_handle(). The point of this triggering
+is to force grace periods to end quickly in order to give tools like KASAN
+a better chance of detecting RCU usage bugs such as leaking RCU-protected
+pointers out of an RCU read-side critical section.
+
+However, this irq-work triggering is unconditional. This works, but
+there is no point in doing this irq-work unless the current grace period
+is waiting on the running CPU or task, which is not the common case.
+After all, in the common case there are many rcu_read_unlock() calls
+per CPU per grace period.
+
+This commit therefore triggers the irq-work only when the current grace
+period is waiting on the running CPU or task.
+
+This change was tested as follows on a four-CPU system:
+
+ echo rcu_preempt_deferred_qs_handler > /sys/kernel/debug/tracing/set_ftrace_filter
+ echo 1 > /sys/kernel/debug/tracing/function_profile_enabled
+ insmod rcutorture.ko
+ sleep 20
+ rmmod rcutorture.ko
+ echo 0 > /sys/kernel/debug/tracing/function_profile_enabled
+ echo > /sys/kernel/debug/tracing/set_ftrace_filter
+
+This procedure produces results in this per-CPU set of files:
+
+ /sys/kernel/debug/tracing/trace_stat/function*
+
+Sample output from one of these files is as follows:
+
+ Function Hit Time Avg s^2
+ -------- --- ---- --- ---
+ rcu_preempt_deferred_qs_handle 838746 182650.3 us 0.217 us 0.004 us
+
+The baseline sum of the "Hit" values (the number of calls to this
+function) was 3,319,015. With this commit, that sum was 1,140,359,
+for a 2.9x reduction. The worst-case variance across the CPUs was less
+than 25%, so this large effect size is statistically significant.
+
+The raw data is available in the Link: URL.
+
+Link: https://lore.kernel.org/all/20220808022626.12825-1-qiang1.zhang@intel.com/
+Signed-off-by: Zqiang <qiang1.zhang@intel.com>
+Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/rcu/tree_plugin.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h
+index ef2dd131e955..f1a73a1f8472 100644
+--- a/kernel/rcu/tree_plugin.h
++++ b/kernel/rcu/tree_plugin.h
+@@ -638,7 +638,8 @@ static void rcu_read_unlock_special(struct task_struct *t)
+
+ expboost = (t->rcu_blocked_node && READ_ONCE(t->rcu_blocked_node->exp_tasks)) ||
+ (rdp->grpmask & READ_ONCE(rnp->expmask)) ||
+- IS_ENABLED(CONFIG_RCU_STRICT_GRACE_PERIOD) ||
++ (IS_ENABLED(CONFIG_RCU_STRICT_GRACE_PERIOD) &&
++ ((rdp->grpmask & READ_ONCE(rnp->qsmask)) || t->rcu_blocked_node)) ||
+ (IS_ENABLED(CONFIG_RCU_BOOST) && irqs_were_disabled &&
+ t->rcu_blocked_node);
+ // Need to defer quiescent state until everything is enabled.
+--
+2.35.1
+
--- /dev/null
+From fec7f1370335e581a69364b3643c5d0406717771 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 13:47:11 +0200
+Subject: rcu: Back off upon fill_page_cache_func() allocation failure
+
+From: Michal Hocko <mhocko@suse.com>
+
+[ Upstream commit 093590c16b447f53e66771c8579ae66c96f6ef61 ]
+
+The fill_page_cache_func() function allocates couple of pages to store
+kvfree_rcu_bulk_data structures. This is a lightweight (GFP_NORETRY)
+allocation which can fail under memory pressure. The function will,
+however keep retrying even when the previous attempt has failed.
+
+This retrying is in theory correct, but in practice the allocation is
+invoked from workqueue context, which means that if the memory reclaim
+gets stuck, these retries can hog the worker for quite some time.
+Although the workqueues subsystem automatically adjusts concurrency, such
+adjustment is not guaranteed to happen until the worker context sleeps.
+And the fill_page_cache_func() function's retry loop is not guaranteed
+to sleep (see the should_reclaim_retry() function).
+
+And we have seen this function cause workqueue lockups:
+
+kernel: BUG: workqueue lockup - pool cpus=93 node=1 flags=0x1 nice=0 stuck for 32s!
+[...]
+kernel: pool 74: cpus=37 node=0 flags=0x1 nice=0 hung=32s workers=2 manager: 2146
+kernel: pwq 498: cpus=249 node=1 flags=0x1 nice=0 active=4/256 refcnt=5
+kernel: in-flight: 1917:fill_page_cache_func
+kernel: pending: dbs_work_handler, free_work, kfree_rcu_monitor
+
+Originally, we thought that the root cause of this lockup was several
+retries with direct reclaim, but this is not yet confirmed. Furthermore,
+we have seen similar lockups without any heavy memory pressure. This
+suggests that there are other factors contributing to these lockups.
+However, it is not really clear that endless retries are desireable.
+
+So let's make the fill_page_cache_func() function back off after
+allocation failure.
+
+Cc: Uladzislau Rezki (Sony) <urezki@gmail.com>
+Cc: "Paul E. McKenney" <paulmck@kernel.org>
+Cc: Frederic Weisbecker <frederic@kernel.org>
+Cc: Neeraj Upadhyay <quic_neeraju@quicinc.com>
+Cc: Josh Triplett <josh@joshtriplett.org>
+Cc: Steven Rostedt <rostedt@goodmis.org>
+Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
+Cc: Lai Jiangshan <jiangshanlai@gmail.com>
+Cc: Joel Fernandes <joel@joelfernandes.org>
+Signed-off-by: Michal Hocko <mhocko@suse.com>
+Reviewed-by: Uladzislau Rezki (Sony) <urezki@gmail.com>
+Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/rcu/tree.c | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
+index a4a9d68b1fdc..63f7ce228cc3 100644
+--- a/kernel/rcu/tree.c
++++ b/kernel/rcu/tree.c
+@@ -3419,15 +3419,16 @@ static void fill_page_cache_func(struct work_struct *work)
+ bnode = (struct kvfree_rcu_bulk_data *)
+ __get_free_page(GFP_KERNEL | __GFP_NORETRY | __GFP_NOMEMALLOC | __GFP_NOWARN);
+
+- if (bnode) {
+- raw_spin_lock_irqsave(&krcp->lock, flags);
+- pushed = put_cached_bnode(krcp, bnode);
+- raw_spin_unlock_irqrestore(&krcp->lock, flags);
++ if (!bnode)
++ break;
+
+- if (!pushed) {
+- free_page((unsigned long) bnode);
+- break;
+- }
++ raw_spin_lock_irqsave(&krcp->lock, flags);
++ pushed = put_cached_bnode(krcp, bnode);
++ raw_spin_unlock_irqrestore(&krcp->lock, flags);
++
++ if (!pushed) {
++ free_page((unsigned long) bnode);
++ break;
+ }
+ }
+
+--
+2.35.1
+
--- /dev/null
+From e7f9fad5c008f2b361b2db2a1489818d3f6e15e8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Jul 2022 16:26:05 +0800
+Subject: rcu-tasks: Convert RCU_LOCKDEP_WARN() to WARN_ONCE()
+
+From: Zqiang <qiang1.zhang@intel.com>
+
+[ Upstream commit fcd53c8a4dfa38bafb89efdd0b0f718f3a03f884 ]
+
+Kernels built with CONFIG_PROVE_RCU=y and CONFIG_DEBUG_LOCK_ALLOC=y
+attempt to emit a warning when the synchronize_rcu_tasks_generic()
+function is called during early boot while the rcu_scheduler_active
+variable is RCU_SCHEDULER_INACTIVE. However the warnings is not
+actually be printed because the debug_lockdep_rcu_enabled() returns
+false, exactly because the rcu_scheduler_active variable is still equal
+to RCU_SCHEDULER_INACTIVE.
+
+This commit therefore replaces RCU_LOCKDEP_WARN() with WARN_ONCE()
+to force these warnings to actually be printed.
+
+Signed-off-by: Zqiang <qiang1.zhang@intel.com>
+Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/rcu/tasks.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h
+index 60c9eacac25b..ae8396032b5d 100644
+--- a/kernel/rcu/tasks.h
++++ b/kernel/rcu/tasks.h
+@@ -171,7 +171,7 @@ static void call_rcu_tasks_generic(struct rcu_head *rhp, rcu_callback_t func,
+ static void synchronize_rcu_tasks_generic(struct rcu_tasks *rtp)
+ {
+ /* Complain if the scheduler has not started. */
+- RCU_LOCKDEP_WARN(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE,
++ WARN_ONCE(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE,
+ "synchronize_rcu_tasks called too soon");
+
+ /* Wait for the grace period. */
+--
+2.35.1
+
--- /dev/null
+From 25e78dfb2901a6a86abd2aee74f95c779e535566 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 13:09:02 +0300
+Subject: RDMA/cm: Use SLID in the work completion as the DLID in responder
+ side
+
+From: Mark Zhang <markzhang@nvidia.com>
+
+[ Upstream commit b7d95040c13f61a4a6a859c5355faf583eff9658 ]
+
+The responder should always use WC's SLID as the dlid, to follow the
+IB SPEC section "13.5.4.2 COMMON RESPONSE ACTIONS":
+A responder always takes the following actions in constructing a
+response packet:
+- The SLID of the received packet is used as the DLID in the response
+ packet.
+
+Fixes: ac3a949fb2ff ("IB/CM: Set appropriate slid and dlid when handling CM request")
+Signed-off-by: Mark Zhang <markzhang@nvidia.com>
+Reviewed-by: Mark Bloch <mbloch@nvidia.com>
+Link: https://lore.kernel.org/r/cd17c240231e059d2fc07c17dfe555d548b917eb.1662631201.git.leonro@nvidia.com
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/core/cm.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
+index b985e0d9bc05..5c910f5c01b3 100644
+--- a/drivers/infiniband/core/cm.c
++++ b/drivers/infiniband/core/cm.c
+@@ -1632,14 +1632,13 @@ static void cm_path_set_rec_type(struct ib_device *ib_device, u32 port_num,
+
+ static void cm_format_path_lid_from_req(struct cm_req_msg *req_msg,
+ struct sa_path_rec *primary_path,
+- struct sa_path_rec *alt_path)
++ struct sa_path_rec *alt_path,
++ struct ib_wc *wc)
+ {
+ u32 lid;
+
+ if (primary_path->rec_type != SA_PATH_REC_TYPE_OPA) {
+- sa_path_set_dlid(primary_path,
+- IBA_GET(CM_REQ_PRIMARY_LOCAL_PORT_LID,
+- req_msg));
++ sa_path_set_dlid(primary_path, wc->slid);
+ sa_path_set_slid(primary_path,
+ IBA_GET(CM_REQ_PRIMARY_REMOTE_PORT_LID,
+ req_msg));
+@@ -1676,7 +1675,8 @@ static void cm_format_path_lid_from_req(struct cm_req_msg *req_msg,
+
+ static void cm_format_paths_from_req(struct cm_req_msg *req_msg,
+ struct sa_path_rec *primary_path,
+- struct sa_path_rec *alt_path)
++ struct sa_path_rec *alt_path,
++ struct ib_wc *wc)
+ {
+ primary_path->dgid =
+ *IBA_GET_MEM_PTR(CM_REQ_PRIMARY_LOCAL_PORT_GID, req_msg);
+@@ -1734,7 +1734,7 @@ static void cm_format_paths_from_req(struct cm_req_msg *req_msg,
+ if (sa_path_is_roce(alt_path))
+ alt_path->roce.route_resolved = false;
+ }
+- cm_format_path_lid_from_req(req_msg, primary_path, alt_path);
++ cm_format_path_lid_from_req(req_msg, primary_path, alt_path, wc);
+ }
+
+ static u16 cm_get_bth_pkey(struct cm_work *work)
+@@ -2148,7 +2148,7 @@ static int cm_req_handler(struct cm_work *work)
+ if (cm_req_has_alt_path(req_msg))
+ work->path[1].rec_type = work->path[0].rec_type;
+ cm_format_paths_from_req(req_msg, &work->path[0],
+- &work->path[1]);
++ &work->path[1], work->mad_recv_wc->wc);
+ if (cm_id_priv->av.ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE)
+ sa_path_set_dmac(&work->path[0],
+ cm_id_priv->av.ah_attr.roce.dmac);
+--
+2.35.1
+
--- /dev/null
+From 474f5c316a86d5f4da9443e086fc290d1f6ad99b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 14:13:23 -0500
+Subject: RDMA/irdma: Align AE id codes to correct flush code and event
+
+From: Sindhu-Devale <sindhu.devale@intel.com>
+
+[ Upstream commit 7f51a961f8c6b84752a48e950074a8c4a0808d91 ]
+
+A number of asynchronous event (AE) ids were not aligned to the
+correct flush_code and event_type. Fix these up so that the
+correct IBV error and event codes are returned to application.
+
+Also, add handling for new AE ids like IRDMA_AE_INVALID_REQUEST to
+return the correct WC error code.
+
+Fixes: 44d9e52977a1 ("RDMA/irdma: Implement device initialization definitions")
+Signed-off-by: Sindhu-Devale <sindhu.devale@intel.com>
+Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com>
+Link: https://lore.kernel.org/r/20220907191324.1173-2-shiraz.saleem@intel.com
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/irdma/defs.h | 1 +
+ drivers/infiniband/hw/irdma/hw.c | 51 +++++++++++++++++------------
+ drivers/infiniband/hw/irdma/type.h | 1 +
+ drivers/infiniband/hw/irdma/user.h | 1 +
+ drivers/infiniband/hw/irdma/utils.c | 3 ++
+ drivers/infiniband/hw/irdma/verbs.c | 2 ++
+ 6 files changed, 38 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/infiniband/hw/irdma/defs.h b/drivers/infiniband/hw/irdma/defs.h
+index cc3d9a365b35..b8c10a6ccede 100644
+--- a/drivers/infiniband/hw/irdma/defs.h
++++ b/drivers/infiniband/hw/irdma/defs.h
+@@ -314,6 +314,7 @@ enum irdma_cqp_op_type {
+ #define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d
+ #define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e
+ #define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220
++#define IRDMA_AE_INVALID_REQUEST 0x0223
+ #define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
+ #define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
+ #define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
+diff --git a/drivers/infiniband/hw/irdma/hw.c b/drivers/infiniband/hw/irdma/hw.c
+index 3d5d3f8d5ded..c14f19cff534 100644
+--- a/drivers/infiniband/hw/irdma/hw.c
++++ b/drivers/infiniband/hw/irdma/hw.c
+@@ -138,59 +138,68 @@ static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
+ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+
+ switch (info->ae_id) {
+- case IRDMA_AE_AMP_UNALLOCATED_STAG:
+ case IRDMA_AE_AMP_BOUNDS_VIOLATION:
+ case IRDMA_AE_AMP_INVALID_STAG:
+- qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
+- fallthrough;
++ case IRDMA_AE_AMP_RIGHTS_VIOLATION:
++ case IRDMA_AE_AMP_UNALLOCATED_STAG:
+ case IRDMA_AE_AMP_BAD_PD:
+- case IRDMA_AE_UDA_XMIT_BAD_PD:
++ case IRDMA_AE_AMP_BAD_QP:
++ case IRDMA_AE_AMP_BAD_STAG_KEY:
++ case IRDMA_AE_AMP_BAD_STAG_INDEX:
++ case IRDMA_AE_AMP_TO_WRAP:
++ case IRDMA_AE_PRIV_OPERATION_DENIED:
+ qp->flush_code = FLUSH_PROT_ERR;
++ qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
+ break;
+- case IRDMA_AE_AMP_BAD_QP:
++ case IRDMA_AE_UDA_XMIT_BAD_PD:
+ case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
+ qp->flush_code = FLUSH_LOC_QP_OP_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
++ break;
++ case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
++ case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
++ case IRDMA_AE_UDA_L4LEN_INVALID:
++ case IRDMA_AE_DDP_UBE_INVALID_MO:
++ case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
++ qp->flush_code = FLUSH_LOC_LEN_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+ break;
+- case IRDMA_AE_AMP_BAD_STAG_KEY:
+- case IRDMA_AE_AMP_BAD_STAG_INDEX:
+- case IRDMA_AE_AMP_TO_WRAP:
+- case IRDMA_AE_AMP_RIGHTS_VIOLATION:
+ case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
+- case IRDMA_AE_PRIV_OPERATION_DENIED:
+- case IRDMA_AE_IB_INVALID_REQUEST:
+ case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
+ qp->flush_code = FLUSH_REM_ACCESS_ERR;
+ qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
+ break;
+ case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
+- case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
+- case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
+- case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
+- case IRDMA_AE_UDA_L4LEN_INVALID:
++ case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
+ case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
+- qp->flush_code = FLUSH_LOC_LEN_ERR;
++ case IRDMA_AE_IB_REMOTE_OP_ERROR:
++ qp->flush_code = FLUSH_REM_OP_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+ break;
+ case IRDMA_AE_LCE_QP_CATASTROPHIC:
+ qp->flush_code = FLUSH_FATAL_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+ break;
+- case IRDMA_AE_DDP_UBE_INVALID_MO:
+ case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
+- case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
+ qp->flush_code = FLUSH_GENERAL_ERR;
+ break;
+ case IRDMA_AE_LLP_TOO_MANY_RETRIES:
+ qp->flush_code = FLUSH_RETRY_EXC_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+ break;
+ case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS:
+ case IRDMA_AE_AMP_MWBIND_BIND_DISABLED:
+ case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS:
+ qp->flush_code = FLUSH_MW_BIND_ERR;
++ qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
+ break;
+- case IRDMA_AE_IB_REMOTE_OP_ERROR:
+- qp->flush_code = FLUSH_REM_OP_ERR;
++ case IRDMA_AE_IB_INVALID_REQUEST:
++ qp->flush_code = FLUSH_REM_INV_REQ_ERR;
++ qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
+ break;
+ default:
+- qp->flush_code = FLUSH_FATAL_ERR;
++ qp->flush_code = FLUSH_GENERAL_ERR;
++ qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
+ break;
+ }
+ }
+diff --git a/drivers/infiniband/hw/irdma/type.h b/drivers/infiniband/hw/irdma/type.h
+index 874bc25a938b..1241e5988c10 100644
+--- a/drivers/infiniband/hw/irdma/type.h
++++ b/drivers/infiniband/hw/irdma/type.h
+@@ -99,6 +99,7 @@ enum irdma_term_mpa_errors {
+ enum irdma_qp_event_type {
+ IRDMA_QP_EVENT_CATASTROPHIC,
+ IRDMA_QP_EVENT_ACCESS_ERR,
++ IRDMA_QP_EVENT_REQ_ERR,
+ };
+
+ enum irdma_hw_stats_index_32b {
+diff --git a/drivers/infiniband/hw/irdma/user.h b/drivers/infiniband/hw/irdma/user.h
+index 3dcbb1fbf2c6..7c3cb4288969 100644
+--- a/drivers/infiniband/hw/irdma/user.h
++++ b/drivers/infiniband/hw/irdma/user.h
+@@ -104,6 +104,7 @@ enum irdma_flush_opcode {
+ FLUSH_FATAL_ERR,
+ FLUSH_RETRY_EXC_ERR,
+ FLUSH_MW_BIND_ERR,
++ FLUSH_REM_INV_REQ_ERR,
+ };
+
+ enum irdma_cmpl_status {
+diff --git a/drivers/infiniband/hw/irdma/utils.c b/drivers/infiniband/hw/irdma/utils.c
+index 85d4212f59db..db7d0a300069 100644
+--- a/drivers/infiniband/hw/irdma/utils.c
++++ b/drivers/infiniband/hw/irdma/utils.c
+@@ -2535,6 +2535,9 @@ void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event)
+ case IRDMA_QP_EVENT_ACCESS_ERR:
+ ibevent.event = IB_EVENT_QP_ACCESS_ERR;
+ break;
++ case IRDMA_QP_EVENT_REQ_ERR:
++ ibevent.event = IB_EVENT_QP_REQ_ERR;
++ break;
+ }
+ ibevent.device = iwqp->ibqp.device;
+ ibevent.element.qp = &iwqp->ibqp;
+diff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c
+index 5275616398d8..911902d2b93e 100644
+--- a/drivers/infiniband/hw/irdma/verbs.c
++++ b/drivers/infiniband/hw/irdma/verbs.c
+@@ -3359,6 +3359,8 @@ static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode
+ return IB_WC_RETRY_EXC_ERR;
+ case FLUSH_MW_BIND_ERR:
+ return IB_WC_MW_BIND_ERR;
++ case FLUSH_REM_INV_REQ_ERR:
++ return IB_WC_REM_INV_REQ_ERR;
+ case FLUSH_FATAL_ERR:
+ default:
+ return IB_WC_FATAL_ERR;
+--
+2.35.1
+
--- /dev/null
+From 2842d0266b44c2e797b1230d1540aae27a9769ef Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Feb 2022 21:42:52 -0500
+Subject: RDMA/irdma: Move union irdma_sockaddr to header file
+
+From: Zhu Yanjun <yanjun.zhu@linux.dev>
+
+[ Upstream commit 884194ef264e140a6d22f7a5de2b76765d17734a ]
+
+The union irdma_sockaddr is used frequently. So move it to the header
+file.
+
+Link: https://lore.kernel.org/r/20220223024252.3873736-4-yanjun.zhu@linux.dev
+Signed-off-by: Zhu Yanjun <yanjun.zhu@linux.dev>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Stable-dep-of: 34acb833cc83 ("RDMA/irdma: Validate udata inlen and outlen")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/irdma/verbs.c | 17 +++--------------
+ drivers/infiniband/hw/irdma/verbs.h | 11 +++++++----
+ 2 files changed, 10 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c
+index e1b4bcaa62bb..7212f7f8818a 100644
+--- a/drivers/infiniband/hw/irdma/verbs.c
++++ b/drivers/infiniband/hw/irdma/verbs.c
+@@ -3952,11 +3952,7 @@ static int irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
+ int ret = 0;
+ bool ipv4;
+ u16 vlan_id;
+- union {
+- struct sockaddr saddr;
+- struct sockaddr_in saddr_in;
+- struct sockaddr_in6 saddr_in6;
+- } sgid_addr;
++ union irdma_sockaddr sgid_addr;
+ unsigned char dmac[ETH_ALEN];
+
+ rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
+@@ -4092,11 +4088,7 @@ static int irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
+ struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
+ int ret;
+ unsigned long flags;
+- union {
+- struct sockaddr saddr;
+- struct sockaddr_in saddr_in;
+- struct sockaddr_in6 saddr_in6;
+- } sgid_addr;
++ union irdma_sockaddr sgid_addr;
+
+ rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
+ if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
+@@ -4174,10 +4166,7 @@ static int irdma_create_ah(struct ib_ah *ibah,
+ u32 ah_id = 0;
+ struct irdma_ah_info *ah_info;
+ struct irdma_create_ah_resp uresp;
+- union {
+- struct sockaddr_in saddr_in;
+- struct sockaddr_in6 saddr_in6;
+- } sgid_addr, dgid_addr;
++ union irdma_sockaddr sgid_addr, dgid_addr;
+ int err;
+ u8 dmac[ETH_ALEN];
+
+diff --git a/drivers/infiniband/hw/irdma/verbs.h b/drivers/infiniband/hw/irdma/verbs.h
+index d2d4a7e5f954..541105b728e3 100644
+--- a/drivers/infiniband/hw/irdma/verbs.h
++++ b/drivers/infiniband/hw/irdma/verbs.h
+@@ -25,13 +25,16 @@ struct irdma_pd {
+ struct irdma_sc_pd sc_pd;
+ };
+
++union irdma_sockaddr {
++ struct sockaddr_in saddr_in;
++ struct sockaddr_in6 saddr_in6;
++};
++
+ struct irdma_av {
+ u8 macaddr[16];
+ struct rdma_ah_attr attrs;
+- union {
+- struct sockaddr_in saddr_in;
+- struct sockaddr_in6 saddr_in6;
+- } sgid_addr, dgid_addr;
++ union irdma_sockaddr sgid_addr;
++ union irdma_sockaddr dgid_addr;
+ u8 net_type;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 73c68da08750317f0e2feb3ffc9203816d04a8b2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Feb 2022 21:42:51 -0500
+Subject: RDMA/irdma: Remove the unnecessary variable saddr
+
+From: Zhu Yanjun <yanjun.zhu@linux.dev>
+
+[ Upstream commit 8627da62cc3b9de4d299f2558a9f16b4c3c13a5d ]
+
+Firstly the variable saddr was to check the type of a network. Now the
+variable net_type is used to do the same work. So it is removed.
+
+Link: https://lore.kernel.org/r/20220223024252.3873736-3-yanjun.zhu@linux.dev
+Signed-off-by: Zhu Yanjun <yanjun.zhu@linux.dev>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Stable-dep-of: 34acb833cc83 ("RDMA/irdma: Validate udata inlen and outlen")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/irdma/verbs.c | 1 -
+ drivers/infiniband/hw/irdma/verbs.h | 1 -
+ 2 files changed, 2 deletions(-)
+
+diff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c
+index 911902d2b93e..e1b4bcaa62bb 100644
+--- a/drivers/infiniband/hw/irdma/verbs.c
++++ b/drivers/infiniband/hw/irdma/verbs.c
+@@ -4175,7 +4175,6 @@ static int irdma_create_ah(struct ib_ah *ibah,
+ struct irdma_ah_info *ah_info;
+ struct irdma_create_ah_resp uresp;
+ union {
+- struct sockaddr saddr;
+ struct sockaddr_in saddr_in;
+ struct sockaddr_in6 saddr_in6;
+ } sgid_addr, dgid_addr;
+diff --git a/drivers/infiniband/hw/irdma/verbs.h b/drivers/infiniband/hw/irdma/verbs.h
+index d0fdef8d09ea..d2d4a7e5f954 100644
+--- a/drivers/infiniband/hw/irdma/verbs.h
++++ b/drivers/infiniband/hw/irdma/verbs.h
+@@ -29,7 +29,6 @@ struct irdma_av {
+ u8 macaddr[16];
+ struct rdma_ah_attr attrs;
+ union {
+- struct sockaddr saddr;
+ struct sockaddr_in saddr_in;
+ struct sockaddr_in6 saddr_in6;
+ } sgid_addr, dgid_addr;
+--
+2.35.1
+
--- /dev/null
+From 5c239de2798314f2289beea0ed6a6081aa61eb96 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 31 Jul 2022 11:26:36 +0300
+Subject: RDMA/mlx5: Don't compare mkey tags in DEVX indirect mkey
+
+From: Aharon Landau <aharonl@nvidia.com>
+
+[ Upstream commit 13ad1125b941a5f257d9d3ae70485773abd34792 ]
+
+According to the ib spec:
+If the CI supports the Base Memory Management Extensions defined in this
+specification, the L_Key format must consist of:
+24 bit index in the most significant bits of the R_Key, and
+8 bit key in the least significant bits of the R_Key
+Through a successful Allocate L_Key verb invocation, the CI must let the
+consumer own the key portion of the returned R_Key
+
+Therefore, when creating a mkey using DEVX, the consumer is allowed to
+change the key part. The kernel should compare only the index part of a
+R_Key to determine equality with another R_Key.
+
+Adding capability in order not to break backward compatibility.
+
+Fixes: 534fd7aac56a ("IB/mlx5: Manage indirection mkey upon DEVX flow for ODP")
+Link: https://lore.kernel.org/r/3d669aacea85a3a15c3b3b953b3eaba3f80ef9be.1659255945.git.leonro@nvidia.com
+Signed-off-by: Aharon Landau <aharonl@nvidia.com>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/mlx5/main.c | 3 +++
+ drivers/infiniband/hw/mlx5/odp.c | 3 ++-
+ include/uapi/rdma/mlx5-abi.h | 1 +
+ 3 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
+index 8664bcf6d3f5..827ee3040bea 100644
+--- a/drivers/infiniband/hw/mlx5/main.c
++++ b/drivers/infiniband/hw/mlx5/main.c
+@@ -1847,6 +1847,9 @@ static int set_ucontext_resp(struct ib_ucontext *uctx,
+ if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
+ resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
+
++ resp->comp_mask |=
++ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
++
+ return 0;
+ }
+
+diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/odp.c
+index d0d98e584ebc..fcf6447b4a4e 100644
+--- a/drivers/infiniband/hw/mlx5/odp.c
++++ b/drivers/infiniband/hw/mlx5/odp.c
+@@ -792,7 +792,8 @@ static bool mkey_is_eq(struct mlx5_core_mkey *mmkey, u32 key)
+ {
+ if (!mmkey)
+ return false;
+- if (mmkey->type == MLX5_MKEY_MW)
++ if (mmkey->type == MLX5_MKEY_MW ||
++ mmkey->type == MLX5_MKEY_INDIRECT_DEVX)
+ return mlx5_base_mkey(mmkey->key) == mlx5_base_mkey(key);
+ return mmkey->key == key;
+ }
+diff --git a/include/uapi/rdma/mlx5-abi.h b/include/uapi/rdma/mlx5-abi.h
+index 86be4a92b67b..a96b7d2770e1 100644
+--- a/include/uapi/rdma/mlx5-abi.h
++++ b/include/uapi/rdma/mlx5-abi.h
+@@ -104,6 +104,7 @@ enum mlx5_ib_alloc_ucontext_resp_mask {
+ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
+ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
+ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
++ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5,
+ };
+
+ enum mlx5_user_cmds_supp_uhw {
+--
+2.35.1
+
--- /dev/null
+From 503bdab3e5e23c14fbd1b52bd584b16d3cf0c941 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 21 Aug 2022 21:16:13 -0400
+Subject: RDMA/rxe: Fix "kernel NULL pointer dereference" error
+
+From: Zhu Yanjun <yanjun.zhu@linux.dev>
+
+[ Upstream commit a625ca30eff806395175ebad3ac1399014bdb280 ]
+
+When rxe_queue_init in the function rxe_qp_init_req fails,
+both qp->req.task.func and qp->req.task.arg are not initialized.
+
+Because of creation of qp fails, the function rxe_create_qp will
+call rxe_qp_do_cleanup to handle allocated resource.
+
+Before calling __rxe_do_task, both qp->req.task.func and
+qp->req.task.arg should be checked.
+
+Fixes: 8700e3e7c485 ("Soft RoCE driver")
+Link: https://lore.kernel.org/r/20220822011615.805603-2-yanjun.zhu@linux.dev
+Reported-by: syzbot+ab99dc4c6e961eed8b8e@syzkaller.appspotmail.com
+Signed-off-by: Zhu Yanjun <yanjun.zhu@linux.dev>
+Reviewed-by: Li Zhijian <lizhijian@fujitsu.com>
+Reviewed-by: Bob Pearson <rpearsonhpe@gmail.com>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/rxe/rxe_qp.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c
+index 661b83d65af3..4a6eb6de3b08 100644
+--- a/drivers/infiniband/sw/rxe/rxe_qp.c
++++ b/drivers/infiniband/sw/rxe/rxe_qp.c
+@@ -793,7 +793,9 @@ void rxe_qp_destroy(struct rxe_qp *qp)
+ rxe_cleanup_task(&qp->comp.task);
+
+ /* flush out any receive wr's or pending requests */
+- __rxe_do_task(&qp->req.task);
++ if (qp->req.task.func)
++ __rxe_do_task(&qp->req.task);
++
+ if (qp->sq.queue) {
+ __rxe_do_task(&qp->comp.task);
+ __rxe_do_task(&qp->req.task);
+--
+2.35.1
+
--- /dev/null
+From 67a65eaa9091904c80c30f826d21dca783546c47 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 17:14:47 -0500
+Subject: RDMA/rxe: Fix resize_finish() in rxe_queue.c
+
+From: Bob Pearson <rpearsonhpe@gmail.com>
+
+[ Upstream commit fda5d0cf8aef12f0a4f714a96a4b2fce039a3e55 ]
+
+Currently in resize_finish() in rxe_queue.c there is a loop which copies
+the entries in the original queue into a newly allocated queue. The
+termination logic for this loop is incorrect. The call to
+queue_next_index() updates cons but has no effect on whether the queue is
+empty. So if the queue starts out empty nothing is copied but if it is not
+then the loop will run forever. This patch changes the loop to compare the
+value of cons to the original producer index.
+
+Fixes: ae6e843fe08d0 ("RDMA/rxe: Add memory barriers to kernel queues")
+Link: https://lore.kernel.org/r/20220825221446.6512-1-rpearsonhpe@gmail.com
+Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com>
+Reviewed-by: Li Zhijian <lizhijian@fujitsu.com>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/rxe/rxe_queue.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/infiniband/sw/rxe/rxe_queue.c b/drivers/infiniband/sw/rxe/rxe_queue.c
+index 6e6e023c1b45..03157de52f5f 100644
+--- a/drivers/infiniband/sw/rxe/rxe_queue.c
++++ b/drivers/infiniband/sw/rxe/rxe_queue.c
+@@ -112,23 +112,25 @@ static int resize_finish(struct rxe_queue *q, struct rxe_queue *new_q,
+ unsigned int num_elem)
+ {
+ enum queue_type type = q->type;
++ u32 new_prod;
+ u32 prod;
+ u32 cons;
+
+ if (!queue_empty(q, q->type) && (num_elem < queue_count(q, type)))
+ return -EINVAL;
+
+- prod = queue_get_producer(new_q, type);
++ new_prod = queue_get_producer(new_q, type);
++ prod = queue_get_producer(q, type);
+ cons = queue_get_consumer(q, type);
+
+- while (!queue_empty(q, type)) {
+- memcpy(queue_addr_from_index(new_q, prod),
++ while ((prod - cons) & q->index_mask) {
++ memcpy(queue_addr_from_index(new_q, new_prod),
+ queue_addr_from_index(q, cons), new_q->elem_size);
+- prod = queue_next_index(new_q, prod);
++ new_prod = queue_next_index(new_q, new_prod);
+ cons = queue_next_index(q, cons);
+ }
+
+- new_q->buf->producer_index = prod;
++ new_q->buf->producer_index = new_prod;
+ q->buf->consumer_index = cons;
+
+ /* update private index copies */
+--
+2.35.1
+
--- /dev/null
+From 6729265f614568f7c56a64b7c1005ad4e6ab56f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 21 Aug 2022 21:16:14 -0400
+Subject: RDMA/rxe: Fix the error caused by qp->sk
+
+From: Zhu Yanjun <yanjun.zhu@linux.dev>
+
+[ Upstream commit 548ce2e66725dcba4e27d1e8ac468d5dd17fd509 ]
+
+When sock_create_kern in the function rxe_qp_init_req fails,
+qp->sk is set to NULL.
+
+Then the function rxe_create_qp will call rxe_qp_do_cleanup
+to handle allocated resource.
+
+Before handling qp->sk, this variable should be checked.
+
+Fixes: 8700e3e7c485 ("Soft RoCE driver")
+Link: https://lore.kernel.org/r/20220822011615.805603-3-yanjun.zhu@linux.dev
+Signed-off-by: Zhu Yanjun <yanjun.zhu@linux.dev>
+Reviewed-by: Li Zhijian <lizhijian@fujitsu.com>
+Reviewed-by: Bob Pearson <rpearsonhpe@gmail.com>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/rxe/rxe_qp.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c
+index 4a6eb6de3b08..57ebf4871608 100644
+--- a/drivers/infiniband/sw/rxe/rxe_qp.c
++++ b/drivers/infiniband/sw/rxe/rxe_qp.c
+@@ -835,8 +835,10 @@ static void rxe_qp_do_cleanup(struct work_struct *work)
+
+ free_rd_atomic_resources(qp);
+
+- kernel_sock_shutdown(qp->sk, SHUT_RDWR);
+- sock_release(qp->sk);
++ if (qp->sk) {
++ kernel_sock_shutdown(qp->sk, SHUT_RDWR);
++ sock_release(qp->sk);
++ }
+ }
+
+ /* called when the last reference to the qp is dropped */
+--
+2.35.1
+
--- /dev/null
+From b12827e980f4c5c9ca78fdca1f55dd148092cfa2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 10:12:02 +0200
+Subject: RDMA/siw: Always consume all skbuf data in sk_data_ready() upcall.
+
+From: Bernard Metzler <bmt@zurich.ibm.com>
+
+[ Upstream commit 754209850df8367c954ac1de7671c7430b1f342c ]
+
+For header and trailer/padding processing, siw did not consume new
+skb data until minimum amount present to fill current header or trailer
+structure, including potential payload padding. Not consuming any
+data during upcall may cause a receive stall, since tcp_read_sock()
+is not upcalling again if no new data arrive.
+A NFSoRDMA client got stuck at RDMA Write reception of unaligned
+payload, if the current skb did contain only the expected 3 padding
+bytes, but not the 4 bytes CRC trailer. Expecting 4 more bytes already
+arrived in another skb, and not consuming those 3 bytes in the current
+upcall left the Write incomplete, waiting for the CRC forever.
+
+Fixes: 8b6a361b8c48 ("rdma/siw: receive path")
+Reported-by: Olga Kornievskaia <kolga@netapp.com>
+Tested-by: Olga Kornievskaia <kolga@netapp.com>
+Signed-off-by: Bernard Metzler <bmt@zurich.ibm.com>
+Link: https://lore.kernel.org/r/20220920081202.223629-1-bmt@zurich.ibm.com
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/siw/siw_qp_rx.c | 27 +++++++++++++++------------
+ 1 file changed, 15 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/infiniband/sw/siw/siw_qp_rx.c b/drivers/infiniband/sw/siw/siw_qp_rx.c
+index 875ea6f1b04a..fd721cc19682 100644
+--- a/drivers/infiniband/sw/siw/siw_qp_rx.c
++++ b/drivers/infiniband/sw/siw/siw_qp_rx.c
+@@ -961,27 +961,28 @@ int siw_proc_terminate(struct siw_qp *qp)
+ static int siw_get_trailer(struct siw_qp *qp, struct siw_rx_stream *srx)
+ {
+ struct sk_buff *skb = srx->skb;
++ int avail = min(srx->skb_new, srx->fpdu_part_rem);
+ u8 *tbuf = (u8 *)&srx->trailer.crc - srx->pad;
+ __wsum crc_in, crc_own = 0;
+
+ siw_dbg_qp(qp, "expected %d, available %d, pad %u\n",
+ srx->fpdu_part_rem, srx->skb_new, srx->pad);
+
+- if (srx->skb_new < srx->fpdu_part_rem)
+- return -EAGAIN;
+-
+- skb_copy_bits(skb, srx->skb_offset, tbuf, srx->fpdu_part_rem);
++ skb_copy_bits(skb, srx->skb_offset, tbuf, avail);
+
+- if (srx->mpa_crc_hd && srx->pad)
+- crypto_shash_update(srx->mpa_crc_hd, tbuf, srx->pad);
++ srx->skb_new -= avail;
++ srx->skb_offset += avail;
++ srx->skb_copied += avail;
++ srx->fpdu_part_rem -= avail;
+
+- srx->skb_new -= srx->fpdu_part_rem;
+- srx->skb_offset += srx->fpdu_part_rem;
+- srx->skb_copied += srx->fpdu_part_rem;
++ if (srx->fpdu_part_rem)
++ return -EAGAIN;
+
+ if (!srx->mpa_crc_hd)
+ return 0;
+
++ if (srx->pad)
++ crypto_shash_update(srx->mpa_crc_hd, tbuf, srx->pad);
+ /*
+ * CRC32 is computed, transmitted and received directly in NBO,
+ * so there's never a reason to convert byte order.
+@@ -1083,10 +1084,9 @@ static int siw_get_hdr(struct siw_rx_stream *srx)
+ * completely received.
+ */
+ if (iwarp_pktinfo[opcode].hdr_len > sizeof(struct iwarp_ctrl_tagged)) {
+- bytes = iwarp_pktinfo[opcode].hdr_len - MIN_DDP_HDR;
++ int hdrlen = iwarp_pktinfo[opcode].hdr_len;
+
+- if (srx->skb_new < bytes)
+- return -EAGAIN;
++ bytes = min_t(int, hdrlen - MIN_DDP_HDR, srx->skb_new);
+
+ skb_copy_bits(skb, srx->skb_offset,
+ (char *)c_hdr + srx->fpdu_part_rcvd, bytes);
+@@ -1096,6 +1096,9 @@ static int siw_get_hdr(struct siw_rx_stream *srx)
+ srx->skb_new -= bytes;
+ srx->skb_offset += bytes;
+ srx->skb_copied += bytes;
++
++ if (srx->fpdu_part_rcvd < hdrlen)
++ return -EAGAIN;
+ }
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From aeb45489562a5d1d787f00e75dfe998a26481459 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 10:25:03 +0200
+Subject: RDMA/siw: Fix QP destroy to wait for all references dropped.
+
+From: Bernard Metzler <bmt@zurich.ibm.com>
+
+[ Upstream commit a3c278807a459e6f50afee6971cabe74cccfb490 ]
+
+Delay QP destroy completion until all siw references to QP are
+dropped. The calling RDMA core will free QP structure after
+successful return from siw_qp_destroy() call, so siw must not
+hold any remaining reference to the QP upon return.
+A use-after-free was encountered in xfstest generic/460, while
+testing NFSoRDMA. Here, after a TCP connection drop by peer,
+the triggered siw_cm_work_handler got delayed until after
+QP destroy call, referencing a QP which has already freed.
+
+Fixes: 303ae1cdfdf7 ("rdma/siw: application interface")
+Reported-by: Olga Kornievskaia <kolga@netapp.com>
+Signed-off-by: Bernard Metzler <bmt@zurich.ibm.com>
+Link: https://lore.kernel.org/r/20220920082503.224189-1-bmt@zurich.ibm.com
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/sw/siw/siw.h | 1 +
+ drivers/infiniband/sw/siw/siw_qp.c | 2 +-
+ drivers/infiniband/sw/siw/siw_verbs.c | 3 +++
+ 3 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/infiniband/sw/siw/siw.h b/drivers/infiniband/sw/siw/siw.h
+index df03d84c6868..2f3a9cda3850 100644
+--- a/drivers/infiniband/sw/siw/siw.h
++++ b/drivers/infiniband/sw/siw/siw.h
+@@ -418,6 +418,7 @@ struct siw_qp {
+ struct ib_qp base_qp;
+ struct siw_device *sdev;
+ struct kref ref;
++ struct completion qp_free;
+ struct list_head devq;
+ int tx_cpu;
+ struct siw_qp_attrs attrs;
+diff --git a/drivers/infiniband/sw/siw/siw_qp.c b/drivers/infiniband/sw/siw/siw_qp.c
+index 7e01f2438afc..e6f634971228 100644
+--- a/drivers/infiniband/sw/siw/siw_qp.c
++++ b/drivers/infiniband/sw/siw/siw_qp.c
+@@ -1342,6 +1342,6 @@ void siw_free_qp(struct kref *ref)
+ vfree(qp->orq);
+
+ siw_put_tx_cpu(qp->tx_cpu);
+-
++ complete(&qp->qp_free);
+ atomic_dec(&sdev->num_qp);
+ }
+diff --git a/drivers/infiniband/sw/siw/siw_verbs.c b/drivers/infiniband/sw/siw/siw_verbs.c
+index aa3f60d54a70..ff33659acffa 100644
+--- a/drivers/infiniband/sw/siw/siw_verbs.c
++++ b/drivers/infiniband/sw/siw/siw_verbs.c
+@@ -478,6 +478,8 @@ int siw_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,
+ list_add_tail(&qp->devq, &sdev->qp_list);
+ spin_unlock_irqrestore(&sdev->lock, flags);
+
++ init_completion(&qp->qp_free);
++
+ return 0;
+
+ err_out_xa:
+@@ -622,6 +624,7 @@ int siw_destroy_qp(struct ib_qp *base_qp, struct ib_udata *udata)
+ qp->scq = qp->rcq = NULL;
+
+ siw_qp_put(qp);
++ wait_for_completion(&qp->qp_free);
+
+ return 0;
+ }
+--
+2.35.1
+
--- /dev/null
+From 254be55a744c04db6cdf46db1d6203acd6d2d6b8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 16:31:39 -0700
+Subject: RDMA/srp: Fix srp_abort()
+
+From: Bart Van Assche <bvanassche@acm.org>
+
+[ Upstream commit 6dbe4a8dead84de474483910b02ec9e6a10fc1a9 ]
+
+Fix the code for converting a SCSI command pointer into an SRP request
+pointer.
+
+Cc: Xiao Yang <yangx.jy@fujitsu.com>
+Fixes: ad215aaea4f9 ("RDMA/srp: Make struct scsi_cmnd and struct srp_request adjacent")
+Signed-off-by: Bart Van Assche <bvanassche@acm.org>
+Link: https://lore.kernel.org/r/20220908233139.3042628-1-bvanassche@acm.org
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/ulp/srp/ib_srp.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
+index 473b3a08cf96..2f4991cea98c 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.c
++++ b/drivers/infiniband/ulp/srp/ib_srp.c
+@@ -2783,7 +2783,7 @@ static int srp_send_tsk_mgmt(struct srp_rdma_ch *ch, u64 req_tag, u64 lun,
+ static int srp_abort(struct scsi_cmnd *scmnd)
+ {
+ struct srp_target_port *target = host_to_target(scmnd->device->host);
+- struct srp_request *req = (struct srp_request *) scmnd->host_scribble;
++ struct srp_request *req = scsi_cmd_priv(scmnd);
+ u32 tag;
+ u16 ch_idx;
+ struct srp_rdma_ch *ch;
+@@ -2791,8 +2791,6 @@ static int srp_abort(struct scsi_cmnd *scmnd)
+
+ shost_printk(KERN_ERR, target->scsi_host, "SRP abort called\n");
+
+- if (!req)
+- return SUCCESS;
+ tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmnd));
+ ch_idx = blk_mq_unique_tag_to_hwq(tag);
+ if (WARN_ON_ONCE(ch_idx >= target->ch_count))
+--
+2.35.1
+
--- /dev/null
+From a5ca65ac73ce8f26ac5ce88364a2cab607e28625 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 14:38:59 -0700
+Subject: RDMA/srp: Handle dev_set_name() failure
+
+From: Bart Van Assche <bvanassche@acm.org>
+
+[ Upstream commit 351e458f725da8106eba920f3cdecf39a0e31136 ]
+
+Instead of ignoring dev_set_name() failure, handle dev_set_name()
+failure. Convert a device_register() call into device_initialize() and
+device_add() calls.
+
+Link: https://lore.kernel.org/r/20220825213900.864587-4-bvanassche@acm.org
+Reported-by: Bo Liu <liubo03@inspur.com>
+Signed-off-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Stable-dep-of: b05398aff9ad ("RDMA/srp: Support more than 255 rdma ports")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/ulp/srp/ib_srp.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
+index 1435d375a6ad..61b3fe4cc5e8 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.c
++++ b/drivers/infiniband/ulp/srp/ib_srp.c
+@@ -3894,12 +3894,13 @@ static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
+ host->srp_dev = device;
+ host->port = port;
+
++ device_initialize(&host->dev);
+ host->dev.class = &srp_class;
+ host->dev.parent = device->dev->dev.parent;
+- dev_set_name(&host->dev, "srp-%s-%d", dev_name(&device->dev->dev),
+- port);
+-
+- if (device_register(&host->dev))
++ if (dev_set_name(&host->dev, "srp-%s-%d", dev_name(&device->dev->dev),
++ port))
++ goto put_host;
++ if (device_add(&host->dev))
+ goto put_host;
+ if (device_create_file(&host->dev, &dev_attr_add_target))
+ goto put_host;
+--
+2.35.1
+
--- /dev/null
+From 8bc9d2fad66e4f5fafb78d84c52d9b9fee98f33d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 14:38:57 -0700
+Subject: RDMA/srp: Rework the srp_add_port() error path
+
+From: Bart Van Assche <bvanassche@acm.org>
+
+[ Upstream commit c8e4c23976554fb9dda1658bd1a3914b202815cd ]
+
+device_register() always calls device_initialize() so calling device_del()
+is safe even if device_register() fails. Implement the following advice
+from the comment block above device_register(): "NOTE: _Never_ directly free
+@dev after calling this function, even if it returned an error! Always use
+put_device() to give up the reference initialized in this function instead."
+Keep the kfree() call in the error path since srp_release_dev() does not
+free the host.
+
+Link: https://lore.kernel.org/r/20220825213900.864587-2-bvanassche@acm.org
+Signed-off-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Stable-dep-of: b05398aff9ad ("RDMA/srp: Support more than 255 rdma ports")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/ulp/srp/ib_srp.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
+index 2f4991cea98c..1435d375a6ad 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.c
++++ b/drivers/infiniband/ulp/srp/ib_srp.c
+@@ -3900,20 +3900,19 @@ static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
+ port);
+
+ if (device_register(&host->dev))
+- goto free_host;
++ goto put_host;
+ if (device_create_file(&host->dev, &dev_attr_add_target))
+- goto err_class;
++ goto put_host;
+ if (device_create_file(&host->dev, &dev_attr_ibdev))
+- goto err_class;
++ goto put_host;
+ if (device_create_file(&host->dev, &dev_attr_port))
+- goto err_class;
++ goto put_host;
+
+ return host;
+
+-err_class:
+- device_unregister(&host->dev);
+-
+-free_host:
++put_host:
++ device_del(&host->dev);
++ put_device(&host->dev);
+ kfree(host);
+
+ return NULL;
+--
+2.35.1
+
--- /dev/null
+From 430c218edd0a8f7f2acd4112b0d16797861becbc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 11:03:07 +0300
+Subject: RDMA/srp: Support more than 255 rdma ports
+
+From: Mikhael Goikhman <migo@nvidia.com>
+
+[ Upstream commit b05398aff9ad9dc701b261183a5d756165d28b51 ]
+
+Currently ib_srp module does not support devices with more than 256
+ports. Switch from u8 to u32 to fix the problem.
+
+Fixes: 1fb7f8973f51 ("RDMA: Support more than 255 rdma ports")
+Reviewed-by: Shay Drory <shayd@nvidia.com>
+Signed-off-by: Mikhael Goikhman <migo@nvidia.com>
+Link: https://lore.kernel.org/r/7d80d8844f1abb3a54170b7259f0a02be38080a6.1663747327.git.leonro@nvidia.com
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/ulp/srp/ib_srp.c | 12 ++++++------
+ drivers/infiniband/ulp/srp/ib_srp.h | 2 +-
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
+index 316355fa6f54..4f7263a735f3 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.c
++++ b/drivers/infiniband/ulp/srp/ib_srp.c
+@@ -2983,7 +2983,7 @@ static ssize_t local_ib_port_show(struct device *dev,
+ {
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
+
+- return sysfs_emit(buf, "%d\n", target->srp_host->port);
++ return sysfs_emit(buf, "%u\n", target->srp_host->port);
+ }
+
+ static DEVICE_ATTR_RO(local_ib_port);
+@@ -3879,7 +3879,7 @@ static ssize_t port_show(struct device *dev, struct device_attribute *attr,
+ {
+ struct srp_host *host = container_of(dev, struct srp_host, dev);
+
+- return sysfs_emit(buf, "%d\n", host->port);
++ return sysfs_emit(buf, "%u\n", host->port);
+ }
+
+ static DEVICE_ATTR_RO(port);
+@@ -3891,7 +3891,7 @@ static struct attribute *srp_class_attrs[] = {
+ NULL
+ };
+
+-static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
++static struct srp_host *srp_add_port(struct srp_device *device, u32 port)
+ {
+ struct srp_host *host;
+
+@@ -3909,7 +3909,7 @@ static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
+ device_initialize(&host->dev);
+ host->dev.class = &srp_class;
+ host->dev.parent = device->dev->dev.parent;
+- if (dev_set_name(&host->dev, "srp-%s-%d", dev_name(&device->dev->dev),
++ if (dev_set_name(&host->dev, "srp-%s-%u", dev_name(&device->dev->dev),
+ port))
+ goto put_host;
+ if (device_add(&host->dev))
+@@ -3933,7 +3933,7 @@ static void srp_rename_dev(struct ib_device *device, void *client_data)
+ list_for_each_entry_safe(host, tmp_host, &srp_dev->dev_list, list) {
+ char name[IB_DEVICE_NAME_MAX + 8];
+
+- snprintf(name, sizeof(name), "srp-%s-%d",
++ snprintf(name, sizeof(name), "srp-%s-%u",
+ dev_name(&device->dev), host->port);
+ device_rename(&host->dev, name);
+ }
+@@ -3945,7 +3945,7 @@ static int srp_add_one(struct ib_device *device)
+ struct ib_device_attr *attr = &device->attrs;
+ struct srp_host *host;
+ int mr_page_shift;
+- unsigned int p;
++ u32 p;
+ u64 max_pages_per_mr;
+ unsigned int flags = 0;
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.h b/drivers/infiniband/ulp/srp/ib_srp.h
+index abccddeea1e3..68b4c2bce156 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.h
++++ b/drivers/infiniband/ulp/srp/ib_srp.h
+@@ -111,7 +111,7 @@ struct srp_device {
+
+ struct srp_host {
+ struct srp_device *srp_dev;
+- u8 port;
++ u32 port;
+ struct device dev;
+ struct list_head target_list;
+ spinlock_t target_lock;
+--
+2.35.1
+
--- /dev/null
+From 6556cbad41c12f06c98d46e9b025d536517bdac6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 14:39:00 -0700
+Subject: RDMA/srp: Use the attribute group mechanism for sysfs attributes
+
+From: Bart Van Assche <bvanassche@acm.org>
+
+[ Upstream commit b8a9c18c2f39bd84b8240b744b666114f7d62054 ]
+
+Simplify the SRP driver by using the attribute group mechanism instead
+of calling device_create_file() explicitly.
+
+Link: https://lore.kernel.org/r/20220825213900.864587-5-bvanassche@acm.org
+Signed-off-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Stable-dep-of: b05398aff9ad ("RDMA/srp: Support more than 255 rdma ports")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/ulp/srp/ib_srp.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
+index 61b3fe4cc5e8..316355fa6f54 100644
+--- a/drivers/infiniband/ulp/srp/ib_srp.c
++++ b/drivers/infiniband/ulp/srp/ib_srp.c
+@@ -3172,8 +3172,13 @@ static void srp_release_dev(struct device *dev)
+ complete(&host->released);
+ }
+
++static struct attribute *srp_class_attrs[];
++
++ATTRIBUTE_GROUPS(srp_class);
++
+ static struct class srp_class = {
+ .name = "infiniband_srp",
++ .dev_groups = srp_class_groups,
+ .dev_release = srp_release_dev
+ };
+
+@@ -3879,6 +3884,13 @@ static ssize_t port_show(struct device *dev, struct device_attribute *attr,
+
+ static DEVICE_ATTR_RO(port);
+
++static struct attribute *srp_class_attrs[] = {
++ &dev_attr_add_target.attr,
++ &dev_attr_ibdev.attr,
++ &dev_attr_port.attr,
++ NULL
++};
++
+ static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
+ {
+ struct srp_host *host;
+@@ -3902,12 +3914,6 @@ static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
+ goto put_host;
+ if (device_add(&host->dev))
+ goto put_host;
+- if (device_create_file(&host->dev, &dev_attr_add_target))
+- goto put_host;
+- if (device_create_file(&host->dev, &dev_attr_ibdev))
+- goto put_host;
+- if (device_create_file(&host->dev, &dev_attr_port))
+- goto put_host;
+
+ return host;
+
+--
+2.35.1
+
--- /dev/null
+From 1225e902195ea6ccd83062ef801fc01c833468d6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 14:59:53 +0200
+Subject: regulator: core: Prevent integer underflow
+
+From: Patrick Rudolph <patrick.rudolph@9elements.com>
+
+[ Upstream commit 8d8e16592022c9650df8aedfe6552ed478d7135b ]
+
+By using a ratio of delay to poll_enabled_time that is not integer
+time_remaining underflows and does not exit the loop as expected.
+As delay could be derived from DT and poll_enabled_time is defined
+in the driver this can easily happen.
+
+Use a signed iterator to make sure that the loop exits once
+the remaining time is negative.
+
+Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
+Link: https://lore.kernel.org/r/20220909125954.577669-1-patrick.rudolph@9elements.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/regulator/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
+index 43613db7af75..aa4d78b02483 100644
+--- a/drivers/regulator/core.c
++++ b/drivers/regulator/core.c
+@@ -2636,7 +2636,7 @@ static int _regulator_do_enable(struct regulator_dev *rdev)
+ * expired, return -ETIMEDOUT.
+ */
+ if (rdev->desc->poll_enabled_time) {
+- unsigned int time_remaining = delay;
++ int time_remaining = delay;
+
+ while (time_remaining > 0) {
+ _regulator_enable_delay(rdev->desc->poll_enabled_time);
+--
+2.35.1
+
--- /dev/null
+From ed34c88c3c75a8dc56c20b609ed793c28405c6b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 6 Aug 2022 00:02:32 +0200
+Subject: remoteproc: imx_rproc: Simplify some error message
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit a1c3611dcfb08e62e165ab5c00122dd13f210166 ]
+
+dev_err_probe() already prints the error code in a human readable way, so
+there is no need to duplicate it as a numerical value at the end of the
+message.
+
+While at it, remove 'ret' that is mostly useless.
+
+Fixes: 2df7062002d0 ("remoteproc: imx_proc: enable virtio/mailbox")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Link: https://lore.kernel.org/r/6b9343c2688117a340661d8ee491c2962c54a09a.1659736936.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/remoteproc/imx_rproc.c | 14 +++++---------
+ 1 file changed, 5 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
+index e8a170ad43c1..776052ae76ae 100644
+--- a/drivers/remoteproc/imx_rproc.c
++++ b/drivers/remoteproc/imx_rproc.c
+@@ -638,7 +638,6 @@ static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
+ struct imx_rproc *priv = rproc->priv;
+ struct device *dev = priv->dev;
+ struct mbox_client *cl;
+- int ret;
+
+ if (!of_get_property(dev->of_node, "mbox-names", NULL))
+ return 0;
+@@ -651,18 +650,15 @@ static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
+ cl->rx_callback = imx_rproc_rx_callback;
+
+ priv->tx_ch = mbox_request_channel_byname(cl, "tx");
+- if (IS_ERR(priv->tx_ch)) {
+- ret = PTR_ERR(priv->tx_ch);
+- return dev_err_probe(cl->dev, ret,
+- "failed to request tx mailbox channel: %d\n", ret);
+- }
++ if (IS_ERR(priv->tx_ch))
++ return dev_err_probe(cl->dev, PTR_ERR(priv->tx_ch),
++ "failed to request tx mailbox channel\n");
+
+ priv->rx_ch = mbox_request_channel_byname(cl, "rx");
+ if (IS_ERR(priv->rx_ch)) {
+ mbox_free_channel(priv->tx_ch);
+- ret = PTR_ERR(priv->rx_ch);
+- return dev_err_probe(cl->dev, ret,
+- "failed to request rx mailbox channel: %d\n", ret);
++ return dev_err_probe(cl->dev, PTR_ERR(priv->rx_ch),
++ "failed to request rx mailbox channel\n");
+ }
+
+ return 0;
+--
+2.35.1
+
--- /dev/null
+From 40dbd4d534ac06fdee8dcffa7719e4f0323c11a3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 20:49:13 +0900
+Subject: Revert "usb: storage: Add quirk for Samsung Fit flash"
+
+From: sunghwan jung <onenowy@gmail.com>
+
+[ Upstream commit ad5dbfc123e6ffbbde194e2a4603323e09f741ee ]
+
+This reverts commit 86d92f5465958752481269348d474414dccb1552,
+which fix the timeout issue for "Samsung Fit Flash".
+
+But the commit affects not only "Samsung Fit Flash" but also other usb
+storages that use the same controller and causes severe performance
+regression.
+
+ # hdparm -t /dev/sda (without the quirk)
+ Timing buffered disk reads: 622 MB in 3.01 seconds = 206.66 MB/sec
+
+ # hdparm -t /dev/sda (with the quirk)
+ Timing buffered disk reads: 220 MB in 3.00 seconds = 73.32 MB/sec
+
+The commit author mentioned that "Issue was reproduced after device has
+bad block", so this quirk should be applied when we have the timeout
+issue with a device that has bad blocks.
+
+We revert the commit so that we apply this quirk by adding kernel
+paramters using a bootloader or other ways when we really need it,
+without the performance regression with devices that don't have the
+issue.
+
+Signed-off-by: sunghwan jung <onenowy@gmail.com>
+Link: https://lore.kernel.org/r/20220913114913.3073-1-onenowy@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/storage/unusual_devs.h | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
+index 4993227ab293..20dcbccb290b 100644
+--- a/drivers/usb/storage/unusual_devs.h
++++ b/drivers/usb/storage/unusual_devs.h
+@@ -1275,12 +1275,6 @@ UNUSUAL_DEV( 0x090a, 0x1200, 0x0000, 0x9999,
+ USB_SC_RBC, USB_PR_BULK, NULL,
+ 0 ),
+
+-UNUSUAL_DEV(0x090c, 0x1000, 0x1100, 0x1100,
+- "Samsung",
+- "Flash Drive FIT",
+- USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+- US_FL_MAX_SECTORS_64),
+-
+ /* aeb */
+ UNUSUAL_DEV( 0x090c, 0x1132, 0x0000, 0xffff,
+ "Feiya",
+--
+2.35.1
+
--- /dev/null
+From 660fdc0abb22d8d104a9ced7e4455f40c2eb27d7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 15:09:37 +0200
+Subject: sbitmap: Avoid leaving waitqueue in invalid state in __sbq_wake_up()
+
+From: Jan Kara <jack@suse.cz>
+
+[ Upstream commit 48c033314f372478548203c583529f53080fd078 ]
+
+When __sbq_wake_up() decrements wait_cnt to 0 but races with someone
+else waking the waiter on the waitqueue (so the waitqueue becomes
+empty), it exits without reseting wait_cnt to wake_batch number. Once
+wait_cnt is 0, nobody will ever reset the wait_cnt or wake the new
+waiters resulting in possible deadlocks or busyloops. Fix the problem by
+making sure we reset wait_cnt even if we didn't wake up anybody in the
+end.
+
+Fixes: 040b83fcecfb ("sbitmap: fix possible io hung due to lost wakeup")
+Reported-by: Keith Busch <kbusch@kernel.org>
+Signed-off-by: Jan Kara <jack@suse.cz>
+Link: https://lore.kernel.org/r/20220908130937.2795-1-jack@suse.cz
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ lib/sbitmap.c | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/lib/sbitmap.c b/lib/sbitmap.c
+index fa30f1645366..fc545994d2eb 100644
+--- a/lib/sbitmap.c
++++ b/lib/sbitmap.c
+@@ -534,6 +534,7 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq)
+ struct sbq_wait_state *ws;
+ unsigned int wake_batch;
+ int wait_cnt;
++ bool ret;
+
+ ws = sbq_wake_ptr(sbq);
+ if (!ws)
+@@ -544,12 +545,23 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq)
+ * For concurrent callers of this, callers should call this function
+ * again to wakeup a new batch on a different 'ws'.
+ */
+- if (wait_cnt < 0 || !waitqueue_active(&ws->wait))
++ if (wait_cnt < 0)
+ return true;
+
++ /*
++ * If we decremented queue without waiters, retry to avoid lost
++ * wakeups.
++ */
+ if (wait_cnt > 0)
+- return false;
++ return !waitqueue_active(&ws->wait);
+
++ /*
++ * When wait_cnt == 0, we have to be particularly careful as we are
++ * responsible to reset wait_cnt regardless whether we've actually
++ * woken up anybody. But in case we didn't wakeup anybody, we still
++ * need to retry.
++ */
++ ret = !waitqueue_active(&ws->wait);
+ wake_batch = READ_ONCE(sbq->wake_batch);
+
+ /*
+@@ -578,7 +590,7 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq)
+ sbq_index_atomic_inc(&sbq->wake_index);
+ atomic_set(&ws->wait_cnt, wake_batch);
+
+- return false;
++ return ret;
+ }
+
+ void sbitmap_queue_wake_up(struct sbitmap_queue *sbq)
+--
+2.35.1
+
--- /dev/null
+From 9169eebf547869e1e560ce8ad702206ae9bdbee2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 3 Aug 2022 20:15:04 +0800
+Subject: sbitmap: fix possible io hung due to lost wakeup
+
+From: Yu Kuai <yukuai3@huawei.com>
+
+[ Upstream commit 040b83fcecfb86f3225d3a5de7fd9b3fbccf83b4 ]
+
+There are two problems can lead to lost wakeup:
+
+1) invalid wakeup on the wrong waitqueue:
+
+For example, 2 * wake_batch tags are put, while only wake_batch threads
+are woken:
+
+__sbq_wake_up
+ atomic_cmpxchg -> reset wait_cnt
+ __sbq_wake_up -> decrease wait_cnt
+ ...
+ __sbq_wake_up -> wait_cnt is decreased to 0 again
+ atomic_cmpxchg
+ sbq_index_atomic_inc -> increase wake_index
+ wake_up_nr -> wake up and waitqueue might be empty
+ sbq_index_atomic_inc -> increase again, one waitqueue is skipped
+ wake_up_nr -> invalid wake up because old wakequeue might be empty
+
+To fix the problem, increasing 'wake_index' before resetting 'wait_cnt'.
+
+2) 'wait_cnt' can be decreased while waitqueue is empty
+
+As pointed out by Jan Kara, following race is possible:
+
+CPU1 CPU2
+__sbq_wake_up __sbq_wake_up
+ sbq_wake_ptr() sbq_wake_ptr() -> the same
+ wait_cnt = atomic_dec_return()
+ /* decreased to 0 */
+ sbq_index_atomic_inc()
+ /* move to next waitqueue */
+ atomic_set()
+ /* reset wait_cnt */
+ wake_up_nr()
+ /* wake up on the old waitqueue */
+ wait_cnt = atomic_dec_return()
+ /*
+ * decrease wait_cnt in the old
+ * waitqueue, while it can be
+ * empty.
+ */
+
+Fix the problem by waking up before updating 'wake_index' and
+'wait_cnt'.
+
+With this patch, noted that 'wait_cnt' is still decreased in the old
+empty waitqueue, however, the wakeup is redirected to a active waitqueue,
+and the extra decrement on the old empty waitqueue is not handled.
+
+Fixes: 88459642cba4 ("blk-mq: abstract tag allocation out into sbitmap library")
+Signed-off-by: Yu Kuai <yukuai3@huawei.com>
+Reviewed-by: Jan Kara <jack@suse.cz>
+Link: https://lore.kernel.org/r/20220803121504.212071-1-yukuai1@huaweicloud.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ lib/sbitmap.c | 55 ++++++++++++++++++++++++++++++---------------------
+ 1 file changed, 33 insertions(+), 22 deletions(-)
+
+diff --git a/lib/sbitmap.c b/lib/sbitmap.c
+index b25db9be938a..fa30f1645366 100644
+--- a/lib/sbitmap.c
++++ b/lib/sbitmap.c
+@@ -540,32 +540,43 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq)
+ return false;
+
+ wait_cnt = atomic_dec_return(&ws->wait_cnt);
+- if (wait_cnt <= 0) {
+- int ret;
++ /*
++ * For concurrent callers of this, callers should call this function
++ * again to wakeup a new batch on a different 'ws'.
++ */
++ if (wait_cnt < 0 || !waitqueue_active(&ws->wait))
++ return true;
+
+- wake_batch = READ_ONCE(sbq->wake_batch);
++ if (wait_cnt > 0)
++ return false;
+
+- /*
+- * Pairs with the memory barrier in sbitmap_queue_resize() to
+- * ensure that we see the batch size update before the wait
+- * count is reset.
+- */
+- smp_mb__before_atomic();
++ wake_batch = READ_ONCE(sbq->wake_batch);
+
+- /*
+- * For concurrent callers of this, the one that failed the
+- * atomic_cmpxhcg() race should call this function again
+- * to wakeup a new batch on a different 'ws'.
+- */
+- ret = atomic_cmpxchg(&ws->wait_cnt, wait_cnt, wake_batch);
+- if (ret == wait_cnt) {
+- sbq_index_atomic_inc(&sbq->wake_index);
+- wake_up_nr(&ws->wait, wake_batch);
+- return false;
+- }
++ /*
++ * Wake up first in case that concurrent callers decrease wait_cnt
++ * while waitqueue is empty.
++ */
++ wake_up_nr(&ws->wait, wake_batch);
+
+- return true;
+- }
++ /*
++ * Pairs with the memory barrier in sbitmap_queue_resize() to
++ * ensure that we see the batch size update before the wait
++ * count is reset.
++ *
++ * Also pairs with the implicit barrier between decrementing wait_cnt
++ * and checking for waitqueue_active() to make sure waitqueue_active()
++ * sees result of the wakeup if atomic_dec_return() has seen the result
++ * of atomic_set().
++ */
++ smp_mb__before_atomic();
++
++ /*
++ * Increase wake_index before updating wait_cnt, otherwise concurrent
++ * callers can see valid wait_cnt in old waitqueue, which can cause
++ * invalid wakeup on the old waitqueue.
++ */
++ sbq_index_atomic_inc(&sbq->wake_index);
++ atomic_set(&ws->wait_cnt, wake_batch);
+
+ return false;
+ }
+--
+2.35.1
+
--- /dev/null
+From 4fdaf7a285b08fb5a48d8d3a880cc935f3f2aacb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 29 Aug 2022 19:01:15 +0800
+Subject: scsi: 3w-9xxx: Avoid disabling device if failing to enable it
+
+From: Letu Ren <fantasquex@gmail.com>
+
+[ Upstream commit 7eff437b5ee1309b34667844361c6bbb5c97df05 ]
+
+The original code will "goto out_disable_device" and call
+pci_disable_device() if pci_enable_device() fails. The kernel will generate
+a warning message like "3w-9xxx 0000:00:05.0: disabling already-disabled
+device".
+
+We shouldn't disable a device that failed to be enabled. A simple return is
+fine.
+
+Link: https://lore.kernel.org/r/20220829110115.38789-1-fantasquex@gmail.com
+Reported-by: Zheyu Ma <zheyuma97@gmail.com>
+Signed-off-by: Letu Ren <fantasquex@gmail.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/3w-9xxx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
+index e41cc354cc8a..6da591508f23 100644
+--- a/drivers/scsi/3w-9xxx.c
++++ b/drivers/scsi/3w-9xxx.c
+@@ -2006,7 +2006,7 @@ static int twa_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
+ retval = pci_enable_device(pdev);
+ if (retval) {
+ TW_PRINTK(host, TW_DRIVER, 0x34, "Failed to enable pci device");
+- goto out_disable_device;
++ return -ENODEV;
+ }
+
+ pci_set_master(pdev);
+--
+2.35.1
+
--- /dev/null
+From 19ff42789bab403696313ddad1e4bd51f408bd07 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Jun 2022 17:45:50 -0500
+Subject: scsi: iscsi: Add recv workqueue helpers
+
+From: Mike Christie <michael.christie@oracle.com>
+
+[ Upstream commit 8af809966c0b34cfacd8da9a412689b8e9910354 ]
+
+Add helpers to allow the drivers to run their recv paths from libiscsi's
+workqueue.
+
+Link: https://lore.kernel.org/r/20220616224557.115234-3-michael.christie@oracle.com
+Reviewed-by: Lee Duncan <lduncan@suse.com>
+Signed-off-by: Mike Christie <michael.christie@oracle.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 57569c37f0ad ("scsi: iscsi: iscsi_tcp: Fix null-ptr-deref while calling getpeername()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/libiscsi.c | 29 +++++++++++++++++++++++++++--
+ include/scsi/libiscsi.h | 4 ++++
+ 2 files changed, 31 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c
+index 1cb18b80d182..73d235540b98 100644
+--- a/drivers/scsi/libiscsi.c
++++ b/drivers/scsi/libiscsi.c
+@@ -93,6 +93,16 @@ inline void iscsi_conn_queue_xmit(struct iscsi_conn *conn)
+ }
+ EXPORT_SYMBOL_GPL(iscsi_conn_queue_xmit);
+
++inline void iscsi_conn_queue_recv(struct iscsi_conn *conn)
++{
++ struct Scsi_Host *shost = conn->session->host;
++ struct iscsi_host *ihost = shost_priv(shost);
++
++ if (ihost->workq && !test_bit(ISCSI_CONN_FLAG_SUSPEND_RX, &conn->flags))
++ queue_work(ihost->workq, &conn->recvwork);
++}
++EXPORT_SYMBOL_GPL(iscsi_conn_queue_recv);
++
+ static void __iscsi_update_cmdsn(struct iscsi_session *session,
+ uint32_t exp_cmdsn, uint32_t max_cmdsn)
+ {
+@@ -1943,7 +1953,7 @@ EXPORT_SYMBOL_GPL(iscsi_suspend_queue);
+
+ /**
+ * iscsi_suspend_tx - suspend iscsi_data_xmit
+- * @conn: iscsi conn tp stop processing IO on.
++ * @conn: iscsi conn to stop processing IO on.
+ *
+ * This function sets the suspend bit to prevent iscsi_data_xmit
+ * from sending new IO, and if work is queued on the xmit thread
+@@ -1956,7 +1966,7 @@ void iscsi_suspend_tx(struct iscsi_conn *conn)
+
+ set_bit(ISCSI_CONN_FLAG_SUSPEND_TX, &conn->flags);
+ if (ihost->workq)
+- flush_workqueue(ihost->workq);
++ flush_work(&conn->xmitwork);
+ }
+ EXPORT_SYMBOL_GPL(iscsi_suspend_tx);
+
+@@ -1966,6 +1976,21 @@ static void iscsi_start_tx(struct iscsi_conn *conn)
+ iscsi_conn_queue_xmit(conn);
+ }
+
++/**
++ * iscsi_suspend_rx - Prevent recvwork from running again.
++ * @conn: iscsi conn to stop.
++ */
++void iscsi_suspend_rx(struct iscsi_conn *conn)
++{
++ struct Scsi_Host *shost = conn->session->host;
++ struct iscsi_host *ihost = shost_priv(shost);
++
++ set_bit(ISCSI_CONN_FLAG_SUSPEND_RX, &conn->flags);
++ if (ihost->workq)
++ flush_work(&conn->recvwork);
++}
++EXPORT_SYMBOL_GPL(iscsi_suspend_rx);
++
+ /*
+ * We want to make sure a ping is in flight. It has timed out.
+ * And we are not busy processing a pdu that is making
+diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
+index ffffce144fdb..5cf84228b51d 100644
+--- a/include/scsi/libiscsi.h
++++ b/include/scsi/libiscsi.h
+@@ -201,6 +201,8 @@ struct iscsi_conn {
+ struct list_head cmdqueue; /* data-path cmd queue */
+ struct list_head requeue; /* tasks needing another run */
+ struct work_struct xmitwork; /* per-conn. xmit workqueue */
++ /* recv */
++ struct work_struct recvwork;
+ unsigned long flags; /* ISCSI_CONN_FLAGs */
+
+ /* negotiated params */
+@@ -441,8 +443,10 @@ extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn,
+ extern int iscsi_conn_get_addr_param(struct sockaddr_storage *addr,
+ enum iscsi_param param, char *buf);
+ extern void iscsi_suspend_tx(struct iscsi_conn *conn);
++extern void iscsi_suspend_rx(struct iscsi_conn *conn);
+ extern void iscsi_suspend_queue(struct iscsi_conn *conn);
+ extern void iscsi_conn_queue_xmit(struct iscsi_conn *conn);
++extern void iscsi_conn_queue_recv(struct iscsi_conn *conn);
+
+ #define iscsi_conn_printk(prefix, _c, fmt, a...) \
+ iscsi_cls_conn_printk(prefix, ((struct iscsi_conn *)_c)->cls_conn, \
+--
+2.35.1
+
--- /dev/null
+From 0a641975c73e0abed2738d4830d5f51b771b82e5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 17:17:00 -0500
+Subject: scsi: iscsi: iscsi_tcp: Fix null-ptr-deref while calling
+ getpeername()
+
+From: Mike Christie <michael.christie@oracle.com>
+
+[ Upstream commit 57569c37f0add1b6489e1a1563c71519daf732cf ]
+
+Fix a NULL pointer crash that occurs when we are freeing the socket at the
+same time we access it via sysfs.
+
+The problem is that:
+
+ 1. iscsi_sw_tcp_conn_get_param() and iscsi_sw_tcp_host_get_param() take
+ the frwd_lock and do sock_hold() then drop the frwd_lock. sock_hold()
+ does a get on the "struct sock".
+
+ 2. iscsi_sw_tcp_release_conn() does sockfd_put() which does the last put
+ on the "struct socket" and that does __sock_release() which sets the
+ sock->ops to NULL.
+
+ 3. iscsi_sw_tcp_conn_get_param() and iscsi_sw_tcp_host_get_param() then
+ call kernel_getpeername() which accesses the NULL sock->ops.
+
+Above we do a get on the "struct sock", but we needed a get on the "struct
+socket". Originally, we just held the frwd_lock the entire time but in
+commit bcf3a2953d36 ("scsi: iscsi: iscsi_tcp: Avoid holding spinlock while
+calling getpeername()") we switched to refcount based because the network
+layer changed and started taking a mutex in that path, so we could no
+longer hold the frwd_lock.
+
+Instead of trying to maintain multiple refcounts, this just has us use a
+mutex for accessing the socket in the interface code paths.
+
+Link: https://lore.kernel.org/r/20220907221700.10302-1-michael.christie@oracle.com
+Fixes: bcf3a2953d36 ("scsi: iscsi: iscsi_tcp: Avoid holding spinlock while calling getpeername()")
+Signed-off-by: Mike Christie <michael.christie@oracle.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/iscsi_tcp.c | 73 ++++++++++++++++++++++++++++------------
+ drivers/scsi/iscsi_tcp.h | 3 ++
+ 2 files changed, 55 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c
+index 20b4394d560b..4d2f33087806 100644
+--- a/drivers/scsi/iscsi_tcp.c
++++ b/drivers/scsi/iscsi_tcp.c
+@@ -595,6 +595,8 @@ iscsi_sw_tcp_conn_create(struct iscsi_cls_session *cls_session,
+ INIT_WORK(&conn->recvwork, iscsi_sw_tcp_recv_data_work);
+ tcp_sw_conn->queue_recv = iscsi_recv_from_iscsi_q;
+
++ mutex_init(&tcp_sw_conn->sock_lock);
++
+ tfm = crypto_alloc_ahash("crc32c", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(tfm))
+ goto free_conn;
+@@ -629,11 +631,15 @@ iscsi_sw_tcp_conn_create(struct iscsi_cls_session *cls_session,
+
+ static void iscsi_sw_tcp_release_conn(struct iscsi_conn *conn)
+ {
+- struct iscsi_session *session = conn->session;
+ struct iscsi_tcp_conn *tcp_conn = conn->dd_data;
+ struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data;
+ struct socket *sock = tcp_sw_conn->sock;
+
++ /*
++ * The iscsi transport class will make sure we are not called in
++ * parallel with start, stop, bind and destroys. However, this can be
++ * called twice if userspace does a stop then a destroy.
++ */
+ if (!sock)
+ return;
+
+@@ -649,9 +655,9 @@ static void iscsi_sw_tcp_release_conn(struct iscsi_conn *conn)
+
+ iscsi_suspend_rx(conn);
+
+- spin_lock_bh(&session->frwd_lock);
++ mutex_lock(&tcp_sw_conn->sock_lock);
+ tcp_sw_conn->sock = NULL;
+- spin_unlock_bh(&session->frwd_lock);
++ mutex_unlock(&tcp_sw_conn->sock_lock);
+ sockfd_put(sock);
+ }
+
+@@ -703,7 +709,6 @@ iscsi_sw_tcp_conn_bind(struct iscsi_cls_session *cls_session,
+ struct iscsi_cls_conn *cls_conn, uint64_t transport_eph,
+ int is_leading)
+ {
+- struct iscsi_session *session = cls_session->dd_data;
+ struct iscsi_conn *conn = cls_conn->dd_data;
+ struct iscsi_tcp_conn *tcp_conn = conn->dd_data;
+ struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data;
+@@ -723,10 +728,10 @@ iscsi_sw_tcp_conn_bind(struct iscsi_cls_session *cls_session,
+ if (err)
+ goto free_socket;
+
+- spin_lock_bh(&session->frwd_lock);
++ mutex_lock(&tcp_sw_conn->sock_lock);
+ /* bind iSCSI connection and socket */
+ tcp_sw_conn->sock = sock;
+- spin_unlock_bh(&session->frwd_lock);
++ mutex_unlock(&tcp_sw_conn->sock_lock);
+
+ /* setup Socket parameters */
+ sk = sock->sk;
+@@ -763,8 +768,15 @@ static int iscsi_sw_tcp_conn_set_param(struct iscsi_cls_conn *cls_conn,
+ break;
+ case ISCSI_PARAM_DATADGST_EN:
+ iscsi_set_param(cls_conn, param, buf, buflen);
++
++ mutex_lock(&tcp_sw_conn->sock_lock);
++ if (!tcp_sw_conn->sock) {
++ mutex_unlock(&tcp_sw_conn->sock_lock);
++ return -ENOTCONN;
++ }
+ tcp_sw_conn->sendpage = conn->datadgst_en ?
+ sock_no_sendpage : tcp_sw_conn->sock->ops->sendpage;
++ mutex_unlock(&tcp_sw_conn->sock_lock);
+ break;
+ case ISCSI_PARAM_MAX_R2T:
+ return iscsi_tcp_set_max_r2t(conn, buf);
+@@ -779,8 +791,8 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn,
+ enum iscsi_param param, char *buf)
+ {
+ struct iscsi_conn *conn = cls_conn->dd_data;
+- struct iscsi_tcp_conn *tcp_conn = conn->dd_data;
+- struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data;
++ struct iscsi_sw_tcp_conn *tcp_sw_conn;
++ struct iscsi_tcp_conn *tcp_conn;
+ struct sockaddr_in6 addr;
+ struct socket *sock;
+ int rc;
+@@ -790,21 +802,36 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn,
+ case ISCSI_PARAM_CONN_ADDRESS:
+ case ISCSI_PARAM_LOCAL_PORT:
+ spin_lock_bh(&conn->session->frwd_lock);
+- if (!tcp_sw_conn || !tcp_sw_conn->sock) {
++ if (!conn->session->leadconn) {
+ spin_unlock_bh(&conn->session->frwd_lock);
+ return -ENOTCONN;
+ }
+- sock = tcp_sw_conn->sock;
+- sock_hold(sock->sk);
++ /*
++ * The conn has been setup and bound, so just grab a ref
++ * incase a destroy runs while we are in the net layer.
++ */
++ iscsi_get_conn(conn->cls_conn);
+ spin_unlock_bh(&conn->session->frwd_lock);
+
++ tcp_conn = conn->dd_data;
++ tcp_sw_conn = tcp_conn->dd_data;
++
++ mutex_lock(&tcp_sw_conn->sock_lock);
++ sock = tcp_sw_conn->sock;
++ if (!sock) {
++ rc = -ENOTCONN;
++ goto sock_unlock;
++ }
++
+ if (param == ISCSI_PARAM_LOCAL_PORT)
+ rc = kernel_getsockname(sock,
+ (struct sockaddr *)&addr);
+ else
+ rc = kernel_getpeername(sock,
+ (struct sockaddr *)&addr);
+- sock_put(sock->sk);
++sock_unlock:
++ mutex_unlock(&tcp_sw_conn->sock_lock);
++ iscsi_put_conn(conn->cls_conn);
+ if (rc < 0)
+ return rc;
+
+@@ -842,17 +869,21 @@ static int iscsi_sw_tcp_host_get_param(struct Scsi_Host *shost,
+ }
+ tcp_conn = conn->dd_data;
+ tcp_sw_conn = tcp_conn->dd_data;
+- sock = tcp_sw_conn->sock;
+- if (!sock) {
+- spin_unlock_bh(&session->frwd_lock);
+- return -ENOTCONN;
+- }
+- sock_hold(sock->sk);
++ /*
++ * The conn has been setup and bound, so just grab a ref
++ * incase a destroy runs while we are in the net layer.
++ */
++ iscsi_get_conn(conn->cls_conn);
+ spin_unlock_bh(&session->frwd_lock);
+
+- rc = kernel_getsockname(sock,
+- (struct sockaddr *)&addr);
+- sock_put(sock->sk);
++ mutex_lock(&tcp_sw_conn->sock_lock);
++ sock = tcp_sw_conn->sock;
++ if (!sock)
++ rc = -ENOTCONN;
++ else
++ rc = kernel_getsockname(sock, (struct sockaddr *)&addr);
++ mutex_unlock(&tcp_sw_conn->sock_lock);
++ iscsi_put_conn(conn->cls_conn);
+ if (rc < 0)
+ return rc;
+
+diff --git a/drivers/scsi/iscsi_tcp.h b/drivers/scsi/iscsi_tcp.h
+index 850a018aefb9..68e14a344904 100644
+--- a/drivers/scsi/iscsi_tcp.h
++++ b/drivers/scsi/iscsi_tcp.h
+@@ -28,6 +28,9 @@ struct iscsi_sw_tcp_send {
+
+ struct iscsi_sw_tcp_conn {
+ struct socket *sock;
++ /* Taken when accessing the sock from the netlink/sysfs interface */
++ struct mutex sock_lock;
++
+ struct work_struct recvwork;
+ bool queue_recv;
+
+--
+2.35.1
+
--- /dev/null
+From ce8d25ec1c21c6b442b3aa3405a2b9d8504d31ee Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Jun 2022 17:45:49 -0500
+Subject: scsi: iscsi: Rename iscsi_conn_queue_work()
+
+From: Mike Christie <michael.christie@oracle.com>
+
+[ Upstream commit 4b9f8ce4d5e823e42944c5a0a4842b0f936365ad ]
+
+Rename iscsi_conn_queue_work() to iscsi_conn_queue_xmit() to reflect that
+it handles queueing of xmits only.
+
+Link: https://lore.kernel.org/r/20220616224557.115234-2-michael.christie@oracle.com
+Reviewed-by: Lee Duncan <lduncan@suse.com>
+Reviewed-by: Wu Bo <wubo40@huawei.com>
+Signed-off-by: Mike Christie <michael.christie@oracle.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 57569c37f0ad ("scsi: iscsi: iscsi_tcp: Fix null-ptr-deref while calling getpeername()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/cxgbi/libcxgbi.c | 2 +-
+ drivers/scsi/iscsi_tcp.c | 2 +-
+ drivers/scsi/libiscsi.c | 12 ++++++------
+ include/scsi/libiscsi.h | 2 +-
+ 4 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/scsi/cxgbi/libcxgbi.c b/drivers/scsi/cxgbi/libcxgbi.c
+index 32abdf0fa9aa..af281e271f88 100644
+--- a/drivers/scsi/cxgbi/libcxgbi.c
++++ b/drivers/scsi/cxgbi/libcxgbi.c
+@@ -1455,7 +1455,7 @@ void cxgbi_conn_tx_open(struct cxgbi_sock *csk)
+ if (conn) {
+ log_debug(1 << CXGBI_DBG_SOCK,
+ "csk 0x%p, cid %d.\n", csk, conn->id);
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ }
+ }
+ EXPORT_SYMBOL_GPL(cxgbi_conn_tx_open);
+diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c
+index 0e52c6499eaf..e7976785dae6 100644
+--- a/drivers/scsi/iscsi_tcp.c
++++ b/drivers/scsi/iscsi_tcp.c
+@@ -205,7 +205,7 @@ static void iscsi_sw_tcp_write_space(struct sock *sk)
+ old_write_space(sk);
+
+ ISCSI_SW_TCP_DBG(conn, "iscsi_write_space\n");
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ }
+
+ static void iscsi_sw_tcp_conn_set_callbacks(struct iscsi_conn *conn)
+diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c
+index 78de36250b31..1cb18b80d182 100644
+--- a/drivers/scsi/libiscsi.c
++++ b/drivers/scsi/libiscsi.c
+@@ -83,7 +83,7 @@ MODULE_PARM_DESC(debug_libiscsi_eh,
+ "%s " dbg_fmt, __func__, ##arg); \
+ } while (0);
+
+-inline void iscsi_conn_queue_work(struct iscsi_conn *conn)
++inline void iscsi_conn_queue_xmit(struct iscsi_conn *conn)
+ {
+ struct Scsi_Host *shost = conn->session->host;
+ struct iscsi_host *ihost = shost_priv(shost);
+@@ -91,7 +91,7 @@ inline void iscsi_conn_queue_work(struct iscsi_conn *conn)
+ if (ihost->workq)
+ queue_work(ihost->workq, &conn->xmitwork);
+ }
+-EXPORT_SYMBOL_GPL(iscsi_conn_queue_work);
++EXPORT_SYMBOL_GPL(iscsi_conn_queue_xmit);
+
+ static void __iscsi_update_cmdsn(struct iscsi_session *session,
+ uint32_t exp_cmdsn, uint32_t max_cmdsn)
+@@ -765,7 +765,7 @@ __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr,
+ goto free_task;
+ } else {
+ list_add_tail(&task->running, &conn->mgmtqueue);
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ }
+
+ return task;
+@@ -1513,7 +1513,7 @@ void iscsi_requeue_task(struct iscsi_task *task)
+ */
+ iscsi_put_task(task);
+ }
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ spin_unlock_bh(&conn->session->frwd_lock);
+ }
+ EXPORT_SYMBOL_GPL(iscsi_requeue_task);
+@@ -1782,7 +1782,7 @@ int iscsi_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *sc)
+ }
+ } else {
+ list_add_tail(&task->running, &conn->cmdqueue);
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ }
+
+ session->queued_cmdsn++;
+@@ -1963,7 +1963,7 @@ EXPORT_SYMBOL_GPL(iscsi_suspend_tx);
+ static void iscsi_start_tx(struct iscsi_conn *conn)
+ {
+ clear_bit(ISCSI_CONN_FLAG_SUSPEND_TX, &conn->flags);
+- iscsi_conn_queue_work(conn);
++ iscsi_conn_queue_xmit(conn);
+ }
+
+ /*
+diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
+index a071f6ffd7fa..ffffce144fdb 100644
+--- a/include/scsi/libiscsi.h
++++ b/include/scsi/libiscsi.h
+@@ -442,7 +442,7 @@ extern int iscsi_conn_get_addr_param(struct sockaddr_storage *addr,
+ enum iscsi_param param, char *buf);
+ extern void iscsi_suspend_tx(struct iscsi_conn *conn);
+ extern void iscsi_suspend_queue(struct iscsi_conn *conn);
+-extern void iscsi_conn_queue_work(struct iscsi_conn *conn);
++extern void iscsi_conn_queue_xmit(struct iscsi_conn *conn);
+
+ #define iscsi_conn_printk(prefix, _c, fmt, a...) \
+ iscsi_cls_conn_printk(prefix, ((struct iscsi_conn *)_c)->cls_conn, \
+--
+2.35.1
+
--- /dev/null
+From a55b58153633e1cf0bae3bea071e9101d9f974b5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Jun 2022 17:45:51 -0500
+Subject: scsi: iscsi: Run recv path from workqueue
+
+From: Mike Christie <michael.christie@oracle.com>
+
+[ Upstream commit f1d269765ee29da56b32818b7a08054484ed89f2 ]
+
+We don't always want to run the recv path from the network softirq because
+when we have to have multiple sessions sharing the same CPUs, some sessions
+can eat up the NAPI softirq budget and affect other sessions or users.
+
+Allow us to queue the recv handling to the iscsi workqueue so we can have
+the scheduler/wq code try to balance the work and CPU use across all
+sessions' worker threads.
+
+Note: It wasn't the original intent of the change but a nice side effect is
+that for some workloads/configs we get a nice performance boost. For a
+simple read heavy test:
+
+ fio --direct=1 --filename=/dev/dm-0 --rw=randread --bs=256K
+ --ioengine=libaio --iodepth=128 --numjobs=4
+
+where the iscsi threads, fio jobs, and rps_cpus share CPUs we see a 32%
+throughput boost. We also see increases for small I/O IOPs tests but it's
+not as high.
+
+Link: https://lore.kernel.org/r/20220616224557.115234-4-michael.christie@oracle.com
+Reviewed-by: Lee Duncan <lduncan@suse.com>
+Signed-off-by: Mike Christie <michael.christie@oracle.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 57569c37f0ad ("scsi: iscsi: iscsi_tcp: Fix null-ptr-deref while calling getpeername()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/iscsi_tcp.c | 65 ++++++++++++++++++++++++++++++++--------
+ drivers/scsi/iscsi_tcp.h | 2 ++
+ 2 files changed, 54 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c
+index e7976785dae6..20b4394d560b 100644
+--- a/drivers/scsi/iscsi_tcp.c
++++ b/drivers/scsi/iscsi_tcp.c
+@@ -52,6 +52,10 @@ static struct iscsi_transport iscsi_sw_tcp_transport;
+ static unsigned int iscsi_max_lun = ~0;
+ module_param_named(max_lun, iscsi_max_lun, uint, S_IRUGO);
+
++static bool iscsi_recv_from_iscsi_q;
++module_param_named(recv_from_iscsi_q, iscsi_recv_from_iscsi_q, bool, 0644);
++MODULE_PARM_DESC(recv_from_iscsi_q, "Set to true to read iSCSI data/headers from the iscsi_q workqueue. The default is false which will perform reads from the network softirq context.");
++
+ static int iscsi_sw_tcp_dbg;
+ module_param_named(debug_iscsi_tcp, iscsi_sw_tcp_dbg, int,
+ S_IRUGO | S_IWUSR);
+@@ -122,20 +126,13 @@ static inline int iscsi_sw_sk_state_check(struct sock *sk)
+ return 0;
+ }
+
+-static void iscsi_sw_tcp_data_ready(struct sock *sk)
++static void iscsi_sw_tcp_recv_data(struct iscsi_conn *conn)
+ {
+- struct iscsi_conn *conn;
+- struct iscsi_tcp_conn *tcp_conn;
++ struct iscsi_tcp_conn *tcp_conn = conn->dd_data;
++ struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data;
++ struct sock *sk = tcp_sw_conn->sock->sk;
+ read_descriptor_t rd_desc;
+
+- read_lock_bh(&sk->sk_callback_lock);
+- conn = sk->sk_user_data;
+- if (!conn) {
+- read_unlock_bh(&sk->sk_callback_lock);
+- return;
+- }
+- tcp_conn = conn->dd_data;
+-
+ /*
+ * Use rd_desc to pass 'conn' to iscsi_tcp_recv.
+ * We set count to 1 because we want the network layer to
+@@ -144,13 +141,48 @@ static void iscsi_sw_tcp_data_ready(struct sock *sk)
+ */
+ rd_desc.arg.data = conn;
+ rd_desc.count = 1;
+- tcp_read_sock(sk, &rd_desc, iscsi_sw_tcp_recv);
+
+- iscsi_sw_sk_state_check(sk);
++ tcp_read_sock(sk, &rd_desc, iscsi_sw_tcp_recv);
+
+ /* If we had to (atomically) map a highmem page,
+ * unmap it now. */
+ iscsi_tcp_segment_unmap(&tcp_conn->in.segment);
++
++ iscsi_sw_sk_state_check(sk);
++}
++
++static void iscsi_sw_tcp_recv_data_work(struct work_struct *work)
++{
++ struct iscsi_conn *conn = container_of(work, struct iscsi_conn,
++ recvwork);
++ struct iscsi_tcp_conn *tcp_conn = conn->dd_data;
++ struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data;
++ struct sock *sk = tcp_sw_conn->sock->sk;
++
++ lock_sock(sk);
++ iscsi_sw_tcp_recv_data(conn);
++ release_sock(sk);
++}
++
++static void iscsi_sw_tcp_data_ready(struct sock *sk)
++{
++ struct iscsi_sw_tcp_conn *tcp_sw_conn;
++ struct iscsi_tcp_conn *tcp_conn;
++ struct iscsi_conn *conn;
++
++ read_lock_bh(&sk->sk_callback_lock);
++ conn = sk->sk_user_data;
++ if (!conn) {
++ read_unlock_bh(&sk->sk_callback_lock);
++ return;
++ }
++ tcp_conn = conn->dd_data;
++ tcp_sw_conn = tcp_conn->dd_data;
++
++ if (tcp_sw_conn->queue_recv)
++ iscsi_conn_queue_recv(conn);
++ else
++ iscsi_sw_tcp_recv_data(conn);
+ read_unlock_bh(&sk->sk_callback_lock);
+ }
+
+@@ -276,6 +308,9 @@ static int iscsi_sw_tcp_xmit_segment(struct iscsi_tcp_conn *tcp_conn,
+ if (segment->total_copied + segment->size < segment->total_size)
+ flags |= MSG_MORE;
+
++ if (tcp_sw_conn->queue_recv)
++ flags |= MSG_DONTWAIT;
++
+ /* Use sendpage if we can; else fall back to sendmsg */
+ if (!segment->data) {
+ sg = segment->sg;
+@@ -557,6 +592,8 @@ iscsi_sw_tcp_conn_create(struct iscsi_cls_session *cls_session,
+ conn = cls_conn->dd_data;
+ tcp_conn = conn->dd_data;
+ tcp_sw_conn = tcp_conn->dd_data;
++ INIT_WORK(&conn->recvwork, iscsi_sw_tcp_recv_data_work);
++ tcp_sw_conn->queue_recv = iscsi_recv_from_iscsi_q;
+
+ tfm = crypto_alloc_ahash("crc32c", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(tfm))
+@@ -610,6 +647,8 @@ static void iscsi_sw_tcp_release_conn(struct iscsi_conn *conn)
+ iscsi_sw_tcp_conn_restore_callbacks(conn);
+ sock_put(sock->sk);
+
++ iscsi_suspend_rx(conn);
++
+ spin_lock_bh(&session->frwd_lock);
+ tcp_sw_conn->sock = NULL;
+ spin_unlock_bh(&session->frwd_lock);
+diff --git a/drivers/scsi/iscsi_tcp.h b/drivers/scsi/iscsi_tcp.h
+index 791453195099..850a018aefb9 100644
+--- a/drivers/scsi/iscsi_tcp.h
++++ b/drivers/scsi/iscsi_tcp.h
+@@ -28,6 +28,8 @@ struct iscsi_sw_tcp_send {
+
+ struct iscsi_sw_tcp_conn {
+ struct socket *sock;
++ struct work_struct recvwork;
++ bool queue_recv;
+
+ struct iscsi_sw_tcp_send out;
+ /* old values for socket callbacks */
+--
+2.35.1
+
--- /dev/null
+From 8f4409a7756215adc8c9e08884326e5249917a68 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 22:42:13 +0800
+Subject: scsi: libsas: Fix use-after-free bug in smp_execute_task_sg()
+
+From: Duoming Zhou <duoming@zju.edu.cn>
+
+[ Upstream commit 46ba53c30666717cb06c2b3c5d896301cd00d0c0 ]
+
+When executing SMP task failed, the smp_execute_task_sg() calls del_timer()
+to delete "slow_task->timer". However, if the timer handler
+sas_task_internal_timedout() is running, the del_timer() in
+smp_execute_task_sg() will not stop it and a UAF will happen. The process
+is shown below:
+
+ (thread 1) | (thread 2)
+smp_execute_task_sg() | sas_task_internal_timedout()
+ ... |
+ del_timer() |
+ ... | ...
+ sas_free_task(task) |
+ kfree(task->slow_task) //FREE|
+ | task->slow_task->... //USE
+
+Fix by calling del_timer_sync() in smp_execute_task_sg(), which makes sure
+the timer handler have finished before the "task->slow_task" is
+deallocated.
+
+Link: https://lore.kernel.org/r/20220920144213.10536-1-duoming@zju.edu.cn
+Fixes: 2908d778ab3e ("[SCSI] aic94xx: new driver")
+Reviewed-by: Jason Yan <yanaijie@huawei.com>
+Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/libsas/sas_expander.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/scsi/libsas/sas_expander.c b/drivers/scsi/libsas/sas_expander.c
+index c2150a818423..9ae35631135d 100644
+--- a/drivers/scsi/libsas/sas_expander.c
++++ b/drivers/scsi/libsas/sas_expander.c
+@@ -85,7 +85,7 @@ static int smp_execute_task_sg(struct domain_device *dev,
+ res = i->dft->lldd_execute_task(task, GFP_KERNEL);
+
+ if (res) {
+- del_timer(&task->slow_task->timer);
++ del_timer_sync(&task->slow_task->timer);
+ pr_notice("executing SMP task failed:%d\n", res);
+ break;
+ }
+--
+2.35.1
+
--- /dev/null
+From 4f53b72231d8ab8fc2953a035b95edd3fec6a26a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 19 May 2022 05:31:07 -0700
+Subject: scsi: nvme-fc: Add new routine nvme_fc_io_getuuid()
+
+From: Muneendra Kumar <muneendra.kumar@broadcom.com>
+
+[ Upstream commit 827fc630e4c8087df5a8e8ee013b686bd6f13736 ]
+
+Add nvme_fc_io_getuuid() to the nvme-fc transport. The routine is invoked
+by the FC LLDD on a per-I/O request basis. The routine translates from the
+FC-specific request structure to the bio and the cgroup structure in order
+to obtain the FC appid stored in the cgroup structure. If a value is not
+set or a bio is not found, a NULL appid (aka uuid) will be returned to the
+LLDD.
+
+Link: https://lore.kernel.org/r/20220519123110.17361-2-jsmart2021@gmail.com
+Reviewed-by: Hannes Reinecke <hare@suse.de>
+Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
+Acked-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Muneendra Kumar <muneendra.kumar@broadcom.com>
+Signed-off-by: James Smart <jsmart2021@gmail.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: a4de8356b68e ("scsi: lpfc: Fix various issues reported by tools")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/nvme/host/fc.c | 18 ++++++++++++++++++
+ include/linux/nvme-fc-driver.h | 14 ++++++++++++++
+ 2 files changed, 32 insertions(+)
+
+diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c
+index aa14ad963d91..fe21fd161897 100644
+--- a/drivers/nvme/host/fc.c
++++ b/drivers/nvme/host/fc.c
+@@ -1898,6 +1898,24 @@ nvme_fc_ctrl_ioerr_work(struct work_struct *work)
+ nvme_fc_error_recovery(ctrl, "transport detected io error");
+ }
+
++/*
++ * nvme_fc_io_getuuid - Routine called to get the appid field
++ * associated with request by the lldd
++ * @req:IO request from nvme fc to driver
++ * Returns: UUID if there is an appid associated with VM or
++ * NULL if the user/libvirt has not set the appid to VM
++ */
++char *nvme_fc_io_getuuid(struct nvmefc_fcp_req *req)
++{
++ struct nvme_fc_fcp_op *op = fcp_req_to_fcp_op(req);
++ struct request *rq = op->rq;
++
++ if (!IS_ENABLED(CONFIG_BLK_CGROUP_FC_APPID) || !rq->bio)
++ return NULL;
++ return blkcg_get_fc_appid(rq->bio);
++}
++EXPORT_SYMBOL_GPL(nvme_fc_io_getuuid);
++
+ static void
+ nvme_fc_fcpio_done(struct nvmefc_fcp_req *req)
+ {
+diff --git a/include/linux/nvme-fc-driver.h b/include/linux/nvme-fc-driver.h
+index 2a38f2b477a5..9a274b999a48 100644
+--- a/include/linux/nvme-fc-driver.h
++++ b/include/linux/nvme-fc-driver.h
+@@ -561,6 +561,15 @@ int nvme_fc_rcv_ls_req(struct nvme_fc_remote_port *remoteport,
+ void *lsreqbuf, u32 lsreqbuf_len);
+
+
++/*
++ * Routine called to get the appid field associated with request by the lldd
++ *
++ * If the return value is NULL : the user/libvirt has not set the appid to VM
++ * If the return value is non-zero: Returns the appid associated with VM
++ *
++ * @req: IO request from nvme fc to driver
++ */
++char *nvme_fc_io_getuuid(struct nvmefc_fcp_req *req);
+
+ /*
+ * *************** LLDD FC-NVME Target/Subsystem API ***************
+@@ -1041,5 +1050,10 @@ int nvmet_fc_rcv_fcp_req(struct nvmet_fc_target_port *tgtport,
+
+ void nvmet_fc_rcv_fcp_abort(struct nvmet_fc_target_port *tgtport,
+ struct nvmefc_tgt_fcp_req *fcpreq);
++/*
++ * add a define, visible to the compiler, that indicates support
++ * for feature. Allows for conditional compilation in LLDDs.
++ */
++#define NVME_FC_FEAT_UUID 0x0001
+
+ #endif /* _NVME_FC_DRIVER_H */
+--
+2.35.1
+
--- /dev/null
+From 6dfe3990e4f450d8abae8ddb71ba0a20651877af Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 16:33:08 -0700
+Subject: scsi: tracing: Fix compile error in trace_array calls when TRACING is
+ disabled
+
+From: Arun Easi <aeasi@marvell.com>
+
+[ Upstream commit 1a77dd1c2bb5d4a58c16d198cf593720787c02e4 ]
+
+Fix this compilation error seen when CONFIG_TRACING is not enabled:
+
+drivers/scsi/qla2xxx/qla_os.c: In function 'qla_trace_init':
+drivers/scsi/qla2xxx/qla_os.c:2854:25: error: implicit declaration of function
+'trace_array_get_by_name'; did you mean 'trace_array_set_clr_event'?
+[-Werror=implicit-function-declaration]
+ 2854 | qla_trc_array = trace_array_get_by_name("qla2xxx");
+ | ^~~~~~~~~~~~~~~~~~~~~~~
+ | trace_array_set_clr_event
+
+drivers/scsi/qla2xxx/qla_os.c: In function 'qla_trace_uninit':
+drivers/scsi/qla2xxx/qla_os.c:2869:9: error: implicit declaration of function
+'trace_array_put' [-Werror=implicit-function-declaration]
+ 2869 | trace_array_put(qla_trc_array);
+ | ^~~~~~~~~~~~~~~
+
+Link: https://lore.kernel.org/r/20220907233308.4153-2-aeasi@marvell.com
+Reported-by: kernel test robot <lkp@intel.com>
+Reviewed-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Arun Easi <aeasi@marvell.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/trace.h | 36 ++++++++++++++++++++++++++++++++++--
+ 1 file changed, 34 insertions(+), 2 deletions(-)
+
+diff --git a/include/linux/trace.h b/include/linux/trace.h
+index bf169612ffe1..b5e16e438448 100644
+--- a/include/linux/trace.h
++++ b/include/linux/trace.h
+@@ -2,8 +2,6 @@
+ #ifndef _LINUX_TRACE_H
+ #define _LINUX_TRACE_H
+
+-#ifdef CONFIG_TRACING
+-
+ #define TRACE_EXPORT_FUNCTION BIT(0)
+ #define TRACE_EXPORT_EVENT BIT(1)
+ #define TRACE_EXPORT_MARKER BIT(2)
+@@ -28,6 +26,8 @@ struct trace_export {
+ int flags;
+ };
+
++#ifdef CONFIG_TRACING
++
+ int register_ftrace_export(struct trace_export *export);
+ int unregister_ftrace_export(struct trace_export *export);
+
+@@ -48,6 +48,38 @@ void osnoise_arch_unregister(void);
+ void osnoise_trace_irq_entry(int id);
+ void osnoise_trace_irq_exit(int id, const char *desc);
+
++#else /* CONFIG_TRACING */
++static inline int register_ftrace_export(struct trace_export *export)
++{
++ return -EINVAL;
++}
++static inline int unregister_ftrace_export(struct trace_export *export)
++{
++ return 0;
++}
++static inline void trace_printk_init_buffers(void)
++{
++}
++static inline int trace_array_printk(struct trace_array *tr, unsigned long ip,
++ const char *fmt, ...)
++{
++ return 0;
++}
++static inline int trace_array_init_printk(struct trace_array *tr)
++{
++ return -EINVAL;
++}
++static inline void trace_array_put(struct trace_array *tr)
++{
++}
++static inline struct trace_array *trace_array_get_by_name(const char *name)
++{
++ return NULL;
++}
++static inline int trace_array_destroy(struct trace_array *tr)
++{
++ return 0;
++}
+ #endif /* CONFIG_TRACING */
+
+ #endif /* _LINUX_TRACE_H */
+--
+2.35.1
+
--- /dev/null
+From 7570689b32a7e44eafdaf9b1aa77aad92390a6af Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 14:10:13 -0400
+Subject: sctp: handle the error returned from sctp_auth_asoc_init_active_key
+
+From: Xin Long <lucien.xin@gmail.com>
+
+[ Upstream commit 022152aaebe116a25c39818a07e175a8cd3c1e11 ]
+
+When it returns an error from sctp_auth_asoc_init_active_key(), the
+active_key is actually not updated. The old sh_key will be freeed
+while it's still used as active key in asoc. Then an use-after-free
+will be triggered when sending patckets, as found by syzbot:
+
+ sctp_auth_shkey_hold+0x22/0xa0 net/sctp/auth.c:112
+ sctp_set_owner_w net/sctp/socket.c:132 [inline]
+ sctp_sendmsg_to_asoc+0xbd5/0x1a20 net/sctp/socket.c:1863
+ sctp_sendmsg+0x1053/0x1d50 net/sctp/socket.c:2025
+ inet_sendmsg+0x99/0xe0 net/ipv4/af_inet.c:819
+ sock_sendmsg_nosec net/socket.c:714 [inline]
+ sock_sendmsg+0xcf/0x120 net/socket.c:734
+
+This patch is to fix it by not replacing the sh_key when it returns
+errors from sctp_auth_asoc_init_active_key() in sctp_auth_set_key().
+For sctp_auth_set_active_key(), old active_key_id will be set back
+to asoc->active_key_id when the same thing happens.
+
+Fixes: 58acd1009226 ("sctp: update active_key for asoc when old key is being replaced")
+Reported-by: syzbot+a236dd8e9622ed8954a3@syzkaller.appspotmail.com
+Signed-off-by: Xin Long <lucien.xin@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/sctp/auth.c | 18 ++++++++++++++----
+ 1 file changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/net/sctp/auth.c b/net/sctp/auth.c
+index db6b7373d16c..34964145514e 100644
+--- a/net/sctp/auth.c
++++ b/net/sctp/auth.c
+@@ -863,12 +863,17 @@ int sctp_auth_set_key(struct sctp_endpoint *ep,
+ }
+
+ list_del_init(&shkey->key_list);
+- sctp_auth_shkey_release(shkey);
+ list_add(&cur_key->key_list, sh_keys);
+
+- if (asoc && asoc->active_key_id == auth_key->sca_keynumber)
+- sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL);
++ if (asoc && asoc->active_key_id == auth_key->sca_keynumber &&
++ sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL)) {
++ list_del_init(&cur_key->key_list);
++ sctp_auth_shkey_release(cur_key);
++ list_add(&shkey->key_list, sh_keys);
++ return -ENOMEM;
++ }
+
++ sctp_auth_shkey_release(shkey);
+ return 0;
+ }
+
+@@ -902,8 +907,13 @@ int sctp_auth_set_active_key(struct sctp_endpoint *ep,
+ return -EINVAL;
+
+ if (asoc) {
++ __u16 active_key_id = asoc->active_key_id;
++
+ asoc->active_key_id = key_id;
+- sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL);
++ if (sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL)) {
++ asoc->active_key_id = active_key_id;
++ return -ENOMEM;
++ }
+ } else
+ ep->active_key_id = key_id;
+
+--
+2.35.1
+
--- /dev/null
+From 760c9c3184458f07e3b93f1b3be18011c62735f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 09:15:18 -0400
+Subject: selftest: tpm2: Add Client.__del__() to close /dev/tpm* handle
+
+From: Stefan Berger <stefanb@linux.ibm.com>
+
+[ Upstream commit 2d869f0b458547386fbcd8cf3004b271b7347b7f ]
+
+The following output can bee seen when the test is executed:
+
+ test_flush_context (tpm2_tests.SpaceTest) ... \
+ /usr/lib64/python3.6/unittest/case.py:605: ResourceWarning: \
+ unclosed file <_io.FileIO name='/dev/tpmrm0' mode='rb+' closefd=True>
+
+An instance of Client does not implicitly close /dev/tpm* handle, once it
+gets destroyed. Close the file handle in the class destructor
+Client.__del__().
+
+Fixes: 6ea3dfe1e0732 ("selftests: add TPM 2.0 tests")
+Cc: Shuah Khan <shuah@kernel.org>
+Cc: linux-kselftest@vger.kernel.org
+Cc: Jarkko Sakkinen <jarkko@kernel.org>
+Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
+Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
+Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/tpm2/tpm2.py | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/tools/testing/selftests/tpm2/tpm2.py b/tools/testing/selftests/tpm2/tpm2.py
+index f34486cd7342..3e67fdb518ec 100644
+--- a/tools/testing/selftests/tpm2/tpm2.py
++++ b/tools/testing/selftests/tpm2/tpm2.py
+@@ -370,6 +370,10 @@ class Client:
+ fcntl.fcntl(self.tpm, fcntl.F_SETFL, flags)
+ self.tpm_poll = select.poll()
+
++ def __del__(self):
++ if self.tpm:
++ self.tpm.close()
++
+ def close(self):
+ self.tpm.close()
+
+--
+2.35.1
+
--- /dev/null
+From 4d3881eb92faefb485682cc65edb701ab10d456f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Sep 2022 21:36:12 +0800
+Subject: selftests/cpu-hotplug: Use return instead of exit
+
+From: Zhao Gongyi <zhaogongyi@huawei.com>
+
+[ Upstream commit 972cf4ce51ef5532d56822af17defb148aac0ccb ]
+
+Some cpus will be left in offline state when online
+function exits in some error conditions. Use return
+instead of exit to fix it.
+
+Signed-off-by: Zhao Gongyi <zhaogongyi@huawei.com>
+Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../selftests/cpu-hotplug/cpu-on-off-test.sh | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh b/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh
+index 0d26b5e3f966..940b68c940bb 100755
+--- a/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh
++++ b/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh
+@@ -4,6 +4,7 @@
+ SYSFS=
+ # Kselftest framework requirement - SKIP code is 4.
+ ksft_skip=4
++retval=0
+
+ prerequisite()
+ {
+@@ -102,10 +103,10 @@ online_cpu_expect_success()
+
+ if ! online_cpu $cpu; then
+ echo $FUNCNAME $cpu: unexpected fail >&2
+- exit 1
++ retval=1
+ elif ! cpu_is_online $cpu; then
+ echo $FUNCNAME $cpu: unexpected offline >&2
+- exit 1
++ retval=1
+ fi
+ }
+
+@@ -128,10 +129,10 @@ offline_cpu_expect_success()
+
+ if ! offline_cpu $cpu; then
+ echo $FUNCNAME $cpu: unexpected fail >&2
+- exit 1
++ retval=1
+ elif ! cpu_is_offline $cpu; then
+ echo $FUNCNAME $cpu: unexpected offline >&2
+- exit 1
++ retval=1
+ fi
+ }
+
+@@ -201,7 +202,7 @@ if [ $allcpus -eq 0 ]; then
+ offline_cpu_expect_success $present_max
+ online_cpu $present_max
+ fi
+- exit 0
++ exit $retval
+ else
+ echo "Full scope test: all hotplug cpus"
+ echo -e "\t online all offline cpus"
+@@ -291,3 +292,5 @@ done
+
+ echo 0 > $NOTIFIER_ERR_INJECT_DIR/actions/CPU_DOWN_PREPARE/error
+ /sbin/modprobe -q -r cpu-notifier-error-inject
++
++exit $retval
+--
+2.35.1
+
--- /dev/null
+From 8eab566380953d479e3be19881b465072a488991 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 13:26:45 -0700
+Subject: selftests/xsk: Avoid use-after-free on ctx
+
+From: Ian Rogers <irogers@google.com>
+
+[ Upstream commit af515a5587b8f45f19e11657746e0c89411b0380 ]
+
+The put lowers the reference count to 0 and frees ctx, reading it
+afterwards is invalid. Move the put after the uses and determine the
+last use by the reference count being 1.
+
+Fixes: 39e940d4abfa ("selftests/xsk: Destroy BPF resources only when ctx refcount drops to 0")
+Signed-off-by: Ian Rogers <irogers@google.com>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: Magnus Karlsson <magnus.karlsson@intel.com>
+Link: https://lore.kernel.org/bpf/20220901202645.1463552-1-irogers@google.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/lib/bpf/xsk.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/tools/lib/bpf/xsk.c b/tools/lib/bpf/xsk.c
+index 42b8437b0535..2be3197914e4 100644
+--- a/tools/lib/bpf/xsk.c
++++ b/tools/lib/bpf/xsk.c
+@@ -1245,15 +1245,15 @@ void xsk_socket__delete(struct xsk_socket *xsk)
+ ctx = xsk->ctx;
+ umem = ctx->umem;
+
+- xsk_put_ctx(ctx, true);
+-
+- if (!ctx->refcount) {
++ if (ctx->refcount == 1) {
+ xsk_delete_bpf_maps(xsk);
+ close(ctx->prog_fd);
+ if (ctx->has_bpf_link)
+ close(ctx->link_fd);
+ }
+
++ xsk_put_ctx(ctx, true);
++
+ err = xsk_get_mmap_offsets(xsk->fd, &off);
+ if (!err) {
+ if (xsk->rx) {
+--
+2.35.1
+
--- /dev/null
+From cd741992f7e252c15425d085293ed84f19ff223a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 12:43:24 +0200
+Subject: serial: 8250: Fix restoring termios speed after suspend
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Pali Rohár <pali@kernel.org>
+
+[ Upstream commit 379a33786d489ab81885ff0b3935cfeb36137fea ]
+
+Since commit edc6afc54968 ("tty: switch to ktermios and new framework")
+termios speed is no longer stored only in c_cflag member but also in new
+additional c_ispeed and c_ospeed members. If BOTHER flag is set in c_cflag
+then termios speed is stored only in these new members.
+
+Since commit 027b57170bf8 ("serial: core: Fix initializing and restoring
+termios speed") termios speed is available also in struct console.
+
+So properly restore also c_ispeed and c_ospeed members after suspend to fix
+restoring termios speed which is not represented by Bnnn constant.
+
+Fixes: 4516d50aabed ("serial: 8250: Use canary to restart console after suspend")
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Link: https://lore.kernel.org/r/20220924104324.4035-1-pali@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/8250/8250_port.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
+index ee457f5d504f..ec7846223f3a 100644
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -3318,8 +3318,13 @@ static void serial8250_console_restore(struct uart_8250_port *up)
+ unsigned int baud, quot, frac = 0;
+
+ termios.c_cflag = port->cons->cflag;
+- if (port->state->port.tty && termios.c_cflag == 0)
++ termios.c_ispeed = port->cons->ispeed;
++ termios.c_ospeed = port->cons->ospeed;
++ if (port->state->port.tty && termios.c_cflag == 0) {
+ termios.c_cflag = port->state->port.tty->termios.c_cflag;
++ termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
++ termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
++ }
+
+ baud = serial8250_get_baud_rate(port, &termios, NULL);
+ quot = serial8250_get_divisor(port, baud, &frac);
+--
+2.35.1
+
--- /dev/null
+From 18fbbee3bfe5cedde24f9b0234d76b7369eafa2c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 10:00:05 +0300
+Subject: serial: 8250: Toggle IER bits on only after irq has been set up
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+
+[ Upstream commit 039d4926379b1d1c17b51cf21c500a5eed86899e ]
+
+Invoking TIOCVHANGUP on 8250_mid port on Ice Lake-D and then reopening
+the port triggers these faults during serial8250_do_startup():
+
+ DMAR: DRHD: handling fault status reg 3
+ DMAR: [DMA Write NO_PASID] Request device [00:1a.0] fault addr 0x0 [fault reason 0x05] PTE Write access is not set
+
+If the IRQ hasn't been set up yet, the UART will have zeroes in its MSI
+address/data registers. Disabling the IRQ at the interrupt controller
+won't stop the UART from performing a DMA write to the address programmed
+in its MSI address register (zero) when it wants to signal an interrupt.
+
+The UARTs (in Ice Lake-D) implement PCI 2.1 style MSI without masking
+capability, so there is no way to mask the interrupt at the source PCI
+function level, except disabling the MSI capability entirely, but that
+would cause it to fall back to INTx# assertion, and the PCI specification
+prohibits disabling the MSI capability as a way to mask a function's
+interrupt service request.
+
+The MSI address register is zeroed by the hangup as the irq is freed.
+The interrupt is signalled during serial8250_do_startup() performing a
+THRE test that temporarily toggles THRI in IER. The THRE test currently
+occurs before UART's irq (and MSI address) is properly set up.
+
+Refactor serial8250_do_startup() such that irq is set up before the
+THRE test. The current irq setup code is intermixed with the timer
+setup code. As THRE test must be performed prior to the timer setup,
+extract it into own function and call it only after the THRE test.
+
+The ->setup_timer() needs to be part of the struct uart_8250_ops in
+order to not create circular dependency between 8250 and 8250_base
+modules.
+
+Fixes: 40b36daad0ac ("[PATCH] 8250 UART backup timer")
+Reported-by: Lennert Buytenhek <buytenh@arista.com>
+Tested-by: Lennert Buytenhek <buytenh@arista.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+Link: https://lore.kernel.org/r/20220922070005.2965-1-ilpo.jarvinen@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/8250/8250_core.c | 16 +++++++++++-----
+ drivers/tty/serial/8250/8250_port.c | 8 +++++---
+ include/linux/serial_8250.h | 1 +
+ 3 files changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
+index 30b7890645ac..c3348d5af922 100644
+--- a/drivers/tty/serial/8250/8250_core.c
++++ b/drivers/tty/serial/8250/8250_core.c
+@@ -300,10 +300,9 @@ static void serial8250_backup_timeout(struct timer_list *t)
+ jiffies + uart_poll_timeout(&up->port) + HZ / 5);
+ }
+
+-static int univ8250_setup_irq(struct uart_8250_port *up)
++static void univ8250_setup_timer(struct uart_8250_port *up)
+ {
+ struct uart_port *port = &up->port;
+- int retval = 0;
+
+ /*
+ * The above check will only give an accurate result the first time
+@@ -324,10 +323,16 @@ static int univ8250_setup_irq(struct uart_8250_port *up)
+ */
+ if (!port->irq)
+ mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
+- else
+- retval = serial_link_irq_chain(up);
++}
+
+- return retval;
++static int univ8250_setup_irq(struct uart_8250_port *up)
++{
++ struct uart_port *port = &up->port;
++
++ if (port->irq)
++ return serial_link_irq_chain(up);
++
++ return 0;
+ }
+
+ static void univ8250_release_irq(struct uart_8250_port *up)
+@@ -383,6 +388,7 @@ static struct uart_ops univ8250_port_ops;
+ static const struct uart_8250_ops univ8250_driver_ops = {
+ .setup_irq = univ8250_setup_irq,
+ .release_irq = univ8250_release_irq,
++ .setup_timer = univ8250_setup_timer,
+ };
+
+ static struct uart_8250_port serial8250_ports[UART_NR];
+diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
+index b07326b71834..ee457f5d504f 100644
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -2280,6 +2280,10 @@ int serial8250_do_startup(struct uart_port *port)
+ if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
+ up->port.irqflags |= IRQF_SHARED;
+
++ retval = up->ops->setup_irq(up);
++ if (retval)
++ goto out;
++
+ if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
+ unsigned char iir1;
+
+@@ -2322,9 +2326,7 @@ int serial8250_do_startup(struct uart_port *port)
+ }
+ }
+
+- retval = up->ops->setup_irq(up);
+- if (retval)
+- goto out;
++ up->ops->setup_timer(up);
+
+ /*
+ * Now, initialize the UART
+diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
+index 5db211f43b29..68abc6bdd891 100644
+--- a/include/linux/serial_8250.h
++++ b/include/linux/serial_8250.h
+@@ -74,6 +74,7 @@ struct uart_8250_port;
+ struct uart_8250_ops {
+ int (*setup_irq)(struct uart_8250_port *);
+ void (*release_irq)(struct uart_8250_port *);
++ void (*setup_timer)(struct uart_8250_port *);
+ };
+
+ struct uart_8250_em485 {
+--
+2.35.1
+
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+crypto-ccp-release-dma-channels-before-dmaengine-unr.patch
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+tools-power-turbostat-separate-spr-from-icx.patch
+tools-power-turbostat-use-standard-energy-unit-for-s.patch
+selftest-tpm2-add-client.__del__-to-close-dev-tpm-ha.patch
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+acpi-tables-fpdt-don-t-call-acpi_os_map_memory-on-in.patch
+cpufreq-intel_pstate-add-tigerlake-support-in-no-hwp.patch
+mips-bcm47xx-cast-memcmp-of-function-to-void.patch
+powercap-intel_rapl-fix-ubsan-shift-out-of-bounds-is.patch
+thermal-intel_powerclamp-use-get_cpu-instead-of-smp_.patch
+arm-decompressor-include-.data.rel.ro.local.patch
+acpi-x86-add-a-quirk-for-dell-inspiron-14-2-in-1-for.patch
+x86-entry-work-around-clang-__bdos-bug.patch
+nfsd-return-nfserr_serverfault-if-splice_ok-but-buf-.patch
+nfsd-fix-use-after-free-on-source-server-when-doing-.patch
+wifi-rtw88-phy-fix-warning-of-possible-buffer-overfl.patch
+wifi-brcmfmac-fix-invalid-address-access-when-enabli.patch
+bpftool-clear-errno-after-libcap-s-checks.patch
+ice-set-tx_tstamps-when-creating-new-tx-rings-via-et.patch
+net-ethernet-ti-davinci_mdio-add-workaround-for-erra.patch
+openvswitch-fix-double-reporting-of-drops-in-dropwat.patch
+openvswitch-fix-overreporting-of-drops-in-dropwatch.patch
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+x86-mce-retrieve-poison-range-from-hardware.patch
+wifi-ath9k-avoid-uninit-memory-read-in-ath9k_htc_rx_.patch
+thunderbolt-add-back-intel-falcon-ridge-end-to-end-f.patch
+xfrm-update-ipcomp_scratches-with-null-when-freed.patch
+net-broadcom-fix-return-type-for-implementation-of.patch
+net-xscale-fix-return-type-for-implementation-of-ndo.patch
+net-lantiq_etop-fix-return-type-for-implementation-o.patch
+net-ftmac100-fix-endianness-related-issues-from-spar.patch
+iavf-fix-race-between-iavf_close-and-iavf_reset_task.patch
+wifi-brcmfmac-fix-use-after-free-bug-in-brcmf_netdev.patch
+bluetooth-btintel-mark-intel-controller-to-support-l.patch
+regulator-core-prevent-integer-underflow.patch
+wifi-mt76-mt7921-reset-msta-airtime_ac-while-clearin.patch
+bluetooth-l2cap-initialize-delayed-works-at-l2cap_ch.patch
+net-davicom-fix-return-type-of-dm9000_start_xmit.patch
+net-ethernet-ti-davinci_emac-fix-return-type-of-emac.patch
+net-ethernet-litex-fix-return-type-of-liteeth_start_.patch
+net-korina-fix-return-type-of-korina_send_packet.patch
+net-wwan-iosm-fix-return-type-of-ipc_wwan_link_trans.patch
+bluetooth-hci_sysfs-fix-attempting-to-call-device_ad.patch
+wifi-ath10k-reset-pointer-after-memory-free-to-avoid.patch
+can-bcm-check-the-result-of-can_send-in-bcm_can_tx.patch
+wifi-rt2x00-don-t-run-rt5592-iq-calibration-on-mt762.patch
+wifi-rt2x00-set-correct-tx_sw_cfg1-mac-register-for-.patch
+wifi-rt2x00-set-vgc-gain-for-both-chains-of-mt7620.patch
+wifi-rt2x00-set-soc-wmac-clock-register.patch
+wifi-rt2x00-correctly-set-bbp-register-86-for-mt7620.patch
+hwmon-sht4x-do-not-overflow-clamping-operation-on-32.patch
+net-if-sock-is-dead-don-t-access-sock-s-sk_wq-in-sk_.patch
+bluetooth-l2cap-fix-user-after-free.patch
+libbpf-fix-overrun-in-netlink-attribute-iteration.patch
+r8152-rate-limit-overflow-messages.patch
+drm-nouveau-nouveau_bo-fix-potential-memory-leak-in-.patch
+drm-use-size_t-type-for-len-variable-in-drm_copy_fie.patch
+drm-prevent-drm_copy_field-to-attempt-copying-a-null.patch
+drm-komeda-fix-handling-of-atomic-commits-in-the-ato.patch
+gpu-lontium-lt9611-fix-null-pointer-dereference-in-l.patch
+drm-amd-display-fix-overflow-on-min_i64-definition.patch
+alsa-usb-audio-add-quirk-to-enable-avid-mbox-3-suppo.patch
+udmabuf-set-ubuf-sg-null-if-the-creation-of-sg-table.patch
+drm-bridge-dw_hdmi-only-trigger-hotplug-event-on-lin.patch
+alsa-usb-audio-register-card-at-the-last-interface.patch
+drm-vc4-vec-fix-timings-for-vec-modes.patch
+drm-panel-orientation-quirks-add-quirk-for-anbernic-.patch
+platform-chrome-cros_ec-notify-the-pm-of-wake-events.patch
+platform-x86-msi-laptop-change-dmi-match-alias-strin.patch
+asoc-sof-pci-change-dmi-match-info-to-support-all-ch.patch
+drm-amdgpu-fix-initial-connector-audio-value.patch
+drm-meson-reorder-driver-deinit-sequence-to-fix-use-.patch
+drm-meson-explicitly-remove-aggregate-driver-at-modu.patch
+drm-exynos-fix-return-type-for-mixer_mode_valid-and-.patch
+mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch
+drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch
+drm-amd-display-remove-interface-for-periodic-interr.patch
+drm-amd-display-fix-array-bounds-error-in-dc_stream_.patch
+arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
+arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch
+arm64-dts-qcom-sc7280-idp-correct-adc-channel-node-n.patch
+arm-dts-imx6q-add-missing-properties-for-sram.patch
+arm-dts-imx6dl-add-missing-properties-for-sram.patch
+arm-dts-imx6qp-add-missing-properties-for-sram.patch
+arm-dts-imx6sl-add-missing-properties-for-sram.patch
+arm-dts-imx6sll-add-missing-properties-for-sram.patch
+arm-dts-imx6sx-add-missing-properties-for-sram.patch
+kselftest-arm64-fix-validatation-termination-record-.patch
+sparc-fix-the-generic-io-helpers.patch
+arm64-run-softirqs-on-the-per-cpu-irq-stack.patch
+arm64-dts-imx8mq-librem5-add-bq25895-as-max17055-s-p.patch
+arm-orion-fix-include-path.patch
+btrfs-dump-extra-info-if-one-free-space-cache-has-mo.patch
+btrfs-add-macros-for-annotating-wait-events-with-loc.patch
+btrfs-change-the-lockdep-class-of-free-space-inode-s.patch
+btrfs-scrub-try-to-fix-super-block-errors.patch
+btrfs-don-t-print-information-about-space-cache-or-t.patch
+btrfs-check-superblock-to-ensure-the-fs-was-not-modi.patch
+btrfs-add-kcsan-annotations-for-unlocked-access-to-b.patch
+btrfs-separate-out-the-eb-and-extent-state-leak-help.patch
+arm64-dts-uniphier-add-usb-device-support-for-pxs3-r.patch
+arm-9242-1-kasan-only-map-modules-if-config_kasan_vm.patch
+selftests-cpu-hotplug-use-return-instead-of-exit.patch
+clk-zynqmp-fix-stack-out-of-bounds-in-strncpy.patch
+media-cx88-fix-a-null-ptr-deref-bug-in-buffer_prepar.patch
+media-platform-fix-some-double-free-in-meson-ge2d-an.patch
+clk-zynqmp-pll-rectify-rate-rounding-in-zynqmp_pll_r.patch
+usb-host-xhci-plat-suspend-and-resume-clocks.patch
+usb-host-xhci-plat-suspend-resume-clks-for-brcm.patch
+dmaengine-ti-k3-udma-reset-udma_chan_rt-byte-counter.patch
+scsi-3w-9xxx-avoid-disabling-device-if-failing-to-en.patch
+nbd-fix-hung-when-signal-interrupts-nbd_start_device.patch
+iommu-arm-smmu-v3-make-default-domain-type-of-hisili.patch
+power-supply-adp5061-fix-out-of-bounds-read-in-adp50.patch
+staging-vt6655-fix-potential-memory-leak.patch
+blk-throttle-prevent-overflow-while-calculating-wait.patch
+ata-libahci_platform-sanity-check-the-dt-child-nodes.patch
+bcache-fix-set_at_max_writeback_rate-for-multiple-at.patch
+soundwire-cadence-don-t-overwrite-msg-buf-during-wri.patch
+soundwire-intel-fix-error-handling-on-dai-registrati.patch
+hid-topre-add-driver-fixing-report-descriptor.patch
+habanalabs-remove-some-f-w-descriptor-validations.patch
+hid-roccat-fix-use-after-free-in-roccat_read.patch
+hsi-ssi_protocol-fix-potential-resource-leak-in-ssip.patch
+eventfd-guard-wake_up-in-eventfd-fs-calls-as-well.patch
+md-raid5-wait-for-md_sb_change_pending-in-raid5d.patch
+usb-host-xhci-fix-potential-memory-leak-in-xhci_allo.patch
+usb-musb-fix-musb_gadget.c-rxstate-overflow-bug.patch
+arm64-dts-imx8mp-add-snps-gfladj-refclk-lpm-sel-quir.patch
+usb-dwc3-core-enable-guctl1-bit-10-for-fixing-termin.patch
+revert-usb-storage-add-quirk-for-samsung-fit-flash.patch
+staging-rtl8723bs-fix-potential-memory-leak-in-rtw_i.patch
+staging-rtl8723bs-fix-a-potential-memory-leak-in-rtw.patch
+scsi-tracing-fix-compile-error-in-trace_array-calls-.patch
+ext2-use-kvmalloc-for-group-descriptor-array.patch
+nvme-copy-firmware_rev-on-each-init.patch
+nvmet-tcp-add-bounds-check-on-transfer-tag.patch
+usb-idmouse-fix-an-uninit-value-in-idmouse_open.patch
+fsi-master-ast-cf-fix-missing-of_node_put-in-fsi_mas.patch
+clk-bcm2835-make-peripheral-pllc-critical.patch
+clk-bcm2835-round-uart-input-clock-up.patch
--- /dev/null
+From 5757e7e02e249d8045c2892345540430b6ff66a9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 16:40:44 -0700
+Subject: sh: machvec: Use char[] for section boundaries
+
+From: Kees Cook <keescook@chromium.org>
+
+[ Upstream commit c5783af354688b24abd359f7086c282ec74de993 ]
+
+As done for other sections, define the extern as a character array,
+which relaxes many of the compiler-time object size checks, which would
+otherwise assume it's a single long. Solves the following build error:
+
+arch/sh/kernel/machvec.c: error: array subscript 'struct sh_machine_vector[0]' is partly outside array bounds of 'long int[1]' [-Werror=array-bounds]: => 105:33
+
+Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
+Cc: Rich Felker <dalias@libc.org>
+Cc: linux-sh@vger.kernel.org
+Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Link: https://lore.kernel.org/lkml/alpine.DEB.2.22.394.2209050944290.964530@ramsan.of.borg/
+Fixes: 9655ad03af2d ("sh: Fixup machvec support.")
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
+Acked-by: Rich Felker <dalias@libc.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/sh/include/asm/sections.h | 2 +-
+ arch/sh/kernel/machvec.c | 10 +++++-----
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
+index 8edb824049b9..0cb0ca149ac3 100644
+--- a/arch/sh/include/asm/sections.h
++++ b/arch/sh/include/asm/sections.h
+@@ -4,7 +4,7 @@
+
+ #include <asm-generic/sections.h>
+
+-extern long __machvec_start, __machvec_end;
++extern char __machvec_start[], __machvec_end[];
+ extern char __uncached_start, __uncached_end;
+ extern char __start_eh_frame[], __stop_eh_frame[];
+
+diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
+index d606679a211e..57efaf5b82ae 100644
+--- a/arch/sh/kernel/machvec.c
++++ b/arch/sh/kernel/machvec.c
+@@ -20,8 +20,8 @@
+ #define MV_NAME_SIZE 32
+
+ #define for_each_mv(mv) \
+- for ((mv) = (struct sh_machine_vector *)&__machvec_start; \
+- (mv) && (unsigned long)(mv) < (unsigned long)&__machvec_end; \
++ for ((mv) = (struct sh_machine_vector *)__machvec_start; \
++ (mv) && (unsigned long)(mv) < (unsigned long)__machvec_end; \
+ (mv)++)
+
+ static struct sh_machine_vector * __init get_mv_byname(const char *name)
+@@ -87,8 +87,8 @@ void __init sh_mv_setup(void)
+ if (!machvec_selected) {
+ unsigned long machvec_size;
+
+- machvec_size = ((unsigned long)&__machvec_end -
+- (unsigned long)&__machvec_start);
++ machvec_size = ((unsigned long)__machvec_end -
++ (unsigned long)__machvec_start);
+
+ /*
+ * Sanity check for machvec section alignment. Ensure
+@@ -102,7 +102,7 @@ void __init sh_mv_setup(void)
+ * vector (usually the only one) from .machvec.init.
+ */
+ if (machvec_size >= sizeof(struct sh_machine_vector))
+- sh_mv = *(struct sh_machine_vector *)&__machvec_start;
++ sh_mv = *(struct sh_machine_vector *)__machvec_start;
+ }
+
+ pr_notice("Booting machvec: %s\n", get_system_type());
+--
+2.35.1
+
--- /dev/null
+From e8f19298f3c4ce670bff64f3811caeaf5f11b6b1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 15:13:11 +0800
+Subject: skmsg: Schedule psock work if the cached skb exists on the psock
+
+From: Liu Jian <liujian56@huawei.com>
+
+[ Upstream commit bec217197b412d74168c6a42fc0f76d0cc9cad00 ]
+
+In sk_psock_backlog function, for ingress direction skb, if no new data
+packet arrives after the skb is cached, the cached skb does not have a
+chance to be added to the receive queue of psock. As a result, the cached
+skb cannot be received by the upper-layer application. Fix this by reschedule
+the psock work to dispose the cached skb in sk_msg_recvmsg function.
+
+Fixes: 604326b41a6f ("bpf, sockmap: convert to generic sk_msg interface")
+Signed-off-by: Liu Jian <liujian56@huawei.com>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Link: https://lore.kernel.org/bpf/20220907071311.60534-1-liujian56@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/core/skmsg.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/net/core/skmsg.c b/net/core/skmsg.c
+index 054073c7cbb9..736d8b035a67 100644
+--- a/net/core/skmsg.c
++++ b/net/core/skmsg.c
+@@ -435,8 +435,10 @@ int sk_msg_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg,
+ if (copied + copy > len)
+ copy = len - copied;
+ copy = copy_page_to_iter(page, sge->offset, copy, iter);
+- if (!copy)
+- return copied ? copied : -EFAULT;
++ if (!copy) {
++ copied = copied ? copied : -EFAULT;
++ goto out;
++ }
+
+ copied += copy;
+ if (likely(!peek)) {
+@@ -456,7 +458,7 @@ int sk_msg_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg,
+ * didn't copy the entire length lets just break.
+ */
+ if (copy != sge->length)
+- return copied;
++ goto out;
+ sk_msg_iter_var_next(i);
+ }
+
+@@ -478,7 +480,9 @@ int sk_msg_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg,
+ }
+ msg_rx = sk_psock_peek_msg(psock);
+ }
+-
++out:
++ if (psock->work_state.skb && copied > 0)
++ schedule_work(&psock->work);
+ return copied;
+ }
+ EXPORT_SYMBOL_GPL(sk_msg_recvmsg);
+--
+2.35.1
+
--- /dev/null
+From 3ea0049441a2abf3a6bdaaff158450bbc6f2a164 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 13:29:10 +0100
+Subject: slimbus: qcom-ngd-ctrl: allow compile testing without
+ QCOM_RPROC_COMMON
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit e291691c69776ad278cd39dec2306dd39d681a9f ]
+
+The Qualcomm common remote-proc code (CONFIG_QCOM_RPROC_COMMON) has
+necessary stubs, so it is not needed for compile testing.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20220916122910.170730-5-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: 42992cf187e4 ("slimbus: qcom-ngd: Add error handling in of_qcom_slim_ngd_register")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/slimbus/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
+index 1235b7dc8496..2ed821f75816 100644
+--- a/drivers/slimbus/Kconfig
++++ b/drivers/slimbus/Kconfig
+@@ -22,7 +22,8 @@ config SLIM_QCOM_CTRL
+
+ config SLIM_QCOM_NGD_CTRL
+ tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component"
+- depends on HAS_IOMEM && DMA_ENGINE && NET && QCOM_RPROC_COMMON
++ depends on HAS_IOMEM && DMA_ENGINE && NET
++ depends on QCOM_RPROC_COMMON || COMPILE_TEST
+ depends on ARCH_QCOM || COMPILE_TEST
+ select QCOM_QMI_HELPERS
+ select QCOM_PDR_HELPERS
+--
+2.35.1
+
--- /dev/null
+From 6c819a35a8605c5123fd44805e6a99c6c70cf54e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Jul 2022 21:52:17 +0800
+Subject: soc: qcom: smem_state: Add refcounting for the 'state->of_node'
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 90681f53b9381c23ff7762a3b13826d620c272de ]
+
+In qcom_smem_state_register() and qcom_smem_state_release(), we
+should better use of_node_get() and of_node_put() for the reference
+creation and destruction of 'device_node'.
+
+Fixes: 9460ae2ff308 ("soc: qcom: Introduce common SMEM state machine code")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220721135217.1301039-2-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soc/qcom/smem_state.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/soc/qcom/smem_state.c b/drivers/soc/qcom/smem_state.c
+index 31faf4aa868e..e848cc9a3cf8 100644
+--- a/drivers/soc/qcom/smem_state.c
++++ b/drivers/soc/qcom/smem_state.c
+@@ -136,6 +136,7 @@ static void qcom_smem_state_release(struct kref *ref)
+ struct qcom_smem_state *state = container_of(ref, struct qcom_smem_state, refcount);
+
+ list_del(&state->list);
++ of_node_put(state->of_node);
+ kfree(state);
+ }
+
+@@ -205,7 +206,7 @@ struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node,
+
+ kref_init(&state->refcount);
+
+- state->of_node = of_node;
++ state->of_node = of_node_get(of_node);
+ state->ops = *ops;
+ state->priv = priv;
+
+--
+2.35.1
+
--- /dev/null
+From 335deff0ac34ca3396d07acf5acd40482b6c282c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Jul 2022 21:52:16 +0800
+Subject: soc: qcom: smsm: Fix refcount leak bugs in qcom_smsm_probe()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit af8f6f39b8afd772fda4f8e61823ef8c021bf382 ]
+
+There are two refcount leak bugs in qcom_smsm_probe():
+
+(1) The 'local_node' is escaped out from for_each_child_of_node() as
+the break of iteration, we should call of_node_put() for it in error
+path or when it is not used anymore.
+(2) The 'node' is escaped out from for_each_available_child_of_node()
+as the 'goto', we should call of_node_put() for it in goto target.
+
+Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220721135217.1301039-1-windhl@126.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soc/qcom/smsm.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c
+index 9df9bba242f3..3e8994d6110e 100644
+--- a/drivers/soc/qcom/smsm.c
++++ b/drivers/soc/qcom/smsm.c
+@@ -526,7 +526,7 @@ static int qcom_smsm_probe(struct platform_device *pdev)
+ for (id = 0; id < smsm->num_hosts; id++) {
+ ret = smsm_parse_ipc(smsm, id);
+ if (ret < 0)
+- return ret;
++ goto out_put;
+ }
+
+ /* Acquire the main SMSM state vector */
+@@ -534,13 +534,14 @@ static int qcom_smsm_probe(struct platform_device *pdev)
+ smsm->num_entries * sizeof(u32));
+ if (ret < 0 && ret != -EEXIST) {
+ dev_err(&pdev->dev, "unable to allocate shared state entry\n");
+- return ret;
++ goto out_put;
+ }
+
+ states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL);
+ if (IS_ERR(states)) {
+ dev_err(&pdev->dev, "Unable to acquire shared state entry\n");
+- return PTR_ERR(states);
++ ret = PTR_ERR(states);
++ goto out_put;
+ }
+
+ /* Acquire the list of interrupt mask vectors */
+@@ -548,13 +549,14 @@ static int qcom_smsm_probe(struct platform_device *pdev)
+ ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, size);
+ if (ret < 0 && ret != -EEXIST) {
+ dev_err(&pdev->dev, "unable to allocate smsm interrupt mask\n");
+- return ret;
++ goto out_put;
+ }
+
+ intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL);
+ if (IS_ERR(intr_mask)) {
+ dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n");
+- return PTR_ERR(intr_mask);
++ ret = PTR_ERR(intr_mask);
++ goto out_put;
+ }
+
+ /* Setup the reference to the local state bits */
+@@ -565,7 +567,8 @@ static int qcom_smsm_probe(struct platform_device *pdev)
+ smsm->state = qcom_smem_state_register(local_node, &smsm_state_ops, smsm);
+ if (IS_ERR(smsm->state)) {
+ dev_err(smsm->dev, "failed to register qcom_smem_state\n");
+- return PTR_ERR(smsm->state);
++ ret = PTR_ERR(smsm->state);
++ goto out_put;
+ }
+
+ /* Register handlers for remote processor entries of interest. */
+@@ -595,16 +598,19 @@ static int qcom_smsm_probe(struct platform_device *pdev)
+ }
+
+ platform_set_drvdata(pdev, smsm);
++ of_node_put(local_node);
+
+ return 0;
+
+ unwind_interfaces:
++ of_node_put(node);
+ for (id = 0; id < smsm->num_entries; id++)
+ if (smsm->entries[id].domain)
+ irq_domain_remove(smsm->entries[id].domain);
+
+ qcom_smem_state_unregister(smsm->state);
+-
++out_put:
++ of_node_put(local_node);
+ return ret;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From fa91eb5ebf198d2af4fba1827fc9b625df94a8e4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 23 Sep 2020 03:34:21 +0300
+Subject: soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA
+
+From: Dmitry Osipenko <digetx@gmail.com>
+
+[ Upstream commit 2254182807fc09ba9dec9a42ef239e373796f1b2 ]
+
+The DMA subsystem could be entirely disabled in Kconfig and then the
+TEGRA20_APB_DMA option isn't available too. Hence kernel configuration
+fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable
+dependency.
+
+The FUSE driver isn't a critical driver and currently it only provides
+NVMEM interface to userspace which isn't known to be widely used, and
+thus, it's fine if FUSE driver fails to load.
+
+Let's remove the erroneous Kconfig dependency and let the FUSE driver to
+fail the probing if DMA is unavailable.
+
+Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20")
+Reported-by: Necip Fazil Yildiran <fazilyildiran@gmail.com>
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soc/tegra/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
+index 8b53ed1cc67e..1224e1c8c2c9 100644
+--- a/drivers/soc/tegra/Kconfig
++++ b/drivers/soc/tegra/Kconfig
+@@ -136,7 +136,6 @@ config SOC_TEGRA_FUSE
+ def_bool y
+ depends on ARCH_TEGRA
+ select SOC_BUS
+- select TEGRA20_APB_DMA if ARCH_TEGRA_2x_SOC
+
+ config SOC_TEGRA_FLOWCTRL
+ bool
+--
+2.35.1
+
--- /dev/null
+From a0434b8e91a3955fb38b6fcc2c6f92e37bd1a104 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 11:35:05 +0100
+Subject: soundwire: cadence: Don't overwrite msg->buf during write commands
+
+From: Richard Fitzgerald <rf@opensource.cirrus.com>
+
+[ Upstream commit ba05b39d265bdd16913f7684600d9d41e2796745 ]
+
+The buf passed in struct sdw_msg must only be written for a READ,
+in that case the RDATA part of the response is the data value of the
+register.
+
+For a write command there is no RDATA, and buf should be assumed to
+be const and unmodifable. The original caller should not expect its data
+buffer to be corrupted by an sdw_nwrite().
+
+Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
+Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Link: https://lore.kernel.org/r/20220916103505.1562210-1-rf@opensource.cirrus.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soundwire/cadence_master.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c
+index 4fcc3ba93004..18d2f9b3e201 100644
+--- a/drivers/soundwire/cadence_master.c
++++ b/drivers/soundwire/cadence_master.c
+@@ -545,9 +545,12 @@ cdns_fill_msg_resp(struct sdw_cdns *cdns,
+ return SDW_CMD_IGNORED;
+ }
+
+- /* fill response */
+- for (i = 0; i < count; i++)
+- msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA, cdns->response_buf[i]);
++ if (msg->flags == SDW_MSG_FLAG_READ) {
++ /* fill response */
++ for (i = 0; i < count; i++)
++ msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA,
++ cdns->response_buf[i]);
++ }
+
+ return SDW_CMD_OK;
+ }
+--
+2.35.1
+
--- /dev/null
+From f02e3cd032761e6bbdffd455cb9ff7db03fa562d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 01:57:11 +0800
+Subject: soundwire: intel: fix error handling on dai registration issues
+
+From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+
+[ Upstream commit c6867cda906aadbce5e71efde9c78a26108b2bad ]
+
+The call to intel_register_dai() may fail because of memory allocation
+issues or problems reported by the ASoC core. In all cases, when a
+error is thrown the component is not registered, it's invalid to
+unregister it.
+
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Reviewed-by: Rander Wang <rander.wang@intel.com>
+Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
+Link: https://lore.kernel.org/r/20220919175721.354679-2-yung-chuan.liao@linux.intel.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soundwire/intel.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
+index 38e7f1a2bb97..89ee033f0c35 100644
+--- a/drivers/soundwire/intel.c
++++ b/drivers/soundwire/intel.c
+@@ -1407,7 +1407,6 @@ int intel_link_startup(struct auxiliary_device *auxdev)
+ ret = intel_register_dai(sdw);
+ if (ret) {
+ dev_err(dev, "DAI registration failed: %d\n", ret);
+- snd_soc_unregister_component(dev);
+ goto err_interrupt;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 0a3c7246dc046fe1f0c115275cc1a00836dae9e0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 21:55:53 +0200
+Subject: sparc: Fix the generic IO helpers
+
+From: Linus Walleij <linus.walleij@linaro.org>
+
+[ Upstream commit 2c230431e1e809270178905974f57cf3878939f5 ]
+
+This enables the Sparc to use <asm-generic/io.h> to fill in the
+missing (undefined) [read|write]sq I/O accessor functions.
+
+This is needed if Sparc[64] ever wants to uses CONFIG_REGMAP_MMIO
+which has been patches to use accelerated _noinc accessors
+such as readsq/writesq that Sparc64, while being a 64bit platform,
+as of now not yet provide.
+
+This comes with the requirement that everything the architecture
+already provides needs to be defined, rather than just being,
+say, static inline functions.
+
+Bite the bullet and just provide the definitions and make it work.
+Compile-tested on sparc32 and sparc64.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Cc: David S. Miller <davem@davemloft.net>
+Cc: sparclinux@vger.kernel.org
+Cc: linux-arch@vger.kernel.org
+Cc: Mark Brown <broonie@kernel.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Link: https://lore.kernel.org/linux-arm-kernel/202208201639.HXye3ke4-lkp@intel.com/
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/sparc/include/asm/io.h | 2 ++
+ arch/sparc/include/asm/io_64.h | 22 ++++++++++++++++++++++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h
+index 2eefa526b38f..2dad9be9ec75 100644
+--- a/arch/sparc/include/asm/io.h
++++ b/arch/sparc/include/asm/io.h
+@@ -19,4 +19,6 @@
+ #define writel_be(__w, __addr) __raw_writel(__w, __addr)
+ #define writew_be(__l, __addr) __raw_writew(__l, __addr)
+
++#include <asm-generic/io.h>
++
+ #endif
+diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
+index 5ffa820dcd4d..9303270b22f3 100644
+--- a/arch/sparc/include/asm/io_64.h
++++ b/arch/sparc/include/asm/io_64.h
+@@ -9,6 +9,7 @@
+ #include <asm/page.h> /* IO address mapping routines need this */
+ #include <asm/asi.h>
+ #include <asm-generic/pci_iomap.h>
++#define pci_iomap pci_iomap
+
+ /* BIO layer definitions. */
+ extern unsigned long kern_base, kern_size;
+@@ -239,38 +240,51 @@ static inline void outl(u32 l, unsigned long addr)
+ void outsb(unsigned long, const void *, unsigned long);
+ void outsw(unsigned long, const void *, unsigned long);
+ void outsl(unsigned long, const void *, unsigned long);
++#define outsb outsb
++#define outsw outsw
++#define outsl outsl
+ void insb(unsigned long, void *, unsigned long);
+ void insw(unsigned long, void *, unsigned long);
+ void insl(unsigned long, void *, unsigned long);
++#define insb insb
++#define insw insw
++#define insl insl
+
+ static inline void readsb(void __iomem *port, void *buf, unsigned long count)
+ {
+ insb((unsigned long __force)port, buf, count);
+ }
++#define readsb readsb
++
+ static inline void readsw(void __iomem *port, void *buf, unsigned long count)
+ {
+ insw((unsigned long __force)port, buf, count);
+ }
++#define readsw readsw
+
+ static inline void readsl(void __iomem *port, void *buf, unsigned long count)
+ {
+ insl((unsigned long __force)port, buf, count);
+ }
++#define readsl readsl
+
+ static inline void writesb(void __iomem *port, const void *buf, unsigned long count)
+ {
+ outsb((unsigned long __force)port, buf, count);
+ }
++#define writesb writesb
+
+ static inline void writesw(void __iomem *port, const void *buf, unsigned long count)
+ {
+ outsw((unsigned long __force)port, buf, count);
+ }
++#define writesw writesw
+
+ static inline void writesl(void __iomem *port, const void *buf, unsigned long count)
+ {
+ outsl((unsigned long __force)port, buf, count);
+ }
++#define writesl writesl
+
+ #define ioread8_rep(p,d,l) readsb(p,d,l)
+ #define ioread16_rep(p,d,l) readsw(p,d,l)
+@@ -344,6 +358,7 @@ static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t
+ d++;
+ }
+ }
++#define memset_io memset_io
+
+ static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
+ __kernel_size_t n)
+@@ -369,6 +384,7 @@ static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
+ src++;
+ }
+ }
++#define memcpy_fromio memcpy_fromio
+
+ static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
+ __kernel_size_t n)
+@@ -395,6 +411,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
+ d++;
+ }
+ }
++#define memcpy_toio memcpy_toio
+
+ #ifdef __KERNEL__
+
+@@ -412,7 +429,9 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
+ static inline void __iomem *ioremap_np(unsigned long offset, unsigned long size)
+ {
+ return NULL;
++
+ }
++#define ioremap_np ioremap_np
+
+ static inline void iounmap(volatile void __iomem *addr)
+ {
+@@ -432,10 +451,13 @@ static inline void iounmap(volatile void __iomem *addr)
+ /* Create a virtual mapping cookie for an IO port range */
+ void __iomem *ioport_map(unsigned long port, unsigned int nr);
+ void ioport_unmap(void __iomem *);
++#define ioport_map ioport_map
++#define ioport_unmap ioport_unmap
+
+ /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+ struct pci_dev;
+ void pci_iounmap(struct pci_dev *dev, void __iomem *);
++#define pci_iounmap pci_iounmap
+
+ static inline int sbus_can_dma_64bit(void)
+ {
+--
+2.35.1
+
--- /dev/null
+From 5ed574b23e9d9d4f21121adc8c169f2f59478232 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 20:13:08 +0800
+Subject: spi: dw: Fix PM disable depth imbalance in dw_spi_bt1_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit 618d815fc93477b1675878f3c04ff32657cc18b4 ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context.
+
+Fixes:abf00907538e2 ("spi: dw: Add Baikal-T1 SPI Controller glue driver")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220924121310.78331-3-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-dw-bt1.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-dw-bt1.c b/drivers/spi/spi-dw-bt1.c
+index 5be6b7b80c21..7e3ff54f6616 100644
+--- a/drivers/spi/spi-dw-bt1.c
++++ b/drivers/spi/spi-dw-bt1.c
+@@ -293,8 +293,10 @@ static int dw_spi_bt1_probe(struct platform_device *pdev)
+ pm_runtime_enable(&pdev->dev);
+
+ ret = dw_spi_add_host(&pdev->dev, dws);
+- if (ret)
++ if (ret) {
++ pm_runtime_disable(&pdev->dev);
+ goto err_disable_clk;
++ }
+
+ platform_set_drvdata(pdev, dwsbt1);
+
+--
+2.35.1
+
--- /dev/null
+From fc4a4d15f0bafeda1b706497f948dfa92db27cca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Sep 2022 13:34:08 +0200
+Subject: spi: Ensure that sg_table won't be used after being freed
+
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+
+[ Upstream commit 8e9204cddcc3fea9affcfa411715ba4f66e97587 ]
+
+SPI code checks for non-zero sgt->orig_nents to determine if the buffer
+has been DMA-mapped. Ensure that sg_table is really zeroed after free to
+avoid potential NULL pointer dereference if the given SPI xfer object is
+reused again without being DMA-mapped.
+
+Fixes: 0c17ba73c08f ("spi: Fix cache corruption due to DMA/PIO overlap")
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Link: https://lore.kernel.org/r/20220930113408.19720-1-m.szyprowski@samsung.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
+index 556d65af5e23..06dd1be54925 100644
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -1007,6 +1007,8 @@ void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
+ if (sgt->orig_nents) {
+ dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
+ sg_free_table(sgt);
++ sgt->orig_nents = 0;
++ sgt->nents = 0;
+ }
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 4ab36a33f0f1eadd6c5287952ebf9d1aaa5e414d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Sep 2022 14:18:03 +0200
+Subject: spi: meson-spicc: do not rely on busy flag in pow2 clk ops
+
+From: Neil Armstrong <narmstrong@baylibre.com>
+
+[ Upstream commit 36acf80fc0c4b5ebe6fa010b524d442ee7f08fd3 ]
+
+Since [1], controller's busy flag isn't set anymore when the
+__spi_transfer_message_noqueue() is used instead of the
+__spi_pump_transfer_message() logic for spi_sync transfers.
+
+Since the pow2 clock ops were limited to only be available when a
+transfer is ongoing (between prepare_transfer_hardware and
+unprepare_transfer_hardware callbacks), the only way to track this
+down is to check for the controller cur_msg.
+
+[1] ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync")
+
+Fixes: 09992025dacd ("spi: meson-spicc: add local pow2 clock ops to preserve rate between messages")
+Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync")
+Reported-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Tested-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Link: https://lore.kernel.org/r/20220908121803.919943-1-narmstrong@baylibre.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-meson-spicc.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
+index e4cb52e1fe26..6974a1c947aa 100644
+--- a/drivers/spi/spi-meson-spicc.c
++++ b/drivers/spi/spi-meson-spicc.c
+@@ -537,7 +537,7 @@ static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
+ struct clk_divider *divider = to_clk_divider(hw);
+ struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
+
+- if (!spicc->master->cur_msg || !spicc->master->busy)
++ if (!spicc->master->cur_msg)
+ return 0;
+
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+@@ -549,7 +549,7 @@ static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
+ struct clk_divider *divider = to_clk_divider(hw);
+ struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
+
+- if (!spicc->master->cur_msg || !spicc->master->busy)
++ if (!spicc->master->cur_msg)
+ return -EINVAL;
+
+ return clk_divider_ops.determine_rate(hw, req);
+@@ -561,7 +561,7 @@ static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
+ struct clk_divider *divider = to_clk_divider(hw);
+ struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
+
+- if (!spicc->master->cur_msg || !spicc->master->busy)
++ if (!spicc->master->cur_msg)
+ return -EINVAL;
+
+ return clk_divider_ops.set_rate(hw, rate, parent_rate);
+--
+2.35.1
+
--- /dev/null
+From 1bb13b98f1cf4bcde00339925af355f3f487c185 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 27 Aug 2022 13:42:07 +0200
+Subject: spi: mt7621: Fix an error message in mt7621_spi_probe()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 2b2bf6b7faa9010fae10dc7de76627a3fdb525b3 ]
+
+'status' is known to be 0 at this point. The expected error code is
+PTR_ERR(clk).
+
+Switch to dev_err_probe() in order to display the expected error code (in a
+human readable way).
+This also filters -EPROBE_DEFER cases, should it happen.
+
+Fixes: 1ab7f2a43558 ("staging: mt7621-spi: add mt7621 support")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Link: https://lore.kernel.org/r/928f3fb507d53ba0774df27cea0bbba4b055993b.1661599671.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-mt7621.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
+index b4b9b7309b5e..351b0ef52bbc 100644
+--- a/drivers/spi/spi-mt7621.c
++++ b/drivers/spi/spi-mt7621.c
+@@ -340,11 +340,9 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ return PTR_ERR(base);
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(clk)) {
+- dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
+- status);
+- return PTR_ERR(clk);
+- }
++ if (IS_ERR(clk))
++ return dev_err_probe(&pdev->dev, PTR_ERR(clk),
++ "unable to get SYS clock\n");
+
+ status = clk_prepare_enable(clk);
+ if (status)
+--
+2.35.1
+
--- /dev/null
+From 84a811ab10f0493b64d1bf22a71f9b1085d810bd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 20:13:09 +0800
+Subject: spi/omap100k:Fix PM disable depth imbalance in omap1_spi100k_probe
+
+From: Zhang Qilong <zhangqilong3@huawei.com>
+
+[ Upstream commit 29f65f2171c85a9633daa380df14009a365f42f2 ]
+
+The pm_runtime_enable will increase power disable depth. Thus
+a pairing decrement is needed on the error handling path to
+keep it balanced according to context.
+
+Fixes:db91841b58f9a ("spi/omap100k: Convert to runtime PM")
+
+Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
+Link: https://lore.kernel.org/r/20220924121310.78331-4-zhangqilong3@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-omap-100k.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
+index 20b047172965..061f7394e5b9 100644
+--- a/drivers/spi/spi-omap-100k.c
++++ b/drivers/spi/spi-omap-100k.c
+@@ -412,6 +412,7 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
+ return status;
+
+ err_fck:
++ pm_runtime_disable(&pdev->dev);
+ clk_disable_unprepare(spi100k->fck);
+ err_ick:
+ clk_disable_unprepare(spi100k->ick);
+--
+2.35.1
+
--- /dev/null
+From 51f5072533fb791365f21b080330990a735e123e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 06:53:23 +0000
+Subject: spi: qup: add missing clk_disable_unprepare on error in
+ spi_qup_resume()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Xu Qiang <xuqiang36@huawei.com>
+
+[ Upstream commit 70034320fdc597b8f58b4a43bb547f17c4c5557a ]
+
+Add the missing clk_disable_unprepare() before return
+from spi_qup_resume() in the error handling case.
+
+Fixes: 64ff247a978f (“spi: Add Qualcomm QUP SPI controller support”)
+Signed-off-by: Xu Qiang <xuqiang36@huawei.com>
+Link: https://lore.kernel.org/r/20220825065324.68446-1-xuqiang36@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-qup.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
+index d39dec6d1c91..668d79922fac 100644
+--- a/drivers/spi/spi-qup.c
++++ b/drivers/spi/spi-qup.c
+@@ -1246,14 +1246,25 @@ static int spi_qup_resume(struct device *device)
+ return ret;
+
+ ret = clk_prepare_enable(controller->cclk);
+- if (ret)
++ if (ret) {
++ clk_disable_unprepare(controller->iclk);
+ return ret;
++ }
+
+ ret = spi_qup_set_state(controller, QUP_STATE_RESET);
+ if (ret)
+- return ret;
++ goto disable_clk;
++
++ ret = spi_master_resume(master);
++ if (ret)
++ goto disable_clk;
+
+- return spi_master_resume(master);
++ return 0;
++
++disable_clk:
++ clk_disable_unprepare(controller->cclk);
++ clk_disable_unprepare(controller->iclk);
++ return ret;
+ }
+ #endif /* CONFIG_PM_SLEEP */
+
+--
+2.35.1
+
--- /dev/null
+From 1bdf0e08e8bd5cbe570f2551ac4bce35b8a0178d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 06:53:24 +0000
+Subject: spi: qup: add missing clk_disable_unprepare on error in
+ spi_qup_pm_resume_runtime()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Xu Qiang <xuqiang36@huawei.com>
+
+[ Upstream commit 494a22765ce479c9f8ad181c5d24cffda9f534bb ]
+
+Add the missing clk_disable_unprepare() before return
+from spi_qup_pm_resume_runtime() in the error handling case.
+
+Fixes: dae1a7700b34 (“spi: qup: Handle clocks in pm_runtime suspend and resume”)
+Signed-off-by: Xu Qiang <xuqiang36@huawei.com>
+Link: https://lore.kernel.org/r/20220825065324.68446-2-xuqiang36@huawei.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-qup.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
+index 668d79922fac..f3877eeb3da6 100644
+--- a/drivers/spi/spi-qup.c
++++ b/drivers/spi/spi-qup.c
+@@ -1199,8 +1199,10 @@ static int spi_qup_pm_resume_runtime(struct device *device)
+ return ret;
+
+ ret = clk_prepare_enable(controller->cclk);
+- if (ret)
++ if (ret) {
++ clk_disable_unprepare(controller->iclk);
+ return ret;
++ }
+
+ /* Disable clocks auto gaiting */
+ config = readl_relaxed(controller->base + QUP_CONFIG);
+--
+2.35.1
+
--- /dev/null
+From 77dc173d1b5c743b418bb1b6f296f3b3d2f0353f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 13:21:17 +0200
+Subject: spi: s3c64xx: Fix large transfers with DMA
+
+From: Vincent Whitchurch <vincent.whitchurch@axis.com>
+
+[ Upstream commit 1224e29572f655facfcd850cf0f0a4784f36a903 ]
+
+The COUNT_VALUE in the PACKET_CNT register is 16-bit so the maximum
+value is 65535. Asking the driver to transfer a larger size currently
+leads to the DMA transfer timing out. Implement ->max_transfer_size()
+and have the core split the transfer as needed.
+
+Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver")
+Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
+Link: https://lore.kernel.org/r/20220927112117.77599-5-vincent.whitchurch@axis.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-s3c64xx.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
+index 8755cd85e83c..90c70d53e85e 100644
+--- a/drivers/spi/spi-s3c64xx.c
++++ b/drivers/spi/spi-s3c64xx.c
+@@ -85,6 +85,7 @@
+ #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
+
+ #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
++#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
+
+ #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
+ #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
+@@ -661,6 +662,13 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master,
+ return 0;
+ }
+
++static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
++{
++ struct spi_controller *ctlr = spi->controller;
++
++ return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
++}
++
+ static int s3c64xx_spi_transfer_one(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *xfer)
+@@ -1130,6 +1138,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
+ master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
+ master->prepare_message = s3c64xx_spi_prepare_message;
+ master->transfer_one = s3c64xx_spi_transfer_one;
++ master->max_transfer_size = s3c64xx_spi_max_transfer_size;
+ master->num_chipselect = sci->num_cs;
+ master->dma_alignment = 8;
+ master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
+--
+2.35.1
+
--- /dev/null
+From faa9b180886f29a6b666bb061f2b50de3c29017d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 17:50:16 -0700
+Subject: spmi: pmic-arb: correct duplicate APID to PPID mapping logic
+
+From: David Collins <collinsd@codeaurora.org>
+
+[ Upstream commit 1f1693118c2476cb1666ad357edcf3cf48bf9b16 ]
+
+Correct the way that duplicate PPID mappings are handled for PMIC
+arbiter v5. The final APID mapped to a given PPID should be the
+one which has write owner = APPS EE, if it exists, or if not
+that, then the first APID mapped to the PPID, if it exists.
+
+Fixes: 40f318f0ed67 ("spmi: pmic-arb: add support for HW version 5")
+Signed-off-by: David Collins <collinsd@codeaurora.org>
+Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
+Link: https://lore.kernel.org/r/1655004286-11493-7-git-send-email-quic_fenglinw@quicinc.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Link: https://lore.kernel.org/r/20220930005019.2663064-8-sboyd@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spmi/spmi-pmic-arb.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
+index bbbd311eda03..e6de2aeece8d 100644
+--- a/drivers/spmi/spmi-pmic-arb.c
++++ b/drivers/spmi/spmi-pmic-arb.c
+@@ -887,7 +887,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
+ * version 5, there is more than one APID mapped to each PPID.
+ * The owner field for each of these mappings specifies the EE which is
+ * allowed to write to the APID. The owner of the last (highest) APID
+- * for a given PPID will receive interrupts from the PPID.
++ * which has the IRQ owner bit set for a given PPID will receive
++ * interrupts from the PPID.
+ */
+ for (i = 0; ; i++, apidd++) {
+ offset = pmic_arb->ver_ops->apid_map_offset(i);
+@@ -910,16 +911,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
+ apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+ prev_apidd = &pmic_arb->apid_data[apid];
+
+- if (valid && is_irq_ee &&
+- prev_apidd->write_ee == pmic_arb->ee) {
++ if (!valid || apidd->write_ee == pmic_arb->ee) {
++ /* First PPID mapping or one for this EE */
++ pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
++ } else if (valid && is_irq_ee &&
++ prev_apidd->write_ee == pmic_arb->ee) {
+ /*
+ * Duplicate PPID mapping after the one for this EE;
+ * override the irq owner
+ */
+ prev_apidd->irq_ee = apidd->irq_ee;
+- } else if (!valid || is_irq_ee) {
+- /* First PPID mapping or duplicate for another EE */
+- pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
+ }
+
+ apidd->ppid = ppid;
+--
+2.35.1
+
--- /dev/null
+From 0a899cb4ea7fcccd8d0813ffa98d3f45993bc27e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 19:27:21 +0800
+Subject: staging: rtl8723bs: fix a potential memory leak in
+ rtw_init_cmd_priv()
+
+From: Xiaoke Wang <xkernel.wang@foxmail.com>
+
+[ Upstream commit 708056fba733a73d926772ea4ce9a42d240345da ]
+
+In rtw_init_cmd_priv(), if `pcmdpriv->rsp_allocated_buf` is allocated
+in failure, then `pcmdpriv->cmd_allocated_buf` will be not properly
+released. Besides, considering there are only two error paths and the
+first one can directly return, so we do not need implicitly jump to the
+`exit` tag to execute the error handler.
+
+So this patch added `kfree(pcmdpriv->cmd_allocated_buf);` on the error
+path to release the resource and simplified the return logic of
+rtw_init_cmd_priv(). As there is no proper device to test with, no runtime
+testing was performed.
+
+Signed-off-by: Xiaoke Wang <xkernel.wang@foxmail.com>
+Link: https://lore.kernel.org/r/tencent_2B7931B79BA38E22205C5A09EFDF11E48805@qq.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/staging/rtl8723bs/core/rtw_cmd.c | 16 ++++++----------
+ 1 file changed, 6 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/staging/rtl8723bs/core/rtw_cmd.c b/drivers/staging/rtl8723bs/core/rtw_cmd.c
+index d494c06dab96..93e3a4c9e115 100644
+--- a/drivers/staging/rtl8723bs/core/rtw_cmd.c
++++ b/drivers/staging/rtl8723bs/core/rtw_cmd.c
+@@ -161,8 +161,6 @@ static struct cmd_hdl wlancmds[] = {
+
+ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
+ {
+- int res = 0;
+-
+ init_completion(&pcmdpriv->cmd_queue_comp);
+ init_completion(&pcmdpriv->terminate_cmdthread_comp);
+
+@@ -174,18 +172,16 @@ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
+
+ pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
+
+- if (!pcmdpriv->cmd_allocated_buf) {
+- res = -ENOMEM;
+- goto exit;
+- }
++ if (!pcmdpriv->cmd_allocated_buf)
++ return -ENOMEM;
+
+ pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1));
+
+ pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);
+
+ if (!pcmdpriv->rsp_allocated_buf) {
+- res = -ENOMEM;
+- goto exit;
++ kfree(pcmdpriv->cmd_allocated_buf);
++ return -ENOMEM;
+ }
+
+ pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);
+@@ -195,8 +191,8 @@ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
+ pcmdpriv->rsp_cnt = 0;
+
+ mutex_init(&pcmdpriv->sctx_mutex);
+-exit:
+- return res;
++
++ return 0;
+ }
+
+ static void c2h_wk_callback(struct work_struct *work);
+--
+2.35.1
+
--- /dev/null
+From 1ef1859c48c93b97a963cf6ab6ec796bdef19d18 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 18:39:35 +0800
+Subject: staging: rtl8723bs: fix potential memory leak in rtw_init_drv_sw()
+
+From: Xiaoke Wang <xkernel.wang@foxmail.com>
+
+[ Upstream commit 5a5aa9cce621e2c0e25a1e5d72d6be1749167cc0 ]
+
+In rtw_init_drv_sw(), there are various init functions are called to
+populate the padapter structure and some checks for their return value.
+However, except for the first one error path, the other five error paths
+do not properly release the previous allocated resources, which leads to
+various memory leaks.
+
+This patch fixes them and keeps the success and error separate.
+Note that these changes keep the form of `rtw_init_drv_sw()` in
+"drivers/staging/r8188eu/os_dep/os_intfs.c". As there is no proper device
+to test with, no runtime testing was performed.
+
+Signed-off-by: Xiaoke Wang <xkernel.wang@foxmail.com>
+Link: https://lore.kernel.org/r/tencent_C3B899D2FC3F1BC827F3552E0B0734056006@qq.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/staging/rtl8723bs/os_dep/os_intfs.c | 60 +++++++++++----------
+ 1 file changed, 31 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/staging/rtl8723bs/os_dep/os_intfs.c b/drivers/staging/rtl8723bs/os_dep/os_intfs.c
+index f78bf174de8e..23f4f706f935 100644
+--- a/drivers/staging/rtl8723bs/os_dep/os_intfs.c
++++ b/drivers/staging/rtl8723bs/os_dep/os_intfs.c
+@@ -664,51 +664,36 @@ void rtw_reset_drv_sw(struct adapter *padapter)
+
+ u8 rtw_init_drv_sw(struct adapter *padapter)
+ {
+- u8 ret8 = _SUCCESS;
+-
+ rtw_init_default_value(padapter);
+
+ rtw_init_hal_com_default_value(padapter);
+
+- if (rtw_init_cmd_priv(&padapter->cmdpriv)) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (rtw_init_cmd_priv(&padapter->cmdpriv))
++ return _FAIL;
+
+ padapter->cmdpriv.padapter = padapter;
+
+- if (rtw_init_evt_priv(&padapter->evtpriv)) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (rtw_init_evt_priv(&padapter->evtpriv))
++ goto free_cmd_priv;
+
+-
+- if (rtw_init_mlme_priv(padapter) == _FAIL) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (rtw_init_mlme_priv(padapter) == _FAIL)
++ goto free_evt_priv;
+
+ init_mlme_ext_priv(padapter);
+
+- if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL)
++ goto free_mlme_ext;
+
+- if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL)
++ goto free_xmit_priv;
+ /* add for CONFIG_IEEE80211W, none 11w also can use */
+ spin_lock_init(&padapter->security_key_mutex);
+
+ /* We don't need to memset padapter->XXX to zero, because adapter is allocated by vzalloc(). */
+ /* memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */
+
+- if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) {
+- ret8 = _FAIL;
+- goto exit;
+- }
++ if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL)
++ goto free_recv_priv;
+
+ padapter->stapriv.padapter = padapter;
+ padapter->setband = GHZ24_50;
+@@ -719,9 +704,26 @@ u8 rtw_init_drv_sw(struct adapter *padapter)
+
+ rtw_hal_dm_init(padapter);
+
+-exit:
++ return _SUCCESS;
++
++free_recv_priv:
++ _rtw_free_recv_priv(&padapter->recvpriv);
++
++free_xmit_priv:
++ _rtw_free_xmit_priv(&padapter->xmitpriv);
++
++free_mlme_ext:
++ free_mlme_ext_priv(&padapter->mlmeextpriv);
+
+- return ret8;
++ rtw_free_mlme_priv(&padapter->mlmepriv);
++
++free_evt_priv:
++ rtw_free_evt_priv(&padapter->evtpriv);
++
++free_cmd_priv:
++ rtw_free_cmd_priv(&padapter->cmdpriv);
++
++ return _FAIL;
+ }
+
+ void rtw_cancel_all_timer(struct adapter *padapter)
+--
+2.35.1
+
--- /dev/null
+From 04b83dbd7b2dcc09538a787a8e5521108273511b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 9 Sep 2022 16:13:39 +0200
+Subject: staging: vt6655: fix potential memory leak
+
+From: Nam Cao <namcaov@gmail.com>
+
+[ Upstream commit c8ff91535880d41b49699b3829fb6151942de29e ]
+
+In function device_init_td0_ring, memory is allocated for member
+td_info of priv->apTD0Rings[i], with i increasing from 0. In case of
+allocation failure, the memory is freed in reversed order, with i
+decreasing to 0. However, the case i=0 is left out and thus memory is
+leaked.
+
+Modify the memory freeing loop to include the case i=0.
+
+Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
+Signed-off-by: Nam Cao <namcaov@gmail.com>
+Link: https://lore.kernel.org/r/20220909141338.19343-1-namcaov@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/staging/vt6655/device_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c
+index 43e32360b6d9..775537b243aa 100644
+--- a/drivers/staging/vt6655/device_main.c
++++ b/drivers/staging/vt6655/device_main.c
+@@ -676,7 +676,7 @@ static int device_init_td0_ring(struct vnt_private *priv)
+ return 0;
+
+ err_free_desc:
+- while (--i) {
++ while (i--) {
+ desc = &priv->apTD0Rings[i];
+ kfree(desc->td_info);
+ }
+--
+2.35.1
+
--- /dev/null
+From ec023fbeb4c0e00b93813df8c4207ca6413a361a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 12 Sep 2022 19:04:31 +0200
+Subject: staging: vt6655: fix some erroneous memory clean-up loops
+
+From: Nam Cao <namcaov@gmail.com>
+
+[ Upstream commit 2a2db520e3ca5aafba7c211abfd397666c9b5f9d ]
+
+In some initialization functions of this driver, memory is allocated with
+'i' acting as an index variable and increasing from 0. The commit in
+"Fixes" introduces some clean-up codes in case of allocation failure,
+which free memory in reverse order with 'i' decreasing to 0. However,
+there are some problems:
+ - The case i=0 is left out. Thus memory is leaked.
+ - In case memory allocation fails right from the start, the memory
+ freeing loops will start with i=-1 and invalid memory locations will
+ be accessed.
+
+One of these loops has been fixed in commit c8ff91535880 ("staging:
+vt6655: fix potential memory leak"). Fix the remaining erroneous loops.
+
+Link: https://lore.kernel.org/linux-staging/Yx9H1zSpxmNqx6Xc@kadam/
+Fixes: 5341ee0adb17 ("staging: vt6655: check for memory allocation failures")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
+Signed-off-by: Nam Cao <namcaov@gmail.com>
+Link: https://lore.kernel.org/r/20220912170429.29852-1-namcaov@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/staging/vt6655/device_main.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c
+index d40c2ac14928..43e32360b6d9 100644
+--- a/drivers/staging/vt6655/device_main.c
++++ b/drivers/staging/vt6655/device_main.c
+@@ -565,7 +565,7 @@ static int device_init_rd0_ring(struct vnt_private *priv)
+ kfree(desc->rd_info);
+
+ err_free_desc:
+- while (--i) {
++ while (i--) {
+ desc = &priv->aRD0Ring[i];
+ device_free_rx_buf(priv, desc);
+ kfree(desc->rd_info);
+@@ -611,7 +611,7 @@ static int device_init_rd1_ring(struct vnt_private *priv)
+ kfree(desc->rd_info);
+
+ err_free_desc:
+- while (--i) {
++ while (i--) {
+ desc = &priv->aRD1Ring[i];
+ device_free_rx_buf(priv, desc);
+ kfree(desc->rd_info);
+@@ -716,7 +716,7 @@ static int device_init_td1_ring(struct vnt_private *priv)
+ return 0;
+
+ err_free_desc:
+- while (--i) {
++ while (i--) {
+ desc = &priv->apTD1Rings[i];
+ kfree(desc->td_info);
+ }
+--
+2.35.1
+
--- /dev/null
+From 03be175dcba269c75dd860acd3f5c3a45ffc4c72 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Oct 2021 11:57:28 -0400
+Subject: SUNRPC: Change return value type of .pc_decode
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit c44b31c263798ec34614dd394c31ef1a2e7e716e ]
+
+Returning an undecorated integer is an age-old trope, but it's
+not clear (even to previous experts in this code) that the only
+valid return values are 1 and 0. These functions do not return
+a negative errno, rpc_stat value, or a positive length.
+
+Document there are only two valid return values by having
+.pc_decode return only true or false.
+
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: J. Bruce Fields <bfields@redhat.com>
+Stable-dep-of: 7518a3dc5ea2 ("NFSD: Fix handling of oversized NFSv4 COMPOUND requests")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/lockd/xdr.c | 96 +++++++++++++++---------------
+ fs/lockd/xdr4.c | 97 +++++++++++++++---------------
+ fs/nfsd/nfs2acl.c | 30 +++++-----
+ fs/nfsd/nfs3acl.c | 22 +++----
+ fs/nfsd/nfs3xdr.c | 118 ++++++++++++++++++-------------------
+ fs/nfsd/nfs4xdr.c | 24 ++++----
+ fs/nfsd/nfsd.h | 2 +-
+ fs/nfsd/nfssvc.c | 6 +-
+ fs/nfsd/nfsxdr.c | 62 +++++++++----------
+ fs/nfsd/xdr.h | 20 +++----
+ fs/nfsd/xdr3.h | 30 +++++-----
+ fs/nfsd/xdr4.h | 2 +-
+ include/linux/lockd/xdr.h | 18 +++---
+ include/linux/lockd/xdr4.h | 18 +++---
+ include/linux/sunrpc/svc.h | 2 +-
+ 15 files changed, 274 insertions(+), 273 deletions(-)
+
+diff --git a/fs/lockd/xdr.c b/fs/lockd/xdr.c
+index 895f15222104..622c2ca37dbf 100644
+--- a/fs/lockd/xdr.c
++++ b/fs/lockd/xdr.c
+@@ -145,103 +145,103 @@ svcxdr_encode_testrply(struct xdr_stream *xdr, const struct nlm_res *resp)
+ * Decode Call arguments
+ */
+
+-int
++bool
+ nlmsvc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &argp->block) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+ if (xdr_stream_decode_bool(xdr, &argp->reclaim) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+ argp->monitor = 1; /* monitor client by default */
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &argp->block) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ argp->lock.fl.fl_type = F_UNLCK;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_res *resp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &resp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_stats(xdr, &resp->status))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_reboot *argp = rqstp->rq_argp;
+@@ -249,25 +249,25 @@ nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ u32 len;
+
+ if (xdr_stream_decode_u32(xdr, &len) < 0)
+- return 0;
++ return false;
+ if (len > SM_MAXSTRLEN)
+- return 0;
++ return false;
+ p = xdr_inline_decode(xdr, len);
+ if (!p)
+- return 0;
++ return false;
+ argp->len = len;
+ argp->mon = (char *)p;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+ p = xdr_inline_decode(xdr, SM_PRIV_SIZE);
+ if (!p)
+- return 0;
++ return false;
+ memcpy(&argp->priv.data, p, sizeof(argp->priv.data));
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+@@ -278,34 +278,34 @@ nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ lock->svid = ~(u32)0;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_string(xdr, &lock->caller, &lock->len))
+- return 0;
++ return false;
+ if (!svcxdr_decode_fhandle(xdr, &lock->fh))
+- return 0;
++ return false;
+ if (!svcxdr_decode_owner(xdr, &lock->oh))
+- return 0;
++ return false;
+ /* XXX: Range checks are missing in the original code */
+ if (xdr_stream_decode_u32(xdr, &argp->fsm_mode) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->fsm_access) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlmsvc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+ if (!svcxdr_decode_string(xdr, &lock->caller, &lock->len))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+
+diff --git a/fs/lockd/xdr4.c b/fs/lockd/xdr4.c
+index 05f203f622d8..0173865ed39f 100644
+--- a/fs/lockd/xdr4.c
++++ b/fs/lockd/xdr4.c
+@@ -129,102 +129,103 @@ svcxdr_encode_testrply(struct xdr_stream *xdr, const struct nlm_res *resp)
+ * Decode Call arguments
+ */
+
+-int
++bool
+ nlm4svc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &argp->block) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+ if (xdr_stream_decode_bool(xdr, &argp->reclaim) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+ argp->monitor = 1; /* monitor client by default */
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &argp->block) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_bool(xdr, &exclusive) < 0)
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ if (exclusive)
+ argp->lock.fl.fl_type = F_WRLCK;
+- return 1;
++
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_lock(xdr, &argp->lock))
+- return 0;
++ return false;
+ argp->lock.fl.fl_type = F_UNLCK;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_res *resp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &resp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_stats(xdr, &resp->status))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_reboot *argp = rqstp->rq_argp;
+@@ -232,25 +233,25 @@ nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ u32 len;
+
+ if (xdr_stream_decode_u32(xdr, &len) < 0)
+- return 0;
++ return false;
+ if (len > SM_MAXSTRLEN)
+- return 0;
++ return false;
+ p = xdr_inline_decode(xdr, len);
+ if (!p)
+- return 0;
++ return false;
+ argp->len = len;
+ argp->mon = (char *)p;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+ p = xdr_inline_decode(xdr, SM_PRIV_SIZE);
+ if (!p)
+- return 0;
++ return false;
+ memcpy(&argp->priv.data, p, sizeof(argp->priv.data));
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+@@ -261,34 +262,34 @@ nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ lock->svid = ~(u32)0;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+- return 0;
++ return false;
+ if (!svcxdr_decode_string(xdr, &lock->caller, &lock->len))
+- return 0;
++ return false;
+ if (!svcxdr_decode_fhandle(xdr, &lock->fh))
+- return 0;
++ return false;
+ if (!svcxdr_decode_owner(xdr, &lock->oh))
+- return 0;
++ return false;
+ /* XXX: Range checks are missing in the original code */
+ if (xdr_stream_decode_u32(xdr, &argp->fsm_mode) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->fsm_access) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nlm4svc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+ if (!svcxdr_decode_string(xdr, &lock->caller, &lock->len))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->state) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+
+diff --git a/fs/nfsd/nfs2acl.c b/fs/nfsd/nfs2acl.c
+index 0069c0fdb94f..cf6ba5e7937e 100644
+--- a/fs/nfsd/nfs2acl.c
++++ b/fs/nfsd/nfs2acl.c
+@@ -188,51 +188,51 @@ static __be32 nfsacld_proc_access(struct svc_rqst *rqstp)
+ * XDR decode functions
+ */
+
+-static int
++static bool
+ nfsaclsvc_decode_getaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_getaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &argp->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->mask) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-static int
++static bool
+ nfsaclsvc_decode_setaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_setaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &argp->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->mask) < 0)
+- return 0;
++ return false;
+ if (argp->mask & ~NFS_ACL_MASK)
+- return 0;
++ return false;
+ if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask & NFS_ACL) ?
+ &argp->acl_access : NULL))
+- return 0;
++ return false;
+ if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask & NFS_DFACL) ?
+ &argp->acl_default : NULL))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-static int
++static bool
+ nfsaclsvc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_accessargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->access) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+ /*
+diff --git a/fs/nfsd/nfs3acl.c b/fs/nfsd/nfs3acl.c
+index b1e352ed2436..9e9f6afb2e00 100644
+--- a/fs/nfsd/nfs3acl.c
++++ b/fs/nfsd/nfs3acl.c
+@@ -127,38 +127,38 @@ static __be32 nfsd3_proc_setacl(struct svc_rqst *rqstp)
+ * XDR decode functions
+ */
+
+-static int
++static bool
+ nfs3svc_decode_getaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_getaclargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->mask) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-static int
++static bool
+ nfs3svc_decode_setaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_setaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &argp->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &argp->mask) < 0)
+- return 0;
++ return false;
+ if (argp->mask & ~NFS_ACL_MASK)
+- return 0;
++ return false;
+ if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask & NFS_ACL) ?
+ &argp->acl_access : NULL))
+- return 0;
++ return false;
+ if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask & NFS_DFACL) ?
+ &argp->acl_default : NULL))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+ /*
+diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c
+index 4ce0cdb3751d..2b2307666859 100644
+--- a/fs/nfsd/nfs3xdr.c
++++ b/fs/nfsd/nfs3xdr.c
+@@ -546,7 +546,7 @@ void fill_post_wcc(struct svc_fh *fhp)
+ * XDR decode functions
+ */
+
+-int
++bool
+ nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_fhandle *args = rqstp->rq_argp;
+@@ -554,7 +554,7 @@ nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ return svcxdr_decode_nfs_fh3(xdr, &args->fh);
+ }
+
+-int
++bool
+ nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_sattrargs *args = rqstp->rq_argp;
+@@ -564,7 +564,7 @@ nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ svcxdr_decode_sattrguard3(xdr, args);
+ }
+
+-int
++bool
+ nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_diropargs *args = rqstp->rq_argp;
+@@ -572,75 +572,75 @@ nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ return svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len);
+ }
+
+-int
++bool
+ nfs3svc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_accessargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->access) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_readargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u64(xdr, &args->offset) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_writeargs *args = rqstp->rq_argp;
+ u32 max_blocksize = svc_max_payload(rqstp);
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u64(xdr, &args->offset) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->stable) < 0)
+- return 0;
++ return false;
+
+ /* opaque data */
+ if (xdr_stream_decode_u32(xdr, &args->len) < 0)
+- return 0;
++ return false;
+
+ /* request sanity */
+ if (args->count != args->len)
+- return 0;
++ return false;
+ if (args->count > max_blocksize) {
+ args->count = max_blocksize;
+ args->len = max_blocksize;
+ }
+ if (!xdr_stream_subsegment(xdr, &args->payload, args->count))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_createargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->createmode) < 0)
+- return 0;
++ return false;
+ switch (args->createmode) {
+ case NFS3_CREATE_UNCHECKED:
+ case NFS3_CREATE_GUARDED:
+@@ -648,15 +648,15 @@ nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ case NFS3_CREATE_EXCLUSIVE:
+ args->verf = xdr_inline_decode(xdr, NFS3_CREATEVERFSIZE);
+ if (!args->verf)
+- return 0;
++ return false;
+ break;
+ default:
+- return 0;
++ return false;
+ }
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_createargs *args = rqstp->rq_argp;
+@@ -666,7 +666,7 @@ nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ svcxdr_decode_sattr3(rqstp, xdr, &args->attrs);
+ }
+
+-int
++bool
+ nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_symlinkargs *args = rqstp->rq_argp;
+@@ -675,33 +675,33 @@ nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ size_t remaining;
+
+ if (!svcxdr_decode_diropargs3(xdr, &args->ffh, &args->fname, &args->flen))
+- return 0;
++ return false;
+ if (!svcxdr_decode_sattr3(rqstp, xdr, &args->attrs))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->tlen) < 0)
+- return 0;
++ return false;
+
+ /* request sanity */
+ remaining = head->iov_len + rqstp->rq_arg.page_len + tail->iov_len;
+ remaining -= xdr_stream_pos(xdr);
+ if (remaining < xdr_align_size(args->tlen))
+- return 0;
++ return false;
+
+ args->first.iov_base = xdr->p;
+ args->first.iov_len = head->iov_len - xdr_stream_pos(xdr);
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_mknodargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->ftype) < 0)
+- return 0;
++ return false;
+ switch (args->ftype) {
+ case NF3CHR:
+ case NF3BLK:
+@@ -715,13 +715,13 @@ nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ /* Valid XDR but illegal file types */
+ break;
+ default:
+- return 0;
++ return false;
+ }
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_renameargs *args = rqstp->rq_argp;
+@@ -732,7 +732,7 @@ nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ &args->tname, &args->tlen);
+ }
+
+-int
++bool
+ nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_linkargs *args = rqstp->rq_argp;
+@@ -742,59 +742,59 @@ nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ &args->tname, &args->tlen);
+ }
+
+-int
++bool
+ nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_readdirargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u64(xdr, &args->cookie) < 0)
+- return 0;
++ return false;
+ args->verf = xdr_inline_decode(xdr, NFS3_COOKIEVERFSIZE);
+ if (!args->verf)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_readdirargs *args = rqstp->rq_argp;
+ u32 dircount;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u64(xdr, &args->cookie) < 0)
+- return 0;
++ return false;
+ args->verf = xdr_inline_decode(xdr, NFS3_COOKIEVERFSIZE);
+ if (!args->verf)
+- return 0;
++ return false;
+ /* dircount is ignored */
+ if (xdr_stream_decode_u32(xdr, &dircount) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfs3svc_decode_commitargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd3_commitargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u64(xdr, &args->offset) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+ /*
+diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
+index 3a2a73a85032..4504d1246d14 100644
+--- a/fs/nfsd/nfs4xdr.c
++++ b/fs/nfsd/nfs4xdr.c
+@@ -2319,7 +2319,7 @@ nfsd4_opnum_in_range(struct nfsd4_compoundargs *argp, struct nfsd4_op *op)
+ return true;
+ }
+
+-static int
++static bool
+ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+ {
+ struct nfsd4_op *op;
+@@ -2332,25 +2332,25 @@ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+ int i;
+
+ if (xdr_stream_decode_u32(argp->xdr, &argp->taglen) < 0)
+- return 0;
++ return false;
+ max_reply += XDR_UNIT;
+ argp->tag = NULL;
+ if (unlikely(argp->taglen)) {
+ if (argp->taglen > NFSD4_MAX_TAGLEN)
+- return 0;
++ return false;
+ p = xdr_inline_decode(argp->xdr, argp->taglen);
+ if (!p)
+- return 0;
++ return false;
+ argp->tag = svcxdr_savemem(argp, p, argp->taglen);
+ if (!argp->tag)
+- return 0;
++ return false;
+ max_reply += xdr_align_size(argp->taglen);
+ }
+
+ if (xdr_stream_decode_u32(argp->xdr, &argp->minorversion) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(argp->xdr, &argp->opcnt) < 0)
+- return 0;
++ return false;
+
+ /*
+ * NFS4ERR_RESOURCE is a more helpful error than GARBAGE_ARGS
+@@ -2358,14 +2358,14 @@ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+ * nfsd4_proc can handle this is an NFS-level error.
+ */
+ if (argp->opcnt > NFSD_MAX_OPS_PER_COMPOUND)
+- return 1;
++ return true;
+
+ if (argp->opcnt > ARRAY_SIZE(argp->iops)) {
+ argp->ops = kzalloc(argp->opcnt * sizeof(*argp->ops), GFP_KERNEL);
+ if (!argp->ops) {
+ argp->ops = argp->iops;
+ dprintk("nfsd: couldn't allocate room for COMPOUND\n");
+- return 0;
++ return false;
+ }
+ }
+
+@@ -2377,7 +2377,7 @@ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+ op->replay = NULL;
+
+ if (xdr_stream_decode_u32(argp->xdr, &op->opnum) < 0)
+- return 0;
++ return false;
+ if (nfsd4_opnum_in_range(argp, op)) {
+ op->status = nfsd4_dec_ops[op->opnum](argp, &op->u);
+ if (op->status != nfs_ok)
+@@ -2424,7 +2424,7 @@ nfsd4_decode_compound(struct nfsd4_compoundargs *argp)
+ if (readcount > 1 || max_reply > PAGE_SIZE - auth_slack)
+ clear_bit(RQ_SPLICE_OK, &argp->rqstp->rq_flags);
+
+- return 1;
++ return true;
+ }
+
+ static __be32 *encode_change(__be32 *p, struct kstat *stat, struct inode *inode,
+@@ -5407,7 +5407,7 @@ void nfsd4_release_compoundargs(struct svc_rqst *rqstp)
+ }
+ }
+
+-int
++bool
+ nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd4_compoundargs *args = rqstp->rq_argp;
+diff --git a/fs/nfsd/nfsd.h b/fs/nfsd/nfsd.h
+index 6e8ad5f9757c..bfcddd4c7534 100644
+--- a/fs/nfsd/nfsd.h
++++ b/fs/nfsd/nfsd.h
+@@ -78,7 +78,7 @@ extern const struct seq_operations nfs_exports_op;
+ */
+ struct nfsd_voidargs { };
+ struct nfsd_voidres { };
+-int nfssvc_decode_voidarg(struct svc_rqst *rqstp,
++bool nfssvc_decode_voidarg(struct svc_rqst *rqstp,
+ struct xdr_stream *xdr);
+ int nfssvc_encode_voidres(struct svc_rqst *rqstp, __be32 *p);
+
+diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c
+index 7cd13e9474ff..beb564e8a3db 100644
+--- a/fs/nfsd/nfssvc.c
++++ b/fs/nfsd/nfssvc.c
+@@ -1067,10 +1067,10 @@ int nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp)
+ * @xdr: XDR stream positioned at arguments to decode
+ *
+ * Return values:
+- * %0: Arguments were not valid
+- * %1: Decoding was successful
++ * %false: Arguments were not valid
++ * %true: Decoding was successful
+ */
+-int nfssvc_decode_voidarg(struct svc_rqst *rqstp, struct xdr_stream *xdr)
++bool nfssvc_decode_voidarg(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ return 1;
+ }
+diff --git a/fs/nfsd/nfsxdr.c b/fs/nfsd/nfsxdr.c
+index 38c4b199a10f..921c1c4344ef 100644
+--- a/fs/nfsd/nfsxdr.c
++++ b/fs/nfsd/nfsxdr.c
+@@ -272,7 +272,7 @@ svcxdr_encode_fattr(struct svc_rqst *rqstp, struct xdr_stream *xdr,
+ * XDR decode functions
+ */
+
+-int
++bool
+ nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_fhandle *args = rqstp->rq_argp;
+@@ -280,7 +280,7 @@ nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ return svcxdr_decode_fhandle(xdr, &args->fh);
+ }
+
+-int
++bool
+ nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_sattrargs *args = rqstp->rq_argp;
+@@ -289,7 +289,7 @@ nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ svcxdr_decode_sattr(rqstp, xdr, &args->attrs);
+ }
+
+-int
++bool
+ nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_diropargs *args = rqstp->rq_argp;
+@@ -297,54 +297,54 @@ nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ return svcxdr_decode_diropargs(xdr, &args->fh, &args->name, &args->len);
+ }
+
+-int
++bool
+ nfssvc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_readargs *args = rqstp->rq_argp;
+ u32 totalcount;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->offset) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+ /* totalcount is ignored */
+ if (xdr_stream_decode_u32(xdr, &totalcount) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfssvc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_writeargs *args = rqstp->rq_argp;
+ u32 beginoffset, totalcount;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+- return 0;
++ return false;
+ /* beginoffset is ignored */
+ if (xdr_stream_decode_u32(xdr, &beginoffset) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->offset) < 0)
+- return 0;
++ return false;
+ /* totalcount is ignored */
+ if (xdr_stream_decode_u32(xdr, &totalcount) < 0)
+- return 0;
++ return false;
+
+ /* opaque data */
+ if (xdr_stream_decode_u32(xdr, &args->len) < 0)
+- return 0;
++ return false;
+ if (args->len > NFSSVC_MAXBLKSIZE_V2)
+- return 0;
++ return false;
+ if (!xdr_stream_subsegment(xdr, &args->payload, args->len))
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+-int
++bool
+ nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_createargs *args = rqstp->rq_argp;
+@@ -354,7 +354,7 @@ nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ svcxdr_decode_sattr(rqstp, xdr, &args->attrs);
+ }
+
+-int
++bool
+ nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_renameargs *args = rqstp->rq_argp;
+@@ -365,7 +365,7 @@ nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ &args->tname, &args->tlen);
+ }
+
+-int
++bool
+ nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_linkargs *args = rqstp->rq_argp;
+@@ -375,39 +375,39 @@ nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ &args->tname, &args->tlen);
+ }
+
+-int
++bool
+ nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_symlinkargs *args = rqstp->rq_argp;
+ struct kvec *head = rqstp->rq_arg.head;
+
+ if (!svcxdr_decode_diropargs(xdr, &args->ffh, &args->fname, &args->flen))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->tlen) < 0)
+- return 0;
++ return false;
+ if (args->tlen == 0)
+- return 0;
++ return false;
+
+ args->first.iov_len = head->iov_len - xdr_stream_pos(xdr);
+ args->first.iov_base = xdr_inline_decode(xdr, args->tlen);
+ if (!args->first.iov_base)
+- return 0;
++ return false;
+ return svcxdr_decode_sattr(rqstp, xdr, &args->attrs);
+ }
+
+-int
++bool
+ nfssvc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd_readdirargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->cookie) < 0)
+- return 0;
++ return false;
+ if (xdr_stream_decode_u32(xdr, &args->count) < 0)
+- return 0;
++ return false;
+
+- return 1;
++ return true;
+ }
+
+ /*
+diff --git a/fs/nfsd/xdr.h b/fs/nfsd/xdr.h
+index 19e281382bb9..d897c198c912 100644
+--- a/fs/nfsd/xdr.h
++++ b/fs/nfsd/xdr.h
+@@ -141,16 +141,16 @@ union nfsd_xdrstore {
+ #define NFS2_SVC_XDRSIZE sizeof(union nfsd_xdrstore)
+
+
+-int nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfssvc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfssvc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+
+ int nfssvc_encode_statres(struct svc_rqst *, __be32 *);
+ int nfssvc_encode_attrstatres(struct svc_rqst *, __be32 *);
+diff --git a/fs/nfsd/xdr3.h b/fs/nfsd/xdr3.h
+index 60a8909205e5..ef72bc4868da 100644
+--- a/fs/nfsd/xdr3.h
++++ b/fs/nfsd/xdr3.h
+@@ -265,21 +265,21 @@ union nfsd3_xdrstore {
+
+ #define NFS3_SVC_XDRSIZE sizeof(union nfsd3_xdrstore)
+
+-int nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nfs3svc_decode_commitargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs3svc_decode_commitargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+
+ int nfs3svc_encode_getattrres(struct svc_rqst *, __be32 *);
+ int nfs3svc_encode_wccstat(struct svc_rqst *, __be32 *);
+diff --git a/fs/nfsd/xdr4.h b/fs/nfsd/xdr4.h
+index 1d1b8771bdcf..8812256cd520 100644
+--- a/fs/nfsd/xdr4.h
++++ b/fs/nfsd/xdr4.h
+@@ -756,7 +756,7 @@ set_change_info(struct nfsd4_change_info *cinfo, struct svc_fh *fhp)
+
+
+ bool nfsd4_mach_creds_match(struct nfs4_client *cl, struct svc_rqst *rqstp);
+-int nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+ int nfs4svc_encode_compoundres(struct svc_rqst *, __be32 *);
+ __be32 nfsd4_check_resp_size(struct nfsd4_compoundres *, u32);
+ void nfsd4_encode_operation(struct nfsd4_compoundres *, struct nfsd4_op *);
+diff --git a/include/linux/lockd/xdr.h b/include/linux/lockd/xdr.h
+index 931bd0b064e6..a3d0bc4fd210 100644
+--- a/include/linux/lockd/xdr.h
++++ b/include/linux/lockd/xdr.h
+@@ -98,15 +98,15 @@ struct nlm_reboot {
+ */
+ #define NLMSVC_XDRSIZE sizeof(struct nlm_args)
+
+-int nlmsvc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlmsvc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlmsvc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+
+ int nlmsvc_encode_testres(struct svc_rqst *, __be32 *);
+ int nlmsvc_encode_res(struct svc_rqst *, __be32 *);
+diff --git a/include/linux/lockd/xdr4.h b/include/linux/lockd/xdr4.h
+index 68e14e0f2b1f..376b8f6a3763 100644
+--- a/include/linux/lockd/xdr4.h
++++ b/include/linux/lockd/xdr4.h
+@@ -22,15 +22,15 @@
+ #define nlm4_fbig cpu_to_be32(NLM_FBIG)
+ #define nlm4_failed cpu_to_be32(NLM_FAILED)
+
+-int nlm4svc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+-int nlm4svc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++bool nlm4svc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+
+ int nlm4svc_encode_testres(struct svc_rqst *, __be32 *);
+ int nlm4svc_encode_res(struct svc_rqst *, __be32 *);
+diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
+index 4eaad981a89f..56a4e6b2de7e 100644
+--- a/include/linux/sunrpc/svc.h
++++ b/include/linux/sunrpc/svc.h
+@@ -458,7 +458,7 @@ struct svc_procedure {
+ /* process the request: */
+ __be32 (*pc_func)(struct svc_rqst *);
+ /* XDR decode args: */
+- int (*pc_decode)(struct svc_rqst *rqstp,
++ bool (*pc_decode)(struct svc_rqst *rqstp,
+ struct xdr_stream *xdr);
+ /* XDR encode result: */
+ int (*pc_encode)(struct svc_rqst *, __be32 *data);
+--
+2.35.1
+
--- /dev/null
+From b5a535d6ab638ff6fc6b8cb674301d5e50defdcc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 15:09:53 -0400
+Subject: SUNRPC: Fix svcxdr_init_decode's end-of-buffer calculation
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit 90bfc37b5ab91c1a6165e3e5cfc49bf04571b762 ]
+
+Ensure that stream-based argument decoding can't go past the actual
+end of the receive buffer. xdr_init_decode's calculation of the
+value of xdr->end over-estimates the end of the buffer because the
+Linux kernel RPC server code does not remove the size of the RPC
+header from rqstp->rq_arg before calling the upper layer's
+dispatcher.
+
+The server-side still uses the svc_getnl() macros to decode the
+RPC call header. These macros reduce the length of the head iov
+but do not update the total length of the message in the buffer
+(buf->len).
+
+A proper fix for this would be to replace the use of svc_getnl() and
+friends in the RPC header decoder, but that would be a large and
+invasive change that would be difficult to backport.
+
+Fixes: 5191955d6fc6 ("SUNRPC: Prepare for xdr_stream-style decoding on the server-side")
+Reviewed-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/sunrpc/svc.h | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
+index 01f09adccc63..6be55d0e73fd 100644
+--- a/include/linux/sunrpc/svc.h
++++ b/include/linux/sunrpc/svc.h
+@@ -566,16 +566,27 @@ static inline void svc_reserve_auth(struct svc_rqst *rqstp, int space)
+ }
+
+ /**
+- * svcxdr_init_decode - Prepare an xdr_stream for svc Call decoding
++ * svcxdr_init_decode - Prepare an xdr_stream for Call decoding
+ * @rqstp: controlling server RPC transaction context
+ *
++ * This function currently assumes the RPC header in rq_arg has
++ * already been decoded. Upon return, xdr->p points to the
++ * location of the upper layer header.
+ */
+ static inline void svcxdr_init_decode(struct svc_rqst *rqstp)
+ {
+ struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+- struct kvec *argv = rqstp->rq_arg.head;
++ struct xdr_buf *buf = &rqstp->rq_arg;
++ struct kvec *argv = buf->head;
+
+- xdr_init_decode(xdr, &rqstp->rq_arg, argv->iov_base, NULL);
++ /*
++ * svc_getnl() and friends do not keep the xdr_buf's ::len
++ * field up to date. Refresh that field before initializing
++ * the argument decoding stream.
++ */
++ buf->len = buf->head->iov_len + buf->page_len + buf->tail->iov_len;
++
++ xdr_init_decode(xdr, buf, argv->iov_base, NULL);
+ xdr_set_scratch_page(xdr, rqstp->rq_scratch_page);
+ }
+
+--
+2.35.1
+
--- /dev/null
+From c001d6331baa0bef0d35e79301df8053e62743cb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 15:09:59 -0400
+Subject: SUNRPC: Fix svcxdr_init_encode's buflen calculation
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit 1242a87da0d8cd2a428e96ca68e7ea899b0f4624 ]
+
+Commit 2825a7f90753 ("nfsd4: allow encoding across page boundaries")
+added an explicit computation of the remaining length in the rq_res
+XDR buffer.
+
+The computation appears to suffer from an "off-by-one" bug. Because
+buflen is too large by one page, XDR encoding can run off the end of
+the send buffer by eventually trying to use the struct page address
+in rq_page_end, which always contains NULL.
+
+Fixes: bddfdbcddbe2 ("NFSD: Extract the svcxdr_init_encode() helper")
+Reviewed-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/sunrpc/svc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
+index 6be55d0e73fd..045f34add206 100644
+--- a/include/linux/sunrpc/svc.h
++++ b/include/linux/sunrpc/svc.h
+@@ -609,7 +609,7 @@ static inline void svcxdr_init_encode(struct svc_rqst *rqstp)
+ xdr->end = resv->iov_base + PAGE_SIZE - rqstp->rq_auth_slack;
+ buf->len = resv->iov_len;
+ xdr->page_ptr = buf->pages - 1;
+- buf->buflen = PAGE_SIZE * (1 + rqstp->rq_page_end - buf->pages);
++ buf->buflen = PAGE_SIZE * (rqstp->rq_page_end - buf->pages);
+ buf->buflen -= rqstp->rq_auth_slack;
+ xdr->rqst = NULL;
+ }
+--
+2.35.1
+
--- /dev/null
+From d42246ab2d8bc058fba38276edb80a021d57f8ce Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Oct 2021 11:57:22 -0400
+Subject: SUNRPC: Replace the "__be32 *p" parameter to .pc_decode
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+[ Upstream commit 16c663642c7ec03cd4cee5fec520bb69e97babe4 ]
+
+The passed-in value of the "__be32 *p" parameter is now unused in
+every server-side XDR decoder, and can be removed.
+
+Note also that there is a line in each decoder that sets up a local
+pointer to a struct xdr_stream. Passing that pointer from the
+dispatcher instead saves one line per decoder function.
+
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: J. Bruce Fields <bfields@redhat.com>
+Stable-dep-of: 7518a3dc5ea2 ("NFSD: Fix handling of oversized NFSv4 COMPOUND requests")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/lockd/svc.c | 3 +--
+ fs/lockd/xdr.c | 27 +++++++++--------------
+ fs/lockd/xdr4.c | 27 +++++++++--------------
+ fs/nfsd/nfs2acl.c | 12 +++++-----
+ fs/nfsd/nfs3acl.c | 8 +++----
+ fs/nfsd/nfs3xdr.c | 45 +++++++++++++-------------------------
+ fs/nfsd/nfs4xdr.c | 4 ++--
+ fs/nfsd/nfsd.h | 3 ++-
+ fs/nfsd/nfssvc.c | 7 +++---
+ fs/nfsd/nfsxdr.c | 30 +++++++++----------------
+ fs/nfsd/xdr.h | 21 +++++++++---------
+ fs/nfsd/xdr3.h | 31 +++++++++++++-------------
+ fs/nfsd/xdr4.h | 2 +-
+ include/linux/lockd/xdr.h | 19 ++++++++--------
+ include/linux/lockd/xdr4.h | 19 ++++++++--------
+ include/linux/sunrpc/svc.h | 3 ++-
+ 16 files changed, 112 insertions(+), 149 deletions(-)
+
+diff --git a/fs/lockd/svc.c b/fs/lockd/svc.c
+index b632be3ad57b..9a82471bda07 100644
+--- a/fs/lockd/svc.c
++++ b/fs/lockd/svc.c
+@@ -780,11 +780,10 @@ module_exit(exit_nlm);
+ static int nlmsvc_dispatch(struct svc_rqst *rqstp, __be32 *statp)
+ {
+ const struct svc_procedure *procp = rqstp->rq_procinfo;
+- struct kvec *argv = rqstp->rq_arg.head;
+ struct kvec *resv = rqstp->rq_res.head;
+
+ svcxdr_init_decode(rqstp);
+- if (!procp->pc_decode(rqstp, argv->iov_base))
++ if (!procp->pc_decode(rqstp, &rqstp->rq_arg_stream))
+ goto out_decode_err;
+
+ *statp = procp->pc_func(rqstp);
+diff --git a/fs/lockd/xdr.c b/fs/lockd/xdr.c
+index 9235e60b1769..895f15222104 100644
+--- a/fs/lockd/xdr.c
++++ b/fs/lockd/xdr.c
+@@ -146,15 +146,14 @@ svcxdr_encode_testrply(struct xdr_stream *xdr, const struct nlm_res *resp)
+ */
+
+ int
+-nlmsvc_decode_void(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ return 1;
+ }
+
+ int
+-nlmsvc_decode_testargs(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -171,9 +170,8 @@ nlmsvc_decode_testargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_lockargs(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -197,9 +195,8 @@ nlmsvc_decode_lockargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_cancargs(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -218,9 +215,8 @@ nlmsvc_decode_cancargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+@@ -233,9 +229,8 @@ nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_res(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_res *resp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &resp->cookie))
+@@ -247,10 +242,10 @@ nlmsvc_decode_res(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_reboot(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_reboot *argp = rqstp->rq_argp;
++ __be32 *p;
+ u32 len;
+
+ if (xdr_stream_decode_u32(xdr, &len) < 0)
+@@ -273,9 +268,8 @@ nlmsvc_decode_reboot(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_shareargs(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+@@ -301,9 +295,8 @@ nlmsvc_decode_shareargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlmsvc_decode_notify(struct svc_rqst *rqstp, __be32 *p)
++nlmsvc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+diff --git a/fs/lockd/xdr4.c b/fs/lockd/xdr4.c
+index 72f7d190fb3b..05f203f622d8 100644
+--- a/fs/lockd/xdr4.c
++++ b/fs/lockd/xdr4.c
+@@ -130,15 +130,14 @@ svcxdr_encode_testrply(struct xdr_stream *xdr, const struct nlm_res *resp)
+ */
+
+ int
+-nlm4svc_decode_void(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ return 1;
+ }
+
+ int
+-nlm4svc_decode_testargs(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -155,9 +154,8 @@ nlm4svc_decode_testargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_lockargs(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -181,9 +179,8 @@ nlm4svc_decode_lockargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_cancargs(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ u32 exclusive;
+
+@@ -201,9 +198,8 @@ nlm4svc_decode_cancargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &argp->cookie))
+@@ -216,9 +212,8 @@ nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_res(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_res *resp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_cookie(xdr, &resp->cookie))
+@@ -230,10 +225,10 @@ nlm4svc_decode_res(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_reboot(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_reboot *argp = rqstp->rq_argp;
++ __be32 *p;
+ u32 len;
+
+ if (xdr_stream_decode_u32(xdr, &len) < 0)
+@@ -256,9 +251,8 @@ nlm4svc_decode_reboot(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_shareargs(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+@@ -284,9 +278,8 @@ nlm4svc_decode_shareargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nlm4svc_decode_notify(struct svc_rqst *rqstp, __be32 *p)
++nlm4svc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nlm_args *argp = rqstp->rq_argp;
+ struct nlm_lock *lock = &argp->lock;
+
+diff --git a/fs/nfsd/nfs2acl.c b/fs/nfsd/nfs2acl.c
+index 4b43929c1f25..0069c0fdb94f 100644
+--- a/fs/nfsd/nfs2acl.c
++++ b/fs/nfsd/nfs2acl.c
+@@ -188,9 +188,9 @@ static __be32 nfsacld_proc_access(struct svc_rqst *rqstp)
+ * XDR decode functions
+ */
+
+-static int nfsaclsvc_decode_getaclargs(struct svc_rqst *rqstp, __be32 *p)
++static int
++nfsaclsvc_decode_getaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_getaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &argp->fh))
+@@ -201,9 +201,9 @@ static int nfsaclsvc_decode_getaclargs(struct svc_rqst *rqstp, __be32 *p)
+ return 1;
+ }
+
+-static int nfsaclsvc_decode_setaclargs(struct svc_rqst *rqstp, __be32 *p)
++static int
++nfsaclsvc_decode_setaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_setaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &argp->fh))
+@@ -222,9 +222,9 @@ static int nfsaclsvc_decode_setaclargs(struct svc_rqst *rqstp, __be32 *p)
+ return 1;
+ }
+
+-static int nfsaclsvc_decode_accessargs(struct svc_rqst *rqstp, __be32 *p)
++static int
++nfsaclsvc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_accessargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+diff --git a/fs/nfsd/nfs3acl.c b/fs/nfsd/nfs3acl.c
+index 5dfe7644a517..b1e352ed2436 100644
+--- a/fs/nfsd/nfs3acl.c
++++ b/fs/nfsd/nfs3acl.c
+@@ -127,9 +127,9 @@ static __be32 nfsd3_proc_setacl(struct svc_rqst *rqstp)
+ * XDR decode functions
+ */
+
+-static int nfs3svc_decode_getaclargs(struct svc_rqst *rqstp, __be32 *p)
++static int
++nfs3svc_decode_getaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_getaclargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+@@ -140,9 +140,9 @@ static int nfs3svc_decode_getaclargs(struct svc_rqst *rqstp, __be32 *p)
+ return 1;
+ }
+
+-static int nfs3svc_decode_setaclargs(struct svc_rqst *rqstp, __be32 *p)
++static int
++nfs3svc_decode_setaclargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_setaclargs *argp = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &argp->fh))
+diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c
+index 48d4f99b7f90..4ce0cdb3751d 100644
+--- a/fs/nfsd/nfs3xdr.c
++++ b/fs/nfsd/nfs3xdr.c
+@@ -547,18 +547,16 @@ void fill_post_wcc(struct svc_fh *fhp)
+ */
+
+ int
+-nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_fhandle *args = rqstp->rq_argp;
+
+ return svcxdr_decode_nfs_fh3(xdr, &args->fh);
+ }
+
+ int
+-nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_sattrargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_nfs_fh3(xdr, &args->fh) &&
+@@ -567,18 +565,16 @@ nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_diropargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_diropargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len);
+ }
+
+ int
+-nfs3svc_decode_accessargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_accessargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+@@ -590,9 +586,8 @@ nfs3svc_decode_accessargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_readargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_readargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+@@ -606,9 +601,8 @@ nfs3svc_decode_readargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_writeargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_writeargs *args = rqstp->rq_argp;
+ u32 max_blocksize = svc_max_payload(rqstp);
+
+@@ -639,9 +633,8 @@ nfs3svc_decode_writeargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_createargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_createargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len))
+@@ -664,9 +657,8 @@ nfs3svc_decode_createargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_createargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs3(xdr, &args->fh,
+@@ -675,9 +667,8 @@ nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_symlinkargs *args = rqstp->rq_argp;
+ struct kvec *head = rqstp->rq_arg.head;
+ struct kvec *tail = rqstp->rq_arg.tail;
+@@ -703,9 +694,8 @@ nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_mknodargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_diropargs3(xdr, &args->fh, &args->name, &args->len))
+@@ -732,9 +722,8 @@ nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_renameargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_renameargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs3(xdr, &args->ffh,
+@@ -744,9 +733,8 @@ nfs3svc_decode_renameargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_linkargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_linkargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_nfs_fh3(xdr, &args->ffh) &&
+@@ -755,9 +743,8 @@ nfs3svc_decode_linkargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_readdirargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+@@ -774,9 +761,8 @@ nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_readdirargs *args = rqstp->rq_argp;
+ u32 dircount;
+
+@@ -797,9 +783,8 @@ nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfs3svc_decode_commitargs(struct svc_rqst *rqstp, __be32 *p)
++nfs3svc_decode_commitargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd3_commitargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_nfs_fh3(xdr, &args->fh))
+diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
+index f6d385e0efec..3a2a73a85032 100644
+--- a/fs/nfsd/nfs4xdr.c
++++ b/fs/nfsd/nfs4xdr.c
+@@ -5408,14 +5408,14 @@ void nfsd4_release_compoundargs(struct svc_rqst *rqstp)
+ }
+
+ int
+-nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, __be32 *p)
++nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ struct nfsd4_compoundargs *args = rqstp->rq_argp;
+
+ /* svcxdr_tmp_alloc */
+ args->to_free = NULL;
+
+- args->xdr = &rqstp->rq_arg_stream;
++ args->xdr = xdr;
+ args->ops = args->iops;
+ args->rqstp = rqstp;
+
+diff --git a/fs/nfsd/nfsd.h b/fs/nfsd/nfsd.h
+index 9664303afdaf..6e8ad5f9757c 100644
+--- a/fs/nfsd/nfsd.h
++++ b/fs/nfsd/nfsd.h
+@@ -78,7 +78,8 @@ extern const struct seq_operations nfs_exports_op;
+ */
+ struct nfsd_voidargs { };
+ struct nfsd_voidres { };
+-int nfssvc_decode_voidarg(struct svc_rqst *rqstp, __be32 *p);
++int nfssvc_decode_voidarg(struct svc_rqst *rqstp,
++ struct xdr_stream *xdr);
+ int nfssvc_encode_voidres(struct svc_rqst *rqstp, __be32 *p);
+
+ /*
+diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c
+index ccb59e91011b..7cd13e9474ff 100644
+--- a/fs/nfsd/nfssvc.c
++++ b/fs/nfsd/nfssvc.c
+@@ -1004,7 +1004,6 @@ nfsd(void *vrqstp)
+ int nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp)
+ {
+ const struct svc_procedure *proc = rqstp->rq_procinfo;
+- struct kvec *argv = &rqstp->rq_arg.head[0];
+ struct kvec *resv = &rqstp->rq_res.head[0];
+ __be32 *p;
+
+@@ -1015,7 +1014,7 @@ int nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp)
+ rqstp->rq_cachetype = proc->pc_cachetype;
+
+ svcxdr_init_decode(rqstp);
+- if (!proc->pc_decode(rqstp, argv->iov_base))
++ if (!proc->pc_decode(rqstp, &rqstp->rq_arg_stream))
+ goto out_decode_err;
+
+ switch (nfsd_cache_lookup(rqstp)) {
+@@ -1065,13 +1064,13 @@ int nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp)
+ /**
+ * nfssvc_decode_voidarg - Decode void arguments
+ * @rqstp: Server RPC transaction context
+- * @p: buffer containing arguments to decode
++ * @xdr: XDR stream positioned at arguments to decode
+ *
+ * Return values:
+ * %0: Arguments were not valid
+ * %1: Decoding was successful
+ */
+-int nfssvc_decode_voidarg(struct svc_rqst *rqstp, __be32 *p)
++int nfssvc_decode_voidarg(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+ return 1;
+ }
+diff --git a/fs/nfsd/nfsxdr.c b/fs/nfsd/nfsxdr.c
+index 26a42f87c240..38c4b199a10f 100644
+--- a/fs/nfsd/nfsxdr.c
++++ b/fs/nfsd/nfsxdr.c
+@@ -273,18 +273,16 @@ svcxdr_encode_fattr(struct svc_rqst *rqstp, struct xdr_stream *xdr,
+ */
+
+ int
+-nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_fhandle *args = rqstp->rq_argp;
+
+ return svcxdr_decode_fhandle(xdr, &args->fh);
+ }
+
+ int
+-nfssvc_decode_sattrargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_sattrargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_fhandle(xdr, &args->fh) &&
+@@ -292,18 +290,16 @@ nfssvc_decode_sattrargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_diropargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_diropargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs(xdr, &args->fh, &args->name, &args->len);
+ }
+
+ int
+-nfssvc_decode_readargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_readargs *args = rqstp->rq_argp;
+ u32 totalcount;
+
+@@ -321,9 +317,8 @@ nfssvc_decode_readargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_writeargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_writeargs *args = rqstp->rq_argp;
+ u32 beginoffset, totalcount;
+
+@@ -350,9 +345,8 @@ nfssvc_decode_writeargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_createargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_createargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs(xdr, &args->fh,
+@@ -361,9 +355,8 @@ nfssvc_decode_createargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_renameargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_renameargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_diropargs(xdr, &args->ffh,
+@@ -373,9 +366,8 @@ nfssvc_decode_renameargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_linkargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_linkargs *args = rqstp->rq_argp;
+
+ return svcxdr_decode_fhandle(xdr, &args->ffh) &&
+@@ -384,9 +376,8 @@ nfssvc_decode_linkargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_symlinkargs *args = rqstp->rq_argp;
+ struct kvec *head = rqstp->rq_arg.head;
+
+@@ -405,9 +396,8 @@ nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, __be32 *p)
+ }
+
+ int
+-nfssvc_decode_readdirargs(struct svc_rqst *rqstp, __be32 *p)
++nfssvc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr)
+ {
+- struct xdr_stream *xdr = &rqstp->rq_arg_stream;
+ struct nfsd_readdirargs *args = rqstp->rq_argp;
+
+ if (!svcxdr_decode_fhandle(xdr, &args->fh))
+diff --git a/fs/nfsd/xdr.h b/fs/nfsd/xdr.h
+index 863a35f24910..19e281382bb9 100644
+--- a/fs/nfsd/xdr.h
++++ b/fs/nfsd/xdr.h
+@@ -141,16 +141,17 @@ union nfsd_xdrstore {
+ #define NFS2_SVC_XDRSIZE sizeof(union nfsd_xdrstore)
+
+
+-int nfssvc_decode_fhandleargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_sattrargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_diropargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_readargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_writeargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_createargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_renameargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_linkargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_symlinkargs(struct svc_rqst *, __be32 *);
+-int nfssvc_decode_readdirargs(struct svc_rqst *, __be32 *);
++int nfssvc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfssvc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++
+ int nfssvc_encode_statres(struct svc_rqst *, __be32 *);
+ int nfssvc_encode_attrstatres(struct svc_rqst *, __be32 *);
+ int nfssvc_encode_diropres(struct svc_rqst *, __be32 *);
+diff --git a/fs/nfsd/xdr3.h b/fs/nfsd/xdr3.h
+index 712c117300cb..60a8909205e5 100644
+--- a/fs/nfsd/xdr3.h
++++ b/fs/nfsd/xdr3.h
+@@ -265,21 +265,22 @@ union nfsd3_xdrstore {
+
+ #define NFS3_SVC_XDRSIZE sizeof(union nfsd3_xdrstore)
+
+-int nfs3svc_decode_fhandleargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_sattrargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_diropargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_accessargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_readargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_writeargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_createargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_mkdirargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_mknodargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_renameargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_linkargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_symlinkargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_readdirargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_readdirplusargs(struct svc_rqst *, __be32 *);
+-int nfs3svc_decode_commitargs(struct svc_rqst *, __be32 *);
++int nfs3svc_decode_fhandleargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_sattrargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_diropargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_accessargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_readargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_writeargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_createargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_mkdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_mknodargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_renameargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_linkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_symlinkargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_readdirargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_readdirplusargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nfs3svc_decode_commitargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++
+ int nfs3svc_encode_getattrres(struct svc_rqst *, __be32 *);
+ int nfs3svc_encode_wccstat(struct svc_rqst *, __be32 *);
+ int nfs3svc_encode_lookupres(struct svc_rqst *, __be32 *);
+diff --git a/fs/nfsd/xdr4.h b/fs/nfsd/xdr4.h
+index 3e4052e3bd50..1d1b8771bdcf 100644
+--- a/fs/nfsd/xdr4.h
++++ b/fs/nfsd/xdr4.h
+@@ -756,7 +756,7 @@ set_change_info(struct nfsd4_change_info *cinfo, struct svc_fh *fhp)
+
+
+ bool nfsd4_mach_creds_match(struct nfs4_client *cl, struct svc_rqst *rqstp);
+-int nfs4svc_decode_compoundargs(struct svc_rqst *, __be32 *);
++int nfs4svc_decode_compoundargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+ int nfs4svc_encode_compoundres(struct svc_rqst *, __be32 *);
+ __be32 nfsd4_check_resp_size(struct nfsd4_compoundres *, u32);
+ void nfsd4_encode_operation(struct nfsd4_compoundres *, struct nfsd4_op *);
+diff --git a/include/linux/lockd/xdr.h b/include/linux/lockd/xdr.h
+index bed63156b052..931bd0b064e6 100644
+--- a/include/linux/lockd/xdr.h
++++ b/include/linux/lockd/xdr.h
+@@ -98,18 +98,19 @@ struct nlm_reboot {
+ */
+ #define NLMSVC_XDRSIZE sizeof(struct nlm_args)
+
+-int nlmsvc_decode_testargs(struct svc_rqst *, __be32 *);
++int nlmsvc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlmsvc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++
+ int nlmsvc_encode_testres(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_lockargs(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_cancargs(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_unlockargs(struct svc_rqst *, __be32 *);
+ int nlmsvc_encode_res(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_res(struct svc_rqst *, __be32 *);
+ int nlmsvc_encode_void(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_void(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_shareargs(struct svc_rqst *, __be32 *);
+ int nlmsvc_encode_shareres(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_notify(struct svc_rqst *, __be32 *);
+-int nlmsvc_decode_reboot(struct svc_rqst *, __be32 *);
+
+ #endif /* LOCKD_XDR_H */
+diff --git a/include/linux/lockd/xdr4.h b/include/linux/lockd/xdr4.h
+index 5ae766f26e04..68e14e0f2b1f 100644
+--- a/include/linux/lockd/xdr4.h
++++ b/include/linux/lockd/xdr4.h
+@@ -22,21 +22,20 @@
+ #define nlm4_fbig cpu_to_be32(NLM_FBIG)
+ #define nlm4_failed cpu_to_be32(NLM_FAILED)
+
++int nlm4svc_decode_void(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_testargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_lockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_cancargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_unlockargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_res(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_reboot(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_shareargs(struct svc_rqst *rqstp, struct xdr_stream *xdr);
++int nlm4svc_decode_notify(struct svc_rqst *rqstp, struct xdr_stream *xdr);
+
+-
+-int nlm4svc_decode_testargs(struct svc_rqst *, __be32 *);
+ int nlm4svc_encode_testres(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_lockargs(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_cancargs(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_unlockargs(struct svc_rqst *, __be32 *);
+ int nlm4svc_encode_res(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_res(struct svc_rqst *, __be32 *);
+ int nlm4svc_encode_void(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_void(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_shareargs(struct svc_rqst *, __be32 *);
+ int nlm4svc_encode_shareres(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_notify(struct svc_rqst *, __be32 *);
+-int nlm4svc_decode_reboot(struct svc_rqst *, __be32 *);
+
+ extern const struct rpc_version nlm_version4;
+
+diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
+index 045f34add206..4eaad981a89f 100644
+--- a/include/linux/sunrpc/svc.h
++++ b/include/linux/sunrpc/svc.h
+@@ -458,7 +458,8 @@ struct svc_procedure {
+ /* process the request: */
+ __be32 (*pc_func)(struct svc_rqst *);
+ /* XDR decode args: */
+- int (*pc_decode)(struct svc_rqst *, __be32 *data);
++ int (*pc_decode)(struct svc_rqst *rqstp,
++ struct xdr_stream *xdr);
+ /* XDR encode result: */
+ int (*pc_encode)(struct svc_rqst *, __be32 *data);
+ /* XDR free result: */
+--
+2.35.1
+
--- /dev/null
+From 5a22eb2129e55a9e43d45904cfcb4b7b7c109369 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 22 Aug 2022 21:15:28 +0000
+Subject: tcp: annotate data-race around tcp_md5sig_pool_populated
+
+From: Eric Dumazet <edumazet@google.com>
+
+[ Upstream commit aacd467c0a576e5e44d2de4205855dc0fe43f6fb ]
+
+tcp_md5sig_pool_populated can be read while another thread
+changes its value.
+
+The race has no consequence because allocations
+are protected with tcp_md5sig_mutex.
+
+This patch adds READ_ONCE() and WRITE_ONCE() to document
+the race and silence KCSAN.
+
+Reported-by: Abhishek Shah <abhishek.shah@columbia.edu>
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/ipv4/tcp.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+index b604c7664350..5b4e170b6a34 100644
+--- a/net/ipv4/tcp.c
++++ b/net/ipv4/tcp.c
+@@ -4331,12 +4331,16 @@ static void __tcp_alloc_md5sig_pool(void)
+ * to memory. See smp_rmb() in tcp_get_md5sig_pool()
+ */
+ smp_wmb();
+- tcp_md5sig_pool_populated = true;
++ /* Paired with READ_ONCE() from tcp_alloc_md5sig_pool()
++ * and tcp_get_md5sig_pool().
++ */
++ WRITE_ONCE(tcp_md5sig_pool_populated, true);
+ }
+
+ bool tcp_alloc_md5sig_pool(void)
+ {
+- if (unlikely(!tcp_md5sig_pool_populated)) {
++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */
++ if (unlikely(!READ_ONCE(tcp_md5sig_pool_populated))) {
+ mutex_lock(&tcp_md5sig_mutex);
+
+ if (!tcp_md5sig_pool_populated) {
+@@ -4347,7 +4351,8 @@ bool tcp_alloc_md5sig_pool(void)
+
+ mutex_unlock(&tcp_md5sig_mutex);
+ }
+- return tcp_md5sig_pool_populated;
++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */
++ return READ_ONCE(tcp_md5sig_pool_populated);
+ }
+ EXPORT_SYMBOL(tcp_alloc_md5sig_pool);
+
+@@ -4363,7 +4368,8 @@ struct tcp_md5sig_pool *tcp_get_md5sig_pool(void)
+ {
+ local_bh_disable();
+
+- if (tcp_md5sig_pool_populated) {
++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */
++ if (READ_ONCE(tcp_md5sig_pool_populated)) {
+ /* coupled with smp_wmb() in __tcp_alloc_md5sig_pool() */
+ smp_rmb();
+ return this_cpu_ptr(&tcp_md5sig_pool);
+--
+2.35.1
+
--- /dev/null
+From cc267cb820e6df8649e814cf096344eab668007f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 16:03:31 -0400
+Subject: tcp: fix tcp_cwnd_validate() to not forget is_cwnd_limited
+
+From: Neal Cardwell <ncardwell@google.com>
+
+[ Upstream commit f4ce91ce12a7c6ead19b128ffa8cff6e3ded2a14 ]
+
+This commit fixes a bug in the tracking of max_packets_out and
+is_cwnd_limited. This bug can cause the connection to fail to remember
+that is_cwnd_limited is true, causing the connection to fail to grow
+cwnd when it should, causing throughput to be lower than it should be.
+
+The following event sequence is an example that triggers the bug:
+
+ (a) The connection is cwnd_limited, but packets_out is not at its
+ peak due to TSO deferral deciding not to send another skb yet.
+ In such cases the connection can advance max_packets_seq and set
+ tp->is_cwnd_limited to true and max_packets_out to a small
+ number.
+
+(b) Then later in the round trip the connection is pacing-limited (not
+ cwnd-limited), and packets_out is larger. In such cases the
+ connection would raise max_packets_out to a bigger number but
+ (unexpectedly) flip tp->is_cwnd_limited from true to false.
+
+This commit fixes that bug.
+
+One straightforward fix would be to separately track (a) the next
+window after max_packets_out reaches a maximum, and (b) the next
+window after tp->is_cwnd_limited is set to true. But this would
+require consuming an extra u32 sequence number.
+
+Instead, to save space we track only the most important
+information. Specifically, we track the strongest available signal of
+the degree to which the cwnd is fully utilized:
+
+(1) If the connection is cwnd-limited then we remember that fact for
+the current window.
+
+(2) If the connection not cwnd-limited then we track the maximum
+number of outstanding packets in the current window.
+
+In particular, note that the new logic cannot trigger the buggy
+(a)/(b) sequence above because with the new logic a condition where
+tp->packets_out > tp->max_packets_out can only trigger an update of
+tp->is_cwnd_limited if tp->is_cwnd_limited is false.
+
+This first showed up in a testing of a BBRv2 dev branch, but this
+buggy behavior highlighted a general issue with the
+tcp_cwnd_validate() logic that can cause cwnd to fail to increase at
+the proper rate for any TCP congestion control, including Reno or
+CUBIC.
+
+Fixes: ca8a22634381 ("tcp: make cwnd-limited checks measurement-based, and gentler")
+Signed-off-by: Neal Cardwell <ncardwell@google.com>
+Signed-off-by: Kevin(Yudong) Yang <yyd@google.com>
+Signed-off-by: Yuchung Cheng <ycheng@google.com>
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/tcp.h | 2 +-
+ include/net/tcp.h | 5 ++++-
+ net/ipv4/tcp.c | 2 ++
+ net/ipv4/tcp_output.c | 19 ++++++++++++-------
+ 4 files changed, 19 insertions(+), 9 deletions(-)
+
+diff --git a/include/linux/tcp.h b/include/linux/tcp.h
+index 48d8a363319e..a7ebadf83c68 100644
+--- a/include/linux/tcp.h
++++ b/include/linux/tcp.h
+@@ -265,7 +265,7 @@ struct tcp_sock {
+ u32 packets_out; /* Packets which are "in flight" */
+ u32 retrans_out; /* Retransmitted packets out */
+ u32 max_packets_out; /* max packets_out in last window */
+- u32 max_packets_seq; /* right edge of max_packets_out flight */
++ u32 cwnd_usage_seq; /* right edge of cwnd usage tracking flight */
+
+ u16 urg_data; /* Saved octet of OOB data and control flags */
+ u8 ecn_flags; /* ECN status bits. */
+diff --git a/include/net/tcp.h b/include/net/tcp.h
+index d3646645cb9e..d2de3b7788a9 100644
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -1281,11 +1281,14 @@ static inline bool tcp_is_cwnd_limited(const struct sock *sk)
+ {
+ const struct tcp_sock *tp = tcp_sk(sk);
+
++ if (tp->is_cwnd_limited)
++ return true;
++
+ /* If in slow start, ensure cwnd grows to twice what was ACKed. */
+ if (tcp_in_slow_start(tp))
+ return tcp_snd_cwnd(tp) < 2 * tp->max_packets_out;
+
+- return tp->is_cwnd_limited;
++ return false;
+ }
+
+ /* BBR congestion control needs pacing.
+diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+index 4f6b897ccf23..b604c7664350 100644
+--- a/net/ipv4/tcp.c
++++ b/net/ipv4/tcp.c
+@@ -3025,6 +3025,8 @@ int tcp_disconnect(struct sock *sk, int flags)
+ tp->snd_ssthresh = TCP_INFINITE_SSTHRESH;
+ tcp_snd_cwnd_set(tp, TCP_INIT_CWND);
+ tp->snd_cwnd_cnt = 0;
++ tp->is_cwnd_limited = 0;
++ tp->max_packets_out = 0;
+ tp->window_clamp = 0;
+ tp->delivered = 0;
+ tp->delivered_ce = 0;
+diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
+index ed2e1836c0c0..33ba1268a111 100644
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -1878,15 +1878,20 @@ static void tcp_cwnd_validate(struct sock *sk, bool is_cwnd_limited)
+ const struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops;
+ struct tcp_sock *tp = tcp_sk(sk);
+
+- /* Track the maximum number of outstanding packets in each
+- * window, and remember whether we were cwnd-limited then.
++ /* Track the strongest available signal of the degree to which the cwnd
++ * is fully utilized. If cwnd-limited then remember that fact for the
++ * current window. If not cwnd-limited then track the maximum number of
++ * outstanding packets in the current window. (If cwnd-limited then we
++ * chose to not update tp->max_packets_out to avoid an extra else
++ * clause with no functional impact.)
+ */
+- if (!before(tp->snd_una, tp->max_packets_seq) ||
+- tp->packets_out > tp->max_packets_out ||
+- is_cwnd_limited) {
+- tp->max_packets_out = tp->packets_out;
+- tp->max_packets_seq = tp->snd_nxt;
++ if (!before(tp->snd_una, tp->cwnd_usage_seq) ||
++ is_cwnd_limited ||
++ (!tp->is_cwnd_limited &&
++ tp->packets_out > tp->max_packets_out)) {
+ tp->is_cwnd_limited = is_cwnd_limited;
++ tp->max_packets_out = tp->packets_out;
++ tp->cwnd_usage_seq = tp->snd_nxt;
+ }
+
+ if (tcp_is_cwnd_limited(sk)) {
+--
+2.35.1
+
--- /dev/null
+From fb1766e9613c957ac9c8a724748981a1da77fd15 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 25 Aug 2022 19:40:17 +0800
+Subject: thermal: cpufreq_cooling: Check the policy first in
+ cpufreq_cooling_register()
+
+From: Xuewen Yan <xuewen.yan@unisoc.com>
+
+[ Upstream commit cff895277c8558221ba180aefe26799dcb4eec86 ]
+
+Since the policy needs to be accessed first when obtaining cpu devices,
+first check whether the policy is legal before this.
+
+Fixes: 5130802ddbb1 ("thermal: cpu_cooling: Switch to QoS requests for freq limits")
+Signed-off-by: Xuewen Yan <xuewen.yan@unisoc.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/thermal/cpufreq_cooling.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/thermal/cpufreq_cooling.c b/drivers/thermal/cpufreq_cooling.c
+index 43b1ae8a7789..12a60415af95 100644
+--- a/drivers/thermal/cpufreq_cooling.c
++++ b/drivers/thermal/cpufreq_cooling.c
+@@ -525,17 +525,17 @@ __cpufreq_cooling_register(struct device_node *np,
+ struct thermal_cooling_device_ops *cooling_ops;
+ char *name;
+
++ if (IS_ERR_OR_NULL(policy)) {
++ pr_err("%s: cpufreq policy isn't valid: %p\n", __func__, policy);
++ return ERR_PTR(-EINVAL);
++ }
++
+ dev = get_cpu_device(policy->cpu);
+ if (unlikely(!dev)) {
+ pr_warn("No cpu device for cpu %d\n", policy->cpu);
+ return ERR_PTR(-ENODEV);
+ }
+
+- if (IS_ERR_OR_NULL(policy)) {
+- pr_err("%s: cpufreq policy isn't valid: %p\n", __func__, policy);
+- return ERR_PTR(-EINVAL);
+- }
+-
+ i = cpufreq_table_count_valid_entries(policy);
+ if (!i) {
+ pr_debug("%s: CPUFreq table not found or has no valid entries\n",
+--
+2.35.1
+
--- /dev/null
+From 5c0c6cc0f40d3643e27eb1f3b642e69b35470fae Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Aug 2022 12:50:14 +0200
+Subject: thermal/drivers/qcom/tsens-v0_1: Fix MSM8939 fourth sensor hw_id
+
+From: Vincent Knecht <vincent.knecht@mailoo.org>
+
+[ Upstream commit b0c883e900702f408d62cf92b0ef01303ed69be9 ]
+
+Reading temperature from this sensor fails with 'Invalid argument'.
+
+Looking at old vendor dts [1], its hw_id should be 3 instead of 4.
+Change this hw_id accordingly.
+
+[1] https://github.com/msm8916-mainline/android_kernel_qcom_msm8916/blob/master/arch/arm/boot/dts/qcom/msm8939-common.dtsi#L511
+
+Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939")
+Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Bjorn Andersson <andersson@kernel.org>
+Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+Link: https://lore.kernel.org/r/20220811105014.7194-1-vincent.knecht@mailoo.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/thermal/qcom/tsens-v0_1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c
+index f136cb350238..327f37202c69 100644
+--- a/drivers/thermal/qcom/tsens-v0_1.c
++++ b/drivers/thermal/qcom/tsens-v0_1.c
+@@ -604,7 +604,7 @@ static const struct tsens_ops ops_8939 = {
+ struct tsens_plat_data data_8939 = {
+ .num_sensors = 10,
+ .ops = &ops_8939,
+- .hw_ids = (unsigned int []){ 0, 1, 2, 4, 5, 6, 7, 8, 9, 10 },
++ .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 },
+
+ .feat = &tsens_v0_1_feat,
+ .fields = tsens_v0_1_regfields,
+--
+2.35.1
+
--- /dev/null
+From c7764d02f56f81bbb3fe8a47eb5e5bc643c640b7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 04:06:57 -0700
+Subject: thermal: intel_powerclamp: Use get_cpu() instead of
+ smp_processor_id() to avoid crash
+
+From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+
+[ Upstream commit 68b99e94a4a2db6ba9b31fe0485e057b9354a640 ]
+
+When CPU 0 is offline and intel_powerclamp is used to inject
+idle, it generates kernel BUG:
+
+BUG: using smp_processor_id() in preemptible [00000000] code: bash/15687
+caller is debug_smp_processor_id+0x17/0x20
+CPU: 4 PID: 15687 Comm: bash Not tainted 5.19.0-rc7+ #57
+Call Trace:
+<TASK>
+dump_stack_lvl+0x49/0x63
+dump_stack+0x10/0x16
+check_preemption_disabled+0xdd/0xe0
+debug_smp_processor_id+0x17/0x20
+powerclamp_set_cur_state+0x7f/0xf9 [intel_powerclamp]
+...
+...
+
+Here CPU 0 is the control CPU by default and changed to the current CPU,
+if CPU 0 offlined. This check has to be performed under cpus_read_lock(),
+hence the above warning.
+
+Use get_cpu() instead of smp_processor_id() to avoid this BUG.
+
+Suggested-by: Chen Yu <yu.c.chen@intel.com>
+Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+[ rjw: Subject edits ]
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/thermal/intel/intel_powerclamp.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/thermal/intel/intel_powerclamp.c b/drivers/thermal/intel/intel_powerclamp.c
+index a5b58ea89cc6..9121ae4f5068 100644
+--- a/drivers/thermal/intel/intel_powerclamp.c
++++ b/drivers/thermal/intel/intel_powerclamp.c
+@@ -532,8 +532,10 @@ static int start_power_clamp(void)
+
+ /* prefer BSP */
+ control_cpu = 0;
+- if (!cpu_online(control_cpu))
+- control_cpu = smp_processor_id();
++ if (!cpu_online(control_cpu)) {
++ control_cpu = get_cpu();
++ put_cpu();
++ }
+
+ clamping = true;
+ schedule_delayed_work(&poll_pkg_cstate_work, 0);
+--
+2.35.1
+
--- /dev/null
+From 69376e17fdd2c665b3d89c20df09e1b17de336cf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 18:32:48 +0300
+Subject: thunderbolt: Add back Intel Falcon Ridge end-to-end flow control
+ workaround
+
+From: Mika Westerberg <mika.westerberg@linux.intel.com>
+
+[ Upstream commit 54669e2f17cb5a4c41ade89427f074dc22cecb17 ]
+
+As we are now enabling full end-to-end flow control to the Thunderbolt
+networking driver, in order for it to work properly on second generation
+Thunderbolt hardware (Falcon Ridge), we need to add back the workaround
+that was removed with commit 53f13319d131 ("thunderbolt: Get rid of E2E
+workaround"). However, this time we only apply it for Falcon Ridge
+controllers as a form of an additional quirk. For non-Falcon Ridge this
+does nothing.
+
+While there fix a typo 'reqister' -> 'register' in the comment.
+
+Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/thunderbolt/nhi.c | 49 +++++++++++++++++++++++++++++++++------
+ 1 file changed, 42 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
+index c73da0532be4..aa6cf7f2f438 100644
+--- a/drivers/thunderbolt/nhi.c
++++ b/drivers/thunderbolt/nhi.c
+@@ -25,7 +25,11 @@
+ #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
+
+ #define RING_FIRST_USABLE_HOPID 1
+-
++/*
++ * Used with QUIRK_E2E to specify an unused HopID the Rx credits are
++ * transferred.
++ */
++#define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID
+ /*
+ * Minimal number of vectors when we use MSI-X. Two for control channel
+ * Rx/Tx and the rest four are for cross domain DMA paths.
+@@ -35,7 +39,9 @@
+
+ #define NHI_MAILBOX_TIMEOUT 500 /* ms */
+
++/* Host interface quirks */
+ #define QUIRK_AUTO_CLEAR_INT BIT(0)
++#define QUIRK_E2E BIT(1)
+
+ static int ring_interrupt_index(struct tb_ring *ring)
+ {
+@@ -455,8 +461,18 @@ static void ring_release_msix(struct tb_ring *ring)
+
+ static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
+ {
++ unsigned int start_hop = RING_FIRST_USABLE_HOPID;
+ int ret = 0;
+
++ if (nhi->quirks & QUIRK_E2E) {
++ start_hop = RING_FIRST_USABLE_HOPID + 1;
++ if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
++ dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n",
++ ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID);
++ ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID;
++ }
++ }
++
+ spin_lock_irq(&nhi->lock);
+
+ if (ring->hop < 0) {
+@@ -466,7 +482,7 @@ static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
+ * Automatically allocate HopID from the non-reserved
+ * range 1 .. hop_count - 1.
+ */
+- for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
++ for (i = start_hop; i < nhi->hop_count; i++) {
+ if (ring->is_tx) {
+ if (!nhi->tx_rings[i]) {
+ ring->hop = i;
+@@ -481,6 +497,11 @@ static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
+ }
+ }
+
++ if (ring->hop > 0 && ring->hop < start_hop) {
++ dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
++ ret = -EINVAL;
++ goto err_unlock;
++ }
+ if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
+ dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
+ ret = -EINVAL;
+@@ -1094,12 +1115,26 @@ static void nhi_shutdown(struct tb_nhi *nhi)
+
+ static void nhi_check_quirks(struct tb_nhi *nhi)
+ {
+- /*
+- * Intel hardware supports auto clear of the interrupt status
+- * reqister right after interrupt is being issued.
+- */
+- if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)
++ if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) {
++ /*
++ * Intel hardware supports auto clear of the interrupt
++ * status register right after interrupt is being
++ * issued.
++ */
+ nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
++
++ switch (nhi->pdev->device) {
++ case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
++ case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
++ /*
++ * Falcon Ridge controller needs the end-to-end
++ * flow control workaround to avoid losing Rx
++ * packets when RING_FLAG_E2E is set.
++ */
++ nhi->quirks |= QUIRK_E2E;
++ break;
++ }
++ }
+ }
+
+ static int nhi_init_msi(struct tb_nhi *nhi)
+--
+2.35.1
+
--- /dev/null
+From 10436a0553b019ff0cc7d81a8b601bd5b7fdd7e8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 26 Jul 2022 18:29:32 +0300
+Subject: tools/power turbostat: separate SPR from ICX
+
+From: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
+
+[ Upstream commit 684e40e99e594e0da1dc1b358fbd51c03c606e75 ]
+
+Before this patch, SPR platform was considered identical to ICX platform. This
+patch separates SPR support from ICX.
+
+This patch is a preparation for adding SPR-specific package C-state limits
+support.
+
+Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
+Reviewed-by: Chen Yu <yu.c.chen@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Stable-dep-of: b2d433ae6376 ("tools/power turbostat: Use standard Energy Unit for SPR Dram RAPL domain")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/power/x86/turbostat/turbostat.c | 31 ++++++++++++++++++++++-----
+ 1 file changed, 26 insertions(+), 5 deletions(-)
+
+diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
+index 4f176bbf29f4..2a185a7c993c 100644
+--- a/tools/power/x86/turbostat/turbostat.c
++++ b/tools/power/x86/turbostat/turbostat.c
+@@ -2432,6 +2432,7 @@ int has_turbo_ratio_group_limits(int family, int model)
+ case INTEL_FAM6_ATOM_GOLDMONT:
+ case INTEL_FAM6_SKYLAKE_X:
+ case INTEL_FAM6_ICELAKE_X:
++ case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ case INTEL_FAM6_ATOM_GOLDMONT_D:
+ case INTEL_FAM6_ATOM_TREMONT_D:
+ return 1;
+@@ -3673,6 +3674,7 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
+ has_misc_feature_control = 1;
+ break;
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
++ case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ pkg_cstate_limits = icx_pkg_cstate_limits;
+ has_misc_feature_control = 1;
+ break;
+@@ -3782,6 +3784,22 @@ int is_icx(unsigned int family, unsigned int model)
+ return 0;
+ }
+
++int is_spr(unsigned int family, unsigned int model)
++{
++
++ if (!genuine_intel)
++ return 0;
++
++ if (family != 6)
++ return 0;
++
++ switch (model) {
++ case INTEL_FAM6_SAPPHIRERAPIDS_X:
++ return 1;
++ }
++ return 0;
++}
++
+ int is_ehl(unsigned int family, unsigned int model)
+ {
+ if (!genuine_intel)
+@@ -3890,6 +3908,7 @@ int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
+ case INTEL_FAM6_ATOM_GOLDMONT:
+ case INTEL_FAM6_SKYLAKE_X:
+ case INTEL_FAM6_ICELAKE_X:
++ case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ return 1;
+ default:
+ return 0;
+@@ -3917,7 +3936,7 @@ int has_config_tdp(unsigned int family, unsigned int model)
+ case INTEL_FAM6_CANNONLAKE_L: /* CNL */
+ case INTEL_FAM6_SKYLAKE_X: /* SKX */
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
+-
++ case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
+ return 1;
+ default:
+@@ -4377,6 +4396,7 @@ static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
+ case INTEL_FAM6_SKYLAKE_X: /* SKX */
+ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
++ case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ return (rapl_dram_energy_units = 15.3 / 1000000);
+ default:
+ return (rapl_energy_units);
+@@ -4466,6 +4486,7 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
+ case INTEL_FAM6_BROADWELL_X: /* BDX */
+ case INTEL_FAM6_SKYLAKE_X: /* SKX */
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
++ case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
+ do_rapl =
+ RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
+@@ -4628,13 +4649,13 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model)
+
+ void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
+ {
+- if (is_skx(family, model) || is_bdx(family, model) || is_icx(family, model))
++ if (is_skx(family, model) || is_bdx(family, model) || is_icx(family, model) || is_spr(family, model))
+ has_automatic_cstate_conversion = 1;
+ }
+
+ void prewake_cstate_probe(unsigned int family, unsigned int model)
+ {
+- if (is_icx(family, model))
++ if (is_icx(family, model) || is_spr(family, model))
+ dis_cstate_prewake = 1;
+ }
+
+@@ -4847,6 +4868,7 @@ int has_snb_msrs(unsigned int family, unsigned int model)
+ case INTEL_FAM6_CANNONLAKE_L: /* CNL */
+ case INTEL_FAM6_SKYLAKE_X: /* SKX */
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
++ case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
+ case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
+ case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
+@@ -5216,7 +5238,6 @@ unsigned int intel_model_duplicates(unsigned int model)
+ return INTEL_FAM6_ATOM_TREMONT;
+
+ case INTEL_FAM6_ICELAKE_D:
+- case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ return INTEL_FAM6_ICELAKE_X;
+ }
+ return model;
+@@ -5503,7 +5524,7 @@ void process_cpuid()
+ BIC_NOT_PRESENT(BIC_Pkgpc7);
+ use_c1_residency_msr = 1;
+ }
+- if (is_skx(family, model) || is_icx(family, model)) {
++ if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
+ BIC_NOT_PRESENT(BIC_CPU_c3);
+ BIC_NOT_PRESENT(BIC_Pkgpc3);
+ BIC_NOT_PRESENT(BIC_CPU_c7);
+--
+2.35.1
+
--- /dev/null
+From dfe2b3a971e504495ff5a28fbf4195af1b3977f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 13:47:38 +0800
+Subject: tools/power turbostat: Use standard Energy Unit for SPR Dram RAPL
+ domain
+
+From: Zhang Rui <rui.zhang@intel.com>
+
+[ Upstream commit b2d433ae637626d44c9d4a75dd3330cf68fed9de ]
+
+Intel Xeon servers used to use a fixed energy resolution (15.3uj) for
+Dram RAPL domain. But on SPR, Dram RAPL domain follows the standard
+energy resolution as described in MSR_RAPL_POWER_UNIT.
+
+Remove the SPR rapl_dram_energy_units quirk.
+
+Fixes: e7af1ed3fa47 ("tools/power turbostat: Support additional CPU model numbers")
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Tested-by: Wang Wendy <wendy.wang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/power/x86/turbostat/turbostat.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
+index 2a185a7c993c..6c1b02a754eb 100644
+--- a/tools/power/x86/turbostat/turbostat.c
++++ b/tools/power/x86/turbostat/turbostat.c
+@@ -4396,7 +4396,6 @@ static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
+ case INTEL_FAM6_SKYLAKE_X: /* SKX */
+ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
+ case INTEL_FAM6_ICELAKE_X: /* ICX */
+- case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
+ return (rapl_dram_energy_units = 15.3 / 1000000);
+ default:
+ return (rapl_energy_units);
+--
+2.35.1
+
--- /dev/null
+From 25692a4a5721c1f8820b3b398553a92743b9c3d1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 20:56:28 +0800
+Subject: tracing: kprobe: Fix kprobe event gen test module on exit
+
+From: Yipeng Zou <zouyipeng@huawei.com>
+
+[ Upstream commit ac48e189527fae87253ef2bf58892e782fb36874 ]
+
+Correct gen_kretprobe_test clr event para on module exit.
+This will make it can't to delete.
+
+Link: https://lkml.kernel.org/r/20220919125629.238242-2-zouyipeng@huawei.com
+
+Cc: <linux-riscv@lists.infradead.org>
+Cc: <mingo@redhat.com>
+Cc: <paul.walmsley@sifive.com>
+Cc: <palmer@dabbelt.com>
+Cc: <aou@eecs.berkeley.edu>
+Cc: <zanussi@kernel.org>
+Cc: <liaochang1@huawei.com>
+Cc: <chris.zjh@huawei.com>
+Fixes: 64836248dda2 ("tracing: Add kprobe event command generation test module")
+Signed-off-by: Yipeng Zou <zouyipeng@huawei.com>
+Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/kprobe_event_gen_test.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/trace/kprobe_event_gen_test.c b/kernel/trace/kprobe_event_gen_test.c
+index 18b0f1cbb947..e023154be0f8 100644
+--- a/kernel/trace/kprobe_event_gen_test.c
++++ b/kernel/trace/kprobe_event_gen_test.c
+@@ -206,7 +206,7 @@ static void __exit kprobe_event_gen_test_exit(void)
+ WARN_ON(kprobe_event_delete("gen_kprobe_test"));
+
+ /* Disable the event or you can't remove it */
+- WARN_ON(trace_array_set_clr_event(gen_kprobe_test->tr,
++ WARN_ON(trace_array_set_clr_event(gen_kretprobe_test->tr,
+ "kprobes",
+ "gen_kretprobe_test", false));
+
+--
+2.35.1
+
--- /dev/null
+From 636962b56d38b72010a1d7e44a8804eefb9475ca Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 20:56:29 +0800
+Subject: tracing: kprobe: Make gen test module work in arm and riscv
+
+From: Yipeng Zou <zouyipeng@huawei.com>
+
+[ Upstream commit d8ef45d66c01425ff748e13ef7dd1da7a91cc93c ]
+
+For now, this selftest module can only work in x86 because of the
+kprobe cmd was fixed use of x86 registers.
+This patch adapted to register names under arm and riscv, So that
+this module can be worked on those platform.
+
+Link: https://lkml.kernel.org/r/20220919125629.238242-3-zouyipeng@huawei.com
+
+Cc: <linux-riscv@lists.infradead.org>
+Cc: <mingo@redhat.com>
+Cc: <paul.walmsley@sifive.com>
+Cc: <palmer@dabbelt.com>
+Cc: <aou@eecs.berkeley.edu>
+Cc: <zanussi@kernel.org>
+Cc: <liaochang1@huawei.com>
+Cc: <chris.zjh@huawei.com>
+Fixes: 64836248dda2 ("tracing: Add kprobe event command generation test module")
+Signed-off-by: Yipeng Zou <zouyipeng@huawei.com>
+Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/kprobe_event_gen_test.c | 47 +++++++++++++++++++++++++---
+ 1 file changed, 43 insertions(+), 4 deletions(-)
+
+diff --git a/kernel/trace/kprobe_event_gen_test.c b/kernel/trace/kprobe_event_gen_test.c
+index e023154be0f8..80e04a1e1977 100644
+--- a/kernel/trace/kprobe_event_gen_test.c
++++ b/kernel/trace/kprobe_event_gen_test.c
+@@ -35,6 +35,45 @@
+ static struct trace_event_file *gen_kprobe_test;
+ static struct trace_event_file *gen_kretprobe_test;
+
++#define KPROBE_GEN_TEST_FUNC "do_sys_open"
++
++/* X86 */
++#if defined(CONFIG_X86_64) || defined(CONFIG_X86_32)
++#define KPROBE_GEN_TEST_ARG0 "dfd=%ax"
++#define KPROBE_GEN_TEST_ARG1 "filename=%dx"
++#define KPROBE_GEN_TEST_ARG2 "flags=%cx"
++#define KPROBE_GEN_TEST_ARG3 "mode=+4($stack)"
++
++/* ARM64 */
++#elif defined(CONFIG_ARM64)
++#define KPROBE_GEN_TEST_ARG0 "dfd=%x0"
++#define KPROBE_GEN_TEST_ARG1 "filename=%x1"
++#define KPROBE_GEN_TEST_ARG2 "flags=%x2"
++#define KPROBE_GEN_TEST_ARG3 "mode=%x3"
++
++/* ARM */
++#elif defined(CONFIG_ARM)
++#define KPROBE_GEN_TEST_ARG0 "dfd=%r0"
++#define KPROBE_GEN_TEST_ARG1 "filename=%r1"
++#define KPROBE_GEN_TEST_ARG2 "flags=%r2"
++#define KPROBE_GEN_TEST_ARG3 "mode=%r3"
++
++/* RISCV */
++#elif defined(CONFIG_RISCV)
++#define KPROBE_GEN_TEST_ARG0 "dfd=%a0"
++#define KPROBE_GEN_TEST_ARG1 "filename=%a1"
++#define KPROBE_GEN_TEST_ARG2 "flags=%a2"
++#define KPROBE_GEN_TEST_ARG3 "mode=%a3"
++
++/* others */
++#else
++#define KPROBE_GEN_TEST_ARG0 NULL
++#define KPROBE_GEN_TEST_ARG1 NULL
++#define KPROBE_GEN_TEST_ARG2 NULL
++#define KPROBE_GEN_TEST_ARG3 NULL
++#endif
++
++
+ /*
+ * Test to make sure we can create a kprobe event, then add more
+ * fields.
+@@ -58,14 +97,14 @@ static int __init test_gen_kprobe_cmd(void)
+ * fields.
+ */
+ ret = kprobe_event_gen_cmd_start(&cmd, "gen_kprobe_test",
+- "do_sys_open",
+- "dfd=%ax", "filename=%dx");
++ KPROBE_GEN_TEST_FUNC,
++ KPROBE_GEN_TEST_ARG0, KPROBE_GEN_TEST_ARG1);
+ if (ret)
+ goto free;
+
+ /* Use kprobe_event_add_fields to add the rest of the fields */
+
+- ret = kprobe_event_add_fields(&cmd, "flags=%cx", "mode=+4($stack)");
++ ret = kprobe_event_add_fields(&cmd, KPROBE_GEN_TEST_ARG2, KPROBE_GEN_TEST_ARG3);
+ if (ret)
+ goto free;
+
+@@ -128,7 +167,7 @@ static int __init test_gen_kretprobe_cmd(void)
+ * Define the kretprobe event.
+ */
+ ret = kretprobe_event_gen_cmd_start(&cmd, "gen_kretprobe_test",
+- "do_sys_open",
++ KPROBE_GEN_TEST_FUNC,
+ "$retval");
+ if (ret)
+ goto free;
+--
+2.35.1
+
--- /dev/null
+From 69f960a07f241c8011631b171b1b484cbc8a75ea Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 08:49:32 -0600
+Subject: tracing/osnoise: Fix possible recursive locking in
+ stop_per_cpu_kthreads
+
+From: Nico Pache <npache@redhat.com>
+
+[ Upstream commit 99ee9317a1305cd5626736785c8cb38b0e47686c ]
+
+There is a recursive lock on the cpu_hotplug_lock.
+
+In kernel/trace/trace_osnoise.c:<start/stop>_per_cpu_kthreads:
+ - start_per_cpu_kthreads calls cpus_read_lock() and if
+ start_kthreads returns a error it will call stop_per_cpu_kthreads.
+ - stop_per_cpu_kthreads then calls cpus_read_lock() again causing
+ deadlock.
+
+Fix this by calling cpus_read_unlock() before calling
+stop_per_cpu_kthreads. This behavior can also be seen in commit
+f46b16520a08 ("trace/hwlat: Implement the per-cpu mode").
+
+This error was noticed during the LTP ftrace-stress-test:
+
+WARNING: possible recursive locking detected
+--------------------------------------------
+sh/275006 is trying to acquire lock:
+ffffffffb02f5400 (cpu_hotplug_lock){++++}-{0:0}, at: stop_per_cpu_kthreads
+
+but task is already holding lock:
+ffffffffb02f5400 (cpu_hotplug_lock){++++}-{0:0}, at: start_per_cpu_kthreads
+
+other info that might help us debug this:
+ Possible unsafe locking scenario:
+
+ CPU0
+ ----
+ lock(cpu_hotplug_lock);
+ lock(cpu_hotplug_lock);
+
+ *** DEADLOCK ***
+
+May be due to missing lock nesting notation
+
+3 locks held by sh/275006:
+ #0: ffff8881023f0470 (sb_writers#24){.+.+}-{0:0}, at: ksys_write
+ #1: ffffffffb084f430 (trace_types_lock){+.+.}-{3:3}, at: rb_simple_write
+ #2: ffffffffb02f5400 (cpu_hotplug_lock){++++}-{0:0}, at: start_per_cpu_kthreads
+
+Link: https://lkml.kernel.org/r/20220919144932.3064014-1-npache@redhat.com
+
+Fixes: c8895e271f79 ("trace/osnoise: Support hotplug operations")
+Signed-off-by: Nico Pache <npache@redhat.com>
+Acked-by: Daniel Bristot de Oliveira <bristot@kernel.org>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/trace_osnoise.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_osnoise.c b/kernel/trace/trace_osnoise.c
+index 93de784ee681..6ef1164c0440 100644
+--- a/kernel/trace/trace_osnoise.c
++++ b/kernel/trace/trace_osnoise.c
+@@ -1598,8 +1598,9 @@ static int start_per_cpu_kthreads(struct trace_array *tr)
+ for_each_cpu(cpu, current_mask) {
+ retval = start_kthread(cpu);
+ if (retval) {
++ cpus_read_unlock();
+ stop_per_cpu_kthreads();
+- break;
++ return retval;
+ }
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 77ff1c54261128a26dcd1566ec37423f86ae1ca4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 19:17:03 +0800
+Subject: tty: serial: fsl_lpuart: disable dma rx/tx use flags in
+ lpuart_dma_shutdown
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Sherry Sun <sherry.sun@nxp.com>
+
+[ Upstream commit 316ae95c175a7d770d1bfe4c011192712f57aa4a ]
+
+lpuart_dma_shutdown tears down lpuart dma, but lpuart_flush_buffer can
+still occur which in turn tries to access dma apis if lpuart_dma_tx_use
+flag is true. At this point since dma is torn down, these dma apis can
+abort. Set lpuart_dma_tx_use and the corresponding rx flag
+lpuart_dma_rx_use to false in lpuart_dma_shutdown so that dmas are not
+accessed after they are relinquished.
+
+Otherwise, when try to kill btattach, kernel may panic. This patch may
+fix this issue.
+root@imx8ulpevk:~# btattach -B /dev/ttyLP2 -S 115200
+^C[ 90.182296] Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
+[ 90.189806] Modules linked in: moal(O) mlan(O)
+[ 90.194258] CPU: 0 PID: 503 Comm: btattach Tainted: G O 5.15.32-06136-g34eecdf2f9e4 #37
+[ 90.203554] Hardware name: NXP i.MX8ULP 9X9 EVK (DT)
+[ 90.208513] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[ 90.215470] pc : fsl_edma3_disable_request+0x8/0x60
+[ 90.220358] lr : fsl_edma3_terminate_all+0x34/0x20c
+[ 90.225237] sp : ffff800013f0bac0
+[ 90.228548] x29: ffff800013f0bac0 x28: 0000000000000001 x27: ffff000008404800
+[ 90.235681] x26: ffff000008404960 x25: ffff000008404a08 x24: ffff000008404a00
+[ 90.242813] x23: ffff000008404a60 x22: 0000000000000002 x21: 0000000000000000
+[ 90.249946] x20: ffff800013f0baf8 x19: ffff00000559c800 x18: 0000000000000000
+[ 90.257078] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000
+[ 90.264211] x14: 0000000000000003 x13: 0000000000000000 x12: 0000000000000040
+[ 90.271344] x11: ffff00000600c248 x10: ffff800013f0bb10 x9 : ffff000057bcb090
+[ 90.278477] x8 : fffffc0000241a08 x7 : ffff00000534ee00 x6 : ffff000008404804
+[ 90.285609] x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff0000055b3480
+[ 90.292742] x2 : ffff8000135c0000 x1 : ffff00000534ee00 x0 : ffff00000559c800
+[ 90.299876] Call trace:
+[ 90.302321] fsl_edma3_disable_request+0x8/0x60
+[ 90.306851] lpuart_flush_buffer+0x40/0x160
+[ 90.311037] uart_flush_buffer+0x88/0x120
+[ 90.315050] tty_driver_flush_buffer+0x20/0x30
+[ 90.319496] hci_uart_flush+0x44/0x90
+[ 90.323162] +0x34/0x12c
+[ 90.327253] tty_ldisc_close+0x38/0x70
+[ 90.331005] tty_ldisc_release+0xa8/0x190
+[ 90.335018] tty_release_struct+0x24/0x8c
+[ 90.339022] tty_release+0x3ec/0x4c0
+[ 90.342593] __fput+0x70/0x234
+[ 90.345652] ____fput+0x14/0x20
+[ 90.348790] task_work_run+0x84/0x17c
+[ 90.352455] do_exit+0x310/0x96c
+[ 90.355688] do_group_exit+0x3c/0xa0
+[ 90.359259] __arm64_sys_exit_group+0x1c/0x20
+[ 90.363609] invoke_syscall+0x48/0x114
+[ 90.367362] el0_svc_common.constprop.0+0xd4/0xfc
+[ 90.372068] do_el0_svc+0x2c/0x94
+[ 90.375379] el0_svc+0x28/0x80
+[ 90.378438] el0t_64_sync_handler+0xa8/0x130
+[ 90.382711] el0t_64_sync+0x1a0/0x1a4
+[ 90.386376] Code: 17ffffda d503201f d503233f f9409802 (b9400041)
+[ 90.392467] ---[ end trace 2f60524b4a43f1f6 ]---
+[ 90.397073] note: btattach[503] exited with preempt_count 1
+[ 90.402636] Fixing recursive fault but reboot is needed!
+
+Fixes: 6250cc30c4c4 ("tty: serial: fsl_lpuart: Use scatter/gather DMA for Tx")
+Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+Signed-off-by: Thara Gopinath <tgopinath@microsoft.com>
+Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
+Link: https://lore.kernel.org/r/20220920111703.1532-1-sherry.sun@nxp.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/fsl_lpuart.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index b6548b910d94..185dd417fc49 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -1787,6 +1787,7 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport)
+ if (sport->lpuart_dma_rx_use) {
+ del_timer_sync(&sport->lpuart_timer);
+ lpuart_dma_rx_free(&sport->port);
++ sport->lpuart_dma_rx_use = false;
+ }
+
+ if (sport->lpuart_dma_tx_use) {
+@@ -1795,6 +1796,7 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport)
+ sport->dma_tx_in_progress = false;
+ dmaengine_terminate_all(sport->dma_tx_chan);
+ }
++ sport->lpuart_dma_tx_use = false;
+ }
+
+ if (sport->dma_tx_chan)
+--
+2.35.1
+
--- /dev/null
+From dac1ec5b5355a4bf7e94efe1e2f93b5bb35f196e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 29 Jul 2022 17:17:45 +0530
+Subject: tty: xilinx_uartps: Fix the ignore_status
+
+From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+
+[ Upstream commit b8a6c3b3d4654fba19881cc77da61eac29f57cae ]
+
+Currently the ignore_status is not considered in the isr.
+Add a check to add the ignore_status.
+
+Fixes: 61ec9016988f ("tty/serial: add support for Xilinx PS UART")
+Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+Link: https://lore.kernel.org/r/20220729114748.18332-5-shubhrajyoti.datta@xilinx.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/xilinx_uartps.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
+index d5e243908d9f..815e3e26ee20 100644
+--- a/drivers/tty/serial/xilinx_uartps.c
++++ b/drivers/tty/serial/xilinx_uartps.c
+@@ -375,6 +375,8 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
+ isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
+ }
+
++ isrstatus &= port->read_status_mask;
++ isrstatus &= ~port->ignore_status_mask;
+ /*
+ * Skip RX processing if RX is disabled as RXEMPTY will never be set
+ * as read bytes will not be removed from the FIFO.
+--
+2.35.1
+
--- /dev/null
+From 8122b9d1ef2d984a43501815e59a0ea43303bca5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 23:35:22 -0700
+Subject: udmabuf: Set ubuf->sg = NULL if the creation of sg table fails
+
+From: Vivek Kasireddy <vivek.kasireddy@intel.com>
+
+[ Upstream commit d9c04a1b7a15b5e74b2977461d9511e497f05d8f ]
+
+When userspace tries to map the dmabuf and if for some reason
+(e.g. OOM) the creation of the sg table fails, ubuf->sg needs to be
+set to NULL. Otherwise, when the userspace subsequently closes the
+dmabuf fd, we'd try to erroneously free the invalid sg table from
+release_udmabuf resulting in the following crash reported by syzbot:
+
+general protection fault, probably for non-canonical address
+0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN
+KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007]
+CPU: 0 PID: 3609 Comm: syz-executor487 Not tainted
+5.19.0-syzkaller-13930-g7ebfc85e2cd7 #0
+Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
+Google 07/22/2022
+RIP: 0010:dma_unmap_sgtable include/linux/dma-mapping.h:378 [inline]
+RIP: 0010:put_sg_table drivers/dma-buf/udmabuf.c:89 [inline]
+RIP: 0010:release_udmabuf+0xcb/0x4f0 drivers/dma-buf/udmabuf.c:114
+Code: 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 2b 04 00 00 48 8d 7d 0c 4c
+8b 63 30 48 b8 00 00 00 00 00 fc ff df 48 89 fa 48 c1 ea 03 <0f> b6 14
+02 48 89 f8 83 e0 07 83 c0 03 38 d0 7c 08 84 d2 0f 85 e2
+RSP: 0018:ffffc900037efd30 EFLAGS: 00010246
+RAX: dffffc0000000000 RBX: ffffffff8cb67800 RCX: 0000000000000000
+RDX: 0000000000000000 RSI: ffffffff84ad27e0 RDI: 0000000000000000
+RBP: fffffffffffffff4 R08: 0000000000000005 R09: 0000000000000000
+R10: 0000000000000000 R11: 000000000008c07c R12: ffff88801fa05000
+R13: ffff888073db07e8 R14: ffff888025c25440 R15: 0000000000000000
+FS: 0000555555fc4300(0000) GS:ffff8880b9a00000(0000)
+knlGS:0000000000000000
+CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+CR2: 00007fc1c0ce06e4 CR3: 00000000715e6000 CR4: 00000000003506f0
+DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+Call Trace:
+ <TASK>
+ dma_buf_release+0x157/0x2d0 drivers/dma-buf/dma-buf.c:78
+ __dentry_kill+0x42b/0x640 fs/dcache.c:612
+ dentry_kill fs/dcache.c:733 [inline]
+ dput+0x806/0xdb0 fs/dcache.c:913
+ __fput+0x39c/0x9d0 fs/file_table.c:333
+ task_work_run+0xdd/0x1a0 kernel/task_work.c:177
+ ptrace_notify+0x114/0x140 kernel/signal.c:2353
+ ptrace_report_syscall include/linux/ptrace.h:420 [inline]
+ ptrace_report_syscall_exit include/linux/ptrace.h:482 [inline]
+ syscall_exit_work kernel/entry/common.c:249 [inline]
+ syscall_exit_to_user_mode_prepare+0x129/0x280 kernel/entry/common.c:276
+ __syscall_exit_to_user_mode_work kernel/entry/common.c:281 [inline]
+ syscall_exit_to_user_mode+0x9/0x50 kernel/entry/common.c:294
+ do_syscall_64+0x42/0xb0 arch/x86/entry/common.c:86
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+RIP: 0033:0x7fc1c0c35b6b
+Code: 0f 05 48 3d 00 f0 ff ff 77 45 c3 0f 1f 40 00 48 83 ec 18 89 7c 24
+0c e8 63 fc ff ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 00 0f 05 <48> 3d 00
+f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 a1 fc ff ff 8b 44
+RSP: 002b:00007ffd78a06090 EFLAGS: 00000293 ORIG_RAX: 0000000000000003
+RAX: 0000000000000000 RBX: 0000000000000007 RCX: 00007fc1c0c35b6b
+RDX: 0000000020000280 RSI: 0000000040086200 RDI: 0000000000000006
+RBP: 0000000000000007 R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000293 R12: 000000000000000c
+R13: 0000000000000003 R14: 00007fc1c0cfe4a0 R15: 00007ffd78a06140
+ </TASK>
+Modules linked in:
+---[ end trace 0000000000000000 ]---
+RIP: 0010:dma_unmap_sgtable include/linux/dma-mapping.h:378 [inline]
+RIP: 0010:put_sg_table drivers/dma-buf/udmabuf.c:89 [inline]
+RIP: 0010:release_udmabuf+0xcb/0x4f0 drivers/dma-buf/udmabuf.c:114
+
+Reported-by: syzbot+c80e9ef5d8bb45894db0@syzkaller.appspotmail.com
+Cc: Gerd Hoffmann <kraxel@redhat.com>
+Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/20220825063522.801264-1-vivek.kasireddy@intel.com
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma-buf/udmabuf.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c
+index 38e8767ec371..bf11d32205f3 100644
+--- a/drivers/dma-buf/udmabuf.c
++++ b/drivers/dma-buf/udmabuf.c
+@@ -124,17 +124,20 @@ static int begin_cpu_udmabuf(struct dma_buf *buf,
+ {
+ struct udmabuf *ubuf = buf->priv;
+ struct device *dev = ubuf->device->this_device;
++ int ret = 0;
+
+ if (!ubuf->sg) {
+ ubuf->sg = get_sg_table(dev, buf, direction);
+- if (IS_ERR(ubuf->sg))
+- return PTR_ERR(ubuf->sg);
++ if (IS_ERR(ubuf->sg)) {
++ ret = PTR_ERR(ubuf->sg);
++ ubuf->sg = NULL;
++ }
+ } else {
+ dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents,
+ direction);
+ }
+
+- return 0;
++ return ret;
+ }
+
+ static int end_cpu_udmabuf(struct dma_buf *buf,
+--
+2.35.1
+
--- /dev/null
+From 6c7bcc2aea07b678ca88dbf77a9b47705b99a0be Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 18:38:01 -0700
+Subject: usb: common: debug: Check non-standard control requests
+
+From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+
+[ Upstream commit b6155eaf6b05e558218b44b88a6cad03f15a586c ]
+
+Previously usb_decode_ctrl() only decodes standard control requests, but
+it was used for non-standard requests also. If it's non-standard or
+unknown standard bRequest, print the Setup data values.
+
+Fixes: af32423a2d86 ("usb: dwc3: trace: decode ctrl request")
+Signed-off-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Link: https://lore.kernel.org/r/8d6a30f2f2f953eff833a5bc5aac640a4cc2fc9f.1658971571.git.Thinh.Nguyen@synopsys.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/common/debug.c | 96 +++++++++++++++++++++++++-------------
+ 1 file changed, 64 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/usb/common/debug.c b/drivers/usb/common/debug.c
+index a76a086b9c54..f0c0e8db7038 100644
+--- a/drivers/usb/common/debug.c
++++ b/drivers/usb/common/debug.c
+@@ -207,30 +207,28 @@ static void usb_decode_set_isoch_delay(__u8 wValue, char *str, size_t size)
+ snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", wValue);
+ }
+
+-/**
+- * usb_decode_ctrl - Returns human readable representation of control request.
+- * @str: buffer to return a human-readable representation of control request.
+- * This buffer should have about 200 bytes.
+- * @size: size of str buffer.
+- * @bRequestType: matches the USB bmRequestType field
+- * @bRequest: matches the USB bRequest field
+- * @wValue: matches the USB wValue field (CPU byte order)
+- * @wIndex: matches the USB wIndex field (CPU byte order)
+- * @wLength: matches the USB wLength field (CPU byte order)
+- *
+- * Function returns decoded, formatted and human-readable description of
+- * control request packet.
+- *
+- * The usage scenario for this is for tracepoints, so function as a return
+- * use the same value as in parameters. This approach allows to use this
+- * function in TP_printk
+- *
+- * Important: wValue, wIndex, wLength parameters before invoking this function
+- * should be processed by le16_to_cpu macro.
+- */
+-const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
+- __u8 bRequest, __u16 wValue, __u16 wIndex,
+- __u16 wLength)
++static void usb_decode_ctrl_generic(char *str, size_t size, __u8 bRequestType,
++ __u8 bRequest, __u16 wValue, __u16 wIndex,
++ __u16 wLength)
++{
++ u8 recip = bRequestType & USB_RECIP_MASK;
++ u8 type = bRequestType & USB_TYPE_MASK;
++
++ snprintf(str, size,
++ "Type=%s Recipient=%s Dir=%s bRequest=%u wValue=%u wIndex=%u wLength=%u",
++ (type == USB_TYPE_STANDARD) ? "Standard" :
++ (type == USB_TYPE_VENDOR) ? "Vendor" :
++ (type == USB_TYPE_CLASS) ? "Class" : "Unknown",
++ (recip == USB_RECIP_DEVICE) ? "Device" :
++ (recip == USB_RECIP_INTERFACE) ? "Interface" :
++ (recip == USB_RECIP_ENDPOINT) ? "Endpoint" : "Unknown",
++ (bRequestType & USB_DIR_IN) ? "IN" : "OUT",
++ bRequest, wValue, wIndex, wLength);
++}
++
++static void usb_decode_ctrl_standard(char *str, size_t size, __u8 bRequestType,
++ __u8 bRequest, __u16 wValue, __u16 wIndex,
++ __u16 wLength)
+ {
+ switch (bRequest) {
+ case USB_REQ_GET_STATUS:
+@@ -271,14 +269,48 @@ const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
+ usb_decode_set_isoch_delay(wValue, str, size);
+ break;
+ default:
+- snprintf(str, size, "%02x %02x %02x %02x %02x %02x %02x %02x",
+- bRequestType, bRequest,
+- (u8)(cpu_to_le16(wValue) & 0xff),
+- (u8)(cpu_to_le16(wValue) >> 8),
+- (u8)(cpu_to_le16(wIndex) & 0xff),
+- (u8)(cpu_to_le16(wIndex) >> 8),
+- (u8)(cpu_to_le16(wLength) & 0xff),
+- (u8)(cpu_to_le16(wLength) >> 8));
++ usb_decode_ctrl_generic(str, size, bRequestType, bRequest,
++ wValue, wIndex, wLength);
++ break;
++ }
++}
++
++/**
++ * usb_decode_ctrl - Returns human readable representation of control request.
++ * @str: buffer to return a human-readable representation of control request.
++ * This buffer should have about 200 bytes.
++ * @size: size of str buffer.
++ * @bRequestType: matches the USB bmRequestType field
++ * @bRequest: matches the USB bRequest field
++ * @wValue: matches the USB wValue field (CPU byte order)
++ * @wIndex: matches the USB wIndex field (CPU byte order)
++ * @wLength: matches the USB wLength field (CPU byte order)
++ *
++ * Function returns decoded, formatted and human-readable description of
++ * control request packet.
++ *
++ * The usage scenario for this is for tracepoints, so function as a return
++ * use the same value as in parameters. This approach allows to use this
++ * function in TP_printk
++ *
++ * Important: wValue, wIndex, wLength parameters before invoking this function
++ * should be processed by le16_to_cpu macro.
++ */
++const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
++ __u8 bRequest, __u16 wValue, __u16 wIndex,
++ __u16 wLength)
++{
++ switch (bRequestType & USB_TYPE_MASK) {
++ case USB_TYPE_STANDARD:
++ usb_decode_ctrl_standard(str, size, bRequestType, bRequest,
++ wValue, wIndex, wLength);
++ break;
++ case USB_TYPE_VENDOR:
++ case USB_TYPE_CLASS:
++ default:
++ usb_decode_ctrl_generic(str, size, bRequestType, bRequest,
++ wValue, wIndex, wLength);
++ break;
+ }
+
+ return str;
+--
+2.35.1
+
--- /dev/null
+From aafea8413609b26e0771b0c721fce298b6cb8925 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 10:52:35 +0530
+Subject: usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error
+ after resume bug
+
+From: Piyush Mehta <piyush.mehta@amd.com>
+
+[ Upstream commit 63d7f9810a38102cdb8cad214fac98682081e1a7 ]
+
+When configured in HOST mode, after issuing U3/L2 exit controller fails
+to send proper CRC checksum in CRC5 field. Because of this behavior
+Transaction Error is generated, resulting in reset and re-enumeration of
+usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this
+problem.
+
+When this bit is set to '1', the UTMI/ULPI opmode will be changed to
+"normal" along with HS terminations, term, and xcvr signals after EOR.
+This option is to support certain legacy UTMI/ULPI PHYs.
+
+Added "snps,resume-hs-terminations" quirk to resolved the above issue.
+
+Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
+Link: https://lore.kernel.org/r/20220920052235.194272-3-piyush.mehta@amd.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/core.c | 17 +++++++++++++++++
+ drivers/usb/dwc3/core.h | 4 ++++
+ 2 files changed, 21 insertions(+)
+
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index c32ca691bcc7..a2f3e56aba05 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1041,6 +1041,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
+ dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
+ }
+
++ /*
++ * When configured in HOST mode, after issuing U3/L2 exit controller
++ * fails to send proper CRC checksum in CRC5 feild. Because of this
++ * behaviour Transaction Error is generated, resulting in reset and
++ * re-enumeration of usb device attached. All the termsel, xcvrsel,
++ * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
++ * will correct this problem. This option is to support certain
++ * legacy ULPI PHYs.
++ */
++ if (dwc->resume_hs_terminations) {
++ reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
++ reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
++ dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
++ }
++
+ if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+
+@@ -1383,6 +1398,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
+ "snps,dis-del-phy-power-chg-quirk");
+ dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
+ "snps,dis-tx-ipgap-linecheck-quirk");
++ dwc->resume_hs_terminations = device_property_read_bool(dev,
++ "snps,resume-hs-terminations");
+ dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
+ "snps,parkmode-disable-ss-quirk");
+
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+index 077d03a33388..e82e4cbe4ec7 100644
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -260,6 +260,7 @@
+ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
+ #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
+ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
++#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
+
+ /* Global Status Register */
+ #define DWC3_GSTS_OTG_IP BIT(10)
+@@ -1072,6 +1073,8 @@ struct dwc3_scratchpad_array {
+ * change quirk.
+ * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
+ * check during HS transmit.
++ * @resume-hs-terminations: Set if we enable quirk for fixing improper crc
++ * generation after resume from suspend.
+ * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
+ * instances in park mode.
+ * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
+@@ -1284,6 +1287,7 @@ struct dwc3 {
+ unsigned dis_u2_freeclk_exists_quirk:1;
+ unsigned dis_del_phy_power_chg_quirk:1;
+ unsigned dis_tx_ipgap_linecheck_quirk:1;
++ unsigned resume_hs_terminations:1;
+ unsigned parkmode_disable_ss_quirk:1;
+
+ unsigned tx_de_emphasis_quirk:1;
+--
+2.35.1
+
--- /dev/null
+From 1430f8cf246a60c094d4abf349f003f312d1adfb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 11 Sep 2022 15:37:55 -0700
+Subject: usb: gadget: function: fix dangling pnp_string in f_printer.c
+
+From: Albert Briscoe <albertsbriscoe@gmail.com>
+
+[ Upstream commit 24b7ba2f88e04800b54d462f376512e8c41b8a3c ]
+
+When opts->pnp_string is changed with configfs, new memory is allocated for
+the string. It does not, however, update dev->pnp_string, even though the
+memory is freed. When rquesting the string, the host then gets old or
+corrupted data rather than the new string. The ieee 1284 id string should
+be allowed to change while the device is connected.
+
+The bug was introduced in commit fdc01cc286be ("usb: gadget: printer:
+Remove pnp_string static buffer"), which changed opts->pnp_string from a
+char[] to a char*.
+This patch changes dev->pnp_string from a char* to a char** pointing to
+opts->pnp_string.
+
+Fixes: fdc01cc286be ("usb: gadget: printer: Remove pnp_string static buffer")
+Signed-off-by: Albert Briscoe <albertsbriscoe@gmail.com>
+Link: https://lore.kernel.org/r/20220911223753.20417-1-albertsbriscoe@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/gadget/function/f_printer.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_printer.c b/drivers/usb/gadget/function/f_printer.c
+index abec5c58f525..a881c69b1f2b 100644
+--- a/drivers/usb/gadget/function/f_printer.c
++++ b/drivers/usb/gadget/function/f_printer.c
+@@ -89,7 +89,7 @@ struct printer_dev {
+ u8 printer_cdev_open;
+ wait_queue_head_t wait;
+ unsigned q_len;
+- char *pnp_string; /* We don't own memory! */
++ char **pnp_string; /* We don't own memory! */
+ struct usb_function function;
+ };
+
+@@ -1000,16 +1000,16 @@ static int printer_func_setup(struct usb_function *f,
+ if ((wIndex>>8) != dev->interface)
+ break;
+
+- if (!dev->pnp_string) {
++ if (!*dev->pnp_string) {
+ value = 0;
+ break;
+ }
+- value = strlen(dev->pnp_string);
++ value = strlen(*dev->pnp_string);
+ buf[0] = (value >> 8) & 0xFF;
+ buf[1] = value & 0xFF;
+- memcpy(buf + 2, dev->pnp_string, value);
++ memcpy(buf + 2, *dev->pnp_string, value);
+ DBG(dev, "1284 PNP String: %x %s\n", value,
+- dev->pnp_string);
++ *dev->pnp_string);
+ break;
+
+ case GET_PORT_STATUS: /* Get Port Status */
+@@ -1475,7 +1475,7 @@ static struct usb_function *gprinter_alloc(struct usb_function_instance *fi)
+ kref_init(&dev->kref);
+ ++opts->refcnt;
+ dev->minor = opts->minor;
+- dev->pnp_string = opts->pnp_string;
++ dev->pnp_string = &opts->pnp_string;
+ dev->q_len = opts->q_len;
+ mutex_unlock(&opts->lock);
+
+--
+2.35.1
+
--- /dev/null
+From 1f5897c255ea808a18533589d8af9e40b3e8ab44 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 15:34:45 +0300
+Subject: usb: host: xhci: Fix potential memory leak in
+ xhci_alloc_stream_info()
+
+From: Jianglei Nie <niejianglei2021@163.com>
+
+[ Upstream commit 7e271f42a5cc3768cd2622b929ba66859ae21f97 ]
+
+xhci_alloc_stream_info() allocates stream context array for stream_info
+->stream_ctx_array with xhci_alloc_stream_ctx(). When some error occurs,
+stream_info->stream_ctx_array is not released, which will lead to a
+memory leak.
+
+We can fix it by releasing the stream_info->stream_ctx_array with
+xhci_free_stream_ctx() on the error path to avoid the potential memory
+leak.
+
+Signed-off-by: Jianglei Nie <niejianglei2021@163.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Link: https://lore.kernel.org/r/20220921123450.671459-2-mathias.nyman@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/host/xhci-mem.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index b398d3fdabf6..02cd4d7c3e7e 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -642,7 +642,7 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ num_stream_ctxs, &stream_info->ctx_array_dma,
+ mem_flags);
+ if (!stream_info->stream_ctx_array)
+- goto cleanup_ctx;
++ goto cleanup_ring_array;
+ memset(stream_info->stream_ctx_array, 0,
+ sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
+
+@@ -703,6 +703,11 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ }
+ xhci_free_command(xhci, stream_info->free_streams_command);
+ cleanup_ctx:
++ xhci_free_stream_ctx(xhci,
++ stream_info->num_stream_ctxs,
++ stream_info->stream_ctx_array,
++ stream_info->ctx_array_dma);
++cleanup_ring_array:
+ kfree(stream_info->stream_rings);
+ cleanup_info:
+ kfree(stream_info);
+--
+2.35.1
+
--- /dev/null
+From 908d495977ebc27966ecb8f2cf3fb7d636f802a3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 Aug 2022 15:27:34 -0700
+Subject: usb: host: xhci-plat: suspend and resume clocks
+
+From: Justin Chen <justinpopo6@gmail.com>
+
+[ Upstream commit 8bd954c56197caf5e3a804d989094bc3fe6329aa ]
+
+Introduce XHCI_SUSPEND_RESUME_CLKS quirk as a means to suspend and resume
+clocks if the hardware is capable of doing so. We assume that clocks will
+be needed if the device may wake.
+
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Justin Chen <justinpopo6@gmail.com>
+Link: https://lore.kernel.org/r/1660170455-15781-2-git-send-email-justinpopo6@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/host/xhci-plat.c | 16 +++++++++++++++-
+ drivers/usb/host/xhci.h | 1 +
+ 2 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index dc570ce4e831..2687662f26b6 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -447,7 +447,16 @@ static int __maybe_unused xhci_plat_suspend(struct device *dev)
+ * xhci_suspend() needs `do_wakeup` to know whether host is allowed
+ * to do wakeup during suspend.
+ */
+- return xhci_suspend(xhci, device_may_wakeup(dev));
++ ret = xhci_suspend(xhci, device_may_wakeup(dev));
++ if (ret)
++ return ret;
++
++ if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) {
++ clk_disable_unprepare(xhci->clk);
++ clk_disable_unprepare(xhci->reg_clk);
++ }
++
++ return 0;
+ }
+
+ static int __maybe_unused xhci_plat_resume(struct device *dev)
+@@ -456,6 +465,11 @@ static int __maybe_unused xhci_plat_resume(struct device *dev)
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ int ret;
+
++ if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) {
++ clk_prepare_enable(xhci->clk);
++ clk_prepare_enable(xhci->reg_clk);
++ }
++
+ ret = xhci_priv_resume_quirk(hcd);
+ if (ret)
+ return ret;
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 10a4230d95c3..3b39501f26ea 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1903,6 +1903,7 @@ struct xhci_hcd {
+ #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
+ #define XHCI_BROKEN_D3COLD BIT_ULL(41)
+ #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
++#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
+
+ unsigned int num_active_eps;
+ unsigned int limit_active_eps;
+--
+2.35.1
+
--- /dev/null
+From a0c3a10dc41f835d590d2d4a77e39e76445d9491 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 Aug 2022 15:27:35 -0700
+Subject: usb: host: xhci-plat: suspend/resume clks for brcm
+
+From: Justin Chen <justinpopo6@gmail.com>
+
+[ Upstream commit c69400b09e471a3f1167adead55a808f0da6534a ]
+
+The xhci_plat_brcm xhci block can enter suspend with clock disabled to save
+power and re-enable them on resume. Make use of the XHCI_SUSPEND_RESUME_CLKS
+quirk to do so.
+
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Justin Chen <justinpopo6@gmail.com>
+Link: https://lore.kernel.org/r/1660170455-15781-3-git-send-email-justinpopo6@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/host/xhci-plat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 2687662f26b6..972a44b2a7f1 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -134,7 +134,7 @@ static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
+ };
+
+ static const struct xhci_plat_priv xhci_plat_brcm = {
+- .quirks = XHCI_RESET_ON_RESUME,
++ .quirks = XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS,
+ };
+
+ static const struct of_device_id usb_xhci_of_match[] = {
+--
+2.35.1
+
--- /dev/null
+From 888c47eb90b41b3a4504f0d69d0ff40e35ca5755 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 21:48:44 +0800
+Subject: usb: idmouse: fix an uninit-value in idmouse_open
+
+From: Dongliang Mu <mudongliangabcd@gmail.com>
+
+[ Upstream commit bce2b0539933e485d22d6f6f076c0fcd6f185c4c ]
+
+In idmouse_create_image, if any ftip_command fails, it will
+go to the reset label. However, this leads to the data in
+bulk_in_buffer[HEADER..IMGSIZE] uninitialized. And the check
+for valid image incurs an uninitialized dereference.
+
+Fix this by moving the check before reset label since this
+check only be valid if the data after bulk_in_buffer[HEADER]
+has concrete data.
+
+Note that this is found by KMSAN, so only kernel compilation
+is tested.
+
+Reported-by: syzbot+79832d33eb89fb3cd092@syzkaller.appspotmail.com
+Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com>
+Link: https://lore.kernel.org/r/20220922134847.1101921-1-dzm91@hust.edu.cn
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/misc/idmouse.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/misc/idmouse.c b/drivers/usb/misc/idmouse.c
+index e9437a176518..ea39243efee3 100644
+--- a/drivers/usb/misc/idmouse.c
++++ b/drivers/usb/misc/idmouse.c
+@@ -177,10 +177,6 @@ static int idmouse_create_image(struct usb_idmouse *dev)
+ bytes_read += bulk_read;
+ }
+
+- /* reset the device */
+-reset:
+- ftip_command(dev, FTIP_RELEASE, 0, 0);
+-
+ /* check for valid image */
+ /* right border should be black (0x00) */
+ for (bytes_read = sizeof(HEADER)-1 + WIDTH-1; bytes_read < IMGSIZE; bytes_read += WIDTH)
+@@ -192,6 +188,10 @@ static int idmouse_create_image(struct usb_idmouse *dev)
+ if (dev->bulk_in_buffer[bytes_read] != 0xFF)
+ return -EAGAIN;
+
++ /* reset the device */
++reset:
++ ftip_command(dev, FTIP_RELEASE, 0, 0);
++
+ /* should be IMGSIZE == 65040 */
+ dev_dbg(&dev->interface->dev, "read %d bytes fingerprint data\n",
+ bytes_read);
+--
+2.35.1
+
--- /dev/null
+From d57de08e5b7ab1bdd54a6844f754b292b87b2237 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 Sep 2022 14:44:59 +0800
+Subject: usb: mtu3: fix failed runtime suspend in host only mode
+
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+[ Upstream commit 1c703e29da5efac6180e4c189029fa34b7e48e97 ]
+
+When the dr_mode is "host", after the host enter runtime suspend,
+the mtu3 can't do it, because the mtu3's device wakeup function is
+not enabled, instead it's enabled in gadget init function, to fix
+the issue, init wakeup early in mtu3's probe()
+
+Fixes: 6b587394c65c ("usb: mtu3: support suspend/resume for dual-role mode")
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reported-by: Tianping Fang <tianping.fang@mediatek.com>
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Link: https://lore.kernel.org/r/20220929064459.32522-1-chunfeng.yun@mediatek.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/mtu3/mtu3_core.c | 2 --
+ drivers/usb/mtu3/mtu3_plat.c | 2 ++
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
+index c4a2c37abf62..3ea5145a842b 100644
+--- a/drivers/usb/mtu3/mtu3_core.c
++++ b/drivers/usb/mtu3/mtu3_core.c
+@@ -971,8 +971,6 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
+ goto irq_err;
+ }
+
+- device_init_wakeup(dev, true);
+-
+ /* power down device IP for power saving by default */
+ mtu3_stop(mtu);
+
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index f13531022f4a..4c4dcbf17518 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -332,6 +332,8 @@ static int mtu3_probe(struct platform_device *pdev)
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
++ device_init_wakeup(dev, true);
++
+ ret = ssusb_rscs_init(ssusb);
+ if (ret)
+ goto comm_init_err;
+--
+2.35.1
+
--- /dev/null
+From 54ff97cda96a97c0fbe25807ebdbf9905b9b6423 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Sep 2022 10:21:19 +0800
+Subject: usb: musb: Fix musb_gadget.c rxstate overflow bug
+
+From: Robin Guo <guoweibin@inspur.com>
+
+[ Upstream commit eea4c860c3b366369eff0489d94ee4f0571d467d ]
+
+The usb function device call musb_gadget_queue() adds the passed
+request to musb_ep::req_list,If the (request->length > musb_ep->packet_sz)
+and (is_buffer_mapped(req) return false),the rxstate() will copy all data
+in fifo to request->buf which may cause request->buf out of bounds.
+
+Fix it by add the length check :
+fifocnt = min_t(unsigned, request->length - request->actual, fifocnt);
+
+Signed-off-by: Robin Guo <guoweibin@inspur.com>
+Link: https://lore.kernel.org/r/20220906102119.1b071d07a8391ff115e6d1ef@inspur.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/musb/musb_gadget.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index 51274b87f46c..dc67fff8e941 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -760,6 +760,9 @@ static void rxstate(struct musb *musb, struct musb_request *req)
+ musb_writew(epio, MUSB_RXCSR, csr);
+
+ buffer_aint_mapped:
++ fifo_count = min_t(unsigned int,
++ request->length - request->actual,
++ (unsigned int)fifo_count);
+ musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
+ (request->buf + request->actual));
+ request->actual += fifo_count;
+--
+2.35.1
+
--- /dev/null
+From eba7219babbf4a33191207113d6308d6afbbe729 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 18:48:24 +0800
+Subject: USB: serial: console: move mutex_unlock() before usb_serial_put()
+
+From: Liang He <windhl@126.com>
+
+[ Upstream commit 61dfa797c731754642d1ac500a6ac42f9b47f920 ]
+
+While in current version there is no use-after-free as USB serial
+core holds another reference when the console is registered, we
+should better unlock before dropping the reference in
+usb_console_setup().
+
+Fixes: 7bd032dc2793 ("USB serial: update the console driver")
+Signed-off-by: Liang He <windhl@126.com>
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/serial/console.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c
+index b97aa40ca4d1..da19a5fa414f 100644
+--- a/drivers/usb/serial/console.c
++++ b/drivers/usb/serial/console.c
+@@ -189,8 +189,8 @@ static int usb_console_setup(struct console *co, char *options)
+ info->port = NULL;
+ usb_autopm_put_interface(serial->interface);
+ error_get_interface:
+- usb_serial_put(serial);
+ mutex_unlock(&serial->disc_mutex);
++ usb_serial_put(serial);
+ return retval;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 5c17be3604fc627e09bb2d1ae9e89729bed77955 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 Jul 2022 11:34:51 +0200
+Subject: userfaultfd: open userfaultfds with O_RDONLY
+
+From: Ondrej Mosnacek <omosnace@redhat.com>
+
+[ Upstream commit abec3d015fdfb7c63105c7e1c956188bf381aa55 ]
+
+Since userfaultfd doesn't implement a write operation, it is more
+appropriate to open it read-only.
+
+When userfaultfds are opened read-write like it is now, and such fd is
+passed from one process to another, SELinux will check both read and
+write permissions for the target process, even though it can't actually
+do any write operation on the fd later.
+
+Inspired by the following bug report, which has hit the SELinux scenario
+described above:
+https://bugzilla.redhat.com/show_bug.cgi?id=1974559
+
+Reported-by: Robert O'Callahan <roc@ocallahan.org>
+Fixes: 86039bd3b4e6 ("userfaultfd: add new syscall to provide memory externalization")
+Signed-off-by: Ondrej Mosnacek <omosnace@redhat.com>
+Acked-by: Peter Xu <peterx@redhat.com>
+Acked-by: Christian Brauner (Microsoft) <brauner@kernel.org>
+Signed-off-by: Paul Moore <paul@paul-moore.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/userfaultfd.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c
+index 22bf14ab2d16..b56e8e31d967 100644
+--- a/fs/userfaultfd.c
++++ b/fs/userfaultfd.c
+@@ -982,7 +982,7 @@ static int resolve_userfault_fork(struct userfaultfd_ctx *new,
+ int fd;
+
+ fd = anon_inode_getfd_secure("[userfaultfd]", &userfaultfd_fops, new,
+- O_RDWR | (new->flags & UFFD_SHARED_FCNTL_FLAGS), inode);
++ O_RDONLY | (new->flags & UFFD_SHARED_FCNTL_FLAGS), inode);
+ if (fd < 0)
+ return fd;
+
+@@ -2097,7 +2097,7 @@ SYSCALL_DEFINE1(userfaultfd, int, flags)
+ mmgrab(ctx->mm);
+
+ fd = anon_inode_getfd_secure("[userfaultfd]", &userfaultfd_fops, ctx,
+- O_RDWR | (flags & UFFD_SHARED_FCNTL_FLAGS), NULL);
++ O_RDONLY | (flags & UFFD_SHARED_FCNTL_FLAGS), NULL);
+ if (fd < 0) {
+ mmdrop(ctx->mm);
+ kmem_cache_free(userfaultfd_ctx_cachep, ctx);
+--
+2.35.1
+
--- /dev/null
+From eb6ea04e2995d054b19046947be2d3a0b581f365 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 15:45:38 +0900
+Subject: vhost/vsock: Use kvmalloc/kvfree for larger packets.
+
+From: Junichi Uekawa <uekawa@chromium.org>
+
+[ Upstream commit 0e3f72931fc47bb81686020cc643cde5d9cd0bb8 ]
+
+When copying a large file over sftp over vsock, data size is usually 32kB,
+and kmalloc seems to fail to try to allocate 32 32kB regions.
+
+ vhost-5837: page allocation failure: order:4, mode:0x24040c0
+ Call Trace:
+ [<ffffffffb6a0df64>] dump_stack+0x97/0xdb
+ [<ffffffffb68d6aed>] warn_alloc_failed+0x10f/0x138
+ [<ffffffffb68d868a>] ? __alloc_pages_direct_compact+0x38/0xc8
+ [<ffffffffb664619f>] __alloc_pages_nodemask+0x84c/0x90d
+ [<ffffffffb6646e56>] alloc_kmem_pages+0x17/0x19
+ [<ffffffffb6653a26>] kmalloc_order_trace+0x2b/0xdb
+ [<ffffffffb66682f3>] __kmalloc+0x177/0x1f7
+ [<ffffffffb66e0d94>] ? copy_from_iter+0x8d/0x31d
+ [<ffffffffc0689ab7>] vhost_vsock_handle_tx_kick+0x1fa/0x301 [vhost_vsock]
+ [<ffffffffc06828d9>] vhost_worker+0xf7/0x157 [vhost]
+ [<ffffffffb683ddce>] kthread+0xfd/0x105
+ [<ffffffffc06827e2>] ? vhost_dev_set_owner+0x22e/0x22e [vhost]
+ [<ffffffffb683dcd1>] ? flush_kthread_worker+0xf3/0xf3
+ [<ffffffffb6eb332e>] ret_from_fork+0x4e/0x80
+ [<ffffffffb683dcd1>] ? flush_kthread_worker+0xf3/0xf3
+
+Work around by doing kvmalloc instead.
+
+Fixes: 433fc58e6bf2 ("VSOCK: Introduce vhost_vsock.ko")
+Signed-off-by: Junichi Uekawa <uekawa@chromium.org>
+Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
+Acked-by: Michael S. Tsirkin <mst@redhat.com>
+Link: https://lore.kernel.org/r/20220928064538.667678-1-uekawa@chromium.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/vhost/vsock.c | 2 +-
+ net/vmw_vsock/virtio_transport_common.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c
+index dcb1585819a1..97bfe499222b 100644
+--- a/drivers/vhost/vsock.c
++++ b/drivers/vhost/vsock.c
+@@ -393,7 +393,7 @@ vhost_vsock_alloc_pkt(struct vhost_virtqueue *vq,
+ return NULL;
+ }
+
+- pkt->buf = kmalloc(pkt->len, GFP_KERNEL);
++ pkt->buf = kvmalloc(pkt->len, GFP_KERNEL);
+ if (!pkt->buf) {
+ kfree(pkt);
+ return NULL;
+diff --git a/net/vmw_vsock/virtio_transport_common.c b/net/vmw_vsock/virtio_transport_common.c
+index ec2c2afbf0d0..3a12aee33e92 100644
+--- a/net/vmw_vsock/virtio_transport_common.c
++++ b/net/vmw_vsock/virtio_transport_common.c
+@@ -1342,7 +1342,7 @@ EXPORT_SYMBOL_GPL(virtio_transport_recv_pkt);
+
+ void virtio_transport_free_pkt(struct virtio_vsock_pkt *pkt)
+ {
+- kfree(pkt->buf);
++ kvfree(pkt->buf);
+ kfree(pkt);
+ }
+ EXPORT_SYMBOL_GPL(virtio_transport_free_pkt);
+--
+2.35.1
+
--- /dev/null
+From 3b49be9613943758e169990da97c884c1848596c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Aug 2022 10:19:30 -0400
+Subject: wifi: ath10k: add peer map clean up for peer delete in
+ ath10k_sta_state()
+
+From: Wen Gong <quic_wgong@quicinc.com>
+
+[ Upstream commit f020d9570a04df0762a2ac5c50cf1d8c511c9164 ]
+
+When peer delete failed in a disconnect operation, use-after-free
+detected by KFENCE in below log. It is because for each vdev_id and
+address, it has only one struct ath10k_peer, it is allocated in
+ath10k_peer_map_event(). When connected to an AP, it has more than
+one HTT_T2H_MSG_TYPE_PEER_MAP reported from firmware, then the
+array peer_map of struct ath10k will be set muti-elements to the
+same ath10k_peer in ath10k_peer_map_event(). When peer delete failed
+in ath10k_sta_state(), the ath10k_peer will be free for the 1st peer
+id in array peer_map of struct ath10k, and then use-after-free happened
+for the 2nd peer id because they map to the same ath10k_peer.
+
+And clean up all peers in array peer_map for the ath10k_peer, then
+user-after-free disappeared
+
+peer map event log:
+[ 306.911021] wlan0: authenticate with b0:2a:43:e6:75:0e
+[ 306.957187] ath10k_pci 0000:01:00.0: mac vdev 0 peer create b0:2a:43:e6:75:0e (new sta) sta 1 / 32 peer 1 / 33
+[ 306.957395] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 246
+[ 306.957404] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 198
+[ 306.986924] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 166
+
+peer unmap event log:
+[ 435.715691] wlan0: deauthenticating from b0:2a:43:e6:75:0e by local choice (Reason: 3=DEAUTH_LEAVING)
+[ 435.716802] ath10k_pci 0000:01:00.0: mac vdev 0 peer delete b0:2a:43:e6:75:0e sta ffff990e0e9c2b50 (sta gone)
+[ 435.717177] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 246
+[ 435.717186] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 198
+[ 435.717193] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 166
+
+use-after-free log:
+[21705.888627] wlan0: deauthenticating from d0:76:8f:82:be:75 by local choice (Reason: 3=DEAUTH_LEAVING)
+[21713.799910] ath10k_pci 0000:01:00.0: failed to delete peer d0:76:8f:82:be:75 for vdev 0: -110
+[21713.799925] ath10k_pci 0000:01:00.0: found sta peer d0:76:8f:82:be:75 (ptr 0000000000000000 id 102) entry on vdev 0 after it was supposedly removed
+[21713.799968] ==================================================================
+[21713.799991] BUG: KFENCE: use-after-free read in ath10k_sta_state+0x265/0xb8a [ath10k_core]
+[21713.799991]
+[21713.799997] Use-after-free read at 0x00000000abe1c75e (in kfence-#69):
+[21713.800010] ath10k_sta_state+0x265/0xb8a [ath10k_core]
+[21713.800041] drv_sta_state+0x115/0x677 [mac80211]
+[21713.800059] __sta_info_destroy_part2+0xb1/0x133 [mac80211]
+[21713.800076] __sta_info_flush+0x11d/0x162 [mac80211]
+[21713.800093] ieee80211_set_disassoc+0x12d/0x2f4 [mac80211]
+[21713.800110] ieee80211_mgd_deauth+0x26c/0x29b [mac80211]
+[21713.800137] cfg80211_mlme_deauth+0x13f/0x1bb [cfg80211]
+[21713.800153] nl80211_deauthenticate+0xf8/0x121 [cfg80211]
+[21713.800161] genl_rcv_msg+0x38e/0x3be
+[21713.800166] netlink_rcv_skb+0x89/0xf7
+[21713.800171] genl_rcv+0x28/0x36
+[21713.800176] netlink_unicast+0x179/0x24b
+[21713.800181] netlink_sendmsg+0x3a0/0x40e
+[21713.800187] sock_sendmsg+0x72/0x76
+[21713.800192] ____sys_sendmsg+0x16d/0x1e3
+[21713.800196] ___sys_sendmsg+0x95/0xd1
+[21713.800200] __sys_sendmsg+0x85/0xbf
+[21713.800205] do_syscall_64+0x43/0x55
+[21713.800210] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+[21713.800213]
+[21713.800219] kfence-#69: 0x000000009149b0d5-0x000000004c0697fb, size=1064, cache=kmalloc-2k
+[21713.800219]
+[21713.800224] allocated by task 13 on cpu 0 at 21705.501373s:
+[21713.800241] ath10k_peer_map_event+0x7e/0x154 [ath10k_core]
+[21713.800254] ath10k_htt_t2h_msg_handler+0x586/0x1039 [ath10k_core]
+[21713.800265] ath10k_htt_htc_t2h_msg_handler+0x12/0x28 [ath10k_core]
+[21713.800277] ath10k_htc_rx_completion_handler+0x14c/0x1b5 [ath10k_core]
+[21713.800283] ath10k_pci_process_rx_cb+0x195/0x1df [ath10k_pci]
+[21713.800294] ath10k_ce_per_engine_service+0x55/0x74 [ath10k_core]
+[21713.800305] ath10k_ce_per_engine_service_any+0x76/0x84 [ath10k_core]
+[21713.800310] ath10k_pci_napi_poll+0x49/0x144 [ath10k_pci]
+[21713.800316] net_rx_action+0xdc/0x361
+[21713.800320] __do_softirq+0x163/0x29a
+[21713.800325] asm_call_irq_on_stack+0x12/0x20
+[21713.800331] do_softirq_own_stack+0x3c/0x48
+[21713.800337] __irq_exit_rcu+0x9b/0x9d
+[21713.800342] common_interrupt+0xc9/0x14d
+[21713.800346] asm_common_interrupt+0x1e/0x40
+[21713.800351] ksoftirqd_should_run+0x5/0x16
+[21713.800357] smpboot_thread_fn+0x148/0x211
+[21713.800362] kthread+0x150/0x15f
+[21713.800367] ret_from_fork+0x22/0x30
+[21713.800370]
+[21713.800374] freed by task 708 on cpu 1 at 21713.799953s:
+[21713.800498] ath10k_sta_state+0x2c6/0xb8a [ath10k_core]
+[21713.800515] drv_sta_state+0x115/0x677 [mac80211]
+[21713.800532] __sta_info_destroy_part2+0xb1/0x133 [mac80211]
+[21713.800548] __sta_info_flush+0x11d/0x162 [mac80211]
+[21713.800565] ieee80211_set_disassoc+0x12d/0x2f4 [mac80211]
+[21713.800581] ieee80211_mgd_deauth+0x26c/0x29b [mac80211]
+[21713.800598] cfg80211_mlme_deauth+0x13f/0x1bb [cfg80211]
+[21713.800614] nl80211_deauthenticate+0xf8/0x121 [cfg80211]
+[21713.800619] genl_rcv_msg+0x38e/0x3be
+[21713.800623] netlink_rcv_skb+0x89/0xf7
+[21713.800628] genl_rcv+0x28/0x36
+[21713.800632] netlink_unicast+0x179/0x24b
+[21713.800637] netlink_sendmsg+0x3a0/0x40e
+[21713.800642] sock_sendmsg+0x72/0x76
+[21713.800646] ____sys_sendmsg+0x16d/0x1e3
+[21713.800651] ___sys_sendmsg+0x95/0xd1
+[21713.800655] __sys_sendmsg+0x85/0xbf
+[21713.800659] do_syscall_64+0x43/0x55
+[21713.800663] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+
+Tested-on: QCA6174 hw3.2 PCI WLAN.RM.4.4.1-00288-QCARMSWPZ-1
+
+Fixes: d0eeafad1189 ("ath10k: Clean up peer when sta goes away.")
+Signed-off-by: Wen Gong <quic_wgong@quicinc.com>
+Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
+Link: https://lore.kernel.org/r/20220801141930.16794-1-quic_wgong@quicinc.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ath/ath10k/mac.c | 54 ++++++++++++++-------------
+ 1 file changed, 29 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c
+index 8a80919b627f..8208434d7d2b 100644
+--- a/drivers/net/wireless/ath/ath10k/mac.c
++++ b/drivers/net/wireless/ath/ath10k/mac.c
+@@ -864,11 +864,36 @@ static int ath10k_peer_delete(struct ath10k *ar, u32 vdev_id, const u8 *addr)
+ return 0;
+ }
+
++static void ath10k_peer_map_cleanup(struct ath10k *ar, struct ath10k_peer *peer)
++{
++ int peer_id, i;
++
++ lockdep_assert_held(&ar->conf_mutex);
++
++ for_each_set_bit(peer_id, peer->peer_ids,
++ ATH10K_MAX_NUM_PEER_IDS) {
++ ar->peer_map[peer_id] = NULL;
++ }
++
++ /* Double check that peer is properly un-referenced from
++ * the peer_map
++ */
++ for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) {
++ if (ar->peer_map[i] == peer) {
++ ath10k_warn(ar, "removing stale peer_map entry for %pM (ptr %pK idx %d)\n",
++ peer->addr, peer, i);
++ ar->peer_map[i] = NULL;
++ }
++ }
++
++ list_del(&peer->list);
++ kfree(peer);
++ ar->num_peers--;
++}
++
+ static void ath10k_peer_cleanup(struct ath10k *ar, u32 vdev_id)
+ {
+ struct ath10k_peer *peer, *tmp;
+- int peer_id;
+- int i;
+
+ lockdep_assert_held(&ar->conf_mutex);
+
+@@ -880,25 +905,7 @@ static void ath10k_peer_cleanup(struct ath10k *ar, u32 vdev_id)
+ ath10k_warn(ar, "removing stale peer %pM from vdev_id %d\n",
+ peer->addr, vdev_id);
+
+- for_each_set_bit(peer_id, peer->peer_ids,
+- ATH10K_MAX_NUM_PEER_IDS) {
+- ar->peer_map[peer_id] = NULL;
+- }
+-
+- /* Double check that peer is properly un-referenced from
+- * the peer_map
+- */
+- for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) {
+- if (ar->peer_map[i] == peer) {
+- ath10k_warn(ar, "removing stale peer_map entry for %pM (ptr %pK idx %d)\n",
+- peer->addr, peer, i);
+- ar->peer_map[i] = NULL;
+- }
+- }
+-
+- list_del(&peer->list);
+- kfree(peer);
+- ar->num_peers--;
++ ath10k_peer_map_cleanup(ar, peer);
+ }
+ spin_unlock_bh(&ar->data_lock);
+ }
+@@ -7580,10 +7587,7 @@ static int ath10k_sta_state(struct ieee80211_hw *hw,
+ /* Clean up the peer object as well since we
+ * must have failed to do this above.
+ */
+- list_del(&peer->list);
+- ar->peer_map[i] = NULL;
+- kfree(peer);
+- ar->num_peers--;
++ ath10k_peer_map_cleanup(ar, peer);
+ }
+ }
+ spin_unlock_bh(&ar->data_lock);
+--
+2.35.1
+
--- /dev/null
+From 5cefbba74a78f4f4a636a4ca1096c1b3a4549592 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Sep 2022 18:23:54 +0300
+Subject: wifi: ath10k: reset pointer after memory free to avoid potential
+ use-after-free
+
+From: Wen Gong <quic_wgong@quicinc.com>
+
+[ Upstream commit 1e1cb8e0b73e6f39a9d4a7a15d940b1265387eb5 ]
+
+When running suspend test, kernel crash happened in ath10k, and it is
+fixed by commit b72a4aff947b ("ath10k: skip ath10k_halt during suspend
+for driver state RESTARTING").
+
+Currently the crash is fixed, but as a common code style, it is better
+to set the pointer to NULL after memory is free.
+
+This is to address the code style and it will avoid potential bug of
+use-after-free.
+
+Tested-on: QCA6174 hw3.2 PCI WLAN.RM.4.4.1-00110-QCARMSWP-1
+Signed-off-by: Wen Gong <quic_wgong@quicinc.com>
+Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
+Link: https://lore.kernel.org/r/20220505092248.787-1-quic_wgong@quicinc.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ath/ath10k/htt_rx.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c
+index adbaeb67eedf..9458540b7dde 100644
+--- a/drivers/net/wireless/ath/ath10k/htt_rx.c
++++ b/drivers/net/wireless/ath/ath10k/htt_rx.c
+@@ -297,12 +297,16 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt)
+ ath10k_htt_get_vaddr_ring(htt),
+ htt->rx_ring.base_paddr);
+
++ ath10k_htt_config_paddrs_ring(htt, NULL);
++
+ dma_free_coherent(htt->ar->dev,
+ sizeof(*htt->rx_ring.alloc_idx.vaddr),
+ htt->rx_ring.alloc_idx.vaddr,
+ htt->rx_ring.alloc_idx.paddr);
++ htt->rx_ring.alloc_idx.vaddr = NULL;
+
+ kfree(htt->rx_ring.netbufs_ring);
++ htt->rx_ring.netbufs_ring = NULL;
+ }
+
+ static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
+@@ -823,8 +827,10 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
+ ath10k_htt_get_rx_ring_size(htt),
+ vaddr_ring,
+ htt->rx_ring.base_paddr);
++ ath10k_htt_config_paddrs_ring(htt, NULL);
+ err_dma_ring:
+ kfree(htt->rx_ring.netbufs_ring);
++ htt->rx_ring.netbufs_ring = NULL;
+ err_netbuf:
+ return -ENOMEM;
+ }
+--
+2.35.1
+
--- /dev/null
+From d1b98857bf0022c7aa713adc95808ac6da8b57ce Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 10:35:14 +0300
+Subject: wifi: ath11k: fix number of VHT beamformee spatial streams
+
+From: Jesus Fernandez Manzano <jesus.manzano@galgus.net>
+
+[ Upstream commit 55b5ee3357d7bb98ee578cf9b84a652e7a1bc199 ]
+
+The number of spatial streams used when acting as a beamformee in VHT
+mode are reported by the firmware as 7 (8 sts - 1) both in IPQ6018 and
+IPQ8074 which respectively have 2 and 4 sts each. So the firmware should
+report 1 (2 - 1) and 3 (4 - 1).
+
+Fix this by checking that the number of VHT beamformee sts reported by
+the firmware is not greater than the number of receiving antennas - 1.
+The fix is based on the same approach used in this same function for
+sanitizing the number of sounding dimensions reported by the firmware.
+
+Without this change, acting as a beamformee in VHT mode is not working
+properly.
+
+Tested-on: IPQ6018 hw1.0 AHB WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1
+Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1
+
+Fixes: d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices")
+Signed-off-by: Jesus Fernandez Manzano <jesus.manzano@galgus.net>
+Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
+Link: https://lore.kernel.org/r/20220616173947.21901-1-jesus.manzano@galgus.net
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ath/ath11k/mac.c | 25 ++++++++++++++++++++-----
+ 1 file changed, 20 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath11k/mac.c b/drivers/net/wireless/ath/ath11k/mac.c
+index c7ee373a9d2c..ae6e14fe03c7 100644
+--- a/drivers/net/wireless/ath/ath11k/mac.c
++++ b/drivers/net/wireless/ath/ath11k/mac.c
+@@ -3684,6 +3684,8 @@ static int ath11k_mac_set_txbf_conf(struct ath11k_vif *arvif)
+ if (vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE)) {
+ nsts = vht_cap & IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK;
+ nsts >>= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
++ if (nsts > (ar->num_rx_chains - 1))
++ nsts = ar->num_rx_chains - 1;
+ value |= SM(nsts, WMI_TXBF_STS_CAP_OFFSET);
+ }
+
+@@ -3724,7 +3726,7 @@ static int ath11k_mac_set_txbf_conf(struct ath11k_vif *arvif)
+ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap)
+ {
+ bool subfer, subfee;
+- int sound_dim = 0;
++ int sound_dim = 0, nsts = 0;
+
+ subfer = !!(*vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE));
+ subfee = !!(*vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE));
+@@ -3734,6 +3736,11 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap)
+ subfer = false;
+ }
+
++ if (ar->num_rx_chains < 2) {
++ *vht_cap &= ~(IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE);
++ subfee = false;
++ }
++
+ /* If SU Beaformer is not set, then disable MU Beamformer Capability */
+ if (!subfer)
+ *vht_cap &= ~(IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
+@@ -3746,7 +3753,9 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap)
+ sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
+ *vht_cap &= ~IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
+
+- /* TODO: Need to check invalid STS and Sound_dim values set by FW? */
++ nsts = (*vht_cap & IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK);
++ nsts >>= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
++ *vht_cap &= ~IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK;
+
+ /* Enable Sounding Dimension Field only if SU BF is enabled */
+ if (subfer) {
+@@ -3758,9 +3767,15 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap)
+ *vht_cap |= sound_dim;
+ }
+
+- /* Use the STS advertised by FW unless SU Beamformee is not supported*/
+- if (!subfee)
+- *vht_cap &= ~(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK);
++ /* Enable Beamformee STS Field only if SU BF is enabled */
++ if (subfee) {
++ if (nsts > (ar->num_rx_chains - 1))
++ nsts = ar->num_rx_chains - 1;
++
++ nsts <<= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
++ nsts &= IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK;
++ *vht_cap |= nsts;
++ }
+ }
+
+ static struct ieee80211_sta_vht_cap
+--
+2.35.1
+
--- /dev/null
+From 31265c93d6899e849f5b5d3b21945b61bf52204b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 16 Aug 2022 23:46:13 +0900
+Subject: wifi: ath9k: avoid uninit memory read in ath9k_htc_rx_msg()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+
+[ Upstream commit b383e8abed41cc6ff1a3b34de75df9397fa4878c ]
+
+syzbot is reporting uninit value at ath9k_htc_rx_msg() [1], for
+ioctl(USB_RAW_IOCTL_EP_WRITE) can call ath9k_hif_usb_rx_stream() with
+pkt_len = 0 but ath9k_hif_usb_rx_stream() uses
+__dev_alloc_skb(pkt_len + 32, GFP_ATOMIC) based on an assumption that
+pkt_len is valid. As a result, ath9k_hif_usb_rx_stream() allocates skb
+with uninitialized memory and ath9k_htc_rx_msg() is reading from
+uninitialized memory.
+
+Since bytes accessed by ath9k_htc_rx_msg() is not known until
+ath9k_htc_rx_msg() is called, it would be difficult to check minimal valid
+pkt_len at "if (pkt_len > 2 * MAX_RX_BUF_SIZE) {" line in
+ath9k_hif_usb_rx_stream().
+
+We have two choices. One is to workaround by adding __GFP_ZERO so that
+ath9k_htc_rx_msg() sees 0 if pkt_len is invalid. The other is to let
+ath9k_htc_rx_msg() validate pkt_len before accessing. This patch chose
+the latter.
+
+Note that I'm not sure threshold condition is correct, for I can't find
+details on possible packet length used by this protocol.
+
+Link: https://syzkaller.appspot.com/bug?extid=2ca247c2d60c7023de7f [1]
+Reported-by: syzbot <syzbot+2ca247c2d60c7023de7f@syzkaller.appspotmail.com>
+Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
+Acked-by: Toke Høiland-Jørgensen <toke@toke.dk>
+Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
+Link: https://lore.kernel.org/r/7acfa1be-4b5c-b2ce-de43-95b0593fb3e5@I-love.SAKURA.ne.jp
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ath/ath9k/htc_hst.c | 43 +++++++++++++++---------
+ 1 file changed, 28 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
+index 994ec48b2f66..ca05b07a45e6 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
++++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
+@@ -364,33 +364,27 @@ void ath9k_htc_txcompletion_cb(struct htc_target *htc_handle,
+ }
+
+ static void ath9k_htc_fw_panic_report(struct htc_target *htc_handle,
+- struct sk_buff *skb)
++ struct sk_buff *skb, u32 len)
+ {
+ uint32_t *pattern = (uint32_t *)skb->data;
+
+- switch (*pattern) {
+- case 0x33221199:
+- {
++ if (*pattern == 0x33221199 && len >= sizeof(struct htc_panic_bad_vaddr)) {
+ struct htc_panic_bad_vaddr *htc_panic;
+ htc_panic = (struct htc_panic_bad_vaddr *) skb->data;
+ dev_err(htc_handle->dev, "ath: firmware panic! "
+ "exccause: 0x%08x; pc: 0x%08x; badvaddr: 0x%08x.\n",
+ htc_panic->exccause, htc_panic->pc,
+ htc_panic->badvaddr);
+- break;
+- }
+- case 0x33221299:
+- {
++ return;
++ }
++ if (*pattern == 0x33221299) {
+ struct htc_panic_bad_epid *htc_panic;
+ htc_panic = (struct htc_panic_bad_epid *) skb->data;
+ dev_err(htc_handle->dev, "ath: firmware panic! "
+ "bad epid: 0x%08x\n", htc_panic->epid);
+- break;
+- }
+- default:
+- dev_err(htc_handle->dev, "ath: unknown panic pattern!\n");
+- break;
++ return;
+ }
++ dev_err(htc_handle->dev, "ath: unknown panic pattern!\n");
+ }
+
+ /*
+@@ -411,16 +405,26 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle,
+ if (!htc_handle || !skb)
+ return;
+
++ /* A valid message requires len >= 8.
++ *
++ * sizeof(struct htc_frame_hdr) == 8
++ * sizeof(struct htc_ready_msg) == 8
++ * sizeof(struct htc_panic_bad_vaddr) == 16
++ * sizeof(struct htc_panic_bad_epid) == 8
++ */
++ if (unlikely(len < sizeof(struct htc_frame_hdr)))
++ goto invalid;
+ htc_hdr = (struct htc_frame_hdr *) skb->data;
+ epid = htc_hdr->endpoint_id;
+
+ if (epid == 0x99) {
+- ath9k_htc_fw_panic_report(htc_handle, skb);
++ ath9k_htc_fw_panic_report(htc_handle, skb, len);
+ kfree_skb(skb);
+ return;
+ }
+
+ if (epid < 0 || epid >= ENDPOINT_MAX) {
++invalid:
+ if (pipe_id != USB_REG_IN_PIPE)
+ dev_kfree_skb_any(skb);
+ else
+@@ -432,21 +436,30 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle,
+
+ /* Handle trailer */
+ if (htc_hdr->flags & HTC_FLAGS_RECV_TRAILER) {
+- if (be32_to_cpu(*(__be32 *) skb->data) == 0x00C60000)
++ if (be32_to_cpu(*(__be32 *) skb->data) == 0x00C60000) {
+ /* Move past the Watchdog pattern */
+ htc_hdr = (struct htc_frame_hdr *)(skb->data + 4);
++ len -= 4;
++ }
+ }
+
+ /* Get the message ID */
++ if (unlikely(len < sizeof(struct htc_frame_hdr) + sizeof(__be16)))
++ goto invalid;
+ msg_id = (__be16 *) ((void *) htc_hdr +
+ sizeof(struct htc_frame_hdr));
+
+ /* Now process HTC messages */
+ switch (be16_to_cpu(*msg_id)) {
+ case HTC_MSG_READY_ID:
++ if (unlikely(len < sizeof(struct htc_ready_msg)))
++ goto invalid;
+ htc_process_target_rdy(htc_handle, htc_hdr);
+ break;
+ case HTC_MSG_CONNECT_SERVICE_RESPONSE_ID:
++ if (unlikely(len < sizeof(struct htc_frame_hdr) +
++ sizeof(struct htc_conn_svc_rspmsg)))
++ goto invalid;
+ htc_process_conn_rsp(htc_handle, htc_hdr);
+ break;
+ default:
+--
+2.35.1
+
--- /dev/null
+From 9ca44e0af7e5d58d11d3ed5c77eb0c07244bdf27 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 22 Jul 2022 13:56:28 +0200
+Subject: wifi: brcmfmac: fix invalid address access when enabling SCAN log
+ level
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Wright Feng <wright.feng@cypress.com>
+
+[ Upstream commit aa666b68e73fc06d83c070d96180b9010cf5a960 ]
+
+The variable i is changed when setting random MAC address and causes
+invalid address access when printing the value of pi->reqs[i]->reqid.
+
+We replace reqs index with ri to fix the issue.
+
+[ 136.726473] Unable to handle kernel access to user memory outside uaccess routines at virtual address 0000000000000000
+[ 136.737365] Mem abort info:
+[ 136.740172] ESR = 0x96000004
+[ 136.743359] Exception class = DABT (current EL), IL = 32 bits
+[ 136.749294] SET = 0, FnV = 0
+[ 136.752481] EA = 0, S1PTW = 0
+[ 136.755635] Data abort info:
+[ 136.758514] ISV = 0, ISS = 0x00000004
+[ 136.762487] CM = 0, WnR = 0
+[ 136.765522] user pgtable: 4k pages, 48-bit VAs, pgdp = 000000005c4e2577
+[ 136.772265] [0000000000000000] pgd=0000000000000000
+[ 136.777160] Internal error: Oops: 96000004 [#1] PREEMPT SMP
+[ 136.782732] Modules linked in: brcmfmac(O) brcmutil(O) cfg80211(O) compat(O)
+[ 136.789788] Process wificond (pid: 3175, stack limit = 0x00000000053048fb)
+[ 136.796664] CPU: 3 PID: 3175 Comm: wificond Tainted: G O 4.19.42-00001-g531a5f5 #1
+[ 136.805532] Hardware name: Freescale i.MX8MQ EVK (DT)
+[ 136.810584] pstate: 60400005 (nZCv daif +PAN -UAO)
+[ 136.815429] pc : brcmf_pno_config_sched_scans+0x6cc/0xa80 [brcmfmac]
+[ 136.821811] lr : brcmf_pno_config_sched_scans+0x67c/0xa80 [brcmfmac]
+[ 136.828162] sp : ffff00000e9a3880
+[ 136.831475] x29: ffff00000e9a3890 x28: ffff800020543400
+[ 136.836786] x27: ffff8000b1008880 x26: ffff0000012bf6a0
+[ 136.842098] x25: ffff80002054345c x24: ffff800088d22400
+[ 136.847409] x23: ffff0000012bf638 x22: ffff0000012bf6d8
+[ 136.852721] x21: ffff8000aced8fc0 x20: ffff8000ac164400
+[ 136.858032] x19: ffff00000e9a3946 x18: 0000000000000000
+[ 136.863343] x17: 0000000000000000 x16: 0000000000000000
+[ 136.868655] x15: ffff0000093f3b37 x14: 0000000000000050
+[ 136.873966] x13: 0000000000003135 x12: 0000000000000000
+[ 136.879277] x11: 0000000000000000 x10: ffff000009a61888
+[ 136.884589] x9 : 000000000000000f x8 : 0000000000000008
+[ 136.889900] x7 : 303a32303d726464 x6 : ffff00000a1f957d
+[ 136.895211] x5 : 0000000000000000 x4 : ffff00000e9a3942
+[ 136.900523] x3 : 0000000000000000 x2 : ffff0000012cead8
+[ 136.905834] x1 : ffff0000012bf6d8 x0 : 0000000000000000
+[ 136.911146] Call trace:
+[ 136.913623] brcmf_pno_config_sched_scans+0x6cc/0xa80 [brcmfmac]
+[ 136.919658] brcmf_pno_start_sched_scan+0xa4/0x118 [brcmfmac]
+[ 136.925430] brcmf_cfg80211_sched_scan_start+0x80/0xe0 [brcmfmac]
+[ 136.931636] nl80211_start_sched_scan+0x140/0x308 [cfg80211]
+[ 136.937298] genl_rcv_msg+0x358/0x3f4
+[ 136.940960] netlink_rcv_skb+0xb4/0x118
+[ 136.944795] genl_rcv+0x34/0x48
+[ 136.947935] netlink_unicast+0x264/0x300
+[ 136.951856] netlink_sendmsg+0x2e4/0x33c
+[ 136.955781] __sys_sendto+0x120/0x19c
+
+Signed-off-by: Wright Feng <wright.feng@cypress.com>
+Signed-off-by: Chi-hsien Lin <chi-hsien.lin@cypress.com>
+Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
+Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/20220722115632.620681-4-alvin@pqrs.dk
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../net/wireless/broadcom/brcm80211/brcmfmac/pno.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c
+index fabfbb0b40b0..d0a7465be586 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c
+@@ -158,12 +158,12 @@ static int brcmf_pno_set_random(struct brcmf_if *ifp, struct brcmf_pno_info *pi)
+ struct brcmf_pno_macaddr_le pfn_mac;
+ u8 *mac_addr = NULL;
+ u8 *mac_mask = NULL;
+- int err, i;
++ int err, i, ri;
+
+- for (i = 0; i < pi->n_reqs; i++)
+- if (pi->reqs[i]->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) {
+- mac_addr = pi->reqs[i]->mac_addr;
+- mac_mask = pi->reqs[i]->mac_addr_mask;
++ for (ri = 0; ri < pi->n_reqs; ri++)
++ if (pi->reqs[ri]->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) {
++ mac_addr = pi->reqs[ri]->mac_addr;
++ mac_mask = pi->reqs[ri]->mac_addr_mask;
+ break;
+ }
+
+@@ -185,7 +185,7 @@ static int brcmf_pno_set_random(struct brcmf_if *ifp, struct brcmf_pno_info *pi)
+ pfn_mac.mac[0] |= 0x02;
+
+ brcmf_dbg(SCAN, "enabling random mac: reqid=%llu mac=%pM\n",
+- pi->reqs[i]->reqid, pfn_mac.mac);
++ pi->reqs[ri]->reqid, pfn_mac.mac);
+ err = brcmf_fil_iovar_data_set(ifp, "pfn_macaddr", &pfn_mac,
+ sizeof(pfn_mac));
+ if (err)
+--
+2.35.1
+
--- /dev/null
+From 79bd4ab78ff05cbf986ff072ed1f55260398e005 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Aug 2022 10:49:26 -0700
+Subject: wifi: brcmfmac: fix use-after-free bug in brcmf_netdev_start_xmit()
+
+From: Alexander Coffin <alex.coffin@matician.com>
+
+[ Upstream commit 3f42faf6db431e04bf942d2ebe3ae88975723478 ]
+
+> ret = brcmf_proto_tx_queue_data(drvr, ifp->ifidx, skb);
+
+may be schedule, and then complete before the line
+
+> ndev->stats.tx_bytes += skb->len;
+
+[ 46.912801] ==================================================================
+[ 46.920552] BUG: KASAN: use-after-free in brcmf_netdev_start_xmit+0x718/0x8c8 [brcmfmac]
+[ 46.928673] Read of size 4 at addr ffffff803f5882e8 by task systemd-resolve/328
+[ 46.935991]
+[ 46.937514] CPU: 1 PID: 328 Comm: systemd-resolve Tainted: G O 5.4.199-[REDACTED] #1
+[ 46.947255] Hardware name: [REDACTED]
+[ 46.954568] Call trace:
+[ 46.957037] dump_backtrace+0x0/0x2b8
+[ 46.960719] show_stack+0x24/0x30
+[ 46.964052] dump_stack+0x128/0x194
+[ 46.967557] print_address_description.isra.0+0x64/0x380
+[ 46.972877] __kasan_report+0x1d4/0x240
+[ 46.976723] kasan_report+0xc/0x18
+[ 46.980138] __asan_report_load4_noabort+0x18/0x20
+[ 46.985027] brcmf_netdev_start_xmit+0x718/0x8c8 [brcmfmac]
+[ 46.990613] dev_hard_start_xmit+0x1bc/0xda0
+[ 46.994894] sch_direct_xmit+0x198/0xd08
+[ 46.998827] __qdisc_run+0x37c/0x1dc0
+[ 47.002500] __dev_queue_xmit+0x1528/0x21f8
+[ 47.006692] dev_queue_xmit+0x24/0x30
+[ 47.010366] neigh_resolve_output+0x37c/0x678
+[ 47.014734] ip_finish_output2+0x598/0x2458
+[ 47.018927] __ip_finish_output+0x300/0x730
+[ 47.023118] ip_output+0x2e0/0x430
+[ 47.026530] ip_local_out+0x90/0x140
+[ 47.030117] igmpv3_sendpack+0x14c/0x228
+[ 47.034049] igmpv3_send_cr+0x384/0x6b8
+[ 47.037895] igmp_ifc_timer_expire+0x4c/0x118
+[ 47.042262] call_timer_fn+0x1cc/0xbe8
+[ 47.046021] __run_timers+0x4d8/0xb28
+[ 47.049693] run_timer_softirq+0x24/0x40
+[ 47.053626] __do_softirq+0x2c0/0x117c
+[ 47.057387] irq_exit+0x2dc/0x388
+[ 47.060715] __handle_domain_irq+0xb4/0x158
+[ 47.064908] gic_handle_irq+0x58/0xb0
+[ 47.068581] el0_irq_naked+0x50/0x5c
+[ 47.072162]
+[ 47.073665] Allocated by task 328:
+[ 47.077083] save_stack+0x24/0xb0
+[ 47.080410] __kasan_kmalloc.isra.0+0xc0/0xe0
+[ 47.084776] kasan_slab_alloc+0x14/0x20
+[ 47.088622] kmem_cache_alloc+0x15c/0x468
+[ 47.092643] __alloc_skb+0xa4/0x498
+[ 47.096142] igmpv3_newpack+0x158/0xd78
+[ 47.099987] add_grhead+0x210/0x288
+[ 47.103485] add_grec+0x6b0/0xb70
+[ 47.106811] igmpv3_send_cr+0x2e0/0x6b8
+[ 47.110657] igmp_ifc_timer_expire+0x4c/0x118
+[ 47.115027] call_timer_fn+0x1cc/0xbe8
+[ 47.118785] __run_timers+0x4d8/0xb28
+[ 47.122457] run_timer_softirq+0x24/0x40
+[ 47.126389] __do_softirq+0x2c0/0x117c
+[ 47.130142]
+[ 47.131643] Freed by task 180:
+[ 47.134712] save_stack+0x24/0xb0
+[ 47.138041] __kasan_slab_free+0x108/0x180
+[ 47.142146] kasan_slab_free+0x10/0x18
+[ 47.145904] slab_free_freelist_hook+0xa4/0x1b0
+[ 47.150444] kmem_cache_free+0x8c/0x528
+[ 47.154292] kfree_skbmem+0x94/0x108
+[ 47.157880] consume_skb+0x10c/0x5a8
+[ 47.161466] __dev_kfree_skb_any+0x88/0xa0
+[ 47.165598] brcmu_pkt_buf_free_skb+0x44/0x68 [brcmutil]
+[ 47.171023] brcmf_txfinalize+0xec/0x190 [brcmfmac]
+[ 47.176016] brcmf_proto_bcdc_txcomplete+0x1c0/0x210 [brcmfmac]
+[ 47.182056] brcmf_sdio_sendfromq+0x8dc/0x1e80 [brcmfmac]
+[ 47.187568] brcmf_sdio_dpc+0xb48/0x2108 [brcmfmac]
+[ 47.192529] brcmf_sdio_dataworker+0xc8/0x238 [brcmfmac]
+[ 47.197859] process_one_work+0x7fc/0x1a80
+[ 47.201965] worker_thread+0x31c/0xc40
+[ 47.205726] kthread+0x2d8/0x370
+[ 47.208967] ret_from_fork+0x10/0x18
+[ 47.212546]
+[ 47.214051] The buggy address belongs to the object at ffffff803f588280
+[ 47.214051] which belongs to the cache skbuff_head_cache of size 208
+[ 47.227086] The buggy address is located 104 bytes inside of
+[ 47.227086] 208-byte region [ffffff803f588280, ffffff803f588350)
+[ 47.238814] The buggy address belongs to the page:
+[ 47.243618] page:ffffffff00dd6200 refcount:1 mapcount:0 mapping:ffffff804b6bf800 index:0xffffff803f589900 compound_mapcount: 0
+[ 47.255007] flags: 0x10200(slab|head)
+[ 47.258689] raw: 0000000000010200 ffffffff00dfa980 0000000200000002 ffffff804b6bf800
+[ 47.266439] raw: ffffff803f589900 0000000080190018 00000001ffffffff 0000000000000000
+[ 47.274180] page dumped because: kasan: bad access detected
+[ 47.279752]
+[ 47.281251] Memory state around the buggy address:
+[ 47.286051] ffffff803f588180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ 47.293277] ffffff803f588200: fb fb fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ 47.300502] >ffffff803f588280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+[ 47.307723] ^
+[ 47.314343] ffffff803f588300: fb fb fb fb fb fb fb fb fb fb fc fc fc fc fc fc
+[ 47.321569] ffffff803f588380: fc fc fc fc fc fc fc fc fb fb fb fb fb fb fb fb
+[ 47.328789] ==================================================================
+
+Signed-off-by: Alexander Coffin <alex.coffin@matician.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/20220808174925.3922558-1-alex.coffin@matician.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
+index db5f8535fdb5..e5bae6224521 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
+@@ -295,6 +295,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb,
+ struct brcmf_pub *drvr = ifp->drvr;
+ struct ethhdr *eh;
+ int head_delta;
++ unsigned int tx_bytes = skb->len;
+
+ brcmf_dbg(DATA, "Enter, bsscfgidx=%d\n", ifp->bsscfgidx);
+
+@@ -369,7 +370,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb,
+ ndev->stats.tx_dropped++;
+ } else {
+ ndev->stats.tx_packets++;
+- ndev->stats.tx_bytes += skb->len;
++ ndev->stats.tx_bytes += tx_bytes;
+ }
+
+ /* Return ok: we always eat the packet */
+--
+2.35.1
+
--- /dev/null
+From 3fe8a75ef924b7706e3a2027f58205fe2b86f247 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 12:02:29 +0530
+Subject: wifi: mac80211: allow bw change during channel switch in mesh
+
+From: Hari Chandrakanthan <quic_haric@quicinc.com>
+
+[ Upstream commit 6b75f133fe05c36c52d691ff21545d5757fff721 ]
+
+From 'IEEE Std 802.11-2020 section 11.8.8.4.1':
+ The mesh channel switch may be triggered by the need to avoid
+ interference to a detected radar signal, or to reassign mesh STA
+ channels to ensure the MBSS connectivity.
+
+ A 20/40 MHz MBSS may be changed to a 20 MHz MBSS and a 20 MHz
+ MBSS may be changed to a 20/40 MHz MBSS.
+
+Since the standard allows the change of bandwidth during
+the channel switch in mesh, remove the bandwidth check present in
+ieee80211_set_csa_beacon.
+
+Fixes: c6da674aff94 ("{nl,cfg,mac}80211: enable the triggering of CSA frame in mesh")
+Signed-off-by: Hari Chandrakanthan <quic_haric@quicinc.com>
+Link: https://lore.kernel.org/r/1658903549-21218-1-git-send-email-quic_haric@quicinc.com
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/mac80211/cfg.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
+index 3f625e836a03..4fa216a108ae 100644
+--- a/net/mac80211/cfg.c
++++ b/net/mac80211/cfg.c
+@@ -3384,9 +3384,6 @@ static int ieee80211_set_csa_beacon(struct ieee80211_sub_if_data *sdata,
+ case NL80211_IFTYPE_MESH_POINT: {
+ struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh;
+
+- if (params->chandef.width != sdata->vif.bss_conf.chandef.width)
+- return -EINVAL;
+-
+ /* changes into another band are not supported */
+ if (sdata->vif.bss_conf.chandef.chan->band !=
+ params->chandef.chan->band)
+--
+2.35.1
+
--- /dev/null
+From cbb6083a257c09698c612027e0fc1513b200c581 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Jul 2022 10:26:40 +0200
+Subject: wifi: mt76: mt7615: add mt7615_mutex_acquire/release in
+ mt7615_sta_set_decap_offload
+
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+
+[ Upstream commit 765c69d477a44c088e5d19e7758dfa4db418e3ba ]
+
+Similar to mt7921 driver, introduce mt7615_mutex_acquire/release in
+mt7615_sta_set_decap_offload in order to avoid sending mcu commands
+while the device is in low-power state.
+
+Fixes: d4b98c63d7a77 ("mt76: mt7615: add support for rx decapsulation offload")
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/mediatek/mt76/mt7615/main.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/main.c b/drivers/net/wireless/mediatek/mt76/mt7615/main.c
+index 7c52a4d85cea..8f1338dae211 100644
+--- a/drivers/net/wireless/mediatek/mt76/mt7615/main.c
++++ b/drivers/net/wireless/mediatek/mt76/mt7615/main.c
+@@ -1186,12 +1186,16 @@ static void mt7615_sta_set_decap_offload(struct ieee80211_hw *hw,
+ struct mt7615_dev *dev = mt7615_hw_dev(hw);
+ struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
+
++ mt7615_mutex_acquire(dev);
++
+ if (enabled)
+ set_bit(MT_WCID_FLAG_HDR_TRANS, &msta->wcid.flags);
+ else
+ clear_bit(MT_WCID_FLAG_HDR_TRANS, &msta->wcid.flags);
+
+ mt7615_mcu_set_sta_decap_offload(dev, vif, sta);
++
++ mt7615_mutex_release(dev);
+ }
+
+ #ifdef CONFIG_PM
+--
+2.35.1
+
--- /dev/null
+From 1e6603725b5208c27d303900d4e4c5bd1af27875 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 18 Aug 2022 10:44:07 +0800
+Subject: wifi: mt76: mt7915: do not check state before configuring implicit
+ beamform
+
+From: Howard Hsu <howard-yh.hsu@mediatek.com>
+
+[ Upstream commit d2b5bb6dfab29fe32bedefaade88dcd182c03a00 ]
+
+Do not need to check running state before configuring implicit Tx
+beamform. It is okay to configure implicit Tx beamform in run time.
+Noted that the existing connected stations will be applied for new
+configuration only if they reconnected to the interface.
+
+Fixes: 6d6dc980e07d ("mt76: mt7915: add implicit Tx beamforming support")
+Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+index 64048243e34b..31c1d4bc78dd 100644
+--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
++++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+@@ -12,9 +12,9 @@ mt7915_implicit_txbf_set(void *data, u64 val)
+ {
+ struct mt7915_dev *dev = data;
+
+- if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
+- return -EBUSY;
+-
++ /* The existing connected stations shall reconnect to apply
++ * new implicit txbf configuration.
++ */
+ dev->ibf = !!val;
+
+ return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
+--
+2.35.1
+
--- /dev/null
+From f32ff2a7393b9d353935173e0b34b76c21dcca84 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 06:57:44 +0800
+Subject: wifi: mt76: mt7921: reset msta->airtime_ac while clearing up hw value
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+[ Upstream commit 1bf66dc31032ff5292f4d5b76436653f269fcfbd ]
+
+We should reset mstat->airtime_ac along with clear up the entries in the
+hardware WLAN table for the Rx and Rx accumulative airtime. Otherwsie, the
+value msta->airtime_ac - [tx, rx]_last may be a negative and that is not
+the actual airtime the device took in the last run.
+
+Reported-by: YN Chen <YN.Chen@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/mediatek/mt76/mt7921/main.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/main.c b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
+index 6cb65391427f..7b48df301079 100644
+--- a/drivers/net/wireless/mediatek/mt76/mt7921/main.c
++++ b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
+@@ -627,6 +627,7 @@ void mt7921_mac_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif,
+
+ mt7921_mac_wtbl_update(dev, msta->wcid.idx,
+ MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
++ memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
+
+ mt7921_mcu_sta_update(dev, sta, vif, true, MT76_STA_INFO_STATE_ASSOC);
+
+--
+2.35.1
+
--- /dev/null
+From 75acf95ab0b3a9e23688e03dd930317a30ebfb24 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 23 Jul 2022 05:59:23 +0800
+Subject: wifi: mt76: sdio: fix transmitting packet hangs
+
+From: YN Chen <yn.chen@mediatek.com>
+
+[ Upstream commit 250b1827205846ff346a76044955cb79d4963f70 ]
+
+Fix transmitting packets hangs with continuing to pull the pending packet
+from mac80211 queues when receiving Tx status notification from the device.
+
+Fixes: aac5104bf631 ("mt76: sdio: do not run mt76_txq_schedule directly")
+Acked-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: YN Chen <yn.chen@mediatek.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/mediatek/mt76/sdio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/mediatek/mt76/sdio.c b/drivers/net/wireless/mediatek/mt76/sdio.c
+index 783a15635ec5..9e639d0b9c63 100644
+--- a/drivers/net/wireless/mediatek/mt76/sdio.c
++++ b/drivers/net/wireless/mediatek/mt76/sdio.c
+@@ -213,7 +213,7 @@ static void mt76s_status_worker(struct mt76_worker *w)
+ } while (nframes > 0);
+
+ if (resched)
+- mt76_worker_schedule(&dev->sdio.txrx_worker);
++ mt76_worker_schedule(&dev->tx_worker);
+ }
+
+ static void mt76s_tx_status_data(struct work_struct *work)
+--
+2.35.1
+
--- /dev/null
+From afc5f93bc88ecff71bc3b601f1f4fe5c6cc8d023 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 21:30:09 +0100
+Subject: wifi: rt2x00: correctly set BBP register 86 for MT7620
+
+From: Daniel Golle <daniel@makrotopia.org>
+
+[ Upstream commit c9aada64fe6493461127f1522d7e2f01792d2424 ]
+
+Instead of 0 set the correct value for BBP register 86 for MT7620.
+
+Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/257267247ee4fa7ebc6a5d0c4948b3f8119c0d77.1663445157.git.daniel@makrotopia.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+index d7b862b7bf67..34788bfb34b7 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+@@ -4164,7 +4164,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
+ rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
+ rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
+ rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
+- rt2800_bbp_write(rt2x00dev, 86, 0);
++ if (rt2x00_rt(rt2x00dev, RT6352))
++ rt2800_bbp_write(rt2x00dev, 86, 0x38);
++ else
++ rt2800_bbp_write(rt2x00dev, 86, 0);
+ }
+
+ if (rf->channel <= 14) {
+--
+2.35.1
+
--- /dev/null
+From 869deedf1a07f8ebbcaad7b5584c8243854a994d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 21:28:29 +0100
+Subject: wifi: rt2x00: don't run Rt5592 IQ calibration on MT7620
+
+From: Daniel Golle <daniel@makrotopia.org>
+
+[ Upstream commit d3aad83d05aec0cfd7670cf0028f2ad4b81de92e ]
+
+The function rt2800_iq_calibrate is intended for Rt5592 only.
+Don't call it for MT7620 which has it's own calibration functions.
+
+Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/31a1c34ddbd296b82f38c18c9ae7339059215fdc.1663445157.git.daniel@makrotopia.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+index deddb0afd312..0a47180f321a 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+@@ -4365,7 +4365,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
+ reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
+ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
+
+- rt2800_iq_calibrate(rt2x00dev, rf->channel);
++ if (rt2x00_rt(rt2x00dev, RT5592))
++ rt2800_iq_calibrate(rt2x00dev, rf->channel);
+ }
+
+ bbp = rt2800_bbp_read(rt2x00dev, 4);
+--
+2.35.1
+
--- /dev/null
+From 0ce74e1aa6ae87f7c289bfe21e529666adc52f6b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 21:29:26 +0100
+Subject: wifi: rt2x00: set correct TX_SW_CFG1 MAC register for MT7620
+
+From: Daniel Golle <daniel@makrotopia.org>
+
+[ Upstream commit eeb50acf15762b61921f9df18663f839f387c054 ]
+
+Set correct TX_SW_CFG1 MAC register as it is done also in v3 of the
+vendor driver[1].
+
+[1]: https://gitlab.com/dm38/padavan-ng/-/blob/master/trunk/proprietary/rt_wifi/rtpci/3.0.X.X/mt76x2/chips/rt6352.c#L531
+Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/4be38975ce600a34249e12d09a3cb758c6e71071.1663445157.git.daniel@makrotopia.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+index 0a47180f321a..cc879035acae 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+@@ -5868,7 +5868,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
+ } else if (rt2x00_rt(rt2x00dev, RT6352)) {
+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
+- rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
++ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
+ rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
+--
+2.35.1
+
--- /dev/null
+From e7935595487c2f3af2244fcfb91742f332bab7fd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 21:29:55 +0100
+Subject: wifi: rt2x00: set SoC wmac clock register
+
+From: Daniel Golle <daniel@makrotopia.org>
+
+[ Upstream commit cbde6ed406a51092d9e8a2df058f5f8490f27443 ]
+
+Instead of using the default value 33 (pci), set US_CYC_CNT init based
+on Programming guide:
+If available, set chipset bus clock with fallback to cpu clock/3.
+
+Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/3e275d259f476f597dab91a9c395015ef3fe3284.1663445157.git.daniel@makrotopia.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../net/wireless/ralink/rt2x00/rt2800lib.c | 21 +++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+index 92a5231cdd95..d7b862b7bf67 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+@@ -6131,6 +6131,27 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
+ reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
+ rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
+ rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
++ } else if (rt2x00_is_soc(rt2x00dev)) {
++ struct clk *clk = clk_get_sys("bus", NULL);
++ int rate;
++
++ if (IS_ERR(clk)) {
++ clk = clk_get_sys("cpu", NULL);
++
++ if (IS_ERR(clk)) {
++ rate = 125;
++ } else {
++ rate = clk_get_rate(clk) / 3000000;
++ clk_put(clk);
++ }
++ } else {
++ rate = clk_get_rate(clk) / 1000000;
++ clk_put(clk);
++ }
++
++ reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
++ rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate);
++ rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
+ }
+
+ reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
+--
+2.35.1
+
--- /dev/null
+From eeb70747156ac7a02fe9818befb56df2c5f8ef07 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Sep 2022 21:29:40 +0100
+Subject: wifi: rt2x00: set VGC gain for both chains of MT7620
+
+From: Daniel Golle <daniel@makrotopia.org>
+
+[ Upstream commit 0e09768c085709e10ece3b68f6ac921d3f6a9caa ]
+
+Set bbp66 for all chains of the MT7620.
+
+Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/29e161397e5c9d9399da0fe87d44458aa2b90a78.1663445157.git.daniel@makrotopia.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+index cc879035acae..92a5231cdd95 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+@@ -5645,7 +5645,8 @@ static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
+ if (qual->vgc_level != vgc_level) {
+ if (rt2x00_rt(rt2x00dev, RT3572) ||
+ rt2x00_rt(rt2x00dev, RT3593) ||
+- rt2x00_rt(rt2x00dev, RT3883)) {
++ rt2x00_rt(rt2x00dev, RT3883) ||
++ rt2x00_rt(rt2x00dev, RT6352)) {
+ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
+ vgc_level);
+ } else if (rt2x00_rt(rt2x00dev, RT5592)) {
+--
+2.35.1
+
--- /dev/null
+From eedcbefecdf15e25092266a5eec6a1d882ba0e56 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 18 Sep 2022 15:42:25 +0300
+Subject: wifi: rtl8xxxu: Fix AIFS written to REG_EDCA_*_PARAM
+
+From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+
+[ Upstream commit 5574d3290449916397f3092dcd2bac92415498e1 ]
+
+ieee80211_tx_queue_params.aifs is not supposed to be written directly
+to the REG_EDCA_*_PARAM registers. Instead process it like the vendor
+drivers do. It's kinda hacky but it works.
+
+This change boosts the download speed and makes it more stable.
+
+Tested with RTL8188FU but all the other supported chips should also
+benefit.
+
+Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)")
+Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+Acked-by: Jes Sorensen <jes@trained-monkey.org>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/038cc03f-3567-77ba-a7bd-c4930e3b2fad@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 49 +++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+
+diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+index fb2a5fc1a4e6..e74c885a04e5 100644
+--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+@@ -4507,6 +4507,53 @@ rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
+ return network_type;
+ }
+
++static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
++{
++ u32 reg_edca_param[IEEE80211_NUM_ACS] = {
++ [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,
++ [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,
++ [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,
++ [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,
++ };
++ u32 val32;
++ u16 wireless_mode = 0;
++ u8 aifs, aifsn, sifs;
++ int i;
++
++ if (priv->vif) {
++ struct ieee80211_sta *sta;
++
++ rcu_read_lock();
++ sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid);
++ if (sta)
++ wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);
++ rcu_read_unlock();
++ }
++
++ if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||
++ (wireless_mode & WIRELESS_MODE_N_24G))
++ sifs = 16;
++ else
++ sifs = 10;
++
++ for (i = 0; i < IEEE80211_NUM_ACS; i++) {
++ val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
++
++ /* It was set in conf_tx. */
++ aifsn = val32 & 0xff;
++
++ /* aifsn not set yet or already fixed */
++ if (aifsn < 2 || aifsn > 15)
++ continue;
++
++ aifs = aifsn * slot_time + sifs;
++
++ val32 &= ~0xff;
++ val32 |= aifs;
++ rtl8xxxu_write32(priv, reg_edca_param[i], val32);
++ }
++}
++
+ static void
+ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *bss_conf, u32 changed)
+@@ -4592,6 +4639,8 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ else
+ val8 = 20;
+ rtl8xxxu_write8(priv, REG_SLOT, val8);
++
++ rtl8xxxu_set_aifs(priv, val8);
+ }
+
+ if (changed & BSS_CHANGED_BSSID) {
+--
+2.35.1
+
--- /dev/null
+From e6a379e17ad038ebe9974e02675d7eb13e66c0b2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 19:12:36 +0300
+Subject: wifi: rtl8xxxu: Fix skb misuse in TX queue selection
+
+From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+
+[ Upstream commit edd5747aa12ed61a5ecbfa58d3908623fddbf1e8 ]
+
+rtl8xxxu_queue_select() selects the wrong TX queues because it's
+reading memory from the wrong address. It expects to find ieee80211_hdr
+at skb->data, but that's not the case after skb_push(). Move the call
+to rtl8xxxu_queue_select() before the call to skb_push().
+
+Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)")
+Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/7fa4819a-4f20-b2af-b7a6-8ee01ac49295@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+index 30a2e938d19a..395c31060950 100644
+--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+@@ -4984,6 +4984,8 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
+ if (control && control->sta)
+ sta = control->sta;
+
++ queue = rtl8xxxu_queue_select(hw, skb);
++
+ tx_desc = skb_push(skb, tx_desc_size);
+
+ memset(tx_desc, 0, tx_desc_size);
+@@ -4996,7 +4998,6 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
+ is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
+ tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
+
+- queue = rtl8xxxu_queue_select(hw, skb);
+ tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
+
+ if (tx_info->control.hw_key) {
+--
+2.35.1
+
--- /dev/null
+From 706e8dcd464e457ffd5097eed95c1cfb82f95fd2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 14:48:32 +0300
+Subject: wifi: rtl8xxxu: gen2: Fix mistake in path B IQ calibration
+
+From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+
+[ Upstream commit e963a19c64ac0d2f8785d36a27391abd91ac77aa ]
+
+Found by comparing with the vendor driver. Currently this affects
+only the RTL8192EU, which is the only gen2 chip with 2 TX paths
+supported by this driver. It's unclear what kind of effect the
+mistake had in practice, since I don't have any RTL8192EU devices
+to test it.
+
+Fixes: e1547c535ede ("rtl8xxxu: First stab at adding IQK calibration for 8723bu parts")
+Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/30a59f3a-cfa9-8379-7af0-78a8f4c77cfd@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+index 395c31060950..a74ded84c2ac 100644
+--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+@@ -2925,12 +2925,12 @@ bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
+ }
+
+ if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
+- /* path B RX OK */
++ /* path B TX OK */
+ for (i = 4; i < 6; i++)
+ result[3][i] = result[c1][i];
+ }
+
+- if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
++ if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {
+ /* path B RX OK */
+ for (i = 6; i < 8; i++)
+ result[3][i] = result[c1][i];
+--
+2.35.1
+
--- /dev/null
+From 57a8ce52a9d665d4ae4eb75e9f2e1bf1ddb60d7f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Sep 2022 16:15:30 +0300
+Subject: wifi: rtl8xxxu: Remove copy-paste leftover in gen2_update_rate_mask
+
+From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+
+[ Upstream commit d5350756c03cdf18696295c6b11d7acc4dbf825c ]
+
+It looks like a leftover from copying rtl8xxxu_update_rate_mask,
+which is used with the gen1 chips.
+
+It wasn't causing any problems for my RTL8188FU test device, but it's
+clearly a mistake, so remove it.
+
+Fixes: f653e69009c6 ("rtl8xxxu: Implement basic 8723b specific update_rate_mask() function")
+Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/d5544fe8-9798-28f1-54bd-6839a1974b10@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+index a74ded84c2ac..fb2a5fc1a4e6 100644
+--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+@@ -4338,15 +4338,14 @@ void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
+ h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
+ h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
+
+- h2c.ramask.arg = 0x80;
+ h2c.b_macid_cfg.data1 = rateid;
+ if (sgi)
+ h2c.b_macid_cfg.data1 |= BIT(7);
+
+ h2c.b_macid_cfg.data2 = bw;
+
+- dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
+- __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
++ dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",
++ __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));
+ rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 63134679afc830c92f08788f2a58c8184c644b02 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 19 Aug 2022 08:22:32 +0300
+Subject: wifi: rtl8xxxu: tighten bounds checking in rtl8xxxu_read_efuse()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit 620d5eaeb9059636864bda83ca1c68c20ede34a5 ]
+
+There some bounds checking to ensure that "map_addr" is not out of
+bounds before the start of the loop. But the checking needs to be
+done as we iterate through the loop because "map_addr" gets larger as
+we iterate.
+
+Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Jes Sorensen <Jes.Sorensen@gmail.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/Yv8eGLdBslLAk3Ct@kili
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+index 774341b0005a..30a2e938d19a 100644
+--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+@@ -1874,13 +1874,6 @@ static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
+
+ /* We have 8 bits to indicate validity */
+ map_addr = offset * 8;
+- if (map_addr >= EFUSE_MAP_LEN) {
+- dev_warn(dev, "%s: Illegal map_addr (%04x), "
+- "efuse corrupt!\n",
+- __func__, map_addr);
+- ret = -EINVAL;
+- goto exit;
+- }
+ for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+ /* Check word enable condition in the section */
+ if (word_mask & BIT(i)) {
+@@ -1891,6 +1884,13 @@ static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
+ ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
+ if (ret)
+ goto exit;
++ if (map_addr >= EFUSE_MAP_LEN - 1) {
++ dev_warn(dev, "%s: Illegal map_addr (%04x), "
++ "efuse corrupt!\n",
++ __func__, map_addr);
++ ret = -EINVAL;
++ goto exit;
++ }
+ priv->efuse_wifi.raw[map_addr++] = val8;
+
+ ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
+--
+2.35.1
+
--- /dev/null
+From a0be9fdd70e680cd325c59237a16b6750cf1f7f6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Aug 2022 19:33:45 +0800
+Subject: wifi: rtlwifi: 8192de: correct checking of IQK reload
+
+From: Ping-Ke Shih <pkshih@realtek.com>
+
+[ Upstream commit 93fbc1ebd978cf408ef5765e9c1630fce9a8621b ]
+
+Since IQK could spend time, we make a cache of IQK result matrix that looks
+like iqk_matrix[channel_idx].val[x][y], and we can reload the matrix if we
+have made a cache. To determine a cache is made, we check
+iqk_matrix[channel_idx].val[0][0].
+
+The initial commit 7274a8c22980 ("rtlwifi: rtl8192de: Merge phy routines")
+make a mistake that checks incorrect iqk_matrix[channel_idx].val[0] that
+is always true, and this mistake is found by commit ee3db469dd31
+("wifi: rtlwifi: remove always-true condition pointed out by GCC 12"), so
+I recall the vendor driver to find fix and apply the correctness.
+
+Fixes: 7274a8c22980 ("rtlwifi: rtl8192de: Merge phy routines")
+Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/20220801113345.42016-1-pkshih@realtek.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
+index 743e38a1aa51..4d153bd62c53 100644
+--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
+@@ -2386,11 +2386,10 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
+ "Just Read IQK Matrix reg for channel:%d....\n",
+ channel);
+- _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
+- rtlphy->iqk_matrix[
+- indexforchannel].value, 0,
+- (rtlphy->iqk_matrix[
+- indexforchannel].value[0][2] == 0));
++ if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0)
++ _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
++ rtlphy->iqk_matrix[indexforchannel].value, 0,
++ rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0);
+ if (IS_92D_SINGLEPHY(rtlhal->version)) {
+ if ((rtlphy->iqk_matrix[
+ indexforchannel].value[0][4] != 0)
+--
+2.35.1
+
--- /dev/null
+From ff481bf29b74a18742fea32babd489acbe46b730 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 10:38:17 +0800
+Subject: wifi: rtw88: add missing destroy_workqueue() on error path in
+ rtw_core_init()
+
+From: Yang Yingliang <yangyingliang@huawei.com>
+
+[ Upstream commit b0ea758b30bbdf7c4323c78b7c50c05d2e1224d5 ]
+
+Add the missing destroy_workqueue() before return from rtw_core_init()
+in error path.
+
+Fixes: fe101716c7c9 ("rtw88: replace tx tasklet with work queue")
+Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
+Reviewed-by: Ping-Ke Shih <pkshih@realtek.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/20220826023817.3908255-1-yangyingliang@huawei.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtw88/main.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c
+index 5786995d90d4..d7b7b2cce974 100644
+--- a/drivers/net/wireless/realtek/rtw88/main.c
++++ b/drivers/net/wireless/realtek/rtw88/main.c
+@@ -1869,7 +1869,7 @@ int rtw_core_init(struct rtw_dev *rtwdev)
+ ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
+ if (ret) {
+ rtw_warn(rtwdev, "no firmware loaded\n");
+- return ret;
++ goto out;
+ }
+
+ if (chip->wow_fw_name) {
+@@ -1879,11 +1879,15 @@ int rtw_core_init(struct rtw_dev *rtwdev)
+ wait_for_completion(&rtwdev->fw.completion);
+ if (rtwdev->fw.firmware)
+ release_firmware(rtwdev->fw.firmware);
+- return ret;
++ goto out;
+ }
+ }
+
+ return 0;
++
++out:
++ destroy_workqueue(rtwdev->tx_wq);
++ return ret;
+ }
+ EXPORT_SYMBOL(rtw_core_init);
+
+--
+2.35.1
+
--- /dev/null
+From 8080b5eda66983e2848d063abc706849b0e13ce6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Jul 2022 14:50:03 +0800
+Subject: wifi: rtw88: phy: fix warning of possible buffer overflow
+
+From: Zong-Zhe Yang <kevin_yang@realtek.com>
+
+[ Upstream commit 86331c7e0cd819bf0c1d0dcf895e0c90b0aa9a6f ]
+
+reported by smatch
+
+phy.c:854 rtw_phy_linear_2_db() error: buffer overflow 'db_invert_table[i]'
+8 <= 8 (assuming for loop doesn't break)
+
+However, it seems to be a false alarm because we prevent it originally via
+ if (linear >= db_invert_table[11][7])
+ return 96; /* maximum 96 dB */
+
+Still, we adjust the code to be more readable and avoid smatch warning.
+
+Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
+Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
+Signed-off-by: Kalle Valo <kvalo@kernel.org>
+Link: https://lore.kernel.org/r/20220727065003.28340-5-pkshih@realtek.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/wireless/realtek/rtw88/phy.c | 21 ++++++++-------------
+ 1 file changed, 8 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c
+index 569dd3cfde35..df2edb87468f 100644
+--- a/drivers/net/wireless/realtek/rtw88/phy.c
++++ b/drivers/net/wireless/realtek/rtw88/phy.c
+@@ -751,23 +751,18 @@ static u8 rtw_phy_linear_2_db(u64 linear)
+ u8 j;
+ u32 dB;
+
+- if (linear >= db_invert_table[11][7])
+- return 96; /* maximum 96 dB */
+-
+ for (i = 0; i < 12; i++) {
+- if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7])
+- break;
+- else if (i > 2 && linear <= db_invert_table[i][7])
+- break;
++ for (j = 0; j < 8; j++) {
++ if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
++ goto cnt;
++ else if (i > 2 && linear <= db_invert_table[i][j])
++ goto cnt;
++ }
+ }
+
+- for (j = 0; j < 8; j++) {
+- if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
+- break;
+- else if (i > 2 && linear <= db_invert_table[i][j])
+- break;
+- }
++ return 96; /* maximum 96 dB */
+
++cnt:
+ if (j == 0 && i == 0)
+ goto end;
+
+--
+2.35.1
+
--- /dev/null
+From bb686bdeae033b8b79df46732114b6107f89c8db Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Sep 2022 17:00:54 -0300
+Subject: x86/cpu: Include the header of init_ia32_feat_ctl()'s prototype
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Luciano Leão <lucianorsleao@gmail.com>
+
+[ Upstream commit 30ea703a38ef76ca119673cd8bdd05c6e068e2ac ]
+
+Include the header containing the prototype of init_ia32_feat_ctl(),
+solving the following warning:
+
+ $ make W=1 arch/x86/kernel/cpu/feat_ctl.o
+ arch/x86/kernel/cpu/feat_ctl.c:112:6: warning: no previous prototype for ‘init_ia32_feat_ctl’ [-Wmissing-prototypes]
+ 112 | void init_ia32_feat_ctl(struct cpuinfo_x86 *c)
+
+This warning appeared after commit
+
+ 5d5103595e9e5 ("x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup")
+
+had moved the function init_ia32_feat_ctl()'s prototype from
+arch/x86/kernel/cpu/cpu.h to arch/x86/include/asm/cpu.h.
+
+Note that, before the commit mentioned above, the header include "cpu.h"
+(arch/x86/kernel/cpu/cpu.h) was added by commit
+
+ 0e79ad863df43 ("x86/cpu: Fix a -Wmissing-prototypes warning for init_ia32_feat_ctl()")
+
+solely to fix init_ia32_feat_ctl()'s missing prototype. So, the header
+include "cpu.h" is no longer necessary.
+
+ [ bp: Massage commit message. ]
+
+Fixes: 5d5103595e9e5 ("x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup")
+Signed-off-by: Luciano Leão <lucianorsleao@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Nícolas F. R. A. Prado <n@nfraprado.net>
+Link: https://lore.kernel.org/r/20220922200053.1357470-1-lucianorsleao@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/cpu/feat_ctl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c
+index da696eb4821a..e77032c5f85c 100644
+--- a/arch/x86/kernel/cpu/feat_ctl.c
++++ b/arch/x86/kernel/cpu/feat_ctl.c
+@@ -1,11 +1,11 @@
+ // SPDX-License-Identifier: GPL-2.0
+ #include <linux/tboot.h>
+
++#include <asm/cpu.h>
+ #include <asm/cpufeature.h>
+ #include <asm/msr-index.h>
+ #include <asm/processor.h>
+ #include <asm/vmx.h>
+-#include "cpu.h"
+
+ #undef pr_fmt
+ #define pr_fmt(fmt) "x86/cpu: " fmt
+--
+2.35.1
+
--- /dev/null
+From a43776a1f8ea1e122754d017e679980a7f7f63fb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 Sep 2022 19:45:14 -0700
+Subject: x86/entry: Work around Clang __bdos() bug
+
+From: Kees Cook <keescook@chromium.org>
+
+[ Upstream commit 3e1730842f142add55dc658929221521a9ea62b6 ]
+
+Clang produces a false positive when building with CONFIG_FORTIFY_SOURCE=y
+and CONFIG_UBSAN_BOUNDS=y when operating on an array with a dynamic
+offset. Work around this by using a direct assignment of an empty
+instance. Avoids this warning:
+
+../include/linux/fortify-string.h:309:4: warning: call to __write_overflow_field declared with 'warn
+ing' attribute: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Wat
+tribute-warning]
+ __write_overflow_field(p_size_field, size);
+ ^
+
+which was isolated to the memset() call in xen_load_idt().
+
+Note that this looks very much like another bug that was worked around:
+https://github.com/ClangBuiltLinux/linux/issues/1592
+
+Cc: Juergen Gross <jgross@suse.com>
+Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: Dave Hansen <dave.hansen@linux.intel.com>
+Cc: x86@kernel.org
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: xen-devel@lists.xenproject.org
+Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
+Link: https://lore.kernel.org/lkml/41527d69-e8ab-3f86-ff37-6b298c01d5bc@oracle.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/xen/enlighten_pv.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
+index 133ef31639df..561aad13412f 100644
+--- a/arch/x86/xen/enlighten_pv.c
++++ b/arch/x86/xen/enlighten_pv.c
+@@ -759,6 +759,7 @@ static void xen_load_idt(const struct desc_ptr *desc)
+ {
+ static DEFINE_SPINLOCK(lock);
+ static struct trap_info traps[257];
++ static const struct trap_info zero = { };
+ unsigned out;
+
+ trace_xen_cpu_load_idt(desc);
+@@ -768,7 +769,7 @@ static void xen_load_idt(const struct desc_ptr *desc)
+ memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
+
+ out = xen_convert_trap_info(desc, traps, false);
+- memset(&traps[out], 0, sizeof(traps[0]));
++ traps[out] = zero;
+
+ xen_mc_flush();
+ if (HYPERVISOR_set_trap_table(traps))
+--
+2.35.1
+
--- /dev/null
+From c109ce8e9d10060efd9f604213b2281c4ae5bc50 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 15:37:05 +0200
+Subject: x86/hyperv: Fix 'struct hv_enlightened_vmcs' definition
+
+From: Vitaly Kuznetsov <vkuznets@redhat.com>
+
+[ Upstream commit ea9da788a61e47e7ab9cbad397453e51cd82ac0d ]
+
+Section 1.9 of TLFS v6.0b says:
+
+"All structures are padded in such a way that fields are aligned
+naturally (that is, an 8-byte field is aligned to an offset of 8 bytes
+and so on)".
+
+'struct enlightened_vmcs' has a glitch:
+
+...
+ struct {
+ u32 nested_flush_hypercall:1; /* 836: 0 4 */
+ u32 msr_bitmap:1; /* 836: 1 4 */
+ u32 reserved:30; /* 836: 2 4 */
+ } hv_enlightenments_control; /* 836 4 */
+ u32 hv_vp_id; /* 840 4 */
+ u64 hv_vm_id; /* 844 8 */
+ u64 partition_assist_page; /* 852 8 */
+...
+
+And the observed values in 'partition_assist_page' make no sense at
+all. Fix the layout by padding the structure properly.
+
+Fixes: 68d1eb72ee99 ("x86/hyper-v: define struct hv_enlightened_vmcs and clean field bits")
+Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
+Reviewed-by: Michael Kelley <mikelley@microsoft.com>
+Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
+Signed-off-by: Sean Christopherson <seanjc@google.com>
+Link: https://lore.kernel.org/r/20220830133737.1539624-2-vkuznets@redhat.com
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/include/asm/hyperv-tlfs.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
+index 2322d6bd5883..b54b3e18d94b 100644
+--- a/arch/x86/include/asm/hyperv-tlfs.h
++++ b/arch/x86/include/asm/hyperv-tlfs.h
+@@ -529,7 +529,7 @@ struct hv_enlightened_vmcs {
+ u64 guest_rip;
+
+ u32 hv_clean_fields;
+- u32 hv_padding_32;
++ u32 padding32_1;
+ u32 hv_synthetic_controls;
+ struct {
+ u32 nested_flush_hypercall:1;
+@@ -537,7 +537,7 @@ struct hv_enlightened_vmcs {
+ u32 reserved:30;
+ } __packed hv_enlightenments_control;
+ u32 hv_vp_id;
+-
++ u32 padding32_2;
+ u64 hv_vm_id;
+ u64 partition_assist_page;
+ u64 padding64_4[4];
+--
+2.35.1
+
--- /dev/null
+From 302dba6b57e360e0a6a1d39040e6bc6c1f609c3d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Aug 2022 17:38:51 -0600
+Subject: x86/mce: Retrieve poison range from hardware
+
+From: Jane Chu <jane.chu@oracle.com>
+
+[ Upstream commit f9781bb18ed828e7b83b7bac4a4ad7cd497ee7d7 ]
+
+When memory poison consumption machine checks fire, MCE notifier
+handlers like nfit_handle_mce() record the impacted physical address
+range which is reported by the hardware in the MCi_MISC MSR. The error
+information includes data about blast radius, i.e. how many cachelines
+did the hardware determine are impacted. A recent change
+
+ 7917f9cdb503 ("acpi/nfit: rely on mce->misc to determine poison granularity")
+
+updated nfit_handle_mce() to stop hard coding the blast radius value of
+1 cacheline, and instead rely on the blast radius reported in 'struct
+mce' which can be up to 4K (64 cachelines).
+
+It turns out that apei_mce_report_mem_error() had a similar problem in
+that it hard coded a blast radius of 4K rather than reading the blast
+radius from the error information. Fix apei_mce_report_mem_error() to
+convey the proper poison granularity.
+
+Signed-off-by: Jane Chu <jane.chu@oracle.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Dan Williams <dan.j.williams@intel.com>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Link: https://lore.kernel.org/r/7ed50fd8-521e-cade-77b1-738b8bfb8502@oracle.com
+Link: https://lore.kernel.org/r/20220826233851.1319100-1-jane.chu@oracle.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/cpu/mce/apei.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
+index 0e3ae64d3b76..b08b90cdc2a3 100644
+--- a/arch/x86/kernel/cpu/mce/apei.c
++++ b/arch/x86/kernel/cpu/mce/apei.c
+@@ -29,15 +29,26 @@
+ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
+ {
+ struct mce m;
++ int lsb;
+
+ if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
+ return;
+
++ /*
++ * Even if the ->validation_bits are set for address mask,
++ * to be extra safe, check and reject an error radius '0',
++ * and fall back to the default page size.
++ */
++ if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
++ lsb = find_first_bit((void *)&mem_err->physical_addr_mask, PAGE_SHIFT);
++ else
++ lsb = PAGE_SHIFT;
++
+ mce_setup(&m);
+ m.bank = -1;
+ /* Fake a memory read error with unknown channel */
+ m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
+- m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT;
++ m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb;
+
+ if (severity >= GHES_SEV_RECOVERABLE)
+ m.status |= MCI_STATUS_UC;
+--
+2.35.1
+
--- /dev/null
+From 12b8c22187709406b8fca613e12e3289a39cfbc5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 20:10:10 -0700
+Subject: x86/microcode/AMD: Track patch allocation size explicitly
+
+From: Kees Cook <keescook@chromium.org>
+
+[ Upstream commit 712f210a457d9c32414df246a72781550bc23ef6 ]
+
+In preparation for reducing the use of ksize(), record the actual
+allocation size for later memcpy(). This avoids copying extra
+(uninitialized!) bytes into the patch buffer when the requested
+allocation size isn't exactly the size of a kmalloc bucket.
+Additionally, fix potential future issues where runtime bounds checking
+will notice that the buffer was allocated to a smaller value than
+returned by ksize().
+
+Fixes: 757885e94a22 ("x86, microcode, amd: Early microcode patch loading support for AMD")
+Suggested-by: Daniel Micay <danielmicay@gmail.com>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Link: https://lore.kernel.org/lkml/CA+DvKQ+bp7Y7gmaVhacjv9uF6Ar-o4tet872h4Q8RPYPJjcJQA@mail.gmail.com/
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/include/asm/microcode.h | 1 +
+ arch/x86/kernel/cpu/microcode/amd.c | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
+index fcbfe94903bb..d130d21f4862 100644
+--- a/arch/x86/include/asm/microcode.h
++++ b/arch/x86/include/asm/microcode.h
+@@ -9,6 +9,7 @@
+ struct ucode_patch {
+ struct list_head plist;
+ void *data; /* Intel uses only this one */
++ unsigned int size;
+ u32 patch_id;
+ u16 equiv_cpu;
+ };
+diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
+index 3d4a48336084..5a16844b99d3 100644
+--- a/arch/x86/kernel/cpu/microcode/amd.c
++++ b/arch/x86/kernel/cpu/microcode/amd.c
+@@ -782,6 +782,7 @@ static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
+ kfree(patch);
+ return -EINVAL;
+ }
++ patch->size = *patch_size;
+
+ mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
+ proc_id = mc_hdr->processor_rev_id;
+@@ -863,7 +864,7 @@ load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
+ return ret;
+
+ memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
+- memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
++ memcpy(amd_ucode_patch, p->data, min_t(u32, p->size, PATCH_MAX_SIZE));
+
+ return ret;
+ }
+--
+2.35.1
+
--- /dev/null
+From b2819ea0146927d008c53be21b296aa0a14d7ff0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 Aug 2022 09:44:10 -0700
+Subject: x86/resctrl: Fix to restore to original value when re-enabling
+ hardware prefetch register
+
+From: Kohei Tarumizu <tarumizu.kohei@fujitsu.com>
+
+[ Upstream commit 499c8bb4693d1c8d8f3d6dd38e5bdde3ff5bd906 ]
+
+The current pseudo_lock.c code overwrites the value of the
+MSR_MISC_FEATURE_CONTROL to 0 even if the original value is not 0.
+Therefore, modify it to save and restore the original values.
+
+Fixes: 018961ae5579 ("x86/intel_rdt: Pseudo-lock region creation/removal core")
+Fixes: 443810fe6160 ("x86/intel_rdt: Create debugfs files for pseudo-locking testing")
+Fixes: 8a2fc0e1bc0c ("x86/intel_rdt: More precise L2 hit/miss measurements")
+Signed-off-by: Kohei Tarumizu <tarumizu.kohei@fujitsu.com>
+Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
+Acked-by: Reinette Chatre <reinette.chatre@intel.com>
+Link: https://lkml.kernel.org/r/eb660f3c2010b79a792c573c02d01e8e841206ad.1661358182.git.reinette.chatre@intel.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+index db813f819ad6..4d8398986f78 100644
+--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
++++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+@@ -420,6 +420,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
+ struct pseudo_lock_region *plr = rdtgrp->plr;
+ u32 rmid_p, closid_p;
+ unsigned long i;
++ u64 saved_msr;
+ #ifdef CONFIG_KASAN
+ /*
+ * The registers used for local register variables are also used
+@@ -463,6 +464,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
+ * the buffer and evict pseudo-locked memory read earlier from the
+ * cache.
+ */
++ saved_msr = __rdmsr(MSR_MISC_FEATURE_CONTROL);
+ __wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
+ closid_p = this_cpu_read(pqr_state.cur_closid);
+ rmid_p = this_cpu_read(pqr_state.cur_rmid);
+@@ -514,7 +516,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
+ __wrmsr(IA32_PQR_ASSOC, rmid_p, closid_p);
+
+ /* Re-enable the hardware prefetcher(s) */
+- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0);
++ wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr);
+ local_irq_enable();
+
+ plr->thread_done = 1;
+@@ -871,6 +873,7 @@ bool rdtgroup_pseudo_locked_in_hierarchy(struct rdt_domain *d)
+ static int measure_cycles_lat_fn(void *_plr)
+ {
+ struct pseudo_lock_region *plr = _plr;
++ u32 saved_low, saved_high;
+ unsigned long i;
+ u64 start, end;
+ void *mem_r;
+@@ -879,6 +882,7 @@ static int measure_cycles_lat_fn(void *_plr)
+ /*
+ * Disable hardware prefetchers.
+ */
++ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
+ mem_r = READ_ONCE(plr->kmem);
+ /*
+@@ -895,7 +899,7 @@ static int measure_cycles_lat_fn(void *_plr)
+ end = rdtsc_ordered();
+ trace_pseudo_lock_mem_latency((u32)(end - start));
+ }
+- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0);
++ wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ local_irq_enable();
+ plr->thread_done = 1;
+ wake_up_interruptible(&plr->lock_thread_wq);
+@@ -940,6 +944,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
+ u64 hits_before = 0, hits_after = 0, miss_before = 0, miss_after = 0;
+ struct perf_event *miss_event, *hit_event;
+ int hit_pmcnum, miss_pmcnum;
++ u32 saved_low, saved_high;
+ unsigned int line_size;
+ unsigned int size;
+ unsigned long i;
+@@ -973,6 +978,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
+ /*
+ * Disable hardware prefetchers.
+ */
++ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
+
+ /* Initialize rest of local variables */
+@@ -1031,7 +1037,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
+ */
+ rmb();
+ /* Re-enable hardware prefetchers */
+- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0);
++ wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ local_irq_enable();
+ out_hit:
+ perf_event_release_kernel(hit_event);
+--
+2.35.1
+
--- /dev/null
+From 5d8eac845285c7fdb436c397a291aa8d9d7f95ae Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Sep 2022 16:01:57 +0800
+Subject: xfrm: Reinject transport-mode packets through workqueue
+
+From: Liu Jian <liujian56@huawei.com>
+
+[ Upstream commit 4f4920669d21e1060b7243e5118dc3b71ced1276 ]
+
+The following warning is displayed when the tcp6-multi-diffip11 stress
+test case of the LTP test suite is tested:
+
+watchdog: BUG: soft lockup - CPU#0 stuck for 22s! [ns-tcpserver:48198]
+CPU: 0 PID: 48198 Comm: ns-tcpserver Kdump: loaded Not tainted 6.0.0-rc6+ #39
+Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
+pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+pc : des3_ede_encrypt+0x27c/0x460 [libdes]
+lr : 0x3f
+sp : ffff80000ceaa1b0
+x29: ffff80000ceaa1b0 x28: ffff0000df056100 x27: ffff0000e51e5280
+x26: ffff80004df75030 x25: ffff0000e51e4600 x24: 000000000000003b
+x23: 0000000000802080 x22: 000000000000003d x21: 0000000000000038
+x20: 0000000080000020 x19: 000000000000000a x18: 0000000000000033
+x17: ffff0000e51e4780 x16: ffff80004e2d1448 x15: ffff80004e2d1248
+x14: ffff0000e51e4680 x13: ffff80004e2d1348 x12: ffff80004e2d1548
+x11: ffff80004e2d1848 x10: ffff80004e2d1648 x9 : ffff80004e2d1748
+x8 : ffff80004e2d1948 x7 : 000000000bcaf83d x6 : 000000000000001b
+x5 : ffff80004e2d1048 x4 : 00000000761bf3bf x3 : 000000007f1dd0a3
+x2 : ffff0000e51e4780 x1 : ffff0000e3b9a2f8 x0 : 00000000db44e872
+Call trace:
+ des3_ede_encrypt+0x27c/0x460 [libdes]
+ crypto_des3_ede_encrypt+0x1c/0x30 [des_generic]
+ crypto_cbc_encrypt+0x148/0x190
+ crypto_skcipher_encrypt+0x2c/0x40
+ crypto_authenc_encrypt+0xc8/0xfc [authenc]
+ crypto_aead_encrypt+0x2c/0x40
+ echainiv_encrypt+0x144/0x1a0 [echainiv]
+ crypto_aead_encrypt+0x2c/0x40
+ esp6_output_tail+0x1c8/0x5d0 [esp6]
+ esp6_output+0x120/0x278 [esp6]
+ xfrm_output_one+0x458/0x4ec
+ xfrm_output_resume+0x6c/0x1f0
+ xfrm_output+0xac/0x4ac
+ __xfrm6_output+0x130/0x270
+ xfrm6_output+0x60/0xec
+ ip6_xmit+0x2ec/0x5bc
+ inet6_csk_xmit+0xbc/0x10c
+ __tcp_transmit_skb+0x460/0x8c0
+ tcp_write_xmit+0x348/0x890
+ __tcp_push_pending_frames+0x44/0x110
+ tcp_rcv_established+0x3c8/0x720
+ tcp_v6_do_rcv+0xdc/0x4a0
+ tcp_v6_rcv+0xc24/0xcb0
+ ip6_protocol_deliver_rcu+0xf0/0x574
+ ip6_input_finish+0x48/0x7c
+ ip6_input+0x48/0xc0
+ ip6_rcv_finish+0x80/0x9c
+ xfrm_trans_reinject+0xb0/0xf4
+ tasklet_action_common.constprop.0+0xf8/0x134
+ tasklet_action+0x30/0x3c
+ __do_softirq+0x128/0x368
+ do_softirq+0xb4/0xc0
+ __local_bh_enable_ip+0xb0/0xb4
+ put_cpu_fpsimd_context+0x40/0x70
+ kernel_neon_end+0x20/0x40
+ sha1_base_do_update.constprop.0.isra.0+0x11c/0x140 [sha1_ce]
+ sha1_ce_finup+0x94/0x110 [sha1_ce]
+ crypto_shash_finup+0x34/0xc0
+ hmac_finup+0x48/0xe0
+ crypto_shash_finup+0x34/0xc0
+ shash_digest_unaligned+0x74/0x90
+ crypto_shash_digest+0x4c/0x9c
+ shash_ahash_digest+0xc8/0xf0
+ shash_async_digest+0x28/0x34
+ crypto_ahash_digest+0x48/0xcc
+ crypto_authenc_genicv+0x88/0xcc [authenc]
+ crypto_authenc_encrypt+0xd8/0xfc [authenc]
+ crypto_aead_encrypt+0x2c/0x40
+ echainiv_encrypt+0x144/0x1a0 [echainiv]
+ crypto_aead_encrypt+0x2c/0x40
+ esp6_output_tail+0x1c8/0x5d0 [esp6]
+ esp6_output+0x120/0x278 [esp6]
+ xfrm_output_one+0x458/0x4ec
+ xfrm_output_resume+0x6c/0x1f0
+ xfrm_output+0xac/0x4ac
+ __xfrm6_output+0x130/0x270
+ xfrm6_output+0x60/0xec
+ ip6_xmit+0x2ec/0x5bc
+ inet6_csk_xmit+0xbc/0x10c
+ __tcp_transmit_skb+0x460/0x8c0
+ tcp_write_xmit+0x348/0x890
+ __tcp_push_pending_frames+0x44/0x110
+ tcp_push+0xb4/0x14c
+ tcp_sendmsg_locked+0x71c/0xb64
+ tcp_sendmsg+0x40/0x6c
+ inet6_sendmsg+0x4c/0x80
+ sock_sendmsg+0x5c/0x6c
+ __sys_sendto+0x128/0x15c
+ __arm64_sys_sendto+0x30/0x40
+ invoke_syscall+0x50/0x120
+ el0_svc_common.constprop.0+0x170/0x194
+ do_el0_svc+0x38/0x4c
+ el0_svc+0x28/0xe0
+ el0t_64_sync_handler+0xbc/0x13c
+ el0t_64_sync+0x180/0x184
+
+Get softirq info by bcc tool:
+./softirqs -NT 10
+Tracing soft irq event time... Hit Ctrl-C to end.
+
+15:34:34
+SOFTIRQ TOTAL_nsecs
+block 158990
+timer 20030920
+sched 46577080
+net_rx 676746820
+tasklet 9906067650
+
+15:34:45
+SOFTIRQ TOTAL_nsecs
+block 86100
+sched 38849790
+net_rx 676532470
+timer 1163848790
+tasklet 9409019620
+
+15:34:55
+SOFTIRQ TOTAL_nsecs
+sched 58078450
+net_rx 475156720
+timer 533832410
+tasklet 9431333300
+
+The tasklet software interrupt takes too much time. Therefore, the
+xfrm_trans_reinject executor is changed from tasklet to workqueue. Add add
+spin lock to protect the queue. This reduces the processing flow of the
+tcp_sendmsg function in this scenario.
+
+Fixes: acf568ee859f0 ("xfrm: Reinject transport-mode packets through tasklet")
+Signed-off-by: Liu Jian <liujian56@huawei.com>
+Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/xfrm/xfrm_input.c | 18 +++++++++++++-----
+ 1 file changed, 13 insertions(+), 5 deletions(-)
+
+diff --git a/net/xfrm/xfrm_input.c b/net/xfrm/xfrm_input.c
+index 5f34bc378fdc..3d8668d62e63 100644
+--- a/net/xfrm/xfrm_input.c
++++ b/net/xfrm/xfrm_input.c
+@@ -24,7 +24,8 @@
+ #include "xfrm_inout.h"
+
+ struct xfrm_trans_tasklet {
+- struct tasklet_struct tasklet;
++ struct work_struct work;
++ spinlock_t queue_lock;
+ struct sk_buff_head queue;
+ };
+
+@@ -760,18 +761,22 @@ int xfrm_input_resume(struct sk_buff *skb, int nexthdr)
+ }
+ EXPORT_SYMBOL(xfrm_input_resume);
+
+-static void xfrm_trans_reinject(struct tasklet_struct *t)
++static void xfrm_trans_reinject(struct work_struct *work)
+ {
+- struct xfrm_trans_tasklet *trans = from_tasklet(trans, t, tasklet);
++ struct xfrm_trans_tasklet *trans = container_of(work, struct xfrm_trans_tasklet, work);
+ struct sk_buff_head queue;
+ struct sk_buff *skb;
+
+ __skb_queue_head_init(&queue);
++ spin_lock_bh(&trans->queue_lock);
+ skb_queue_splice_init(&trans->queue, &queue);
++ spin_unlock_bh(&trans->queue_lock);
+
++ local_bh_disable();
+ while ((skb = __skb_dequeue(&queue)))
+ XFRM_TRANS_SKB_CB(skb)->finish(XFRM_TRANS_SKB_CB(skb)->net,
+ NULL, skb);
++ local_bh_enable();
+ }
+
+ int xfrm_trans_queue_net(struct net *net, struct sk_buff *skb,
+@@ -789,8 +794,10 @@ int xfrm_trans_queue_net(struct net *net, struct sk_buff *skb,
+
+ XFRM_TRANS_SKB_CB(skb)->finish = finish;
+ XFRM_TRANS_SKB_CB(skb)->net = net;
++ spin_lock_bh(&trans->queue_lock);
+ __skb_queue_tail(&trans->queue, skb);
+- tasklet_schedule(&trans->tasklet);
++ spin_unlock_bh(&trans->queue_lock);
++ schedule_work(&trans->work);
+ return 0;
+ }
+ EXPORT_SYMBOL(xfrm_trans_queue_net);
+@@ -817,7 +824,8 @@ void __init xfrm_input_init(void)
+ struct xfrm_trans_tasklet *trans;
+
+ trans = &per_cpu(xfrm_trans_tasklet, i);
++ spin_lock_init(&trans->queue_lock);
+ __skb_queue_head_init(&trans->queue);
+- tasklet_setup(&trans->tasklet, xfrm_trans_reinject);
++ INIT_WORK(&trans->work, xfrm_trans_reinject);
+ }
+ }
+--
+2.35.1
+
--- /dev/null
+From 79ce0642652f98ede2bb95ee62b7e9ccfd482837 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 1 Sep 2022 13:12:10 +0600
+Subject: xfrm: Update ipcomp_scratches with NULL when freed
+
+From: Khalid Masum <khalid.masum.92@gmail.com>
+
+[ Upstream commit 8a04d2fc700f717104bfb95b0f6694e448a4537f ]
+
+Currently if ipcomp_alloc_scratches() fails to allocate memory
+ipcomp_scratches holds obsolete address. So when we try to free the
+percpu scratches using ipcomp_free_scratches() it tries to vfree non
+existent vm area. Described below:
+
+static void * __percpu *ipcomp_alloc_scratches(void)
+{
+ ...
+ scratches = alloc_percpu(void *);
+ if (!scratches)
+ return NULL;
+ipcomp_scratches does not know about this allocation failure.
+Therefore holding the old obsolete address.
+ ...
+}
+
+So when we free,
+
+static void ipcomp_free_scratches(void)
+{
+ ...
+ scratches = ipcomp_scratches;
+Assigning obsolete address from ipcomp_scratches
+
+ if (!scratches)
+ return;
+
+ for_each_possible_cpu(i)
+ vfree(*per_cpu_ptr(scratches, i));
+Trying to free non existent page, causing warning: trying to vfree
+existent vm area.
+ ...
+}
+
+Fix this breakage by updating ipcomp_scrtches with NULL when scratches
+is freed
+
+Suggested-by: Herbert Xu <herbert@gondor.apana.org.au>
+Reported-by: syzbot+5ec9bb042ddfe9644773@syzkaller.appspotmail.com
+Tested-by: syzbot+5ec9bb042ddfe9644773@syzkaller.appspotmail.com
+Signed-off-by: Khalid Masum <khalid.masum.92@gmail.com>
+Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/xfrm/xfrm_ipcomp.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/net/xfrm/xfrm_ipcomp.c b/net/xfrm/xfrm_ipcomp.c
+index cb40ff0ff28d..92ad336a83ab 100644
+--- a/net/xfrm/xfrm_ipcomp.c
++++ b/net/xfrm/xfrm_ipcomp.c
+@@ -203,6 +203,7 @@ static void ipcomp_free_scratches(void)
+ vfree(*per_cpu_ptr(scratches, i));
+
+ free_percpu(scratches);
++ ipcomp_scratches = NULL;
+ }
+
+ static void * __percpu *ipcomp_alloc_scratches(void)
+--
+2.35.1
+
--- /dev/null
+From fd344f6b02f1efb86bf6fd24fb0bc4cedb330d7e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Sep 2022 15:34:47 +0300
+Subject: xhci: Don't show warning for reinit on known broken suspend
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit 484d6f7aa3283d082c87654b7fe7a7f725423dfb ]
+
+commit 8b328f8002bc ("xhci: re-initialize the HC during resume if HCE was
+set") introduced a new warning message when the host controller error
+was set and re-initializing.
+
+This is expected behavior on some designs which already set
+`xhci->broken_suspend` so the new warning is alarming to some users.
+
+Modify the code to only show the warning if this was a surprising behavior
+to the XHCI driver.
+
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=216470
+Fixes: 8b328f8002bc ("xhci: re-initialize the HC during resume if HCE was set")
+Reported-by: Artem S. Tashkinov <aros@gmx.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Link: https://lore.kernel.org/r/20220921123450.671459-4-mathias.nyman@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/host/xhci.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 3cac7e40456e..8c7710698428 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -1165,7 +1165,8 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
+ /* re-initialize the HC on Restore Error, or Host Controller Error */
+ if (temp & (STS_SRE | STS_HCE)) {
+ reinit_xhc = true;
+- xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
++ if (!xhci->broken_suspend)
++ xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
+ }
+
+ if (reinit_xhc) {
+--
+2.35.1
+
--- /dev/null
+From 27115acd078fe0ffa586c640644ccb890ed2e569 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 Aug 2022 14:17:05 +0200
+Subject: xsk: Fix backpressure mechanism on Tx
+
+From: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
+
+[ Upstream commit c00c4461689e15ac2cc3b9a595a54e4d8afd3d77 ]
+
+Commit d678cbd2f867 ("xsk: Fix handling of invalid descriptors in XSK TX
+batching API") fixed batch API usage against set of descriptors with
+invalid ones but introduced a problem when AF_XDP SW rings are smaller
+than HW ones. Mismatch of reported Tx'ed frames between HW generator and
+user space app was observed. It turned out that backpressure mechanism
+became a bottleneck when the amount of produced descriptors to CQ is
+lower than what we grabbed from XSK Tx ring.
+
+Say that 512 entries had been taken from XSK Tx ring but we had only 490
+free entries in CQ. Then callsite (ZC driver) will produce only 490
+entries onto HW Tx ring but 512 entries will be released from Tx ring
+and this is what will be seen by the user space.
+
+In order to fix this case, mix XSK Tx/CQ ring interractions by moving
+around internal functions and changing call order:
+
+* pull out xskq_prod_nb_free() from xskq_prod_reserve_addr_batch()
+ up to xsk_tx_peek_release_desc_batch();
+** move xskq_cons_release_n() into xskq_cons_read_desc_batch()
+
+After doing so, algorithm can be described as follows:
+
+1. lookup Tx entries
+2. use value from 1. to reserve space in CQ (*)
+3. Read from Tx ring as much descriptors as value from 2
+ 3a. release descriptors from XSK Tx ring (**)
+4. Finally produce addresses to CQ
+
+Fixes: d678cbd2f867 ("xsk: Fix handling of invalid descriptors in XSK TX batching API")
+Signed-off-by: Magnus Karlsson <magnus.karlsson@intel.com>
+Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Link: https://lore.kernel.org/bpf/20220830121705.8618-1-maciej.fijalkowski@intel.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/xdp/xsk.c | 22 +++++++++++-----------
+ net/xdp/xsk_queue.h | 22 ++++++++++------------
+ 2 files changed, 21 insertions(+), 23 deletions(-)
+
+diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c
+index 10c302f9c6d7..330dd498fc61 100644
+--- a/net/xdp/xsk.c
++++ b/net/xdp/xsk.c
+@@ -370,16 +370,15 @@ static u32 xsk_tx_peek_release_fallback(struct xsk_buff_pool *pool, u32 max_entr
+ return nb_pkts;
+ }
+
+-u32 xsk_tx_peek_release_desc_batch(struct xsk_buff_pool *pool, u32 max_entries)
++u32 xsk_tx_peek_release_desc_batch(struct xsk_buff_pool *pool, u32 nb_pkts)
+ {
+ struct xdp_sock *xs;
+- u32 nb_pkts;
+
+ rcu_read_lock();
+ if (!list_is_singular(&pool->xsk_tx_list)) {
+ /* Fallback to the non-batched version */
+ rcu_read_unlock();
+- return xsk_tx_peek_release_fallback(pool, max_entries);
++ return xsk_tx_peek_release_fallback(pool, nb_pkts);
+ }
+
+ xs = list_first_or_null_rcu(&pool->xsk_tx_list, struct xdp_sock, tx_list);
+@@ -388,12 +387,7 @@ u32 xsk_tx_peek_release_desc_batch(struct xsk_buff_pool *pool, u32 max_entries)
+ goto out;
+ }
+
+- max_entries = xskq_cons_nb_entries(xs->tx, max_entries);
+- nb_pkts = xskq_cons_read_desc_batch(xs->tx, pool, max_entries);
+- if (!nb_pkts) {
+- xs->tx->queue_empty_descs++;
+- goto out;
+- }
++ nb_pkts = xskq_cons_nb_entries(xs->tx, nb_pkts);
+
+ /* This is the backpressure mechanism for the Tx path. Try to
+ * reserve space in the completion queue for all packets, but
+@@ -401,12 +395,18 @@ u32 xsk_tx_peek_release_desc_batch(struct xsk_buff_pool *pool, u32 max_entries)
+ * packets. This avoids having to implement any buffering in
+ * the Tx path.
+ */
+- nb_pkts = xskq_prod_reserve_addr_batch(pool->cq, pool->tx_descs, nb_pkts);
++ nb_pkts = xskq_prod_nb_free(pool->cq, nb_pkts);
+ if (!nb_pkts)
+ goto out;
+
+- xskq_cons_release_n(xs->tx, max_entries);
++ nb_pkts = xskq_cons_read_desc_batch(xs->tx, pool, nb_pkts);
++ if (!nb_pkts) {
++ xs->tx->queue_empty_descs++;
++ goto out;
++ }
++
+ __xskq_cons_release(xs->tx);
++ xskq_prod_write_addr_batch(pool->cq, pool->tx_descs, nb_pkts);
+ xs->sk.sk_write_space(&xs->sk);
+
+ out:
+diff --git a/net/xdp/xsk_queue.h b/net/xdp/xsk_queue.h
+index 0e59b4611f18..51db44bd0b60 100644
+--- a/net/xdp/xsk_queue.h
++++ b/net/xdp/xsk_queue.h
+@@ -201,6 +201,11 @@ static inline bool xskq_cons_read_desc(struct xsk_queue *q,
+ return false;
+ }
+
++static inline void xskq_cons_release_n(struct xsk_queue *q, u32 cnt)
++{
++ q->cached_cons += cnt;
++}
++
+ static inline u32 xskq_cons_read_desc_batch(struct xsk_queue *q, struct xsk_buff_pool *pool,
+ u32 max)
+ {
+@@ -222,6 +227,8 @@ static inline u32 xskq_cons_read_desc_batch(struct xsk_queue *q, struct xsk_buff
+ cached_cons++;
+ }
+
++ /* Release valid plus any invalid entries */
++ xskq_cons_release_n(q, cached_cons - q->cached_cons);
+ return nb_entries;
+ }
+
+@@ -287,11 +294,6 @@ static inline void xskq_cons_release(struct xsk_queue *q)
+ q->cached_cons++;
+ }
+
+-static inline void xskq_cons_release_n(struct xsk_queue *q, u32 cnt)
+-{
+- q->cached_cons += cnt;
+-}
+-
+ static inline u32 xskq_cons_present_entries(struct xsk_queue *q)
+ {
+ /* No barriers needed since data is not accessed */
+@@ -346,21 +348,17 @@ static inline int xskq_prod_reserve_addr(struct xsk_queue *q, u64 addr)
+ return 0;
+ }
+
+-static inline u32 xskq_prod_reserve_addr_batch(struct xsk_queue *q, struct xdp_desc *descs,
+- u32 max)
++static inline void xskq_prod_write_addr_batch(struct xsk_queue *q, struct xdp_desc *descs,
++ u32 nb_entries)
+ {
+ struct xdp_umem_ring *ring = (struct xdp_umem_ring *)q->ring;
+- u32 nb_entries, i, cached_prod;
+-
+- nb_entries = xskq_prod_nb_free(q, max);
++ u32 i, cached_prod;
+
+ /* A, matches D */
+ cached_prod = q->cached_prod;
+ for (i = 0; i < nb_entries; i++)
+ ring->desc[cached_prod++ & q->ring_mask] = descs[i].addr;
+ q->cached_prod = cached_prod;
+-
+- return nb_entries;
+ }
+
+ static inline int xskq_prod_reserve_desc(struct xsk_queue *q,
+--
+2.35.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
