]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
clk: zynqmp: Enable clock driver support for all boards
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Fri, 3 Feb 2017 18:26:52 +0000 (23:56 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 8 Feb 2017 07:20:21 +0000 (08:20 +0100)
Add clock driver support for all ZynqMP boards

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
19 files changed:
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
arch/arm/dts/zynqmp-zcu100-revA.dts
arch/arm/dts/zynqmp-zcu100.dts
arch/arm/dts/zynqmp-zcu102.dts
arch/arm/dts/zynqmp-zcu106.dts
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
configs/xilinx_zynqmp_zcu100_defconfig
configs/xilinx_zynqmp_zcu100_revA_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig
configs/xilinx_zynqmp_zcu106_defconfig

index c13bf2ced6004a2a5f07bff26596c11c204e3a68..d9acd29d511e272734b337a951b717a068f792b7 100644 (file)
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/phy/phy.h>
 
 / {
index 32847e1a66ea8cc82cd846c8036800d19947c836..bae514f994f37d57e7f2c695ae931c935d7354b4 100644 (file)
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm016-dc2 RevA";
index fdb774a73fa59a9d3a11f2e7a1ee8508e5e9cb7d..fd89ba7666a4e990b1ae079f8bdc2cb07e42a052 100644 (file)
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm017-dc3 RevA";
index 1f03a94820e241601c5c5e32a2968cad6923e276..05b803be836bad8dc207f0f19ed099a2df0f8acc 100644 (file)
@@ -14,7 +14,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm018-dc4";
index 698e72e0c5d0c18c46b1410eea0f7ddb854ace9e..9b03eaff681d7e57802bb9d6c27a1af30bd8a2c1 100644 (file)
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 / {
        model = "ZynqMP zc1751-xm019-dc5 RevA";
        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
index 7ea6aecab65d1f8a5e1a5566bea0fb87c53053b1..151b58a4499230bc3586b9c10554f6c31e9a6b3f 100644 (file)
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
index 53f96b16a92d182bf130b36d72696d453ad1c161..0b41ff5b848a37f256cd770108ae475b9921e158 100644 (file)
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
index c0e5f1774fb19b701b315146ab72474426a8e8c3..4df60619704466df61cd42ec189309afeed87326 100644 (file)
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
 
index 6b78fdca20e4dadde4454d5ad152313c828a0c2b..557d1ce1fcfe9eec46883f7e3a43c70c8d5ec425 100644 (file)
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
 
index 0d991f47fc6284204a3f08cf654cd89f7c77008d..3a853d8e1a633b5b9f5f8b5839b74a882ec326e2 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index 5ebc3695f5e33c1b4c1de52c3bca3a4e7efce0f1..a6589a5370b68f8600fb0149d7ae71aef4819d02 100644 (file)
@@ -36,6 +36,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index 4f551bc747ed901bdb55863badd6078e08539bb9..2b21c697aa9667df83e7d6bf4929500c98f818d1 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_SCSI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index 7c75abbe9713ba99608b5eadc46b36769e4aef62..e5b8d613b73cdfbd5e4670b3b3098b074976b8b1 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
index 401c0d676f6b0bda4ca876788dff66fdd5ee288d..33d2086bec92a9fd0ba4cc4fb6e0063d5e86c39e 100644 (file)
@@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
index 326b35a9637b1b0446818aee9738bc955bec2829..e778c98ceb312656f4211550f91a8f79042ad9bd 100644 (file)
@@ -35,6 +35,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index e1dfe1897cad919d483ea1f3e742bb449335ab33..fb491463e4dbd0c5ad54cdb3f50e5e7d726ced2b 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index 7d820ddbf1154b49c4a89c48bc08711fad0f2e41..93c25122a683fff76ff3ce1f0b6b74fff6131377 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_SCSI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index 5f05bde80c04279ad91ec38f3c07a0fdf10619a3..a1e01c9b36eb6331571f89cf384e8c9c571c0196 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_SCSI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
index ddcccf71373262e0b5c76bdca428bfe4249b4dab..320503a1cdc6279a3ee185edb757b8dcbb07e603 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_SCSI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y