arm64: dts: qcom: talos: add the GPU SMMU node

Add the Adreno GPU SMMU node for Talos chipset.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312-qcs615-spin-2-v8-1-fca38edcd6e6@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 9be1e523e9cee2573f9eb3e10b2c73b3fc247183..7fe354c4710f80f8d71c0da216c84b026e9598e8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1846,6 +1846,31 @@
                        #power-domain-cells = <1>;
                };
 
+               adreno_smmu: iommu@50a0000 {
+                       compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu",
+                                    "qcom,smmu-500", "arm,mmu-500";
+                       reg = <0x0 0x050a0000 0x0 0x40000>;
+                       #iommu-cells = <2>;
+                       #global-interrupts = <1>;
+                       interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+                       clock-names = "mem",
+                                     "hlos",
+                                     "iface";
+                       power-domains = <&gpucc CX_GDSC>;
+                       dma-coherent;
+               };
+
                stm@6002000 {
                        compatible = "arm,coresight-stm", "arm,primecell";
                        reg = <0x0 0x06002000 0x0 0x1000>,