iio: frequency: adf4350: Fix ADF4350_REG3_12BIT_CLKDIV_MODE

The clk div bits (2 bits wide) do not start in bit 16 but in bit 15. Fix it
accordingly.

Fixes: e31166f0fd48 ("iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers")
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250829-adf4350-fix-v2-2-0bf543ba797d@analog.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/include/linux/iio/frequency/adf4350.h b/include/linux/iio/frequency/adf4350.h
index de45cf2ee1e4f8278a02cb2efb1540662023d9fb..ce2086f97e3fcf609d77de0bc2c15d5d47f7baae 100644 (file)
--- a/include/linux/iio/frequency/adf4350.h
+++ b/include/linux/iio/frequency/adf4350.h
@@ -51,7 +51,7 @@
 
 /* REG3 Bit Definitions */
 #define ADF4350_REG3_12BIT_CLKDIV(x)           ((x) << 3)
-#define ADF4350_REG3_12BIT_CLKDIV_MODE(x)      ((x) << 16)
+#define ADF4350_REG3_12BIT_CLKDIV_MODE(x)      ((x) << 15)
 #define ADF4350_REG3_12BIT_CSR_EN              (1 << 18)
 #define ADF4351_REG3_CHARGE_CANCELLATION_EN    (1 << 21)
 #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN      (1 << 22)