net/mlx5: Add IFC bit for TIR/SQ order capability

Before this cap, firmware requested a certain creation order between TIR
objects and SQs of the same transport domain to properly support the
self loopback prevention feature. If order is not preserved, explicit
modify_tir operations are necessary after the opening of the SQs.

When set, this cap bit indicates that this firmware requirement /
limitation no longer holds.

Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1758521191-814350-2-git-send-email-tariqt@nvidia.com
Reviewed-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 0cf187e13defa902dd4e1b3368c0016c93b23c16..c0f5fee7a4a59de627eb8808eac58bf4e5e9a585 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1895,7 +1895,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         reserved_at_2a0[0x7];
        u8         mkey_pcie_tph[0x1];
-       u8         reserved_at_2a8[0x2];
+       u8         reserved_at_2a8[0x1];
+       u8         tis_tir_td_order[0x1];
 
        u8         psp[0x1];
        u8         shampo[0x1];