arm64: dts: qcom: ipq5018: Add MDIO buses

IPQ5018 contains two mdio buses of which one bus is used to control the
SoC's internal GE PHY, while the other bus is connected to external PHYs
or switches.

There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
simply add the mdio nodes for them.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index baf583c75e769967a96912e7ea6eacf1877a3269..6e93495ce14c716085274520b94abc5a8288c2f8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -185,6 +185,30 @@
                        status = "disabled";
                };
 
+               mdio0: mdio@88000 {
+                       compatible = "qcom,ipq5018-mdio";
+                       reg = <0x00088000 0x64>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       clocks = <&gcc GCC_MDIO0_AHB_CLK>;
+                       clock-names = "gcc_mdio_ahb_clk";
+
+                       status = "disabled";
+               };
+
+               mdio1: mdio@90000 {
+                       compatible = "qcom,ipq5018-mdio";
+                       reg = <0x00090000 0x64>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       clocks = <&gcc GCC_MDIO1_AHB_CLK>;
+                       clock-names = "gcc_mdio_ahb_clk";
+
+                       status = "disabled";
+               };
+
                qfprom: qfprom@a0000 {
                        compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
                        reg = <0x000a0000 0x1000>;