--- /dev/null
+From 401c90c4d64f2227fc2f4c02d2ad23296bf5ca6f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 27 Aug 2024 14:13:10 -0400
+Subject: drm/amd/display: Block dynamic IPS2 on DCN35 for incompatible FW versions
+
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+
+commit 401c90c4d64f2227fc2f4c02d2ad23296bf5ca6f upstream.
+
+[WHY]
+Hangs with Z8 can occur if running an older unfixed PMFW version.
+
+[HOW]
+Fallback to RCG only for dynamic IPS2 states if it's not newer than
+93.12. Limit to DCN35.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Charlene Liu <charlene.liu@amd.com>
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+@@ -1204,6 +1204,12 @@ void dcn35_clk_mgr_construct(
+ ctx->dc->debug.disable_dpp_power_gate = false;
+ ctx->dc->debug.disable_hubp_power_gate = false;
+ ctx->dc->debug.disable_dsc_power_gate = false;
++
++ /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
++ if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
++ ctx->dce_version == DCN_VERSION_3_5 &&
++ ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
++ ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+ } else {
+ /*let's reset the config control flag*/
+ ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
--- /dev/null
+From 0765b2afc1118a6ab5fee624e206c782d70db28a Mon Sep 17 00:00:00 2001
+From: Dillon Varone <dillon.varone@amd.com>
+Date: Mon, 26 Aug 2024 17:08:33 -0400
+Subject: drm/amd/display: Block timing sync for different output formats in pmo
+
+From: Dillon Varone <dillon.varone@amd.com>
+
+commit 0765b2afc1118a6ab5fee624e206c782d70db28a upstream.
+
+[WHY & HOW]
+If the output format is different for HDMI TMDS signals, they are not
+synchronizable.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
+Signed-off-by: Dillon Varone <dillon.varone@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+@@ -810,9 +810,11 @@ static void build_synchronized_timing_gr
+ /* find synchronizable timing groups */
+ for (j = i + 1; j < display_config->display_config.num_streams; j++) {
+ if (memcmp(master_timing,
+- &display_config->display_config.stream_descriptors[j].timing,
+- sizeof(struct dml2_timing_cfg)) == 0 &&
+- display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) {
++ &display_config->display_config.stream_descriptors[j].timing,
++ sizeof(struct dml2_timing_cfg)) == 0 &&
++ display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder &&
++ (display_config->display_config.stream_descriptors[i].output.output_encoder != dml2_hdmi || //hdmi requires formats match
++ display_config->display_config.stream_descriptors[i].output.output_format == display_config->display_config.stream_descriptors[j].output.output_format)) {
+ set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);
+ set_bit_in_bitfield(&stream_mapped_mask, j);
+ }
--- /dev/null
+From 3766a840e093d30e1a2522f650d8a6ac892a8719 Mon Sep 17 00:00:00 2001
+From: Martin Tsai <martin.tsai@amd.com>
+Date: Mon, 22 Jul 2024 14:12:25 +0800
+Subject: drm/amd/display: Clean up dsc blocks in accelerated mode
+
+From: Martin Tsai <martin.tsai@amd.com>
+
+commit 3766a840e093d30e1a2522f650d8a6ac892a8719 upstream.
+
+[WHY]
+DSC on eDP could be enabled during VBIOS post. The enabled
+DSC may not be disabled when enter to OS, once the system was
+in second screen only mode before entering to S4. In this
+case, OS will not send setTimings to reset eDP path again.
+
+The enabled DSC HW will make a new stream without DSC cannot
+output normally if it reused this pipe with enabled DSC.
+
+[HOW]
+In accelerated mode, to clean up DSC blocks if eDP is on link
+but not active when we are not in fast boot and seamless boot.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Charlene Liu <charlene.liu@amd.com>
+Signed-off-by: Martin Tsai <martin.tsai@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 50 ++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+@@ -57,6 +57,7 @@
+ #include "panel_cntl.h"
+ #include "dc_state_priv.h"
+ #include "dpcd_defs.h"
++#include "dsc.h"
+ /* include DCE11 register header files */
+ #include "dce/dce_11_0_d.h"
+ #include "dce/dce_11_0_sh_mask.h"
+@@ -1815,6 +1816,48 @@ static void get_edp_links_with_sink(
+ }
+ }
+
++static void clean_up_dsc_blocks(struct dc *dc)
++{
++ struct display_stream_compressor *dsc = NULL;
++ struct timing_generator *tg = NULL;
++ struct stream_encoder *se = NULL;
++ struct dccg *dccg = dc->res_pool->dccg;
++ struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
++ int i;
++
++ if (dc->ctx->dce_version != DCN_VERSION_3_5 &&
++ dc->ctx->dce_version != DCN_VERSION_3_51)
++ return;
++
++ for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
++ struct dcn_dsc_state s = {0};
++
++ dsc = dc->res_pool->dscs[i];
++ dsc->funcs->dsc_read_state(dsc, &s);
++ if (s.dsc_fw_en) {
++ /* disable DSC in OPTC */
++ if (i < dc->res_pool->timing_generator_count) {
++ tg = dc->res_pool->timing_generators[i];
++ tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);
++ }
++ /* disable DSC in stream encoder */
++ if (i < dc->res_pool->stream_enc_count) {
++ se = dc->res_pool->stream_enc[i];
++ se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);
++ se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);
++ }
++ /* disable DSC block */
++ if (dccg->funcs->set_ref_dscclk)
++ dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
++ dsc->funcs->dsc_disable(dsc);
++
++ /* power down DSC */
++ if (pg_cntl != NULL)
++ pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
++ }
++ }
++}
++
+ /*
+ * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
+ * 1. Power down all DC HW blocks
+@@ -1917,6 +1960,13 @@ void dce110_enable_accelerated_mode(stru
+ clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+
+ power_down_all_hw_blocks(dc);
++
++ /* DSC could be enabled on eDP during VBIOS post.
++ * To clean up dsc blocks if eDP is in link but not active.
++ */
++ if (edp_link_with_sink && (edp_stream_num == 0))
++ clean_up_dsc_blocks(dc);
++
+ disable_vga_and_power_gate_all_controllers(dc);
+ if (edp_link_with_sink && !keep_edp_vdd_on)
+ dc->hwss.edp_power_control(edp_link_with_sink, false);
--- /dev/null
+From ae5100805f98641ea4112241e350485c97936bbe Mon Sep 17 00:00:00 2001
+From: Sung Joon Kim <Sungjoon.Kim@amd.com>
+Date: Tue, 27 Aug 2024 14:49:44 -0400
+Subject: drm/amd/display: Disable SYMCLK32_LE root clock gating
+
+From: Sung Joon Kim <Sungjoon.Kim@amd.com>
+
+commit ae5100805f98641ea4112241e350485c97936bbe upstream.
+
+[WHY & HOW]
+On display on sequence, enabling SYMCLK32_LE root clock gating
+causes issue in link training so disabling it is needed.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+@@ -736,7 +736,7 @@ static const struct dc_debug_options deb
+ .hdmichar = true,
+ .dpstream = true,
+ .symclk32_se = true,
+- .symclk32_le = true,
++ .symclk32_le = false,
+ .symclk_fe = true,
+ .physymclk = false,
+ .dpiasymclk = true,
--- /dev/null
+From f57b77d667dc6bd2b114d08d04b03869539209f6 Mon Sep 17 00:00:00 2001
+From: Yihan Zhu <Yihan.Zhu@amd.com>
+Date: Mon, 26 Aug 2024 14:44:04 -0400
+Subject: drm/amd/display: Enable DML2 override_det_buffer_size_kbytes
+
+From: Yihan Zhu <Yihan.Zhu@amd.com>
+
+commit f57b77d667dc6bd2b114d08d04b03869539209f6 upstream.
+
+[WHY]
+Corrupted screen will be observed when 4k144 DP/HDMI display and
+4k144 eDP are connected, changing eDP refresh rate from 60Hz to 144Hz.
+
+[HOW]
+override_det_buffer_size_kbytes should be true for DCN35/DCN351.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Roman Li <roman.li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+@@ -2153,6 +2153,7 @@ static bool dcn35_resource_construct(
+
+ dc->dml2_options.max_segments_per_hubp = 24;
+ dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
++ dc->dml2_options.override_det_buffer_size_kbytes = true;
+
+ if (dc->config.sdpif_request_limit_words_per_umc == 0)
+ dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
+--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+@@ -2133,6 +2133,7 @@ static bool dcn351_resource_construct(
+
+ dc->dml2_options.max_segments_per_hubp = 24;
+ dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
++ dc->dml2_options.override_det_buffer_size_kbytes = true;
+
+ if (dc->config.sdpif_request_limit_words_per_umc == 0)
+ dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
--- /dev/null
+From f510dd5c210bf8cc22e4be48cbbda3cb754219f5 Mon Sep 17 00:00:00 2001
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Date: Tue, 3 Sep 2024 10:10:44 -0400
+Subject: drm/amd/display: Fix underflow when setting underscan on DCN401
+
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+
+commit f510dd5c210bf8cc22e4be48cbbda3cb754219f5 upstream.
+
+[WHY & HOW]
+When underscan is set through xrandr, it causes the stream destination
+rect to change in a way it becomes complicated to handle the calculations
+for subvp. Since this is a corner case, disable subvp when underscan is
+set.
+
+Fix the existing check that is supposed to catch this corner case by
+adding a check based on the parameters in the stream
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Dillon Varone <dillon.varone@amd.com>
+Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
+Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+@@ -859,7 +859,9 @@ static void populate_dml21_plane_config_
+
+ plane->immediate_flip = plane_state->flip_immediate;
+
+- plane->composition.rect_out_height_spans_vactive = plane_state->dst_rect.height >= stream->timing.v_addressable;
++ plane->composition.rect_out_height_spans_vactive =
++ plane_state->dst_rect.height >= stream->timing.v_addressable &&
++ stream->dst.height >= stream->timing.v_addressable;
+ }
+
+ //TODO : Could be possibly moved to a common helper layer.
--- /dev/null
+From c03fca619fc687338a3b6511fdbed94096abdf79 Mon Sep 17 00:00:00 2001
+From: Robin Chen <robin.chen@amd.com>
+Date: Fri, 23 Aug 2024 15:00:28 +0800
+Subject: drm/amd/display: Round calculated vtotal
+
+From: Robin Chen <robin.chen@amd.com>
+
+commit c03fca619fc687338a3b6511fdbed94096abdf79 upstream.
+
+[WHY]
+The calculated vtotal may has 1 line deviation. To get precisely
+vtotal number, round the vtotal result.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Anthony Koo <anthony.koo@amd.com>
+Signed-off-by: Robin Chen <robin.chen@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -134,7 +134,7 @@ unsigned int mod_freesync_calc_v_total_f
+
+ v_total = div64_u64(div64_u64(((unsigned long long)(
+ frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
+- stream->timing.h_total), 1000000);
++ stream->timing.h_total) + 500000, 1000000);
+
+ /* v_total cannot be less than nominal */
+ if (v_total < stream->timing.v_total) {
--- /dev/null
+From 4bdc5b504af7de1f649004cfdd37445d36db6703 Mon Sep 17 00:00:00 2001
+From: Zhikai Zhai <zhikai.zhai@amd.com>
+Date: Tue, 27 Aug 2024 14:06:01 +0800
+Subject: drm/amd/display: Skip to enable dsc if it has been off
+
+From: Zhikai Zhai <zhikai.zhai@amd.com>
+
+commit 4bdc5b504af7de1f649004cfdd37445d36db6703 upstream.
+
+[WHY]
+It makes DSC enable when we commit the stream which need
+keep power off, and then it will skip to disable DSC if
+pipe reset at this situation as power has been off. It may
+cause the DSC unexpected enable on the pipe with the
+next new stream which doesn't support DSC.
+
+[HOW]
+Check the DSC used on current pipe status when update stream.
+Skip to enable if it has been off. The operation enable
+DSC should happen when set power on.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
+Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 13 +++++++++++++
+ 2 files changed, 27 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+@@ -1029,6 +1029,20 @@ void dcn32_update_dsc_on_stream(struct p
+ struct dsc_config dsc_cfg;
+ struct dsc_optc_config dsc_optc_cfg = {0};
+ enum optc_dsc_mode optc_dsc_mode;
++ struct dcn_dsc_state dsc_state = {0};
++
++ if (!dsc) {
++ DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++ return;
++ }
++
++ if (dsc->funcs->dsc_read_state) {
++ dsc->funcs->dsc_read_state(dsc, &dsc_state);
++ if (!dsc_state.dsc_fw_en) {
++ DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++ return;
++ }
++ }
+
+ /* Enable DSC hw block */
+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
+--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+@@ -375,7 +375,20 @@ static void update_dsc_on_stream(struct
+ struct dsc_config dsc_cfg;
+ struct dsc_optc_config dsc_optc_cfg = {0};
+ enum optc_dsc_mode optc_dsc_mode;
++ struct dcn_dsc_state dsc_state = {0};
+
++ if (!dsc) {
++ DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++ return;
++ }
++
++ if (dsc->funcs->dsc_read_state) {
++ dsc->funcs->dsc_read_state(dsc, &dsc_state);
++ if (!dsc_state.dsc_fw_en) {
++ DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++ return;
++ }
++ }
+ /* Enable DSC hw block */
+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
+ dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
--- /dev/null
+From 199888aa25b3a3315360224bda9134a9b58c9306 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Thu, 5 Sep 2024 14:22:30 -0400
+Subject: drm/amd/display: Update IPS default mode for DCN35/DCN351
+
+From: Roman Li <Roman.Li@amd.com>
+
+commit 199888aa25b3a3315360224bda9134a9b58c9306 upstream.
+
+[WHY]
+RCG state of IPX in idle is more stable for DCN351 and some variants of
+DCN35 than IPS2.
+
+[HOW]
+Rework dm_get_default_ips_mode() to specify default per ASIC and update
+DCN35/DCN351 defaults accordingly.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 ++++++++++++++--------
+ 1 file changed, 33 insertions(+), 17 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1756,25 +1756,41 @@ static struct dml2_soc_bb *dm_dmub_get_v
+ static enum dmub_ips_disable_type dm_get_default_ips_mode(
+ struct amdgpu_device *adev)
+ {
+- /*
+- * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
+- * cause a hard hang. A fix exists for newer PMFW.
+- *
+- * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
+- * IPS state in all cases, except for s0ix and all displays off (DPMS),
+- * where IPS2 is allowed.
+- *
+- * When checking pmfw version, use the major and minor only.
+- */
+- if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&
+- (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
+- return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
++ enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;
+
+- if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
+- return DMUB_IPS_ENABLE;
++ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
++ case IP_VERSION(3, 5, 0):
++ /*
++ * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
++ * cause a hard hang. A fix exists for newer PMFW.
++ *
++ * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
++ * IPS state in all cases, except for s0ix and all displays off (DPMS),
++ * where IPS2 is allowed.
++ *
++ * When checking pmfw version, use the major and minor only.
++ */
++ if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
++ ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
++ else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))
++ /*
++ * Other ASICs with DCN35 that have residency issues with
++ * IPS2 in idle.
++ * We want them to use IPS2 only in display off cases.
++ */
++ ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
++ break;
++ case IP_VERSION(3, 5, 1):
++ ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
++ break;
++ default:
++ /* ASICs older than DCN35 do not have IPSs */
++ if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
++ ret = DMUB_IPS_DISABLE_ALL;
++ break;
++ }
+
+- /* ASICs older than DCN35 do not have IPSs */
+- return DMUB_IPS_DISABLE_ALL;
++ return ret;
+ }
+
+ static int amdgpu_dm_init(struct amdgpu_device *adev)
--- /dev/null
+From 327e62f47eb57ae5ff63de82b0815557104e439a Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Fri, 13 Sep 2024 13:00:39 -0500
+Subject: drm/amd/display: Validate backlight caps are sane
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit 327e62f47eb57ae5ff63de82b0815557104e439a upstream.
+
+Currently amdgpu takes backlight caps provided by the ACPI tables
+on systems as is. If the firmware sets maximums that are too low
+this means that users don't get a good experience.
+
+To avoid having to maintain a quirk list of such systems, do a sanity
+check on the values. Check that the spread is at least half of the
+values that amdgpu would use if no ACPI table was found and if not
+use the amdgpu defaults.
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3020
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4441,6 +4441,7 @@ static int amdgpu_dm_mode_config_init(st
+
+ #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
+ #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
++#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
+ #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
+
+ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
+@@ -4455,6 +4456,21 @@ static void amdgpu_dm_update_backlight_c
+ return;
+
+ amdgpu_acpi_get_backlight_caps(&caps);
++
++ /* validate the firmware value is sane */
++ if (caps.caps_valid) {
++ int spread = caps.max_input_signal - caps.min_input_signal;
++
++ if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
++ caps.min_input_signal < AMDGPU_DM_DEFAULT_MIN_BACKLIGHT ||
++ spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
++ spread < AMDGPU_DM_MIN_SPREAD) {
++ DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",
++ caps.min_input_signal, caps.max_input_signal);
++ caps.caps_valid = false;
++ }
++ }
++
+ if (caps.caps_valid) {
+ dm->backlight_caps[bl_idx].caps_valid = true;
+ if (caps.aux_support)
drm-amdgpu-mes12-switch-set_shader_debugger-pkt-to-mes-schq-pipe.patch
drm-amdgpu-fix-selfring-initialization-sequence-on-soc24.patch
drm-amd-display-add-hdmi-dsc-native-ycbcr422-support.patch
+drm-amd-display-round-calculated-vtotal.patch
+drm-amd-display-clean-up-dsc-blocks-in-accelerated-mode.patch
+drm-amd-display-block-timing-sync-for-different-output-formats-in-pmo.patch
+drm-amd-display-validate-backlight-caps-are-sane.patch
+drm-amd-display-disable-symclk32_le-root-clock-gating.patch
+drm-amd-display-block-dynamic-ips2-on-dcn35-for-incompatible-fw-versions.patch
+drm-amd-display-enable-dml2-override_det_buffer_size_kbytes.patch
+drm-amd-display-skip-to-enable-dsc-if-it-has-been-off.patch
+drm-amd-display-fix-underflow-when-setting-underscan-on-dcn401.patch
+drm-amd-display-update-ips-default-mode-for-dcn35-dcn351.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
