pinctrl: mediatek: Drop bogus slew rate register range for MT8192

[ Upstream commit e15ab05a6b3ed42f2f43f8bd1a1abdbde64afecd ]

The MT8192 does not support configuring pin slew rate. This is evident
from both the datasheet, and the fact that the driver points the slew
rate register range at the GPIO direction register range.

Drop the bogus setting.

Fixes: d32f38f2a8fc ("pinctrl: mediatek: Add pinctrl driver for mt8192")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240131071910.3950450-2-wenst@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
index e3a76381f7f4eeef03b2c808ada00f9761f5f322..3f8a9dbcb70418bf044eafa83778dac2eccf0d67 100644 (file)
--- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
@@ -1379,7 +1379,6 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
        [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8192_pin_dir_range),
        [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8192_pin_di_range),
        [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8192_pin_do_range),
-       [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8192_pin_dir_range),
        [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8192_pin_smt_range),
        [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8192_pin_ies_range),
        [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8192_pin_pu_range),