fpga: Clean coding style violations

Synchronization with mainline version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index f8185431e7e1c24daf6b5d27ed4a010d23aae52c..fe324ab2d5af15f5c3395bc6f603090659b0efb4 100644 (file)
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
@@ -87,14 +89,14 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                                        __FUNCTION__);
 #endif
                        break;
-               case Xilinx_Zynq:
+               case xilinx_zynq:
 #if defined(CONFIG_FPGA_ZYNQPL)
                        PRINTF("%s: Launching the Zynq PL Loader...\n",
-                                       __func__);
+                              __func__);
                        ret_val = zynq_load(desc, buf, bsize);
 #else
                        printf("%s: No support for Zynq devices.\n",
-                                       __func__);
+                              __func__);
 #endif
                        break;
 
@@ -144,14 +146,14 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
                                        __FUNCTION__);
 #endif
                        break;
-               case Xilinx_Zynq:
+               case xilinx_zynq:
 #if defined(CONFIG_FPGA_ZYNQPL)
                        PRINTF("%s: Launching the Zynq PL Reader...\n",
-                                       __func__);
+                              __func__);
                        ret_val = zynq_dump(desc, buf, bsize);
 #else
                        printf("%s: No support for Zynq devices.\n",
-                                       __func__);
+                              __func__);
 #endif
                        break;
 
@@ -179,7 +181,7 @@ int xilinx_info (Xilinx_desc * desc)
                case Xilinx_Virtex2:
                        printf ("Virtex-II\n");
                        break;
-               case Xilinx_Zynq:
+               case xilinx_zynq:
                        printf("Zynq PL\n");
                        break;
                        /* Add new family types here */
@@ -249,13 +251,13 @@ int xilinx_info (Xilinx_desc * desc)
                                                __FUNCTION__);
 #endif
                                break;
-                       case Xilinx_Zynq:
+                       case xilinx_zynq:
 #if defined(CONFIG_FPGA_ZYNQPL)
                                zynq_info(desc);
 #else
                                /* just in case */
                                printf("%s: No support for Zynq devices.\n",
-                                               __func__);
+                                      __func__);
 #endif
                                /* Add new family types here */
                        default:

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 693199bf0c9c2a0aa03f9efde6a4369b5f48540c..036580370ad9a18cd64e7ecfe6a59834ee187032 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
  *
@@ -19,7 +21,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
  */
 
 #include <common.h>
@@ -88,7 +89,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
        /* Check bitstream size */
        if (bsize != desc->size) {
                printf("Error: File size is wrong - should be %x.\n",
-                                                               desc->size);
+                      desc->size);
                return FPGA_FAIL;
        }
 
@@ -189,9 +190,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
                        debug("Error: isr = 0x%08X\n", isr_status);
                        debug("Write count = 0x%08X\n",
-                               readl(&devcfg_base->write_count));
+                             readl(&devcfg_base->write_count));
                        debug("Read count = 0x%08X\n",
-                               readl(&devcfg_base->read_count));
+                             readl(&devcfg_base->read_count));
 
                        return FPGA_FAIL;
                }

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index f1f182edfb9e243757a500f2a85255f1ad0213a3..38f04f642b93197c3135cd094b714907e516c8a6 100644 (file)
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -88,6 +88,12 @@
 # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
 #endif
 
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY

diff --git a/include/xilinx.h b/include/xilinx.h
index 4cf53cbfb9de0d6249b23bd401994ec9157eb37a..592cbea1f301ad452f904621f41dc77786a3d1d2 100644 (file)
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -71,7 +71,7 @@ typedef enum {                        /* typedef Xilinx_Family */
        Xilinx_VirtexE,         /* Virtex-E Family */
        Xilinx_Virtex2,         /* Virtex2 Family */
        Xilinx_Spartan3,        /* Spartan-III Family */
-       Xilinx_Zynq,            /* Zynq Family */
+       xilinx_zynq,            /* Zynq Family */
        max_xilinx_type         /* insert all new types before this */
 } Xilinx_Family;               /* end, typedef Xilinx_Family */
 

diff --git a/include/zynqpl.h b/include/zynqpl.h
index c9629e149e3cc3ec9e6f0a6808de6eac6608382a..bc9b94815950616db1ca60768a673f964096e3ea 100644 (file)
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
  *
@@ -19,7 +21,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
  */
 
 #ifndef _ZYNQPL_H_
@@ -36,25 +37,23 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_ZYNQ_7030       0xc
 #define XILINX_ZYNQ_7045       0x11
 
-/* Device Image Sizes
- *********************************************************************/
+/* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE    16669920/8
 #define XILINX_XC7Z020_SIZE    32364512/8
 #define XILINX_XC7Z030_SIZE    47839328/8
 #define XILINX_XC7Z045_SIZE    106571232/8
 
-/* Descriptor Macros
- *********************************************************************/
+/* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
-{ Xilinx_Zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie }
 
 #define XILINX_XC7Z020_DESC(cookie) \
-{ Xilinx_Zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie }
 
 #define XILINX_XC7Z030_DESC(cookie) \
-{ Xilinx_Zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie }
 
 #define XILINX_XC7Z045_DESC(cookie) \
-{ Xilinx_Zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie }
 
 #endif /* _ZYNQPL_H_ */