drm/amdgpu: Implement get_xgmi_info callback for mmhub_v4_2

Query memory region assignment and address via mmhub

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
index 1ca9d4ed8063a61a6713bf5054273a333248e126..92918101a95d17d2353a3adf9e83669e69420cdb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
@@ -63,6 +63,7 @@ struct amdgpu_mmhub_funcs {
                                uint64_t page_table_base);
        void (*update_power_gating)(struct amdgpu_device *adev,
                                 bool enable);
+       int (*get_xgmi_info)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_mmhub {

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
index 60bba87e42a01efb29e35dc33d9a0db99bc9d7d4..b025c1fdc52c33115e7a3107c9d2bcc8f1f3d847 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
@@ -72,6 +72,45 @@ static const char *mmhub_client_ids_v4_2_0[][2] = {
        [23][1] = "VCN1",
 };
 
+static int mmhub_v4_2_0_get_xgmi_info(struct amdgpu_device *adev)
+{
+       u32 max_num_physical_nodes;
+       u32 max_physical_node_id;
+       u32 xgmi_lfb_cntl;
+       u32 max_region;
+       u64 seg_size;
+
+       /* limit this callback to A + A configuration only */
+       if (!adev->gmc.xgmi.connected_to_cpu)
+               return 0;
+
+       xgmi_lfb_cntl = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),
+                                    regMMMC_VM_XGMI_LFB_CNTL);
+       seg_size = REG_GET_FIELD(
+               RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMMMC_VM_XGMI_LFB_SIZE),
+               MMMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+       max_region =
+               REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
+
+       max_num_physical_nodes   = 4;
+       max_physical_node_id     = 3;
+
+       adev->gmc.xgmi.num_physical_nodes = max_region + 1;
+
+       if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
+               return -EINVAL;
+
+       adev->gmc.xgmi.physical_node_id =
+               REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
+
+       if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
+               return -EINVAL;
+
+       adev->gmc.xgmi.node_segment_size = seg_size;
+
+       return 0;
+}
+
 static u64 mmhub_v4_2_0_get_fb_location(struct amdgpu_device *adev)
 {
        u64 base;
@@ -884,6 +923,7 @@ const struct amdgpu_mmhub_funcs mmhub_v4_2_0_funcs = {
        .set_fault_enable_default = mmhub_v4_2_0_set_fault_enable_default,
        .set_clockgating = mmhub_v4_2_0_set_clockgating,
        .get_clockgating = mmhub_v4_2_0_get_clockgating,
+       .get_xgmi_info = mmhub_v4_2_0_get_xgmi_info,
 };
 
 static int mmhub_v4_2_0_xcp_resume(void *handle, uint32_t inst_mask)