--- /dev/null
+From 4d9c5b89cf3605bbc39c6e274351ff25f0d83e6a Mon Sep 17 00:00:00 2001
+From: Christoffer Dall <christoffer.dall@linaro.org>
+Date: Sun, 2 Feb 2014 22:21:31 +0100
+Subject: ARM: 7950/1: mm: Fix stage-2 device memory attributes
+
+From: Christoffer Dall <christoffer.dall@linaro.org>
+
+commit 4d9c5b89cf3605bbc39c6e274351ff25f0d83e6a upstream.
+
+The stage-2 memory attributes are distinct from the Hyp memory
+attributes and the Stage-1 memory attributes. We were using the stage-1
+memory attributes for stage-2 mappings causing device mappings to be
+mapped as normal memory. Add the S2 equivalent defines for memory
+attributes and fix the comments explaining the defines while at it.
+
+Add a prot_pte_s2 field to the mem_type struct and fill out the field
+for device mappings accordingly.
+
+Acked-by: Marc Zyngier <marc.zyngier@arm.com>
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/pgtable-3level.h | 15 +++++++++------
+ arch/arm/mm/mm.h | 1 +
+ arch/arm/mm/mmu.c | 7 ++++++-
+ 3 files changed, 16 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/include/asm/pgtable-3level.h
++++ b/arch/arm/include/asm/pgtable-3level.h
+@@ -120,13 +120,16 @@
+ /*
+ * 2nd stage PTE definitions for LPAE.
+ */
+-#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+-#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+-#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
+-#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
+-#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
++#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
++#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
++#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
++#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
++#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
+
+-#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
++#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
++#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
++
++#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
+
+ /*
+ * Hyp-mode PL2 PTE definitions for LPAE.
+--- a/arch/arm/mm/mm.h
++++ b/arch/arm/mm/mm.h
+@@ -38,6 +38,7 @@ static inline pmd_t *pmd_off_k(unsigned
+
+ struct mem_type {
+ pteval_t prot_pte;
++ pteval_t prot_pte_s2;
+ pmdval_t prot_l1;
+ pmdval_t prot_sect;
+ unsigned int domain;
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -231,12 +231,16 @@ __setup("noalign", noalign_setup);
+ #endif /* ifdef CONFIG_CPU_CP15 / else */
+
+ #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
++#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
+ #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
+
+ static struct mem_type mem_types[] = {
+ [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
+ L_PTE_SHARED,
++ .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
++ s2_policy(L_PTE_S2_MT_DEV_SHARED) |
++ L_PTE_SHARED,
+ .prot_l1 = PMD_TYPE_TABLE,
+ .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
+ .domain = DOMAIN_IO,
+@@ -458,7 +462,8 @@ static void __init build_mem_type_table(
+ cp = &cache_policies[cachepolicy];
+ vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+ s2_pgprot = cp->pte_s2;
+- hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
++ hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
++ s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
+
+ /*
+ * ARMv6 and above have extended page tables.
--- /dev/null
+From bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Fri, 7 Feb 2014 19:12:20 +0100
+Subject: ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e upstream.
+
+During __v{6,7}_setup, we invalidate the TLBs since we are about to
+enable the MMU on return to head.S. Unfortunately, without a subsequent
+dsb instruction, the invalidation is not guaranteed to have completed by
+the time we write to the sctlr, potentially exposing us to junk/stale
+translations cached in the TLB.
+
+This patch reworks the init functions so that the dsb used to ensure
+completion of cache/predictor maintenance is also used to ensure
+completion of the TLB invalidation.
+
+Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/proc-v6.S | 3 ++-
+ arch/arm/mm/proc-v7.S | 2 +-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/mm/proc-v6.S
++++ b/arch/arm/mm/proc-v6.S
+@@ -208,7 +208,6 @@ __v6_setup:
+ mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
+- mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+ #ifdef CONFIG_MMU
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
+ mcr p15, 0, r0, c2, c0, 2 @ TTB control register
+@@ -218,6 +217,8 @@ __v6_setup:
+ ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
+ mcr p15, 0, r8, c2, c0, 1 @ load TTB1
+ #endif /* CONFIG_MMU */
++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
++ @ complete invalidations
+ adr r5, v6_crval
+ ldmia r5, {r5, r6}
+ ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
+--- a/arch/arm/mm/proc-v7.S
++++ b/arch/arm/mm/proc-v7.S
+@@ -351,7 +351,6 @@ __v7_setup:
+
+ 4: mov r10, #0
+ mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
+- dsb
+ #ifdef CONFIG_MMU
+ mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
+ v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
+@@ -360,6 +359,7 @@ __v7_setup:
+ mcr p15, 0, r5, c10, c2, 0 @ write PRRR
+ mcr p15, 0, r6, c10, c2, 1 @ write NMRR
+ #endif
++ dsb @ Complete invalidations
+ #ifndef CONFIG_ARM_THUMBEE
+ mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
+ and r0, r0, #(0xf << 12) @ ThumbEE enabled field
--- /dev/null
+From 7c8746a9eb287642deaad0e7c2cdf482dce5e4be Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Fri, 7 Feb 2014 19:12:32 +0100
+Subject: ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 7c8746a9eb287642deaad0e7c2cdf482dce5e4be upstream.
+
+When unlocking a spinlock, we require the following, strictly ordered
+sequence of events:
+
+ <barrier> /* dmb */
+ <unlock>
+ <barrier> /* dsb */
+ <sev>
+
+Whilst the code does indeed reflect this in terms of the architecture,
+the final <barrier> + <sev> have been contracted into a single inline
+asm without a "memory" clobber, therefore the compiler is at liberty to
+reorder the unlock to the end of the above sequence. In such a case,
+a waiting CPU may be woken up before the lock has been unlocked, leading
+to extremely poor performance.
+
+This patch reworks the dsb_sev() function to make use of the dsb()
+macro and ensure ordering against the unlock.
+
+Reported-by: Mark Rutland <mark.rutland@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/spinlock.h | 15 +++------------
+ 1 file changed, 3 insertions(+), 12 deletions(-)
+
+--- a/arch/arm/include/asm/spinlock.h
++++ b/arch/arm/include/asm/spinlock.h
+@@ -37,18 +37,9 @@
+
+ static inline void dsb_sev(void)
+ {
+-#if __LINUX_ARM_ARCH__ >= 7
+- __asm__ __volatile__ (
+- "dsb ishst\n"
+- SEV
+- );
+-#else
+- __asm__ __volatile__ (
+- "mcr p15, 0, %0, c7, c10, 4\n"
+- SEV
+- : : "r" (0)
+- );
+-#endif
++
++ dsb(ishst);
++ __asm__(SEV);
+ }
+
+ /*
--- /dev/null
+From 39544ac9df20f73e49fc6b9ac19ff533388c82c0 Mon Sep 17 00:00:00 2001
+From: Vinayak Kale <vkale@apm.com>
+Date: Wed, 12 Feb 2014 07:30:01 +0100
+Subject: ARM: 7957/1: add DSB after icache flush in __flush_icache_all()
+
+From: Vinayak Kale <vkale@apm.com>
+
+commit 39544ac9df20f73e49fc6b9ac19ff533388c82c0 upstream.
+
+Add DSB after icache flush to complete the cache maintenance operation.
+
+Signed-off-by: Vinayak Kale <vkale@apm.com>
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/cacheflush.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/include/asm/cacheflush.h
++++ b/arch/arm/include/asm/cacheflush.h
+@@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_
+ static inline void __flush_icache_all(void)
+ {
+ __flush_icache_preferred();
++ dsb();
+ }
+
+ /*
--- /dev/null
+From 10c8562f932d89c030083e15f9279971ed637136 Mon Sep 17 00:00:00 2001
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Thu, 16 Jan 2014 15:39:17 +0100
+Subject: ARM: dma-mapping: fix GFP_ATOMIC macro usage
+
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+
+commit 10c8562f932d89c030083e15f9279971ed637136 upstream.
+
+GFP_ATOMIC is not a single gfp flag, but a macro which expands to the other
+flags and LACK of __GFP_WAIT flag. To check if caller wanted to perform an
+atomic allocation, the code must test __GFP_WAIT flag presence. This patch
+fixes the issue introduced in v3.6-rc5
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/dma-mapping.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mm/dma-mapping.c
++++ b/arch/arm/mm/dma-mapping.c
+@@ -1358,7 +1358,7 @@ static void *arm_iommu_alloc_attrs(struc
+ *handle = DMA_ERROR_CODE;
+ size = PAGE_ALIGN(size);
+
+- if (gfp & GFP_ATOMIC)
++ if (!(gfp & __GFP_WAIT))
+ return __iommu_alloc_atomic(dev, size, handle);
+
+ /*
--- /dev/null
+From 28a9f3b078c545064dcf4b46d2c6917554d1642e Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@linaro.org>
+Date: Tue, 18 Feb 2014 10:35:05 +0800
+Subject: ARM: imx6: build pm-imx6q.c independently of CONFIG_PM
+
+From: Shawn Guo <shawn.guo@linaro.org>
+
+commit 28a9f3b078c545064dcf4b46d2c6917554d1642e upstream.
+
+When building a kernel image with only CONFIG_CPU_IDLE but no CONFIG_PM,
+we will get the following link error.
+
+ LD init/built-in.o
+arch/arm/mach-imx/built-in.o: In function `imx6q_enter_wait':
+platform-spi_imx.c:(.text+0x25c0): undefined reference to `imx6q_set_lpm'
+platform-spi_imx.c:(.text+0x25d4): undefined reference to `imx6q_set_lpm'
+arch/arm/mach-imx/built-in.o: In function `imx6q_cpuidle_init':
+platform-spi_imx.c:(.init.text+0x75d4): undefined reference to `imx6q_set_chicken_bit'
+make[1]: *** [vmlinux] Error 1
+
+Since pm-imx6q.c has been a collection of library functions that access
+CCM low-power registers used by not only suspend but also cpuidle and
+other drivers, let's build pm-imx6q.c independently of CONFIG_PM to fix
+above error.
+
+Reported-by: Lucas Stach <l.stach@pengutronix.de>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-imx/Makefile | 2 --
+ arch/arm/mach-imx/common.h | 4 +---
+ 2 files changed, 1 insertion(+), 5 deletions(-)
+
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -100,11 +100,9 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
+
+-ifeq ($(CONFIG_PM),y)
+ obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+ # i.MX6SL reuses i.MX6Q code
+ obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+-endif
+
+ # i.MX5 based machines
+ obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+--- a/arch/arm/mach-imx/common.h
++++ b/arch/arm/mach-imx/common.h
+@@ -143,13 +143,11 @@ void imx6q_set_chicken_bit(void);
+ void imx_cpu_die(unsigned int cpu);
+ int imx_cpu_kill(unsigned int cpu);
+
+-#ifdef CONFIG_PM
+ void imx6q_pm_init(void);
+ void imx6q_pm_set_ccm_base(void __iomem *base);
++#ifdef CONFIG_PM
+ void imx5_pm_init(void);
+ #else
+-static inline void imx6q_pm_init(void) {}
+-static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
+ static inline void imx5_pm_init(void) {}
+ #endif
+
--- /dev/null
+From 6b187b21c92b6e2c7e8ef0b450181c37a3f31681 Mon Sep 17 00:00:00 2001
+From: Pekon Gupta <pekon@ti.com>
+Date: Tue, 28 Jan 2014 11:42:40 +0530
+Subject: ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module
+
+From: Pekon Gupta <pekon@ti.com>
+
+commit 6b187b21c92b6e2c7e8ef0b450181c37a3f31681 upstream.
+
+Fixes: commit bc6b1e7b86f5d8e4a6fc1c0189e64bba4077efe0
+ ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
+
+OMAP SoC(s) depend on GPMC controller driver to parse GPMC DT child nodes and
+register them platform_device for NAND driver to probe later. However this does
+not happen if generic MTD_NAND framework is built as module (CONFIG_MTD_NAND=m).
+
+Therefore, when MTD/NAND and MTD/NAND/OMAP2 modules are loaded, they are unable
+to find any matching platform_device and remain un-binded. This causes on board
+NAND flash to remain un-detected.
+
+This patch causes GPMC controller to parse DT nodes when
+CONFIG_MTD_NAND=y || CONFIG_MTD_NAND=m
+
+Signed-off-by: Pekon Gupta <pekon@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/gpmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-omap2/gpmc.c
++++ b/arch/arm/mach-omap2/gpmc.c
+@@ -1339,7 +1339,7 @@ static void __maybe_unused gpmc_read_tim
+ of_property_read_bool(np, "gpmc,time-para-granularity");
+ }
+
+-#ifdef CONFIG_MTD_NAND
++#if IS_ENABLED(CONFIG_MTD_NAND)
+
+ static const char * const nand_xfer_types[] = {
+ [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
--- /dev/null
+From 980386d2d6d49e0b42f48550853ef1ad6aa5d79a Mon Sep 17 00:00:00 2001
+From: Pekon Gupta <pekon@ti.com>
+Date: Tue, 28 Jan 2014 11:42:41 +0530
+Subject: ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module
+
+From: Pekon Gupta <pekon@ti.com>
+
+commit 980386d2d6d49e0b42f48550853ef1ad6aa5d79a upstream.
+
+Fixes: commit 75d3625e0e86b2d8d77b4e9c6f685fd7ea0d5a96
+ ARM: OMAP2+: gpmc: add DT bindings for OneNAND
+
+OMAP SoC(s) depend on GPMC controller driver to parse GPMC DT child nodes and
+register them platform_device for ONENAND driver to probe later. However this does
+not happen if generic MTD_ONENAND framework is built as module (CONFIG_MTD_ONENAND=m).
+
+Therefore, when MTD/ONENAND and MTD/ONENAND/OMAP2 modules are loaded, they are unable
+to find any matching platform_device and remain un-binded. This causes on board
+ONENAND flash to remain un-detected.
+
+This patch causes GPMC controller to parse DT nodes when
+CONFIG_MTD_ONENAND=y || CONFIG_MTD_ONENAND=m
+
+Signed-off-by: Pekon Gupta <pekon@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/gpmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-omap2/gpmc.c
++++ b/arch/arm/mach-omap2/gpmc.c
+@@ -1429,7 +1429,7 @@ static int gpmc_probe_nand_child(struct
+ }
+ #endif
+
+-#ifdef CONFIG_MTD_ONENAND
++#if IS_ENABLED(CONFIG_MTD_ONENAND)
+ static int gpmc_probe_onenand_child(struct platform_device *pdev,
+ struct device_node *child)
+ {
--- /dev/null
+From 8859685785bfafadf9bc922dd3a2278e59886947 Mon Sep 17 00:00:00 2001
+From: Stephen Warren <swarren@nvidia.com>
+Date: Tue, 18 Feb 2014 16:51:58 -0700
+Subject: ARM: tegra: only run PL310 init on systems with one
+
+From: Stephen Warren <swarren@nvidia.com>
+
+commit 8859685785bfafadf9bc922dd3a2278e59886947 upstream.
+
+Fix tegra_init_cache() to check whether the system has a PL310 cache
+before touching the PL310 registers. This prevents access to non-existent
+registers on Tegra114 and later.
+
+Note for stable kernels:
+In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c.
+
+Signed-off-by: Stephen Warren <swarren@nvidia.com>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-tegra/tegra.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm/mach-tegra/tegra.c
++++ b/arch/arm/mach-tegra/tegra.c
+@@ -74,10 +74,20 @@ u32 tegra_uart_config[4] = {
+ static void __init tegra_init_cache(void)
+ {
+ #ifdef CONFIG_CACHE_L2X0
++ static const struct of_device_id pl310_ids[] __initconst = {
++ { .compatible = "arm,pl310-cache", },
++ {}
++ };
++
++ struct device_node *np;
+ int ret;
+ void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+ u32 aux_ctrl, cache_type;
+
++ np = of_find_matching_node(NULL, pl310_ids);
++ if (!np)
++ return;
++
+ cache_type = readl(p + L2X0_CACHE_TYPE);
+ aux_ctrl = (cache_type & 0x700) << (17-8);
+ aux_ctrl |= 0x7C400001;
--- /dev/null
+From 5745d6a41a4f4aec29e2ccd591c6fb09ed73a955 Mon Sep 17 00:00:00 2001
+From: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Fri, 10 Jan 2014 09:29:39 -0500
+Subject: avr32: fix missing module.h causing build failure in mimc200/fram.c
+
+From: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit 5745d6a41a4f4aec29e2ccd591c6fb09ed73a955 upstream.
+
+Causing this:
+
+In file included from arch/avr32/boards/mimc200/fram.c:13:
+include/linux/miscdevice.h:51: error: field 'list' has incomplete type
+include/linux/miscdevice.h:55: error: expected specifier-qualifier-list before 'mode_t'
+arch/avr32/boards/mimc200/fram.c:42: error: 'THIS_MODULE' undeclared here (not in a function)
+
+Reported-by: Fengguang Wu <fengguang.wu@intel.com>
+Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
+Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
+Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
+Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/avr32/boards/mimc200/fram.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/avr32/boards/mimc200/fram.c
++++ b/arch/avr32/boards/mimc200/fram.c
+@@ -11,6 +11,7 @@
+ #define FRAM_VERSION "1.0"
+
+ #include <linux/miscdevice.h>
++#include <linux/module.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mm.h>
+ #include <linux/io.h>
--- /dev/null
+From 8d80390cfc9434d5aa4fb9e5f9768a66b30cb8a6 Mon Sep 17 00:00:00 2001
+From: Chen Gang <gang.chen.5i5j@gmail.com>
+Date: Sat, 1 Feb 2014 20:35:54 +0800
+Subject: avr32: Makefile: add '-D__linux__' flag for gcc-4.4.7 use
+
+From: Chen Gang <gang.chen.5i5j@gmail.com>
+
+commit 8d80390cfc9434d5aa4fb9e5f9768a66b30cb8a6 upstream.
+
+For avr32 cross compiler, do not define '__linux__' internally, so it
+will cause issue with allmodconfig.
+
+The related error:
+
+ CC [M] fs/coda/psdev.o
+ In file included from include/linux/coda.h:64,
+ from fs/coda/psdev.c:45:
+ include/uapi/linux/coda.h:221: error: expected specifier-qualifier-list before 'u_quad_t'
+
+The related toolchain version (which only download, not re-compile):
+
+ [root@gchen linux-next]# /upstream/toolchain/download/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc -v
+ Using built-in specs.
+ Target: avr32
+ Configured with: /data2/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/src/gcc/configure --target=avr32 --host=i686-pc-linux-gnu --build=x86_64-pc-linux-gnu --prefix=/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/avr32-gnu-toolchain-linux_x86 --enable-languages=c,c++ --disable-nls --disable-libssp --disable-libstdcxx-pch --with-dwarf2 --enable-version-specific-runtime-libs --disable-shared --enable-doc --with-mpfr-lib=/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/avr32-gnu-toolchain-linux_x86/lib --with-mpfr-include=/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/avr32-gnu-toolchain-linux_x86/include --with-gmp=/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/avr32-gnu-toolchain-linux_x86 --with-mpc=/home/toolsbuild/jenkins-knuth/workspace/avr32-gnu-toolchain/avr32-gnu-toolchain-linux_x86 --enable-__cxa_atexit --disable-shared --with-newlib --with-pkgversion=AVR_32_bit_GNU_Toolchain_3.4.2_435 --with-bugurl=http://www
+.atmel.com/avr
+ Thread model: single
+ gcc version 4.4.7 (AVR_32_bit_GNU_Toolchain_3.4.2_435)
+
+Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
+Acked-by: Hans-Christian Egtvedt <hegtvedt@cisco.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/avr32/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/avr32/Makefile
++++ b/arch/avr32/Makefile
+@@ -11,7 +11,7 @@ all: uImage vmlinux.elf
+
+ KBUILD_DEFCONFIG := atstk1002_defconfig
+
+-KBUILD_CFLAGS += -pipe -fno-builtin -mno-pic
++KBUILD_CFLAGS += -pipe -fno-builtin -mno-pic -D__linux__
+ KBUILD_AFLAGS += -mrelax -mno-pic
+ KBUILD_CFLAGS_MODULE += -mno-relax
+ LDFLAGS_vmlinux += --relax
--- /dev/null
+From 92e3b40537707001d17bbad800d150ab04e53bf4 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 17 Feb 2014 20:33:01 -0500
+Subject: jbd2: fix use after free in jbd2_journal_start_reserved()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+commit 92e3b40537707001d17bbad800d150ab04e53bf4 upstream.
+
+If start_this_handle() fails then it leads to a use after free of
+"handle".
+
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: "Theodore Ts'o" <tytso@mit.edu>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ fs/jbd2/transaction.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/fs/jbd2/transaction.c
++++ b/fs/jbd2/transaction.c
+@@ -514,11 +514,13 @@ int jbd2_journal_start_reserved(handle_t
+ * similarly constrained call sites
+ */
+ ret = start_this_handle(journal, handle, GFP_NOFS);
+- if (ret < 0)
++ if (ret < 0) {
+ jbd2_journal_free_reserved(handle);
++ return ret;
++ }
+ handle->h_type = type;
+ handle->h_line_no = line_no;
+- return ret;
++ return 0;
+ }
+ EXPORT_SYMBOL(jbd2_journal_start_reserved);
+
--- /dev/null
+From 5b2e198e50f6ba57081586b853163ea1bb95f1a8 Mon Sep 17 00:00:00 2001
+From: Gavin Shan <shangw@linux.vnet.ibm.com>
+Date: Wed, 12 Feb 2014 15:24:54 +0800
+Subject: powerpc/powernv: Rework EEH reset
+
+From: Gavin Shan <shangw@linux.vnet.ibm.com>
+
+commit 5b2e198e50f6ba57081586b853163ea1bb95f1a8 upstream.
+
+When doing reset in order to recover the affected PE, we issue
+hot reset on PE primary bus if it's not root bus. Otherwise, we
+issue hot or fundamental reset on root port or PHB accordingly.
+For the later case, we didn't cover the situation where PE only
+includes root port and it potentially causes kernel crash upon
+EEH error to the PE.
+
+The patch reworks the logic of EEH reset to improve the code
+readability and also avoid the kernel crash.
+
+Reported-by: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
+Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/powerpc/platforms/powernv/eeh-ioda.c | 29 ++++-------------------------
+ 1 file changed, 4 insertions(+), 25 deletions(-)
+
+--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
++++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
+@@ -490,8 +490,7 @@ static int ioda_eeh_bridge_reset(struct
+ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
+ {
+ struct pci_controller *hose = pe->phb;
+- struct eeh_dev *edev;
+- struct pci_dev *dev;
++ struct pci_bus *bus;
+ int ret;
+
+ /*
+@@ -520,31 +519,11 @@ static int ioda_eeh_reset(struct eeh_pe
+ if (pe->type & EEH_PE_PHB) {
+ ret = ioda_eeh_phb_reset(hose, option);
+ } else {
+- if (pe->type & EEH_PE_DEVICE) {
+- /*
+- * If it's device PE, we didn't refer to the parent
+- * PCI bus yet. So we have to figure it out indirectly.
+- */
+- edev = list_first_entry(&pe->edevs,
+- struct eeh_dev, list);
+- dev = eeh_dev_to_pci_dev(edev);
+- dev = dev->bus->self;
+- } else {
+- /*
+- * If it's bus PE, the parent PCI bus is already there
+- * and just pick it up.
+- */
+- dev = pe->bus->self;
+- }
+-
+- /*
+- * Do reset based on the fact that the direct upstream bridge
+- * is root bridge (port) or not.
+- */
+- if (dev->bus->number == 0)
++ bus = eeh_pe_bus_get(pe);
++ if (pci_is_root_bus(bus))
+ ret = ioda_eeh_root_reset(hose, option);
+ else
+- ret = ioda_eeh_bridge_reset(hose, dev, option);
++ ret = ioda_eeh_bridge_reset(hose, bus->self, option);
+ }
+
+ return ret;
--- /dev/null
+From 1a18a66446f3f289b05b634f18012424d82aa63a Mon Sep 17 00:00:00 2001
+From: Kevin Hao <haokexin@gmail.com>
+Date: Fri, 17 Jan 2014 12:25:28 +0800
+Subject: powerpc: Set the correct ksp_limit on ppc32 when switching to irq stack
+
+From: Kevin Hao <haokexin@gmail.com>
+
+commit 1a18a66446f3f289b05b634f18012424d82aa63a upstream.
+
+Guenter Roeck has got the following call trace on a p2020 board:
+ Kernel stack overflow in process eb3e5a00, r1=eb79df90
+ CPU: 0 PID: 2838 Comm: ssh Not tainted 3.13.0-rc8-juniper-00146-g19eca00 #4
+ task: eb3e5a00 ti: c0616000 task.ti: ef440000
+ NIP: c003a420 LR: c003a410 CTR: c0017518
+ REGS: eb79dee0 TRAP: 0901 Not tainted (3.13.0-rc8-juniper-00146-g19eca00)
+ MSR: 00029000 <CE,EE,ME> CR: 24008444 XER: 00000000
+ GPR00: c003a410 eb79df90 eb3e5a00 00000000 eb05d900 00000001 65d87646 00000000
+ GPR08: 00000000 020b8000 00000000 00000000 44008442
+ NIP [c003a420] __do_softirq+0x94/0x1ec
+ LR [c003a410] __do_softirq+0x84/0x1ec
+ Call Trace:
+ [eb79df90] [c003a410] __do_softirq+0x84/0x1ec (unreliable)
+ [eb79dfe0] [c003a970] irq_exit+0xbc/0xc8
+ [eb79dff0] [c000cc1c] call_do_irq+0x24/0x3c
+ [ef441f20] [c00046a8] do_IRQ+0x8c/0xf8
+ [ef441f40] [c000e7f4] ret_from_except+0x0/0x18
+ --- Exception: 501 at 0xfcda524
+ LR = 0x10024900
+ Instruction dump:
+ 7c781b78 3b40000a 3a73b040 543c0024 3a800000 3b3913a0 7ef5bb78 48201bf9
+ 5463103a 7d3b182e 7e89b92e 7c008146 <3ba00000> 7e7e9b78 48000014 57fff87f
+ Kernel panic - not syncing: kernel stack overflow
+ CPU: 0 PID: 2838 Comm: ssh Not tainted 3.13.0-rc8-juniper-00146-g19eca00 #4
+ Call Trace:
+
+The reason is that we have used the wrong register to calculate the
+ksp_limit in commit cbc9565ee826 (powerpc: Remove ksp_limit on ppc64).
+Just fix it.
+
+As suggested by Benjamin Herrenschmidt, also add the C prototype of the
+function in the comment in order to avoid such kind of errors in the
+future.
+
+Reported-by: Guenter Roeck <linux@roeck-us.net>
+Tested-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Kevin Hao <haokexin@gmail.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/powerpc/kernel/misc_32.S | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/kernel/misc_32.S
++++ b/arch/powerpc/kernel/misc_32.S
+@@ -57,11 +57,14 @@ _GLOBAL(call_do_softirq)
+ mtlr r0
+ blr
+
++/*
++ * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
++ */
+ _GLOBAL(call_do_irq)
+ mflr r0
+ stw r0,4(r1)
+ lwz r10,THREAD+KSP_LIMIT(r2)
+- addi r11,r3,THREAD_INFO_GAP
++ addi r11,r4,THREAD_INFO_GAP
+ stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
+ mr r1,r4
+ stw r10,8(r1)
ext4-fix-online-resize-with-very-large-inode-tables.patch
ext4-fix-online-resize-with-a-non-standard-blocks-per-group-setting.patch
ext4-don-t-leave-i_crtime.tv_sec-uninitialized.patch
+arm-dma-mapping-fix-gfp_atomic-macro-usage.patch
+arm-7950-1-mm-fix-stage-2-device-memory-attributes.patch
+arm-7953-1-mm-ensure-tlb-invalidation-is-complete-before-enabling-mmu.patch
+arm-7955-1-spinlock-ensure-we-have-a-compiler-barrier-before-sev.patch
+arm-7957-1-add-dsb-after-icache-flush-in-__flush_icache_all.patch
+arm-omap2-gpmc-fix-dt-nand-child-nodes-not-probed-when-mtd_nand-is-built-as-module.patch
+arm-omap2-gpmc-fix-dt-onenand-child-nodes-not-probed-when-mtd_onenand-is-built-as-module.patch
+arm-imx6-build-pm-imx6q.c-independently-of-config_pm.patch
+arm-tegra-only-run-pl310-init-on-systems-with-one.patch
+powerpc-set-the-correct-ksp_limit-on-ppc32-when-switching-to-irq-stack.patch
+powerpc-powernv-rework-eeh-reset.patch
+jbd2-fix-use-after-free-in-jbd2_journal_start_reserved.patch
+avr32-fix-missing-module.h-causing-build-failure-in-mimc200-fram.c.patch
+avr32-makefile-add-d__linux__-flag-for-gcc-4.4.7-use.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
