]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu/gart: Add helper to bind VRAM pages (v2)
authorTimur Kristóf <timur.kristof@gmail.com>
Fri, 7 Nov 2025 15:57:35 +0000 (16:57 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 12 Nov 2025 02:54:17 +0000 (21:54 -0500)
Binds pages that located in VRAM to the GART page table.

Useful when a kernel BO is located in VRAM but
needs to be accessed from the GART address space,
for example to give a kernel BO a 32-bit address
when GART is placed in LOW address space.

v2:
- Refactor function to be more reusable

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h

index 83f3b94ed975a7392ee213945283acd5395c4823..d2237ce9da70e289906f3b109677c225b905cc9c 100644 (file)
@@ -367,6 +367,42 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
        drm_dev_exit(idx);
 }
 
+/**
+ * amdgpu_gart_map_vram_range - map VRAM pages into the GART page table
+ *
+ * @adev: amdgpu_device pointer
+ * @pa: physical address of the first page to be mapped
+ * @start_page: first page to map in the GART aperture
+ * @num_pages: number of pages to be mapped
+ * @flags: page table entry flags
+ * @dst: CPU address of the GART table
+ *
+ * Binds a BO that is allocated in VRAM to the GART page table
+ * (all ASICs).
+ *
+ * Useful when a kernel BO is located in VRAM but
+ * needs to be accessed from the GART address space.
+ */
+void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
+                               uint64_t start_page, uint64_t num_pages,
+                               uint64_t flags, void *dst)
+{
+       u32 i, idx;
+
+       /* The SYSTEM flag indicates the pages aren't in VRAM. */
+       WARN_ON_ONCE(flags & AMDGPU_PTE_SYSTEM);
+
+       if (!drm_dev_enter(adev_to_drm(adev), &idx))
+               return;
+
+       for (i = 0; i < num_pages; ++i) {
+               amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
+                       start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);
+       }
+
+       drm_dev_exit(idx);
+}
+
 /**
  * amdgpu_gart_bind - bind pages into the gart page table
  *
index 7cc980bf4725d6b6cf8689525eb547a0e6ba0217..d3118275ddae8f3ae23ddd7e60a11ffdc545df6b 100644 (file)
@@ -64,5 +64,8 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
                     void *dst);
 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                      int pages, dma_addr_t *dma_addr, uint64_t flags);
+void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
+                               uint64_t start_page, uint64_t num_pages,
+                               uint64_t flags, void *dst);
 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
 #endif