net: zynq: Add support for different PHY interface types

MII is setup by default for all cases. The most of boards are using
RGMII but PHY drivers are not doing any specific setting that's why MII
setting was working file. With TI DP83867 is necessary to setup
paramaters based on interface type.

Use one setting per board for it which is something what will be removed
when driver is moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 4674f909f95818ce2001ea07660f9952249b48c0..9a2dbe628457134fb2b46c875b0d7915afd54f06 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -168,6 +168,7 @@ struct zynq_gem_priv {
        int phyaddr;
        u32 emio;
        int init;
+       phy_interface_t interface;
        struct phy_device *phydev;
        struct mii_dev *bus;
 };
@@ -391,7 +392,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 
        /* interface - look at tsec */
        phydev = phy_connect(priv->bus, priv->phyaddr, dev,
-                            PHY_INTERFACE_MODE_MII);
+                            priv->interface);
 
        phydev->supported = supported | ADVERTISED_Pause |
                            ADVERTISED_Asym_Pause;
@@ -623,6 +624,12 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
        priv->phyaddr = phy_addr;
        priv->emio = emio;
 
+#ifndef CONFIG_ZYNQ_GEM_INTERFACE
+       priv->interface = PHY_INTERFACE_MODE_MII;
+#else
+       priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
+#endif
+
        sprintf(dev->name, "Gem.%lx", base_addr);
 
        dev->iobase = base_addr;

diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 1e2cb48150bfd2a24aa6a1810cf5934bc37925e0..ca9cdec3db328b24f1a624de92a64104a66f0860 100644 (file)
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -12,6 +12,7 @@
 
 #define CONFIG_ZYNQ_GEM2
 #define CONFIG_ZYNQ_GEM_PHY_ADDR2      -1
+#define CONFIG_ZYNQ_GEM_INTERFACE      PHY_INTERFACE_MODE_RGMII_ID
 
 #define CONFIG_ZYNQ_SERIAL_UART0
 #define CONFIG_ZYNQ_SERIAL_UART1