]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
nand: Clean nand initialization in mainline way
authorMichal Simek <michal.simek@xilinx.com>
Wed, 1 May 2013 14:38:28 +0000 (16:38 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 14 May 2013 16:07:32 +0000 (18:07 +0200)
Move hardcoded values to hardware.h and use it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/include/asm/arch-zynq/hardware.h
arch/arm/include/asm/arch-zynq/sys_proto.h
board/xilinx/zynq/board.c
drivers/mtd/nand/zynq_nand.c
include/configs/petalinux-auto-board.h.template
include/configs/zynq_common.h

index 5e4f633a238decb41745cfc2192cf4553e7a2166..805c4256fcaeaa138f22663910a27fc2456be2ce 100644 (file)
@@ -34,6 +34,8 @@
 #define ZYNQ_I2C_BASEADDR0             0xE0004000
 #define ZYNQ_I2C_BASEADDR1             0xE0005000
 #define ZYNQ_QSPI_BASEADDR             0xE000D000
+#define ZYNQ_SMC_BASEADDR              0xE000E000
+#define ZYNQ_NAND_BASEADDR             0xE1000000
 
 /* Reflect slcr offsets */
 struct slcr_regs {
index 776c3b2748bcd97a6252a127715ef37619ecc34a..6572172feea3f87706f88175f77f599ddeb50897 100644 (file)
@@ -36,7 +36,6 @@ extern u32 zynq_slcr_get_idcode(void);
 extern int zynq_slcr_get_mio_pin_status(const char *periph);
 
 /* Driver extern functions */
-extern int zynq_nand_init(struct nand_chip *nand_chip);
 extern int zynq_sdhci_init(u32 regbase);
 
 #endif /* _SYS_PROTO_H_ */
index 119cde439ea8548cfe9f6786626b8fb4aca62683..979ddb1392811aeca1a0d790a3a0497f74bf250f 100644 (file)
@@ -174,13 +174,6 @@ int board_mmc_init(bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_CMD_NAND
-int board_nand_init(struct nand_chip *nand_chip)
-{
-       return zynq_nand_init(nand_chip);
-}
-#endif
-
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
index c0390be07a04d99302326dddd999d3c701f044cd..ab1ee378d041594a2b8344e2d3a2a9f574275326 100644 (file)
@@ -21,6 +21,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand_ecc.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
 /* The NAND flash driver defines */
@@ -106,8 +107,7 @@ struct xnandps_smc_regs {
        u32     eval0r;         /* 0x418 */
 };
 
-#define xnandps_smc_base       \
-       ((struct xnandps_smc_regs *) XPSS_CRTL_PARPORT_BASEADDR)
+#define xnandps_smc_base       ((struct xnandps_smc_regs *)ZYNQ_SMC_BASEADDR)
 
 /*
  * struct xnandps_command_format - Defines NAND flash command format
@@ -1032,7 +1032,7 @@ static int xnandps_check_is_16bit_bw_flash(void)
        return is_16bit_bw;
 }
 
-int zynq_nand_init(struct nand_chip *nand_chip)
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 {
        struct xnandps_info *xnand;
        struct mtd_info *mtd;
@@ -1052,7 +1052,7 @@ int zynq_nand_init(struct nand_chip *nand_chip)
                goto free;
        }
 
-       xnand->nand_base = (void *)XPSS_NAND_BASEADDR;
+       xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR;
        mtd = &nand_info[0];
 
        nand_chip->priv = xnand;
@@ -1230,6 +1230,9 @@ int zynq_nand_init(struct nand_chip *nand_chip)
                goto fail;
        }
 
+       if (nand_register(devnum))
+               goto fail;
+
        return 0;
 fail:
        nand_release(mtd);
@@ -1237,3 +1240,13 @@ free:
        kfree(xnand);
        return err;
 }
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+void board_nand_init(void)
+{
+       struct nand_chip *nand = &nand_chip[0];
+
+       if (zynq_nand_init(nand, 0))
+               puts("ZYNQ NAND init failed\n");
+}
index 50d7c4b9d609f53ac80c80020c14cc7ee99a038b..9d4dc034aaf63c5414b28e35b9c50dac9e95e51b 100644 (file)
                #define XILINX_FLASH_SIZE       XILINX_PS7_NOR_FLASH_SIZE
        #endif
        #if defined(XILINX_PS7_NAND_BASEADDR)
-               #define XILINX_NAND_FLASH_BASEDDR       XILINX_PS7_NAND_FLASH_BASEADDR
+               #define XILINX_NAND_FLASH_BASEDDR
                #define CONFIG_CMD_NAND
                #define CONFIG_CMD_NAND_LOCK_UNLOCK
                #define CONFIG_SYS_MAX_NAND_DEVICE 1
-               #define CONFIG_SYS_NAND_BASE XPSS_NAND_BASEADDR
                #define CONFIG_MTD_DEVICE
                #define CONFIG_SYS_NAND_ONFI_DETECTION
        #endif
        #define XILINX_FLASH_START      XILINX_PS7_NOR_FLASH_BASEADDR
        #define XILINX_FLASH_SIZE       XILINX_PS7_NOR_FLASH_SIZE
 #elif defined(ZYNQ_BOOT_NAND) && defined(XILINX_PS7_NAND_FLASH_BASEADDR)
-       #define XILINX_NAND_FLASH_BASEDDR       XILINX_PS7_NAND_FLASH_BASEADDR
+       #define XILINX_NAND_FLASH_BASEDDR
 #elif defined(ZYNQ_BOOT_OTHER)
        #define RAMENV
 #else
 #elif defined(XILINX_NAND_FLASH_BASEDDR) /* NAND Flash */
        #define CONFIG_NAND_FLASH       1
        #define CONFIG_NAND_ZYNQ
-       #define XILINX_NAND_FLASH_BASEDDR       XILINX_PS7_NAND_FLASH_BASEADDR
+       #define CONFIG_SYS_NAND_SELF_INIT
        #define CONFIG_CMD_NAND
        #define CONFIG_CMD_NAND_LOCK_UNLOCK
        #define CONFIG_SYS_MAX_NAND_DEVICE 1
-       #define CONFIG_SYS_NAND_BASE XILINX_NAND_FLASH_BASEDDR
-       #define XPSS_NAND_BASEADDR XILINX_NAND_FLASH_BASEDDR
-       #define XPSS_CRTL_PARPORT_BASEADDR      XILINX_PS7_SMC_BASEADDR
+       #define CONFIG_SYS_NAND_BASE    ZYNQ_NAND_BASEADDR
 
        #define CONFIG_SYS_NO_FLASH     1
        #define CONFIG_MTD_DEVICE
index 494c8e3f8e37be602b759857c6dc7f6e7bf01e79..4e87cbe9620f71affd1b706a919513cc63177e60 100644 (file)
 # define CONFIG_CMD_NAND
 # define CONFIG_CMD_NAND_LOCK_UNLOCK
 # define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE XPSS_NAND_BASEADDR
+# define CONFIG_SYS_NAND_SELF_INIT
 # define CONFIG_SYS_NAND_ONFI_DETECTION
 # define CONFIG_MTD_DEVICE
 #endif
 #define CONFIG_CMD_BOOTZ
 #undef CONFIG_BOOTM_NETBSD
 
-/* FIXME this should be removed pretty soon */
-#define XPSS_NAND_BASEADDR             0xE1000000
-#define XPSS_CRTL_PARPORT_BASEADDR     0xE000E000
-
 #endif /* __CONFIG_ZYNQ_COMMON_H */