Move hardcoded values to hardware.h and use it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
+#define ZYNQ_SMC_BASEADDR 0xE000E000
+#define ZYNQ_NAND_BASEADDR 0xE1000000
/* Reflect slcr offsets */
struct slcr_regs {
extern int zynq_slcr_get_mio_pin_status(const char *periph);
/* Driver extern functions */
-extern int zynq_nand_init(struct nand_chip *nand_chip);
extern int zynq_sdhci_init(u32 regbase);
#endif /* _SYS_PROTO_H_ */
}
#endif
-#ifdef CONFIG_CMD_NAND
-int board_nand_init(struct nand_chip *nand_chip)
-{
- return zynq_nand_init(nand_chip);
-}
-#endif
-
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand_ecc.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
/* The NAND flash driver defines */
u32 eval0r; /* 0x418 */
};
-#define xnandps_smc_base \
- ((struct xnandps_smc_regs *) XPSS_CRTL_PARPORT_BASEADDR)
+#define xnandps_smc_base ((struct xnandps_smc_regs *)ZYNQ_SMC_BASEADDR)
/*
* struct xnandps_command_format - Defines NAND flash command format
return is_16bit_bw;
}
-int zynq_nand_init(struct nand_chip *nand_chip)
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct xnandps_info *xnand;
struct mtd_info *mtd;
goto free;
}
- xnand->nand_base = (void *)XPSS_NAND_BASEADDR;
+ xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR;
mtd = &nand_info[0];
nand_chip->priv = xnand;
goto fail;
}
+ if (nand_register(devnum))
+ goto fail;
+
return 0;
fail:
nand_release(mtd);
kfree(xnand);
return err;
}
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+void board_nand_init(void)
+{
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (zynq_nand_init(nand, 0))
+ puts("ZYNQ NAND init failed\n");
+}
#define XILINX_FLASH_SIZE XILINX_PS7_NOR_FLASH_SIZE
#endif
#if defined(XILINX_PS7_NAND_BASEADDR)
- #define XILINX_NAND_FLASH_BASEDDR XILINX_PS7_NAND_FLASH_BASEADDR
+ #define XILINX_NAND_FLASH_BASEDDR
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_BASE XPSS_NAND_BASEADDR
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
#define XILINX_FLASH_START XILINX_PS7_NOR_FLASH_BASEADDR
#define XILINX_FLASH_SIZE XILINX_PS7_NOR_FLASH_SIZE
#elif defined(ZYNQ_BOOT_NAND) && defined(XILINX_PS7_NAND_FLASH_BASEADDR)
- #define XILINX_NAND_FLASH_BASEDDR XILINX_PS7_NAND_FLASH_BASEADDR
+ #define XILINX_NAND_FLASH_BASEDDR
#elif defined(ZYNQ_BOOT_OTHER)
#define RAMENV
#else
#elif defined(XILINX_NAND_FLASH_BASEDDR) /* NAND Flash */
#define CONFIG_NAND_FLASH 1
#define CONFIG_NAND_ZYNQ
- #define XILINX_NAND_FLASH_BASEDDR XILINX_PS7_NAND_FLASH_BASEADDR
+ #define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_BASE XILINX_NAND_FLASH_BASEDDR
- #define XPSS_NAND_BASEADDR XILINX_NAND_FLASH_BASEDDR
- #define XPSS_CRTL_PARPORT_BASEADDR XILINX_PS7_SMC_BASEADDR
+ #define CONFIG_SYS_NAND_BASE ZYNQ_NAND_BASEADDR
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_MTD_DEVICE
# define CONFIG_CMD_NAND
# define CONFIG_CMD_NAND_LOCK_UNLOCK
# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE XPSS_NAND_BASEADDR
+# define CONFIG_SYS_NAND_SELF_INIT
# define CONFIG_SYS_NAND_ONFI_DETECTION
# define CONFIG_MTD_DEVICE
#endif
#define CONFIG_CMD_BOOTZ
#undef CONFIG_BOOTM_NETBSD
-/* FIXME this should be removed pretty soon */
-#define XPSS_NAND_BASEADDR 0xE1000000
-#define XPSS_CRTL_PARPORT_BASEADDR 0xE000E000
-
#endif /* __CONFIG_ZYNQ_COMMON_H */