PCI: cadence: Write MSI data with 32bits

[ Upstream commit e81e36a96bb56f243b5ac1d114c37c086761595b ]

According to the PCIe specification, although the MSI data is only
16bits, the upper 16bits should be written as 0. Use writel
instead of writew when writing the MSI data to the host.

Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 6692654798d44dc00e0319eb9b2692aefcff6178..c3a088910f48d119f67918066be0be39302ed04f 100644 (file)
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -355,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
                ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
                ep->irq_pci_fn = fn;
        }
-       writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
+       writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
 
        return 0;
 }