drm/xe: Drop CTC_MODE register read

The warning was added for a condition that never triggered even for
platforms prior to Xe2. It's not supported in Xe2 and in Xe3p the
register is removed from the main GT. Just drop the entire function as
it doesn't bring any benefit.

Bspec: 62395
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
[ Drop the entire check for CTC_MODE ]
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-3-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 51f2a03847f9d743a4fc8c9e6a000e190f010b02..21c15441c4537b12b945d09c4c2e6fca88f41675 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -346,10 +346,6 @@
 #define   VDN_HCP_POWERGATE_ENABLE(n)          REG_BIT(3 + 2 * (n))
 #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)     REG_BIT(4 + 2 * (n))
 
-#define CTC_MODE                               XE_REG(0xa26c)
-#define   CTC_SHIFT_PARAMETER_MASK             REG_GENMASK(2, 1)
-#define   CTC_SOURCE_DIVIDE_LOGIC              REG_BIT(0)
-
 #define FORCEWAKE_RENDER                       XE_REG(0xa278)
 
 #define POWERGATE_DOMAIN_STATUS                        XE_REG(0xa2a0)

diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 4f011d1573c65979b9058686d9346b90364f526e..00f5972c14dc54e797d1ec31525914d19822e1bb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -55,30 +55,11 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
        }
 }
 
-static void check_ctc_mode(struct xe_gt *gt)
-{
-       /*
-        * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
-        * platforms.  In theory it could be a valid setting for pre-Xe2
-        * platforms, but there's no documentation on how to properly handle
-        * this case.  Reading TIMESTAMP_OVERRIDE, as the driver attempted in
-        * the past has been confirmed as incorrect by the hardware architects.
-        *
-        * For now just warn if we ever encounter hardware in the wild that
-        * has this setting and move on as if it hadn't been set.
-        */
-       if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
-               xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
-}
-
 int xe_gt_clock_init(struct xe_gt *gt)
 {
        u32 freq;
        u32 c0;
 
-       if (!IS_SRIOV_VF(gt_to_xe(gt)))
-               check_ctc_mode(gt);
-
        c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
        read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);