#define MPIC_PSMCS_MASK (0x7f << 16)
#define MPIC_PSMHT_MASK (0x06 << 24)
-#define MPIC_MDC_CLK_SET (0x06050000)
#define MPSM_MFF_C45 BIT(2)
#define MPSM_MFF_C22 0x0
u32 coma_offset;
u32 etha_offset;
u32 gwca_offset;
+ u32 mpid_mdc_clk;
u8 etha_incr;
u8 gwdcbac_offset;
u8 fwpbfcsdc_offset;
/* Enable Station Management clock */
clrsetbits_le32(etha_mii->addr + MPIC,
MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
- MPIC_MDC_CLK_SET);
+ priv->drv_data->mpid_mdc_clk);
/* Access PHY register */
if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */
/* Enable Station Management clock */
clrsetbits_le32(etha_mii->addr + MPIC,
MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
- MPIC_MDC_CLK_SET);
+ priv->drv_data->mpid_mdc_clk);
/* Access PHY register */
if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */
.coma_offset = 0x9000,
.etha_offset = 0xa000,
.gwca_offset = 0x10000,
+ .mpid_mdc_clk = 0x06050000,
.etha_incr = 0x10,
.gwdcbac_offset = 0x0,
.fwpbfcsdc_offset = 0x0,