riscv: dts: microchip: add icicle kit with production device

With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.

Add a new device tree (mpfs-icicle-kit-prod.dts) for the production
board which includes the icicle kit common dtsi and enable the system
controller SPI flash, which is only accessible on production silicon.

Remove redundant board compatible from fabric dtsi and update board
compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP
cluster communication.

Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f51aeeb9fd3b34fbb32bb31c88e2847495599221..1e2f4e41bf0d85c6957c84dcac0b5f588892ebe5 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
index eafea3b69cd75c433a881c8b78c3785ee19d514b..5c7a8ffad85bc2ae9292f3698e8626c9125e0f43 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -134,6 +134,10 @@
        status = "okay";
 };
 
+&ihc {
+       status = "okay";
+};
+
 &mac0 {
        phy-mode = "sgmii";
        phy-handle = <&phy0>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a6dda55a2d1ddbdbb6ae5b5cc0a5ba25aaef618e..e673b676fd1a220ae8c2cc502e59b4d98688f9e9 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,9 +2,6 @@
 /* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 / {
-       compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
-                    "microchip,mpfs";
-
        core_pwm0: pwm@40000000 {
                compatible = "microchip,corepwm-rtl-v4";
                reg = <0x0 0x40000000 0x0 0xF0>;
@@ -26,6 +23,26 @@
                status = "disabled";
        };
 
+       ihc: mailbox {
+               compatible = "microchip,sbi-ipc";
+               interrupt-parent = <&plic>;
+               interrupts = <180>, <179>, <178>, <177>;
+               interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+               #mbox-cells = <1>;
+               status = "disabled";
+       };
+
+       mailbox@50000000 {
+               compatible = "microchip,miv-ihc-rtl-v2";
+               reg = <0x0 0x50000000 0x0 0x1c000>;
+               interrupt-parent = <&plic>;
+               interrupts = <180>, <179>, <178>, <177>;
+               interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+               #mbox-cells = <1>;
+               microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+               status = "disabled";
+       };
+
        pcie: pcie@3000000000 {
                compatible = "microchip,pcie-host-1.0";
                #address-cells = <0x3>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
new file mode 100644 (file)
index 0000000..8afedec
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs-icicle-kit-common.dtsi"
+
+/ {
+       model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)";
+       compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507",
+                    "microchip,mpfs-icicle-kit-prod",
+                    "microchip,mpfs-icicle-kit",
+                    "microchip,mpfs-prod",
+                    "microchip,mpfs";
+};
+
+&syscontroller {
+       microchip,bitstream-flash = <&sys_ctrl_flash>;
+};
+
+&syscontroller_qspi {
+       status = "okay";
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 2cb08ed0946dba367543334ed847f9ceaa53652e..556aa9638282e22246255ba466630fdd6cd34e37 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -7,6 +7,7 @@
 
 / {
        model = "Microchip PolarFire-SoC Icicle Kit";
-       compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+       compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507",
+                    "microchip,mpfs-icicle-kit",
                     "microchip,mpfs";
 };