#define GRUB_PCI_REG_MIN_GNT 0x3e
#define GRUB_PCI_REG_MAX_LAT 0x3f
+#define GRUB_PCI_COMMAND_IO_ENABLED 0x0001
+#define GRUB_PCI_COMMAND_MEM_ENABLED 0x0002
+#define GRUB_PCI_COMMAND_BUS_MASTER 0x0004
+#define GRUB_PCI_COMMAND_PARITY_ERROR 0x0040
+#define GRUB_PCI_COMMAND_SERR_ENABLE 0x0100
+
+#define GRUB_PCI_STATUS_CAPABILITIES 0x0010
+#define GRUB_PCI_STATUS_66MHZ_CAPABLE 0x0020
+#define GRUB_PCI_STATUS_FAST_B2B_CAPABLE 0x0080
+
+#define GRUB_PCI_STATUS_DEVSEL_TIMING_SHIFT 9
+#define GRUB_PCI_STATUS_DEVSEL_TIMING_MASK 0x0600
+
#ifndef ASM_FILE
typedef grub_uint32_t grub_pci_id_t;
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
grub_pci_write (addr, 0x5025000);
addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
- grub_pci_write (addr, 0x2100146);
+ grub_pci_write_word (addr, GRUB_PCI_COMMAND_SERR_ENABLE
+ | GRUB_PCI_COMMAND_PARITY_ERROR
+ | GRUB_PCI_COMMAND_BUS_MASTER
+ | GRUB_PCI_COMMAND_MEM_ENABLED);
+
+ addr = grub_pci_make_address (dev, GRUB_PCI_REG_STATUS);
+ grub_pci_write_word (addr, 0x0200 | GRUB_PCI_STATUS_CAPABILITIES);
break;
case GRUB_YEELOONG_EHCI_PCIID:
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
grub_pci_write (addr, 0x5026000);
addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
- grub_pci_write (addr, 0x2100146);
+ grub_pci_write_word (addr, GRUB_PCI_COMMAND_SERR_ENABLE
+ | GRUB_PCI_COMMAND_PARITY_ERROR
+ | GRUB_PCI_COMMAND_BUS_MASTER
+ | GRUB_PCI_COMMAND_MEM_ENABLED);
+
+ addr = grub_pci_make_address (dev, GRUB_PCI_REG_STATUS);
+ grub_pci_write_word (addr, (1 << GRUB_PCI_STATUS_DEVSEL_TIMING_SHIFT)
+ | GRUB_PCI_STATUS_CAPABILITIES);
break;
}
return 0;
*((volatile grub_uint32_t *) GRUB_CPU_LOONGSON_PCI_HIT1_SEL_HI) = 0xffffffff;
/* Setup PCI controller. */
- *((volatile grub_uint32_t *) (GRUB_MACHINE_PCI_CONTROLLER_HEADER
- + GRUB_PCI_REG_COMMAND)) = 0x22b00046;
+ *((volatile grub_uint16_t *) (GRUB_MACHINE_PCI_CONTROLLER_HEADER
+ + GRUB_PCI_REG_COMMAND))
+ = GRUB_PCI_COMMAND_PARITY_ERROR | GRUB_PCI_COMMAND_BUS_MASTER
+ | GRUB_PCI_COMMAND_MEM_ENABLED;
+ *((volatile grub_uint16_t *) (GRUB_MACHINE_PCI_CONTROLLER_HEADER
+ + GRUB_PCI_REG_STATUS))
+ = (1 << GRUB_PCI_STATUS_DEVSEL_TIMING_SHIFT)
+ | GRUB_PCI_STATUS_FAST_B2B_CAPABLE | GRUB_PCI_STATUS_66MHZ_CAPABLE
+ | GRUB_PCI_STATUS_CAPABILITIES;
+
*((volatile grub_uint32_t *) (GRUB_MACHINE_PCI_CONTROLLER_HEADER
+ GRUB_PCI_REG_CACHELINE)) = 0xff;
*((volatile grub_uint32_t *) (GRUB_MACHINE_PCI_CONTROLLER_HEADER