Don't bother to do a spill store if the register chosen for spilling

was only instantaneously live (target of a dead store).  I don't think
this is really the right way to fix this, but it works.  A better
question is, if this register is dead before the current insn, why was
it chosen for spilling in the first place?

git-svn-id: svn://svn.valgrind.org/vex/trunk@317

diff --git a/VEX/priv/host-generic/reg_alloc.c b/VEX/priv/host-generic/reg_alloc.c
index cb8cfb947ec200b953897d8050dd571738e52a8e..61fd70b418c694733267b58a7ddcf6d2d101feb5 100644 (file)
--- a/VEX/priv/host-generic/reg_alloc.c
+++ b/VEX/priv/host-generic/reg_alloc.c
@@ -920,10 +920,16 @@ HInstrArray* doRegisterAllocation (
 
          /* So here's the spill store.  Assert that we're spilling a
             live vreg. */
-         vassert(vreg_info[m].dead_before > ii);
-         vassert(vreg_info[m].reg_class != HRcINVALID);
-         EMIT_INSTR( (*genSpill)( state[spillee].rreg,
-                                  vreg_info[m].spill_offset ) );
+        if (vreg_info[m].live_after + 1 == vreg_info[m].dead_before) {
+            /* In this situation, m looks like it is the subject of a
+               dead store -- going live and then instantly dead.  So
+               in fact there's no point in spilling it. */
+        } else {
+            vassert(vreg_info[m].dead_before > ii);
+            vassert(vreg_info[m].reg_class != HRcINVALID);
+            EMIT_INSTR( (*genSpill)( state[spillee].rreg,
+                                     vreg_info[m].spill_offset ) );
+        }
 
          /* Update the state to reflect the new assignment for this
             rreg. */