--- /dev/null
+From 0890540e21cf1156b4cf960a4c1c734db4e816f9 Mon Sep 17 00:00:00 2001
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Date: Wed, 30 Aug 2017 17:12:05 +0100
+Subject: drm/i915: add GT number to intel_device_info
+
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+
+commit 0890540e21cf1156b4cf960a4c1c734db4e816f9 upstream.
+
+Up to Coffeelake we could deduce this GT number from the device ID.
+This doesn't seem to be the case anymore. This change reorders pciids
+per GT and adds a gt field to intel_device_info. We set this field on
+the following platforms :
+
+ - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL
+
+Before & After :
+
+$ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l
+209
+
+v2: Add SNB & IVB (Chris)
+
+v3: Fix compilation error in early-quirks (Lionel)
+
+v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)
+
+Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-2-lionel.g.landwerlin@intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 1
+ drivers/gpu/drm/i915/i915_pci.c | 193 +++++++++++++++++++++++++++++++---------
+ include/drm/i915_pciids.h | 152 +++++++++++++++++++------------
+ 3 files changed, 246 insertions(+), 100 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -842,6 +842,7 @@ struct intel_device_info {
+ u8 gen;
+ u16 gen_mask;
+ enum intel_platform platform;
++ u8 gt; /* GT number, 0 if undefined */
+ u8 ring_mask; /* Rings supported by the HW */
+ u8 num_rings;
+ #define DEFINE_FLAG(name) u8 name:1
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -224,15 +224,34 @@ static const struct intel_device_info in
+ GEN_DEFAULT_PIPEOFFSETS, \
+ CURSOR_OFFSETS
+
+-static const struct intel_device_info intel_sandybridge_d_info = {
+- GEN6_FEATURES,
+- .platform = INTEL_SANDYBRIDGE,
++#define SNB_D_PLATFORM \
++ GEN6_FEATURES, \
++ .platform = INTEL_SANDYBRIDGE
++
++static const struct intel_device_info intel_sandybridge_d_gt1_info = {
++ SNB_D_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_sandybridge_d_gt2_info = {
++ SNB_D_PLATFORM,
++ .gt = 2,
++};
++
++#define SNB_M_PLATFORM \
++ GEN6_FEATURES, \
++ .platform = INTEL_SANDYBRIDGE, \
++ .is_mobile = 1
++
++
++static const struct intel_device_info intel_sandybridge_m_gt1_info = {
++ SNB_M_PLATFORM,
++ .gt = 1,
+ };
+
+-static const struct intel_device_info intel_sandybridge_m_info = {
+- GEN6_FEATURES,
+- .platform = INTEL_SANDYBRIDGE,
+- .is_mobile = 1,
++static const struct intel_device_info intel_sandybridge_m_gt2_info = {
++ SNB_M_PLATFORM,
++ .gt = 2,
+ };
+
+ #define GEN7_FEATURES \
+@@ -249,22 +268,41 @@ static const struct intel_device_info in
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS
+
+-static const struct intel_device_info intel_ivybridge_d_info = {
+- GEN7_FEATURES,
+- .platform = INTEL_IVYBRIDGE,
+- .has_l3_dpf = 1,
++#define IVB_D_PLATFORM \
++ GEN7_FEATURES, \
++ .platform = INTEL_IVYBRIDGE, \
++ .has_l3_dpf = 1
++
++static const struct intel_device_info intel_ivybridge_d_gt1_info = {
++ IVB_D_PLATFORM,
++ .gt = 1,
+ };
+
+-static const struct intel_device_info intel_ivybridge_m_info = {
+- GEN7_FEATURES,
+- .platform = INTEL_IVYBRIDGE,
+- .is_mobile = 1,
+- .has_l3_dpf = 1,
++static const struct intel_device_info intel_ivybridge_d_gt2_info = {
++ IVB_D_PLATFORM,
++ .gt = 2,
++};
++
++#define IVB_M_PLATFORM \
++ GEN7_FEATURES, \
++ .platform = INTEL_IVYBRIDGE, \
++ .is_mobile = 1, \
++ .has_l3_dpf = 1
++
++static const struct intel_device_info intel_ivybridge_m_gt1_info = {
++ IVB_M_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_ivybridge_m_gt2_info = {
++ IVB_M_PLATFORM,
++ .gt = 2,
+ };
+
+ static const struct intel_device_info intel_ivybridge_q_info = {
+ GEN7_FEATURES,
+ .platform = INTEL_IVYBRIDGE,
++ .gt = 2,
+ .num_pipes = 0, /* legal, last one wins */
+ .has_l3_dpf = 1,
+ };
+@@ -299,10 +337,24 @@ static const struct intel_device_info in
+ .has_rc6p = 0 /* RC6p removed-by HSW */, \
+ .has_runtime_pm = 1
+
+-static const struct intel_device_info intel_haswell_info = {
+- HSW_FEATURES,
+- .platform = INTEL_HASWELL,
+- .has_l3_dpf = 1,
++#define HSW_PLATFORM \
++ HSW_FEATURES, \
++ .platform = INTEL_HASWELL, \
++ .has_l3_dpf = 1
++
++static const struct intel_device_info intel_haswell_gt1_info = {
++ HSW_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_haswell_gt2_info = {
++ HSW_PLATFORM,
++ .gt = 2,
++};
++
++static const struct intel_device_info intel_haswell_gt3_info = {
++ HSW_PLATFORM,
++ .gt = 3,
+ };
+
+ #define BDW_FEATURES \
+@@ -318,12 +370,27 @@ static const struct intel_device_info in
+ .gen = 8, \
+ .platform = INTEL_BROADWELL
+
+-static const struct intel_device_info intel_broadwell_info = {
++static const struct intel_device_info intel_broadwell_gt1_info = {
++ BDW_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_broadwell_gt2_info = {
+ BDW_PLATFORM,
++ .gt = 2,
++};
++
++static const struct intel_device_info intel_broadwell_rsvd_info = {
++ BDW_PLATFORM,
++ .gt = 3,
++ /* According to the device ID those devices are GT3, they were
++ * previously treated as not GT3, keep it like that.
++ */
+ };
+
+ static const struct intel_device_info intel_broadwell_gt3_info = {
+ BDW_PLATFORM,
++ .gt = 3,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ };
+
+@@ -358,13 +425,29 @@ static const struct intel_device_info in
+ .has_guc = 1, \
+ .ddb_size = 896
+
+-static const struct intel_device_info intel_skylake_info = {
++static const struct intel_device_info intel_skylake_gt1_info = {
+ SKL_PLATFORM,
++ .gt = 1,
+ };
+
+-static const struct intel_device_info intel_skylake_gt3_info = {
++static const struct intel_device_info intel_skylake_gt2_info = {
+ SKL_PLATFORM,
+- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
++ .gt = 2,
++};
++
++#define SKL_GT3_PLUS_PLATFORM \
++ SKL_PLATFORM, \
++ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
++
++
++static const struct intel_device_info intel_skylake_gt3_info = {
++ SKL_GT3_PLUS_PLATFORM,
++ .gt = 3,
++};
++
++static const struct intel_device_info intel_skylake_gt4_info = {
++ SKL_GT3_PLUS_PLATFORM,
++ .gt = 4,
+ };
+
+ #define GEN9_LP_FEATURES \
+@@ -416,12 +499,19 @@ static const struct intel_device_info in
+ .has_guc = 1, \
+ .ddb_size = 896
+
+-static const struct intel_device_info intel_kabylake_info = {
++static const struct intel_device_info intel_kabylake_gt1_info = {
+ KBL_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_kabylake_gt2_info = {
++ KBL_PLATFORM,
++ .gt = 2,
+ };
+
+ static const struct intel_device_info intel_kabylake_gt3_info = {
+ KBL_PLATFORM,
++ .gt = 3,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ };
+
+@@ -434,20 +524,28 @@ static const struct intel_device_info in
+ .has_guc = 1, \
+ .ddb_size = 896
+
+-static const struct intel_device_info intel_coffeelake_info = {
++static const struct intel_device_info intel_coffeelake_gt1_info = {
++ CFL_PLATFORM,
++ .gt = 1,
++};
++
++static const struct intel_device_info intel_coffeelake_gt2_info = {
+ CFL_PLATFORM,
++ .gt = 2,
+ };
+
+ static const struct intel_device_info intel_coffeelake_gt3_info = {
+ CFL_PLATFORM,
++ .gt = 3,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ };
+
+-static const struct intel_device_info intel_cannonlake_info = {
++static const struct intel_device_info intel_cannonlake_gt2_info = {
+ BDW_FEATURES,
+ .is_alpha_support = 1,
+ .platform = INTEL_CANNONLAKE,
+ .gen = 10,
++ .gt = 2,
+ .ddb_size = 1024,
+ .has_csr = 1,
+ .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
+@@ -476,31 +574,40 @@ static const struct pci_device_id pciidl
+ INTEL_PINEVIEW_IDS(&intel_pineview_info),
+ INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
+ INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+- INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
+- INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
++ INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
++ INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
++ INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
++ INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
+ INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
+- INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
+- INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
+- INTEL_HSW_IDS(&intel_haswell_info),
++ INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
++ INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
++ INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
++ INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
++ INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
++ INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
++ INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
+ INTEL_VLV_IDS(&intel_valleyview_info),
+- INTEL_BDW_GT12_IDS(&intel_broadwell_info),
++ INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
++ INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
+ INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
+- INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
++ INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
+ INTEL_CHV_IDS(&intel_cherryview_info),
+- INTEL_SKL_GT1_IDS(&intel_skylake_info),
+- INTEL_SKL_GT2_IDS(&intel_skylake_info),
++ INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
++ INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
+ INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
+- INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
++ INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
+ INTEL_BXT_IDS(&intel_broxton_info),
+ INTEL_GLK_IDS(&intel_geminilake_info),
+- INTEL_KBL_GT1_IDS(&intel_kabylake_info),
+- INTEL_KBL_GT2_IDS(&intel_kabylake_info),
++ INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
++ INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
+ INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
+ INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
+- INTEL_CFL_S_IDS(&intel_coffeelake_info),
+- INTEL_CFL_H_IDS(&intel_coffeelake_info),
+- INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
+- INTEL_CNL_IDS(&intel_cannonlake_info),
++ INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
++ INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
++ INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
++ INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
++ INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
++ INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
+ {0, 0, 0}
+ };
+ MODULE_DEVICE_TABLE(pci, pciidlist);
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -118,92 +118,125 @@
+ #define INTEL_IRONLAKE_M_IDS(info) \
+ INTEL_VGA_DEVICE(0x0046, info)
+
+-#define INTEL_SNB_D_IDS(info) \
++#define INTEL_SNB_D_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0102, info), \
+- INTEL_VGA_DEVICE(0x0112, info), \
+- INTEL_VGA_DEVICE(0x0122, info), \
+ INTEL_VGA_DEVICE(0x010A, info)
+
+-#define INTEL_SNB_M_IDS(info) \
+- INTEL_VGA_DEVICE(0x0106, info), \
++#define INTEL_SNB_D_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x0112, info), \
++ INTEL_VGA_DEVICE(0x0122, info)
++
++#define INTEL_SNB_D_IDS(info) \
++ INTEL_SNB_D_GT1_IDS(info), \
++ INTEL_SNB_D_GT2_IDS(info)
++
++#define INTEL_SNB_M_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x0106, info)
++
++#define INTEL_SNB_M_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0116, info), \
+ INTEL_VGA_DEVICE(0x0126, info)
+
++#define INTEL_SNB_M_IDS(info) \
++ INTEL_SNB_M_GT1_IDS(info), \
++ INTEL_SNB_M_GT2_IDS(info)
++
++#define INTEL_IVB_M_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
++
++#define INTEL_IVB_M_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
++
+ #define INTEL_IVB_M_IDS(info) \
+- INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
+- INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
++ INTEL_IVB_M_GT1_IDS(info), \
++ INTEL_IVB_M_GT2_IDS(info)
+
+-#define INTEL_IVB_D_IDS(info) \
++#define INTEL_IVB_D_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
++ INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
++
++#define INTEL_IVB_D_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
+ INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
+
++#define INTEL_IVB_D_IDS(info) \
++ INTEL_IVB_D_GT1_IDS(info), \
++ INTEL_IVB_D_GT2_IDS(info)
++
+ #define INTEL_IVB_Q_IDS(info) \
+ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
+
+-#define INTEL_HSW_IDS(info) \
++#define INTEL_HSW_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
+- INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+- INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+- INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+- INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
+- INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
+- INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
+ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+- INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+- INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+- INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+ INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+- INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
+- INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
+- INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
+ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
++ INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
++ INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
++ INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
++ INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
++
++#define INTEL_HSW_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
++ INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
++ INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
++ INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
++ INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
++ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
++ INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
++ INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
++ INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
+- INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
+- INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
+- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
+- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+- INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
++ INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
++
++#define INTEL_HSW_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
++ INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
++ INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
++ INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
++ INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
++ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
++ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
++ INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
++ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
++ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+ INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
+- INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
+- INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
+
++#define INTEL_HSW_IDS(info) \
++ INTEL_HSW_GT1_IDS(info), \
++ INTEL_HSW_GT2_IDS(info), \
++ INTEL_HSW_GT3_IDS(info)
++
+ #define INTEL_VLV_IDS(info) \
+ INTEL_VGA_DEVICE(0x0f30, info), \
+ INTEL_VGA_DEVICE(0x0f31, info), \
+@@ -212,17 +245,19 @@
+ INTEL_VGA_DEVICE(0x0157, info), \
+ INTEL_VGA_DEVICE(0x0155, info)
+
+-#define INTEL_BDW_GT12_IDS(info) \
++#define INTEL_BDW_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+- INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
++ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
++ INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
++
++#define INTEL_BDW_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+- INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
+- INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+- INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
++ INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
+ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+
+@@ -243,7 +278,8 @@
+ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
+
+ #define INTEL_BDW_IDS(info) \
+- INTEL_BDW_GT12_IDS(info), \
++ INTEL_BDW_GT1_IDS(info), \
++ INTEL_BDW_GT2_IDS(info), \
+ INTEL_BDW_GT3_IDS(info), \
+ INTEL_BDW_RSVD_IDS(info)
+
+@@ -335,20 +371,22 @@
+ INTEL_KBL_GT4_IDS(info)
+
+ /* CFL S */
+-#define INTEL_CFL_S_IDS(info) \
++#define INTEL_CFL_S_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
+- INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
++ INTEL_VGA_DEVICE(0x3E93, info) /* SRV GT1 */
++
++#define INTEL_CFL_S_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */
+
+ /* CFL H */
+-#define INTEL_CFL_H_IDS(info) \
++#define INTEL_CFL_H_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+
+ /* CFL U */
+-#define INTEL_CFL_U_IDS(info) \
++#define INTEL_CFL_U_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
projects / thirdparty / kernel / stable-queue.git / commitdiff
