Handle NegF64.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1196

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 505f746340a47e45af38bc24a5a6021d0bb2253b..5acca08592bae562bfb73ef20fa798dfd6d67293 100644 (file)
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -2305,6 +2305,24 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
             return;
          }
 
+         /* Neg64(e) */
+         case Iop_Neg64: {
+            HReg yLo, yHi;
+            HReg tLo = newVRegI(env);
+            HReg tHi = newVRegI(env);
+            /* yHi:yLo = arg */
+            iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
+            /* tLo = 0 - yLo, and set carry */
+            addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tLo));
+            addInstr(env, X86Instr_Alu32R(Xalu_SUB, X86RMI_Reg(yLo), tLo));
+            /* tHi = 0 - yHi - carry */
+            addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tHi));
+            addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(yHi), tHi));
+            *rHi = tHi;
+            *rLo = tLo;
+            return;
+         }
+
          /* ReinterpF64asI64(e) */
          /* Given an IEEE754 double, produce an I64 with the same bit
             pattern. */