drm/i915: Implement .min_plane_width() for PTL+

PTL+ spposedly still has the same plane min width limit
as ADL. Check for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251009211313.30234-4-ville.syrjala@linux.intel.com
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a50d9c48b8cae72b102572861cd0089799334b01..34b193d567633c0775e15c3f8ce923ee3cf36aed 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2819,6 +2819,7 @@ skl_universal_plane_create(struct intel_display *display,
        intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);
 
        if (DISPLAY_VER(display) >= 30) {
+               plane->min_width = adl_plane_min_width;
                plane->max_width = xe3_plane_max_width;
                plane->max_height = icl_plane_max_height;
                plane->min_cdclk = icl_plane_min_cdclk;